Display device

Abstract

A display device includes a plurality of pixels, in which each pixel includes: a first transistor connected between a first node and a second node, and including a gate electrode connected to a third node; a second transistor connected between the data line and the first node, and including a gate electrode; a third transistor connected between the second node and a third node and including a gate electrode; a fourth transistor connected between the first initialization voltage line and the third node, and including a gate electrode; a fifth transistor connected between the first power supply line and the first node, and including a gate electrode; a sixth transistor connected between the second node and the fourth node and including a gate electrode; a storage capacitor connected between the third node and the first power line; and a light emitting element connected between the fourth node and the second power supply line.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to an organic light emitting display device. Background Art

[0002] The display device may include a plurality of pixels. Each of the pixels may include a pixel circuit including a driving transistor and a light emitting element. A driving current may be generated based on a voltage between a gate electrode and a source electrode of the driving transistor, and the light emitting element may emit light based on the driving current.

[0003] When the data voltage is changed due to the coupling effect of the parasitic capacitor formed between the data line configured to transmit the data voltage to the pixel and the source electrode of the driving transistor, the voltage of the source electrode of the driving transistor may be changed. When the voltage of the source electrode of the driving transistor is changed (that is, when the voltage of the source electrode of the driving transistor is unstable), a spot defect such as a Mura phenomenon may occur in the display device. Summary of the invention

[0004] The embodiment provides a display device with improved image quality.

[0005] The display device according to the embodiment may include a plurality of pixels. Each of the plurality of pixels may include: a first transistor connected between a first node and a second node and including a gate electrode connected to a third node; a second transistor connected between a data line configured to transmit a data voltage and the first node and including a gate electrode configured to receive a write gate signal; a third transistor connected between the second node and the third node and including a gate electrode configured to receive a compensation gate signal; a fourth transistor connected between a first initialization voltage line configured to transmit a first initialization voltage and the third node and including a gate electrode configured to receive an initialization gate signal; a fifth transistor connected between a first power line configured to transmit a first power supply voltage and the first node and including a gate electrode configured to receive a compensation gate signal; a sixth transistor connected between the second node and the fourth node and including a gate electrode configured to receive an emission control signal; a storage capacitor connected between the third node and the first power line; and a light emitting element connected between the fourth node and the second power line configured to transmit a second power supply voltage.

[0006] In an embodiment, a frame period during which any one of the plurality of pixels is driven may include an initialization period during which the fourth transistor is turned on in response to the initialization gate signal, a compensation period during which the third transistor is turned on in response to the compensation gate signal, and an emission period during which the sixth transistor is turned on in response to the emission control signal. During a period other than the compensation period in the frame period, the first power supply voltage may be applied to the first node.

[0007] In an embodiment, the frame period may further include a writing period during which the second transistor is turned on in response to the writing gate signal. The writing period may be located within the compensation period.

[0008] In an embodiment, the third transistor may be an N-type transistor, and the fifth transistor may be a P-type transistor.

[0009] In an embodiment, each of the plurality of pixels may further include a parasitic capacitor disposed between the data line and the first node.

[0010] In an embodiment, each of the plurality of pixels may further include a seventh transistor connected between a second initialization voltage line configured to transmit a second initialization voltage and the fourth node and including a gate electrode configured to receive a bypass gate signal.

[0011] The display device according to the embodiment may include a plurality of pixel circuits. Each of the plurality of pixel circuits may include: a first active layer, disposed on a substrate, and including a first channel region, a second channel region, a fifth channel region, and a sixth channel region. Each of the plurality of pixel circuits may further include: a first conductive layer, disposed on the first active layer, and including a first gate pattern overlapping the first channel region, a write gate line overlapping the second channel region, a second gate pattern overlapping the fifth channel region, and an emission control line overlapping the sixth channel region. Each of the plurality of pixel circuits may further include: a second conductive layer, disposed on the first conductive layer, and including a capacitor pattern overlapping the first gate pattern, a first compensation gate line configured to transmit a compensation gate signal, and a first initialization gate line configured to transmit an initialization gate signal. Each of the plurality of pixel circuits may further include: a second active layer, disposed on the second conductive layer, and including a third channel region overlapping the first compensation gate line and a fourth channel region overlapping the first initialization gate line. Each of the plurality of pixel circuits may further include: a third conductive layer disposed on the second active layer and including a second compensation gate line overlapping the third channel region and a second initialization gate line overlapping the fourth channel region; and a fourth conductive layer disposed on the third conductive layer and including a gate connection pattern contacting the first gate pattern and a third drain region of the second active layer located between the third channel region and the fourth channel region, and a compensation connection pattern contacting the second gate pattern and the first compensation gate line.

[0012] In an embodiment, the gate connection pattern may not overlap the second compensation gate line.

[0013] In an embodiment, the capacitor pattern may be disposed between the first compensation gate line and the first initialization gate line when viewed in a plan view.

[0014] In an embodiment, the fourth conductive layer may further include: a data connection pattern contacting the second source region of the first active layer located on one side of the second channel region; a power connection pattern contacting the fifth source region of the first active layer located on one side of the fifth channel region and the capacitor pattern; an active connection pattern contacting the first drain region of the first active layer located on one side of the first channel region and the third source region of the second active layer located on one side of the third channel region; and a first connection pattern contacting the sixth drain region of the first active layer located on one side of the sixth channel region.

[0015] In an embodiment, each of the pixel circuits may further include: a fifth conductive layer disposed on the fourth conductive layer and including a data line contacting the data connection pattern, a first power line contacting the power connection pattern, and a second connection pattern contacting the first connection pattern.

[0016] In an embodiment, the second conductive layer may further include a first initialization voltage line configured to transmit a first initialization voltage. The fourth conductive layer may further include an initialization connection pattern contacting the first initialization voltage line and a fourth source region of the second active layer located at one side of the fourth channel region.

[0017] In an embodiment, the first active layer may further include a seventh channel region overlapping the write gate line. The fourth conductive layer may further include a second initialization voltage line configured to transmit a second initialization voltage and contact a seventh source region of the first active layer located at one side of the seventh channel region.

[0018] In an embodiment, the first active layer may include polysilicon, and the second active layer may include an oxide semiconductor.

[0019] The display device according to the embodiment may include a plurality of pixels. Each of the plurality of pixels may include: a first transistor connected between a first node and a second node and including a gate electrode connected to a third node; a second transistor connected between a data line configured to transmit a data voltage and the second node and including a gate electrode configured to receive a write gate signal; a third transistor connected between the first node and the third node and including a gate electrode configured to receive a compensation gate signal; a fourth transistor connected between a first initialization voltage line configured to transmit a first initialization voltage and the third node and including a gate electrode configured to receive an initialization gate signal; a fifth transistor connected between a first power line configured to transmit a first power supply voltage and the first node and including a gate electrode configured to receive a compensation gate signal; a sixth transistor connected between the second node and the fourth node and including a gate electrode configured to receive an emission control signal; a storage capacitor connected between the third node and the first power line; and a light emitting element connected between the fourth node and the second power line configured to transmit a second power supply voltage.

[0020] In an embodiment, a frame period during which any one of the plurality of pixels is driven may include an initialization period during which the fourth transistor is turned on in response to the initialization gate signal, a compensation period during which the third transistor is turned on in response to the compensation gate signal, and an emission period during which the sixth transistor is turned on in response to the emission control signal. During a period other than the compensation period in the frame period, the first power supply voltage may be applied to the first node.

[0021] In an embodiment, the frame period may further include a writing period during which the second transistor is turned on in response to the writing gate signal. The writing period may be located within the compensation period.

[0022] In an embodiment, the third transistor may be an N-type transistor, and the fifth transistor may be a P-type transistor.

[0023] In an embodiment, each of the plurality of pixels may further include a parasitic capacitor formed between the data line and the second node.

[0024] In an embodiment, each of the plurality of pixels may further include a seventh transistor connected between a second initialization voltage line configured to transmit a second initialization voltage and the fourth node and including a gate electrode configured to receive a bypass gate signal.

[0025] In the display device according to the embodiment, during the frame period other than the compensation period during which the threshold voltage of the first transistor is compensated, the first power supply voltage can be applied to the first electrode of the first transistor (e.g., the driving transistor) through the fifth transistor based on the compensation gate signal, so that the voltage of the first electrode of the first transistor can be stabilized. Accordingly, a spot defect does not occur in the display device, and the image quality of the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Illustrative and non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0027] Figure 1 is a block diagram showing a display device according to an embodiment.

[0028] Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A circuit diagram of an example of a pixel in a display device.

[0029] Figure 3 It is used to describe the Figure 2 Waveform diagram of the pixel operation.

[0030] Figure 4 is a diagram showing a method according to an embodiment of the present invention. Figure 2 A layout diagram of a pixel circuit region in which a pixel circuit in a pixel is arranged.

[0031] Figure 5 is a diagram showing a method according to an embodiment of the present invention. Figure 2 A layout diagram of a pixel circuit region in which a pixel circuit in a pixel is arranged.

[0032] Figure 6 is a diagram showing a method according to an embodiment of the present invention. Figure 2 A layout diagram of a pixel circuit region in which a pixel circuit in a pixel is arranged.

[0033] Figure 7 is a diagram showing a method according to an embodiment of the present invention. Figure 2 A layout diagram of a pixel circuit region in which a pixel circuit in a pixel is arranged.

[0034] Figure 8 is a diagram showing a method according to an embodiment of the present invention. Figure 2 A layout diagram of a pixel circuit region in which a pixel circuit in a pixel is arranged.

[0035] Fig. 9 is a diagram showing a method according to an embodiment of the present invention. Figure 2 A layout diagram of a pixel circuit region in which a pixel circuit in a pixel is arranged.

[0036] Fig.10 is a diagram showing a method according to an embodiment of the present invention. Figure 2 A layout diagram of a pixel circuit region in which a pixel circuit in a pixel is arranged.

[0037] Fig.11 is a diagram showing a method according to an embodiment of the present invention. Figure 2 A layout diagram of a pixel circuit region in which a pixel circuit in a pixel is arranged.

[0038] Fig.12 According to the embodiment along Fig.11 The line A-A' intercepts Fig.11 A cross-sectional view of the layout diagram.

[0039] Fig.13 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A circuit diagram of another example of a pixel in a display device.

[0040] Fig.14 is a block diagram illustrating an electronic device according to an embodiment.

[0041] Fig.15 is a diagram showing a method according to an embodiment of the present invention Fig.14 A perspective view of an example in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0042] Hereinafter, a display device according to an embodiment will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, the same or similar reference numerals will be used for the same elements. However, the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the scope of the present invention to those skilled in the art.

[0043] It will be understood that when an element (or region, layer, portion, etc.) is referred to as being related to another element (such as "on" another element, "connected to" or "coupled to" another element), it can be directly disposed on the other element, directly connected to or coupled to the other element, or intervening elements may be disposed therebetween.

[0044] The same reference numerals or symbols refer to the same elements from beginning to end. In the accompanying drawings, the thickness, proportion and size of the elements are exaggerated in order to effectively describe the technical content. As used in this article, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0045] The term "and / or" includes all combinations of one or more that the associated configurations may define.

[0046] It will be understood that although the terms "first", "second", etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part without departing from the scope of the present invention. Similarly, the second element, component, region, layer or part can be referred to as the first element, component, region, layer or part. As used in this article, the singular form "one" and "the (described)" are intended to also include plural forms, unless the context clearly indicates otherwise.

[0047] In addition, terms such as "below", "on the lower side", "above", or "on the upper side" may be used to describe the relationship of elements illustrated in the drawings. These terms have relative concepts and are described based on directions indicated in the drawings.

[0048] It will be further understood that when used in this specification, the terms "comprising", "including" and / or "having" specify the presence of stated features, integers, steps, operations, elements, components and / or groups thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. As used herein, "directly disposed on" may mean that there are no additional layers, films, regions or plates, etc. between one component such as a layer, film, region or plate and another component. For example, "directly disposed on" may mean that two layers or two components are disposed without using an additional component such as a bonding component therebetween.

[0049] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for that particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurements of a particular quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless so explicitly defined herein.

[0051] Figure 1is a block diagram showing a display device 100 according to an embodiment.

[0052] In the examples and with reference to Figure 1 , the display device 100 may include a display panel 110 , a scan driver 120 , an emission driver 130 , a data driver 140 , and a controller 150 .

[0053] In an embodiment, the display panel 110 may include a pixel PX. According to an embodiment, the pixel PX may include a first pixel configured to emit light having a first color, a second pixel configured to emit light having a second color, and a third pixel configured to emit light having a third color. For example, the first color, the second color, and the third color may be red, green, and blue, respectively.

[0054] In an embodiment, the scan driver 120 may provide a scan signal SS to the pixel PX. The scan driver 120 may sequentially generate first to n-th scan signals SS corresponding to the first to n-th pixel rows, respectively, based on the first control signal CNT1 (where n is a natural number greater than or equal to 2). The first control signal CNT1 may include a scan clock signal, a scan start signal, and the like.

[0055] In an embodiment, the emission driver 130 may provide an emission control signal EM to the pixel PX. The emission driver 130 may sequentially generate first to nth emission control signals EM corresponding to the first to nth pixel rows, respectively, based on the second control signal CNT2. The second control signal CNT2 may include an emission clock signal, an emission start signal, and the like.

[0056] In an embodiment, the data driver 140 may provide a data voltage VDAT to the pixel PX. The data driver 140 may generate first to m-th data voltages VDAT corresponding to the first to m-th pixel columns, respectively, based on the second image data IMD2 and the third control signal CNT3 (where m is a natural number greater than or equal to 2). According to an embodiment, the second image data IMD2 may include a grayscale value corresponding to the pixel PX. The third control signal CNT3 may include a data clock signal, a horizontal start signal, a load signal, and the like.

[0057] In an embodiment, the controller 150 may control the operation (or driving) of the scan driver 120, the operation (or driving) of the emission driver 130, and the operation (or driving) of the data driver 140. The controller 150 may generate a first control signal CNT1, a second control signal CNT2, a second image data IMD2, and a third control signal CNT3 based on the first image data IMD1 and the control signal CNT. According to an embodiment, the first image data IMD1 may include a grayscale value corresponding to the pixel PX. The controller 150 may convert the first image data IMD1 into the second image data IMD2. The control signal CNT may include a main clock signal, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and the like.

[0058] Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 1 is a circuit diagram of an example of a pixel PX1 in the display device 100 .

[0059] In the examples and with reference to Figure 1 and Figure 2 , the pixel PX1 may include a pixel circuit PXC and a light emitting element LED. The pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor CST. According to an embodiment, the pixel circuit PXC may further include a parasitic capacitor CPR. The scan signal SS may include a write gate signal GW, a compensation gate signal GC, an initialization gate signal GI and a bypass gate signal GB.

[0060] In an embodiment, the first transistor T1 may be connected between the first node N1 and the second node N2. The first transistor T1 may include a first electrode connected to the first node N1, a second electrode connected to the second node N2, and a gate electrode connected to the third node N3. The first transistor T1 may generate a driving current corresponding to a voltage between the first node N1 and the third node N3. The first transistor T1 may be referred to as a driving transistor.

[0061] In an embodiment, the second transistor T2 may be connected between a data line DL configured to transmit a data voltage VDAT and a first node N1, and may be turned on in response to a write gate signal GW having a low voltage level. The second transistor T2 may include a first electrode connected to the data line DL, a second electrode connected to the first node N1, and a gate electrode configured to receive the write gate signal GW. The second transistor T2 may transmit the data voltage VDAT to the first node N1 in response to the write gate signal GW having a low voltage level. The second transistor T2 may be referred to as a write transistor.

[0062] In an embodiment, the third transistor T3 may be connected between the second node N2 and the third node N3, and is turned on in response to a compensation gate signal GC having a high voltage level. The third transistor T3 may include a first electrode connected to the second node N2, a second electrode connected to the third node N3, and a gate electrode configured to receive the compensation gate signal GC. The third transistor T3 may connect the second node N2 to the third node N3 in response to the compensation gate signal GC having a high voltage level. The third transistor T3 may be referred to as a compensation transistor.

[0063] According to an embodiment, the third transistor T3 may include a bottom gate electrode and a top gate electrode configured to receive the compensation gate signal GC. In other words, the third transistor T3 may be a dual-gate transistor.

[0064] In an embodiment, the fourth transistor T4 may be connected between a first initialization voltage line VINTL configured to transmit a first initialization voltage VINT and a third node N3, and may be turned on in response to an initialization gate signal GI having a high voltage level. The fourth transistor T4 may include a first electrode connected to the first initialization voltage line VINTL, a second electrode connected to the third node N3, and a gate electrode configured to receive the initialization gate signal GI. The fourth transistor T4 may transmit the first initialization voltage VINT to the third node N3 in response to the initialization gate signal GI having a high voltage level. The fourth transistor T4 may be referred to as an initialization transistor.

[0065] According to an embodiment, the fourth transistor T4 may include a bottom gate electrode and a top gate electrode configured to receive the initialization gate signal GI. In other words, the fourth transistor T4 may be a dual-gate transistor.

[0066] In an embodiment, the fifth transistor T5 may be connected between a first power line PL1 configured to transmit a first power voltage ELVDD and a first node N1, and may be turned on in response to a compensation gate signal GC having a low voltage level. The fifth transistor T5 may include a first electrode connected to the first power line PL1, a second electrode connected to the first node N1, and a gate electrode configured to receive the compensation gate signal GC. The fifth transistor T5 may transmit the first power voltage ELVDD to the first node N1 in response to the compensation gate signal GC having a low voltage level.

[0067] In an embodiment, the sixth transistor T6 may be connected between the second node N2 and the fourth node N4 and turned on in response to an emission control signal EM having a low voltage level. The sixth transistor T6 may include a first electrode connected to the second node N2, a second electrode connected to the fourth node N4, and a gate electrode configured to receive the emission control signal EM. The sixth transistor T6 may connect the second node N2 to the fourth node N4 in response to the emission control signal EM having a low voltage level. The sixth transistor T6 may be referred to as an emission control transistor.

[0068] In an embodiment, the seventh transistor T7 may be connected between a second initialization voltage line VAINTL configured to transmit a second initialization voltage VAINT and a fourth node N4, and may be turned on in response to a bypass gate signal GB having a low voltage level. The seventh transistor T7 may include a first electrode connected to the second initialization voltage line VAINTL, a second electrode connected to the fourth node N4, and a gate electrode configured to receive the bypass gate signal GB. The seventh transistor T7 may transmit the second initialization voltage VAINT to the fourth node N4 in response to the bypass gate signal GB having a low voltage level.

[0069] According to an embodiment, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a P-type transistor (e.g., a PMOS transistor), and each of the third transistor T3 and the fourth transistor T4 may be an N-type transistor (e.g., an NMOS transistor). According to an embodiment, each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a polysilicon transistor, and each of the third transistor T3 and the fourth transistor T4 may be an oxide semiconductor transistor.

[0070] In an embodiment, the storage capacitor CST may be connected between the third node N3 and the first power line PL1. The storage capacitor CST may include a first electrode connected to the third node N3 and a second electrode connected to the first power line PL1. The storage capacitor CST may store a voltage of the third node N3.

[0071] In an embodiment, a parasitic capacitor CPR may be formed between the data line DL and the first node N1. The parasitic capacitor CPR may be an unintended capacitor generated due to the overlap of the data line DL and the first node N1. When the data voltage VDAT transmitted by the data line DL is changed due to the coupling effect of the parasitic capacitor CPR, the voltage of the first node N1 may be changed.

[0072] In an embodiment, the light emitting element LED may be connected between the fourth node N4 and the second power line PL2 configured to transmit the second power voltage ELVSS. The light emitting element LED may include a first electrode (e.g., an anode) connected to the fourth node N4 and a second electrode (e.g., a cathode) connected to the second power line PL2. The light emitting element LED may emit light based on the driving current generated by the first transistor T1.

[0073] According to an embodiment, the light emitting element LED may be an organic light emitting diode. According to another embodiment, the light emitting element LED may be an inorganic light emitting diode, a micro light emitting diode or a quantum dot light emitting diode.

[0074] Figure 3 It is used to describe the Figure 2 A waveform diagram of the operation of the pixel PX1.

[0075] In the examples and with reference to Figure 2 and Figure 3 , the data voltage VDAT, the emission control signal EM, the initialization gate signal GI, the compensation gate signal GC, the write gate signal GW and the bypass gate signal GB may be provided to the pixel PX1. According to an embodiment, the compensation gate signal GC may be a signal obtained by shifting the initialization gate signal GI by a predetermined time. According to an embodiment, the bypass gate signal GB may be a signal obtained by shifting the write gate signal GW by a predetermined time.

[0076] In an embodiment, the frame period FRM during which the pixel PX1 is driven may include an initialization period PI, a compensation period PC, a writing period PW, a bypass period PB, and an emission period PE.

[0077] In an embodiment, in the initialization period PI, the fourth transistor T4 may be turned on in response to the initialization gate signal GI having a high voltage level, and the first initialization voltage VINT may be transmitted to the third node N3 through the fourth transistor T4.

[0078] In an embodiment, in the compensation period PC after the initialization period PI, the third transistor T3 may be turned on in response to the compensation gate signal GC having a high voltage level, and the second node N2 and the third node N3 may be connected to each other. Accordingly, the first transistor T1 may be diode-connected, a voltage (VINT+VTH+VX) obtained by adding the first initialization voltage VINT, the threshold voltage (VTH) of the first transistor T1, and the coupling voltage (VX) may be applied to the first node N1, and a voltage (VINT+VX) obtained by adding the first initialization voltage VINT and the coupling voltage (VX) may be applied to the third node N3. The coupling voltage (VX) may vary depending on the capacitance of the storage capacitor CST and the capacitance of the parasitic capacitor between the first node N1 and the first power line PL1.

[0079] In an embodiment, in a write period PW located within the compensation period PC, the second transistor T2 may be turned on in response to a write gate signal GW having a low voltage level, and the data voltage VDAT may be transmitted to the first node N1 through the second transistor T2. In addition, a voltage (VDAT-VTH) obtained by subtracting a threshold voltage (VTH) of the first transistor T1 from the data voltage VDAT may be applied to the third node N3 through the first transistor T1 diode-connected by the turned-on third transistor T3.

[0080] In an embodiment, in the bypass period PB, the seventh transistor T7 may be turned on in response to the bypass gate signal GB having a low voltage level, and the second initialization voltage VAINT may be transmitted to the fourth node N4 through the seventh transistor T7. In this case, the charge charged in the parasitic capacitor of the light emitting element LED may escape to the second initialization voltage line VAINTL through the seventh transistor T7.

[0081] In an embodiment, in the emission period PE, the sixth transistor T6 may be turned on in response to the emission control signal EM having a low voltage level, and the second node N2 and the fourth node N4 may be connected to each other. Accordingly, the first transistor T1 and the light emitting element LED may be connected to each other through the sixth transistor T6, and a driving current corresponding to a voltage between the first electrode and the gate electrode of the first transistor T1 (a voltage between the first node N1 and the third node N3) may be provided to the light emitting element LED, and the light emitting element LED may emit light based on the driving current.

[0082] In an embodiment, during a period other than the compensation period PC in the frame period FRM, the first power supply voltage ELVDD may be applied to the first node N1. During a period other than the compensation period PC in the frame period FRM, the fifth transistor T5 may be turned on in response to the compensation gate signal GC having a low voltage level, and the first power supply voltage ELVDD may be transmitted to the first node N1 through the fifth transistor T5.

[0083] In an embodiment, the data line DL may be connected to a pixel column including a plurality of pixels. When the data voltage VDAT transmitted to the pixels is changed, the voltage of the first node N1 may be changed due to the coupling effect of the parasitic capacitor CPR formed between the data line DL and the first node N1. When the voltage of the first node N1 is changed, the voltage between the first electrode and the gate electrode of the first transistor T1 may be changed, and due to the change in the voltage between the first electrode and the gate electrode of the first transistor T1, a spot defect such as a Mura phenomenon may occur in the display device 100.

[0084] According to an embodiment, during a period other than the compensation period PC in the frame period FRM, the first power supply voltage ELVDD may be applied to the first node N1, so that the voltage of the first node N1 may be stabilized, and the voltage between the first electrode and the gate electrode of the first transistor T1 may not be changed. Accordingly, a spot defect such as a Mura phenomenon does not occur in the display device 100.

[0085] According to an embodiment, the emission period PE may include a non-emission period PNE. In the non-emission period PNE within the emission period PE, the sixth transistor T6 may be turned off in response to the emission control signal EM having a high voltage level, and the second node N2 and the fourth node N4 may be separated from each other. Accordingly, the driving current may not be provided to the light emitting element LED, and the light emitting element LED may not emit light. The brightness of the light emitted from the pixel PX1 may be controlled by controlling the ratio of the non-emission period PNE to the emission period PE. At the same time, even in the non-emission period PNE, the voltage of the first node N1 may be maintained as the first power supply voltage ELVDD, so that the voltage of the first node N1 may be stabilized.

[0086] Figures 4 to 11 is a diagram showing a method according to an embodiment of the present invention. Figure 2 Layout diagram of a pixel circuit area PXA in which a pixel circuit PXC in a pixel PX1 is disposed. Fig.12 According to the embodiment along Fig.11 2 is a cross-sectional view of the pixel circuit area PXA taken along line AA′.

[0087] In the examples and with reference to Figure 2 as well as Figures 4 to 12 The pixel circuit PXC may include a first active layer ACT1, a first gate insulating layer GI1, a first conductive layer GAT1 (hereinafter, referred to as a “first gate layer”), a second gate insulating layer GI2, a second conductive layer GAT2 (hereinafter, referred to as a “second gate layer”), a first interlayer insulating layer ILD1, a second active layer ACT2, a third gate insulating layer GI3, a third conductive layer GAT3 (hereinafter, referred to as a “third gate layer”), a second interlayer insulating layer ILD2, a fourth conductive layer SD1 (hereinafter, referred to as a “first source-drain layer”), a first through-hole insulating layer VIA1, a fifth conductive layer SD2 (hereinafter, referred to as a “second source-drain layer”) and a second through-hole insulating layer VIA2.

[0088] According to an embodiment, the substrate SUB may be a flexible substrate including an organic material. For example, the substrate SUB may include a first organic layer, a first barrier layer disposed on the first organic layer, a second organic layer disposed on the first barrier layer, and a second barrier layer disposed on the second organic layer. According to another embodiment, the substrate SUB may be a rigid substrate including glass.

[0089] In an embodiment, the buffer layer BUF may be disposed on the substrate SUB. According to an embodiment, the buffer layer BUF may include an inorganic insulating material. For example, the buffer layer BUF may include silicon oxide, silicon nitride and / or silicon oxynitride, etc.

[0090] In an embodiment, the first active layer ACT1 may be disposed on the buffer layer BUF. According to an embodiment, the first active layer ACT1 may include polysilicon. The first active layer ACT1 may include a first channel region C1, a first source region S1 and a first drain region D1 respectively located on both sides of the first channel region C1, a second channel region C2, a second source region S2 and a second drain region D2 respectively located on both sides of the second channel region C2, a fifth channel region C5, a fifth source region S5 and a fifth drain region D5 respectively located on both sides of the fifth channel region C5, a sixth channel region C6, a sixth source region S6 and a sixth drain region D6 respectively located on both sides of the sixth channel region C6, a seventh channel region C7, and a seventh source region S7 and a seventh drain region D7 respectively located on both sides of the seventh channel region C7.

[0091] According to an embodiment, the first source region S1 and the first drain region D1 may respectively correspond to the first electrode and the second electrode of the first transistor T1, the second source region S2 and the second drain region D2 may respectively correspond to the first electrode and the second electrode of the second transistor T2, the fifth source region S5 and the fifth drain region D5 may respectively correspond to the first electrode and the second electrode of the fifth transistor T5, the sixth source region S6 and the sixth drain region D6 may respectively correspond to the first electrode and the second electrode of the sixth transistor T6, and the seventh source region S7 and the seventh drain region D7 may respectively correspond to the first electrode and the second electrode of the seventh transistor T7.

[0092] In an embodiment, the first gate insulating layer GI1 may be disposed on the first active layer ACT1. According to an embodiment, the first gate insulating layer GI1 may include an inorganic insulating material. For example, the first gate insulating layer GI1 may include silicon oxide, silicon nitride, and / or silicon oxynitride, etc.

[0093] In an embodiment, the first gate layer GAT1 may be disposed on the first gate insulating layer GI1. According to an embodiment, the first gate layer GAT1 may include a conductive material. For example, the first gate layer GAT1 may include a metal and / or a metal compound, etc. The first gate layer GAT1 may include a write gate line GWL, a first gate pattern GP1, a second gate pattern GP2, and an emission control line EML.

[0094] In an embodiment, the write gate line GWL may transmit the write gate signal GW. The write gate line GWL may overlap the second channel region C2 and the seventh channel region C7. The portion of the write gate line GWL overlapping the second channel region C2 may correspond to the gate electrode of the second transistor T2, and the portion of the write gate line GWL overlapping the seventh channel region C7 may correspond to the gate electrode of the seventh transistor T7.

[0095] In an embodiment, the first gate pattern GP1 may overlap the first channel region C1. A portion of the first gate pattern GP1 overlapping the first channel region C1 may correspond to the gate electrode of the first transistor T1. In addition, the first gate pattern GP1 may correspond to the first electrode of the storage capacitor CST.

[0096] In an embodiment, the second gate pattern GP2 may overlap the fifth channel region C5. A portion of the second gate pattern GP2 overlapping the fifth channel region C5 may correspond to a gate electrode of the fifth transistor T5.

[0097] In an embodiment, the emission control line EML may transmit the emission control signal EM. The emission control line EML may overlap the sixth channel region C6. A portion of the emission control line EML overlapping the sixth channel region C6 may correspond to a gate electrode of the sixth transistor T6.

[0098] In an embodiment, the second gate insulating layer GI2 may be disposed on the first gate layer GAT1. According to an embodiment, the second gate insulating layer GI2 may include an inorganic insulating material. For example, the second gate insulating layer GI2 may include silicon oxide, silicon nitride and / or silicon oxynitride, etc.

[0099] In an embodiment, the second gate layer GAT2 may be disposed on the second gate insulating layer GI2. According to an embodiment, the second gate layer GAT2 may include a conductive material. For example, the second gate layer GAT2 may include a metal and / or a metal compound, etc. The second gate layer GAT2 may include a first initialization voltage line VINTL, a first initialization gate line GIL1, a capacitor pattern CP, and a first compensation gate line GCL1.

[0100] In an embodiment, the first initialization voltage line VINTL may transmit the first initialization voltage VINT.

[0101] In an embodiment, the first initialization gate line GIL1 may transmit the initialization gate signal GI. A portion of the first initialization gate line GIL1 overlapping the fourth channel region C4 of the second active layer ACT2 may correspond to a bottom gate electrode of the fourth transistor T4.

[0102] In an embodiment, the capacitor pattern CP may overlap the first gate pattern GP1. A portion of the capacitor pattern CP overlapping the first gate pattern GP1 may correspond to a second electrode of the storage capacitor CST.

[0103] In an embodiment, the first compensation gate line GCL1 may transmit the compensation gate signal GC. A portion of the first compensation gate line GCL1 overlapping the third channel region C3 of the second active layer ACT2 may correspond to a bottom gate electrode of the third transistor T3.

[0104] In an embodiment, the capacitor pattern CP may be disposed between the first compensation gate line GCL1 and the first initialization gate line GIL1 when viewed in a plan view. In other words, the first compensation gate line GCL1 may be spaced apart from the first initialization gate line GIL1 when viewed in a plan view with the capacitor pattern CP interposed therebetween.

[0105] In an embodiment, the first interlayer insulating layer ILD1 may be disposed on the second gate layer GAT2. According to an embodiment, the first interlayer insulating layer ILD1 may include an inorganic insulating material. For example, the first interlayer insulating layer ILD1 may include silicon oxide, silicon nitride, and / or silicon oxynitride, etc.

[0106] In an embodiment, the second active layer ACT2 may be disposed on the first interlayer insulating layer ILD1. According to an embodiment, the second active layer ACT2 may include an oxide semiconductor. The second active layer ACT2 may include a third channel region C3, a third source region S3 and a third drain region D3 located at both sides of the third channel region C3, respectively, a fourth channel region C4, and a fourth source region S4 and a fourth drain region D4 located at both sides of the fourth channel region C4, respectively.

[0107] According to an embodiment, the third source region S3 and the third drain region D3 may correspond to the first and second electrodes of the third transistor T3, respectively, and the fourth source region S4 and the fourth drain region D4 may correspond to the first and second electrodes of the fourth transistor T4, respectively.

[0108] In an embodiment, the third gate insulating layer GI3 may be disposed on the second active layer ACT2. According to an embodiment, the third gate insulating layer GI3 may include an inorganic insulating material. For example, the third gate insulating layer GI3 may include silicon oxide, silicon nitride, and / or silicon oxynitride, etc.

[0109] In an embodiment, the third gate layer GAT3 may be disposed on the third gate insulating layer GI3. According to an embodiment, the third gate layer GAT3 may include a conductive material. For example, the third gate layer GAT3 may include a metal and / or a metal compound, etc. The third gate layer GAT3 may include a second initialization gate line GIL2 and a second compensation gate line GCL2.

[0110] In an embodiment, the second initialization gate line GIL2 may transmit the initialization gate signal GI. A portion of the second initialization gate line GIL2 overlapping the fourth channel region C4 of the second active layer ACT2 may correspond to a top gate electrode of the fourth transistor T4.

[0111] In an embodiment, the second compensation gate line GCL2 may transmit the compensation gate signal GC. A portion of the second compensation gate line GCL2 overlapping the third channel region C3 of the second active layer ACT2 may correspond to a top gate electrode of the third transistor T3.

[0112] In an embodiment, the second interlayer insulating layer ILD2 may be disposed on the third gate layer GAT3. According to an embodiment, the second interlayer insulating layer ILD2 may include an inorganic insulating material. For example, the second interlayer insulating layer ILD2 may include silicon oxide, silicon nitride, and / or silicon oxynitride, etc.

[0113] In an embodiment, the first source-drain layer SD1 may be disposed on the second interlayer insulating layer ILD2. According to an embodiment, the first source-drain layer SD1 may include a conductive material. For example, the first source-drain layer SD1 may include a metal and / or a metal compound, etc. The first source-drain layer SD1 may include an initialization connection pattern ICP, a data connection pattern DCP, a second initialization voltage line VAINTL, a gate connection pattern GCP, a power connection pattern PCP, a compensation connection pattern CCP, an active connection pattern ACP, and a first connection pattern CP1.

[0114] In an embodiment, the initialization connection pattern ICP may contact the first initialization voltage line VINTL and the fourth source region S4. The initialization connection pattern ICP may contact the first initialization voltage line VINTL through a first contact hole CNT1 formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, and the first interlayer insulating layer ILD1, and contact the fourth source region S4 through an eleventh contact hole CNT11 formed through the second interlayer insulating layer ILD2 and the third gate insulating layer GI3.

[0115] In an embodiment, the data connection pattern DCP may contact the second source region S2 through a second contact hole CNT2 formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, the first interlayer insulating layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0116] In an embodiment, the second initialization voltage line VAINTL may transmit the second initialization voltage VAINT. The second initialization voltage line VAINTL may contact the seventh source region S7. The second initialization voltage line VAINTL may contact the seventh source region S7 through a third contact hole CNT3 formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, the first interlayer insulating layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0117] In an embodiment, the gate connection pattern GCP may contact the first gate pattern GP1 and the third drain region D3 (or the fourth drain region D4). The gate connection pattern GCP may contact the first gate pattern GP1 through a fourth contact hole CNT4 formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, the first interlayer insulating layer ILD1, and the second gate insulating layer GI2, and contact the third drain region D3 through a twelfth contact hole CNT12 formed through the second interlayer insulating layer ILD2 and the third gate insulating layer GI3.

[0118] In an embodiment, the power connection pattern PCP may contact the capacitor pattern CP and the fifth source region S5. The power connection pattern PCP may contact the capacitor pattern CP through a fifth contact hole CNT5 formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, and the first interlayer insulating layer ILD1, and contact the fifth source region S5 through a sixth contact hole CNT6 formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, the first interlayer insulating layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0119] In an embodiment, the compensation connection pattern CCP may contact the second gate pattern GP2 and the first compensation gate line GCL1. The compensation connection pattern CCP may contact the second gate pattern GP2 through a seventh contact hole CNT7 formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, the first interlayer insulating layer ILD1, and the second gate insulating layer GI2, and contact the first compensation gate line GCL1 through an eighth contact hole CNT8 formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, and the first interlayer insulating layer ILD1.

[0120] In an embodiment, the active connection pattern ACP may contact the first drain region D1 (or the sixth source region S6) and the third source region S3. The active connection pattern ACP may contact the first drain region D1 through a ninth contact hole CNT9 formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, the first interlayer insulating layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1, and contact the third source region S3 through a thirteenth contact hole CNT13 formed through the second interlayer insulating layer ILD2 and the third gate insulating layer GI3.

[0121] In an embodiment, the first connection pattern CP1 may contact the sixth drain region D6 (or the seventh drain region D7). The first connection pattern CP1 may contact the sixth drain region D6 through a tenth contact hole CNT10 formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, the first interlayer insulating layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

[0122] According to an embodiment, the gate connection pattern GCP may not overlap with the second compensation gate line GCL2. When the gate connection pattern GCP overlaps with the second compensation gate line GCL2, a parasitic capacitor may be formed between the gate connection pattern GCP and the second compensation gate line GCL2, and due to the coupling effect of the parasitic capacitor, the gate electrode of the first transistor T1 may be affected by the change of the compensation gate signal GC. However, according to an embodiment, the gate connection pattern GCP may not overlap with the second compensation gate line GCL2, so that a parasitic capacitor may not be formed between the gate connection pattern GCP and the second compensation gate line GCL2, and the gate electrode of the first transistor T1 may not be affected by the change of the compensation gate signal GC.

[0123] In an embodiment, the first through hole insulating layer VIA1 may be disposed on the first source-drain layer SD1. According to an embodiment, the first through hole insulating layer VIA1 may include an inorganic insulating material. For example, the first through hole insulating layer VIA1 may include silicon oxide, silicon nitride and / or silicon oxynitride, etc. According to another embodiment, the first through hole insulating layer VIA1 may include an organic insulating material. For example, the first through hole insulating layer VIA1 may include polyimide (PI), etc.

[0124] In an embodiment, the second source-drain layer SD2 may be disposed on the first through-hole insulating layer VIA1. According to an embodiment, the second source-drain layer SD2 may include a conductive material. For example, the second source-drain layer SD2 may include a metal and / or a metal compound, etc. The second source-drain layer SD2 may include a data line DL, a first power line PL1, and a second connection pattern CP2.

[0125] In an embodiment, the data line DL may make contact with the data connection pattern DCP. The data line DL may make contact with the data connection pattern DCP through a fourteenth contact hole CNT14 formed through the first via insulating layer VIA1.

[0126] In an embodiment, the first power line PL1 may make contact with the power connection pattern PCP. The first power line PL1 may make contact with the power connection pattern PCP through a fifteenth contact hole CNT15 formed through the first via insulating layer VIA1.

[0127] In an embodiment, the second connection pattern CP2 may contact the first connection pattern CP1. The second connection pattern CP2 may contact the first connection pattern CP1 through a sixteenth contact hole CNT16 formed through the first via insulating layer VIA1.

[0128] In an embodiment, the second through hole insulating layer VIA2 may be disposed on the second source-drain layer SD2. According to an embodiment, the second through hole insulating layer VIA2 may include an inorganic insulating material. For example, the second through hole insulating layer VIA2 may include silicon oxide, silicon nitride and / or silicon oxynitride, etc. According to another embodiment, the second through hole insulating layer VIA2 may include an organic insulating material. For example, the second through hole insulating layer VIA2 may include polyimide (PI), etc.

[0129] In an embodiment, the first electrode of the light emitting element LED may contact the second connection pattern CP2. The first electrode of the light emitting element LED may contact the second connection pattern CP2 through a seventeenth contact hole CNT17 formed through the second via insulating layer VIA2.

[0130] Fig.13 is a diagram showing a method according to an embodiment of the present invention. Figure 1 1 is a circuit diagram of another example of a pixel PX2 in the display device 100.

[0131] In the examples and with reference to Figure 1 and Fig.13 , the pixel PX2 may include a pixel circuit PXC and a light emitting element LED. The pixel circuit PXC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor CST. According to an embodiment, the pixel circuit PXC may further include a parasitic capacitor CPR. When referring to Fig.13 When describing the pixel PX2, the reference Figure 2 The components of the pixel PX1 described are substantially the same as or similar to the description of the components.

[0132] In an embodiment, the second transistor T2 may be connected between a data line DL configured to transmit a data voltage VDAT and a second node N2, and may be turned on in response to a write gate signal GW having a low voltage level. The second transistor T2 may include a first electrode connected to the data line DL, a second electrode connected to the second node N2, and a gate electrode configured to receive the write gate signal GW. The second transistor T2 may transmit the data voltage VDAT to the second node N2 in response to the write gate signal GW having a low voltage level.

[0133] In an embodiment, the third transistor T3 may be connected between the first node N1 and the third node N3 and turned on in response to the compensation gate signal GC having a high voltage level. The third transistor T3 may include a first electrode connected to the first node N1, a second electrode connected to the third node N3, and a gate electrode configured to receive the compensation gate signal GC. The third transistor T3 may connect the first node N1 to the third node N3 in response to the compensation gate signal GC having a high voltage level.

[0134] In an embodiment, a parasitic capacitor CPR may be formed between the data line DL and the second node N2. The parasitic capacitor CPR may be an unintended capacitor generated due to the overlap of the data line DL and the second node N2. When the data voltage VDAT transmitted by the data line DL is changed due to the coupling effect of the parasitic capacitor CPR, the voltage of the second node N2 may be changed.

[0135] In an embodiment, Fig.13 The operation of the pixel PX2 can be compared with the reference Figure 3 Description Figure 2 The operations of the pixel PX1 are substantially the same or similar.

[0136] Fig.14 is a block diagram showing an electronic device 1000 according to an embodiment. Fig.15 is a diagram showing a method according to an embodiment of the present invention Fig.14 FIG. 1 is a perspective view of an example in which the electronic device 1000 is implemented as a smart phone.

[0137] In the examples and with reference to Fig.14 and Fig.15 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The display device 1060 may be connected to Figure 1 The electronic device 1000 may further include a plurality of ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc. or communicating with other systems.

[0138] According to an embodiment, Fig.15 As shown in , the electronic device 1000 may be implemented as a smart phone. However, the present invention is not limited thereto, and according to another embodiment, the electronic device 1000 may be implemented as a television, a mobile phone, a video phone, a smart watch, a smart tablet, a tablet PC, a vehicle navigation system, a notebook computer, or a head-mounted display, etc.

[0139] In an embodiment, the processor 1010 may perform a specific calculation or task. According to an embodiment, the processor 1010 may be a microprocessor or a central processing unit (CPU), etc. The processor 1010 may be connected to other components through an address bus, a control bus, and a data bus, etc. According to an embodiment, the processor 1010 may also be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus. According to an embodiment, the processor 1010 may process the first image data ( Figure 1 IMD1) and control signal ( Figure 1 CNT) is provided to the display device 1060.

[0140] In an embodiment, the memory device 1020 may store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include a non-volatile memory device such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), or a ferroelectric random access memory (FRAM). The memory device 1020 may also include a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a mobile DRAM.

[0141] In an embodiment, the storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), and / or a CD-ROM, etc. The I / O device 1040 may include an input device such as a keyboard, a keypad, a touch pad, a touch screen, a mouse, and an output device such as a speaker or a printer. The power supply 1050 may supply the power required for the operation of the electronic device 1000. The display device 1060 may be connected to other components via a bus or other communication links.

[0142] In an embodiment, according to a pixel included in the display device 1060, during a frame period other than a compensation period during which a threshold voltage of the first transistor is compensated, a first power supply voltage may be applied to a first electrode of the first transistor through a fifth transistor based on a compensation gate signal, so that a voltage of the first electrode of the first transistor may be stabilized. Accordingly, a spot defect does not occur in the display device 1060, and the image quality of the display device 1060 may be improved.

[0143] According to an embodiment, the present invention may be applied to a display device included in a computer, a notebook, a mobile phone, a smart phone, a smart tablet, a PMP, a PDA, an MP3 player, or the like.

[0144] Although the display device according to the embodiment has been described with reference to the accompanying drawings, the illustrated embodiment is only an example, and a person of ordinary skill in the relevant technical field may modify and change it without departing from the spirit of the present invention. Accordingly, the present invention should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be comprehensive and complete, and will fully convey the scope of the present invention to those skilled in the art. Moreover, although the present invention has been specifically shown and described with reference to the embodiments of the present invention, a person of ordinary skill in the art will understand that various changes can be made in form and detail without departing from the spirit and scope of the present invention. In addition, embodiments or parts of embodiments may be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A display device, comprising: Multiple pixels, Wherein, each of the plurality of pixels comprises: a first transistor connected between the first node and the second node and including a gate electrode connected to a third node; a second transistor connected between a data line and the first node and comprising a gate electrode configured to receive a write gate signal, wherein the data line is configured to transmit a data voltage; a third transistor connected between the second node and the third node and comprising a gate electrode configured to receive a compensation gate signal; a fourth transistor connected between a first initialization voltage line and the third node and comprising a gate electrode configured to receive an initialization gate signal, wherein the first initialization voltage line is configured to transmit a first initialization voltage; a fifth transistor connected between a first power line and the first node and comprising a gate electrode configured to receive the compensation gate signal, wherein the first power line is configured to transmit a first power supply voltage; a sixth transistor connected between the second node and a fourth node and including a gate electrode configured to receive an emission control signal; a storage capacitor connected between the third node and the first power line; and The light emitting element is connected between the fourth node and a second power line configured to transmit a second power voltage.

2. The display device according to claim 1, wherein: a frame period during which any one of the plurality of pixels is driven includes an initialization period during which the fourth transistor is turned on in response to the initialization gate signal, a compensation period during which the third transistor is turned on in response to the compensation gate signal, and an emission period during which the sixth transistor is turned on in response to the emission control signal, and Wherein, during a period other than the compensation period in the frame period, the first power supply voltage is applied to the first node.

3. The display device according to claim 1, wherein: The third transistor is an N-type transistor, and The fifth transistor is a P-type transistor.

4. The display device according to any one of claims 1 to 3, wherein: Each of the plurality of pixels further includes a parasitic capacitor formed between the data line and the first node.

5. A display device, comprising: Multiple pixel circuits, Wherein, each of the plurality of pixel circuits comprises: A first active layer is disposed on the substrate and includes a first channel region, a second channel region, a fifth channel region, and a sixth channel region; a first conductive layer, disposed on the first active layer, and comprising a first gate pattern overlapping the first channel region, a write gate line overlapping the second channel region, a second gate pattern overlapping the fifth channel region, and an emission control line overlapping the sixth channel region; a second conductive layer disposed on the first conductive layer and comprising a capacitor pattern overlapping the first gate pattern, a first compensation gate line configured to transmit a compensation gate signal, and a first initialization gate line configured to transmit an initialization gate signal; a second active layer disposed on the second conductive layer and comprising a third channel region overlapping the first compensation gate line and a fourth channel region overlapping the first initialization gate line; a third conductive layer disposed on the second active layer and comprising a second compensation gate line overlapping the third channel region and a second initialization gate line overlapping the fourth channel region; and A fourth conductive layer is disposed on the third conductive layer and includes a gate connection pattern contacting the first gate pattern and a third drain region of the second active layer located between the third channel region and the fourth channel region, and a compensation connection pattern contacting the second gate pattern and the first compensation gate line.

6. The display device according to claim 5, wherein: The gate connection pattern does not overlap the second compensation gate line.

7. The display device according to claim 5 or 6, wherein: When viewed in a plan view, the capacitor pattern is disposed between the first compensation gate line and the first initialization gate line.

8. A display device, comprising: Multiple pixels, Wherein, each of the plurality of pixels comprises: a first transistor connected between the first node and the second node and including a gate electrode connected to a third node; a second transistor connected between a data line and the second node and comprising a gate electrode configured to receive a write gate signal, wherein the data line is configured to transmit a data voltage; a third transistor connected between the first node and the third node and comprising a gate electrode configured to receive a compensation gate signal; a fourth transistor connected between a first initialization voltage line and the third node and comprising a gate electrode configured to receive an initialization gate signal, wherein the first initialization voltage line is configured to transmit a first initialization voltage; a fifth transistor connected between a first power line and the first node and comprising a gate electrode configured to receive the compensation gate signal, wherein the first power line is configured to transmit a first power supply voltage; a sixth transistor connected between the second node and a fourth node and including a gate electrode configured to receive an emission control signal; a storage capacitor connected between the third node and the first power line; and The light emitting element is connected between the fourth node and a second power line configured to transmit a second power voltage.

9. The display device according to claim 8, wherein: a frame period during which any one of the plurality of pixels is driven includes an initialization period during which the fourth transistor is turned on in response to the initialization gate signal, a compensation period during which the third transistor is turned on in response to the compensation gate signal, and an emission period during which the sixth transistor is turned on in response to the emission control signal, and Wherein, during a period other than the compensation period in the frame period, the first power supply voltage is applied to the first node.

10. The display device according to claim 8 or 9, wherein: The third transistor is an N-type transistor, and The fifth transistor is a P-type transistor.

Images