Memory device and method of operating memory device

Abstract

The invention relates to a memory device and a method of operating the memory device. The memory device includes: a plurality of memory planes each including a plurality of memory banks, the plurality of memory planes being grouped into memory planes sharing at least one peripheral circuit to constitute one or more plane groups; a plurality of compression circuits connected to the plurality of memory banks, respectively, and outputting compressed data by compressing data read from the plurality of memory banks, respectively; a plurality of first merging circuits receiving the compressed data corresponding to at least a portion of the banks and the output control signal, and outputting first merged data obtained by merging the compressed data corresponding to the banks grouped into a first merged group; a second merging circuit that outputs second merged data obtained by merging the first merged data generated from the banks included in the same plane group; and an output buffer circuit that outputs the second merged data based on at least a portion of the output control signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0102845 filed on August 7, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to a memory device and a method of operating a memory device. Background Art

[0004] The data read in the memory device can be transmitted to the input / output pad via the data line. Due to physical limitations, the number of data lines can be fixed to a predetermined number. Typically, multiple memory areas (memory banks) included in one or more memory devices can share and use a fixed number of data lines.

[0005] Generally, the operation of sharing and using data lines may refer to an operation in which a plurality of memory areas included in one or more memory devices monopolize using a fixed number of data lines in a set order at a set time by time division.

[0006] However, in a specific operation mode such as a compressed read operation, the data read in each of the multiple memory areas included in one or more memory devices can be compressed and output, and the multiple memory areas included in the one or more memory devices can use a certain number of data lines obtained by dividing a fixed number of data lines for each of the multiple memory areas. Therefore, the multiple memory areas included in the one or more memory devices can be used at the same time. For example, when the data read in each of four memory devices is compressed by 1 / 4 and then output, each of the four memory devices uses two data lines obtained by dividing eight data lines for each of the four memory devices. Therefore, the four memory devices can be used at the same time. Summary of the invention

[0007] According to an embodiment of the present disclosure, a memory device includes: a plurality of memory planes, each memory plane including a plurality of memory banks, the plurality of memory planes being grouped into memory planes that share at least one peripheral circuit to constitute one or more plane groups; a plurality of compression circuits, respectively connected to the plurality of memory banks, and configured to output compressed data by respectively compressing data read from the plurality of memory banks in a compression read operation; a plurality of first merging circuits, configured to receive compressed data corresponding to at least a portion of the memory banks and output control signals, and configured to output first merged data obtained by merging compressed data corresponding to the memory banks grouped into a first merged group based on the output control signals; a second merging circuit, configured to receive the first merged data from the first merging circuits, and configured to output second merged data obtained by merging the first merged data generated from the memory banks included in the same plane group; and an output buffer circuit, configured to latch the second merged data, and configured to output the second merged data based on at least a portion of the output control signals.

[0008] According to another embodiment of the present disclosure, a method for operating a memory device includes: generating compressed data obtained by respectively compressing data read from a plurality of memory bodies respectively included in a plurality of memory planes; performing a first merge on the compressed data respectively corresponding to the memory bodies grouped into a first merge group based on an output control signal corresponding to at least a portion of the memory bodies; performing a second merge on the first merged data respectively generated from the memory bodies included in the same second merge group among the first merged data obtained by performing the first merge; and outputting the second merged data obtained by performing the second merge based on at least a portion of the output control signal, wherein the plurality of memory planes are grouped into memory planes sharing at least one peripheral circuit to constitute one or more plane groups, and wherein the second merge group is grouped into memory bodies included in the same plane group. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments will now be described more fully below with reference to the accompanying drawings; however, the embodiments may be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, example embodiments are provided to enable the present disclosure to those skilled in the art.

[0010] In the accompanying drawings, dimensions may be exaggerated for clarity of illustration. It should be understood that when an element is referred to as being "between" two elements, it may be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals refer to the same elements throughout.

[0011] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0012] Figure 2 It is shown Figure 1 A diagram of a first combining circuit is shown.

[0013] Figure 3 It is shown Figure 1 A diagram of a second merging circuit and an output buffer circuit is shown.

[0014] Figure 4 It shows the direction Figure 1 The illustrated memory device provides a diagram of a clock signal generator and a clock signal conditioner for a clock signal.

[0015] Figure 5 It is shown by Figure 4 The clock signal generator and clock signal conditioner shown provide an illustration of an embodiment of a clock signal.

[0016] Figure 6 It is shown by Figure 4 The clock signal generator and clock signal conditioner shown provide an illustration of another embodiment of a clock signal.

[0017] Figure 7 is a timing diagram illustrating output of data when an unregulated clock signal is provided to a memory device according to an embodiment of the present disclosure.

[0018] Figure 8 is a timing diagram illustrating output of data when an adjusted clock signal is provided to a memory device according to an embodiment of the present disclosure.

[0019] Fig. 9 It is shown Figure 3 Schematic diagram of the data merging circuit shown.

[0020] Fig.10 It is shown Fig. 9 A diagram of an example of a multiplexing circuit is shown.

[0021] Fig.11 It is shown Fig.10 Graph of an example of signals used in .

[0022] Fig.12 The present invention is a diagram showing an embodiment of the present invention. Fig. 9 A diagram of a normal read operation of the data merge circuit shown.

[0023] Fig.13 It is shown Fig.12 A diagram of an example of a multiplexing circuit is shown.

[0024] Fig.14 Another embodiment of the present disclosure is shown in FIG. Fig. 9A diagram of a normal read operation of the data merge circuit shown.

[0025] Fig.15 It is shown Fig.14 A diagram of an example of a multiplexing circuit is shown.

[0026] Fig.16 The present invention is a diagram showing an embodiment of the present invention. Fig. 9 A diagram of the compressed read operation of the data merge circuit shown.

[0027] Fig.17 It is shown Fig.16 A diagram of an example of a multiplexing circuit is shown.

[0028] Fig.18 It is shown Figure 1 A block diagram of another embodiment of a memory device is shown.

[0029] Fig.19 is a block diagram illustrating a storage device including a memory device according to an embodiment of the present disclosure.

[0030] Fig. 20 It is shown Fig.19 A diagram of another embodiment of a memory controller is shown.

[0031] Fig.21 is a flowchart illustrating an operating method of a memory device according to an embodiment of the present disclosure.

[0032] Fig. 22 is a flowchart illustrating a process of providing a clock signal to each of memory banks in an operating method of a memory device according to an embodiment of the present disclosure.

[0033] Fig.23 is a flowchart illustrating an operation of a second merging circuit in an operating method of a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] The specific structural and functional descriptions disclosed herein are illustrative only, for the purpose of describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0035] Some embodiments relate to a memory device and a method for operating the memory device, which can reduce or prevent a merge failure that may occur during a data merge process when performing a compressed read operation.

[0036] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0037] Reference Figure 1 , the memory device 1000 may include a plurality of memory banks 1100. Each memory bank 1100 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells. Memory cells connected to the same word line may be defined as a page. Therefore, a memory block may include a plurality of pages.

[0038] In an embodiment, the memory bank 1100 may be memory regions respectively included in different memory devices. In another embodiment, the memory bank 1100 may be different memory regions divided in one memory device.

[0039] exist Figure 1 , it is shown that the memory device 1000 includes eight memory banks 1100 BK0 to BK3 and BK0' to BK3'. However, the number of memory banks 1100 is not limited thereto. For example, the number of memory banks 1100 may be two or more, and may be less than or more than Figure 1 In another example, the number of memory banks 1100 may be 16 or 32.

[0040] In an embodiment, a plurality of memory banks 1100 may be included in the memory plane 1110. For example, the zeroth plane may include memory bank 0BK0 and memory bank 1BK1, the first memory plane may include memory bank 2BK2 and memory bank 3BK3, the second memory plane may include memory bank 0'BK0' and memory bank 1'BK1', and the third memory plane may include memory bank 2'BK2' and memory bank 3'BK3'.

[0041] Among the memory planes 1110, the memory planes 1110 that share at least one peripheral circuit may be grouped to form at least one plane group 1130. For example, the zeroth memory plane 1110 including the memory bank 0BK0 and the memory bank 1BK1 and the first memory plane 1110 including the memory bank 2BK2 and the memory bank 3BK3 may share a peripheral circuit, and thus, the zeroth memory plane and the first memory plane may be grouped into the zeroth plane group 1130. In addition, the second memory plane 1110 including the memory bank 0'BK0' and the memory bank 1'BK1' and the third memory plane 1110 including the memory bank 2'BK2' and the memory bank 3'BK3' may share a peripheral circuit, and thus, the second memory plane and the third memory plane may be grouped into the first plane group 1130.

[0042] In an embodiment, the memory banks 1100 that are physically adjacent to each other may be grouped to form a first merge group 1120. Data output from the memory banks 1100 included in one first merge group 1120 may be merged into the first merged data 1120. st In an embodiment, the memory banks 1100 that are physically adjacent to each other may be grouped to constitute a first merge group 1120. In an embodiment, the memory banks 1100 included in the same plane group 1130 and included in different memory planes 1110 may be grouped to constitute a first merge group 1120. In an embodiment, each of the plane groups 1130 may include a plurality of first merge groups 1120.

[0043] In an embodiment, the memory banks 1100 that are physically adjacent to each other may be grouped to form a second merge group 1140. More specifically, the first merge groups 1120 that are physically adjacent to each other may be grouped to form a second merge group 1140. Data output from the memory banks 1100 included in one second merge group 1140 may be merged into the second merged data 2 nd In an embodiment, the second merge group 1140 may be configured with the memory banks 1100 included in the same plane group 1130, and each of the plane groups 1130 may include at least one second merge group 1140. In an embodiment, as Figure 1 As shown, since one second merge group 1140 includes one plane group 1130, the plane group 1130 and the second merge group 1140 may be the same, but the present disclosure is not limited thereto. In another embodiment, one plane group 1130 may include two or more second merge groups 1140. In an embodiment, the memory bank 1100 included in one first merge group 1120 is included in the same second merge group 1140, but may be included in different memory planes 1110.

[0044] In this specification, under the assumption that the memory banks 1100 included in one plane group 1130 are continuously arranged, the memory banks 1100 that are physically adjacent to each other may be determined only according to the relative distances between the memory banks 1100. That is, in Figure 1 , it is shown that the compression circuit 1200, the first merging circuit 1300, etc. are located between the memory planes 1110 in one plane group 1130. However, since the peripheral circuit including the compression circuit 1200 and the first merging circuit 1300 may be located on a plane different from the plane where the memory bank 1100 is located, the peripheral circuit may not be considered when determining whether the memory banks 1100 are adjacent to each other. Figure 1, the compression circuit 1200 and the first merging circuit 1300 between the memory bank 0BK0 and the memory bank 2BK2 may be located on a plane different from the plane where the memory bank 1100 is located. Therefore, when determining whether the memory banks 1100 are adjacent without the compression circuit 1200 and the first merging circuit 1300, the memory bank 0BK0 and the memory bank 2BK2 may be adjacent memory banks 1100. Similarly, the memory bank 0'BK0' and the memory bank 2'BK2', the memory bank 1BK1 and the memory bank 3BK3, and the memory bank 1'BK1' and the memory bank 3'BK3' may be memory banks 1100 adjacent to each other.

[0045] The compression circuit 1200 may be connected to each of the memory banks 1100. The compression circuit 1200 may be enabled when the memory device 1000 performs a compression read operation. In an embodiment, the memory device 1000 may perform a compression read operation based on a command received from outside the memory device 1000. In another embodiment, the memory device 1000 may perform a compression read operation based on its own decision.

[0046] When performing a compressed read operation, first, read data R.DATA may be output from each of the memory banks 1100. The read data R.DATA may be output in response to an output control signal OUTPUT_CTR. The output control signal OUTPUT_CTR may be generated based on a provided clock signal. The clock signal may be provided from outside the memory device 1000, or may be provided from a power supply in the memory device 1000. Although Figure 1 Only output control signals OUTPUT_CTR0, OUTPUT_CTR1, OUTPUT_CTR0', and OUTPUT_CTR1' outputted from bank 0BK0, bank 1BK1, bank 0'BK0', and bank 1'BK1' are shown, but the present disclosure is not limited thereto, and all banks 1100 may output the output control signal OUTPUT_CTR, respectively.

[0047] Thereafter, read data R.DATA read from each of the memory banks 1100 may be compressed in the compression circuit 1200 connected to each of the memory banks 1100, and thus, compressed data C.DATA may be output from the compression circuit 1200. The compressed data C.DATA may also be output in response to the output control signal OUTPUT_CTR.

[0048] The compression circuit 1200 may compress the read data R.DATA at a compression ratio of 1:N, thereby generating compressed data C.DATA. Here, N may be a natural number greater than 2. For example, when it is assumed that N is 4, the compression circuit 1200 may compress the read data R.DATA at a compression ratio of 1:4 (i.e., 25%), thereby generating compressed data C.DATA. For example, when the read data R.DATA is 16 bits, 4-bit compressed data C.DATA may be output from the compression circuit 1200.

[0049] The compressed data C.DATA output from the compression circuit 1200 may be merged in the first merge circuit 1300. The first merge circuit 1300 may merge the compressed data C.DATA corresponding to different memory banks 1100. More specifically, the first merge circuit 1300 may merge the compressed data C.DATA corresponding to the memory banks 1100 included in the same first merge group 1120. For example, Figure 1 As shown, the memory bank 0BK0 and the memory bank 2BK2 may be included in one first merge group 1120, and the compressed data C.DATA0 corresponding to the memory bank 0BK0 and the compressed data C.DATA2 corresponding to the memory bank 2BK2 may be merged in the first merge circuit 1300. Likewise, the compressed data C.DATA1 corresponding to the memory bank 1BK1 and the compressed data C.DATA3 corresponding to the memory bank 3BK3, the compressed data C.DATA0' corresponding to the memory bank 0'BK0' and the compressed data C.DATA2' corresponding to the memory bank 2'BK2', and the compressed data C.DATA1' corresponding to the memory bank 1'BK1' and the compressed data C.DATA3' corresponding to the memory bank 3'BK3' may be merged in the first merge circuit 1300, respectively. That is, the first merge circuit 1300 may generate the first merge data 1 corresponding to the first merge group 1120, respectively. st M. DATA.

[0050] In an embodiment, the first merge circuit 1300 may receive the compressed data C.DATA corresponding to the memory bank 1100 in the first merge group 1120 and the output control signal OUTPUT_CTR, and merge the compressed data C.DATA corresponding to the memory bank 1100 in the first merge group 1120 using the output control signal OUTPUT_CTR. In an embodiment, the first merge circuit 1300 may latch the compressed data C.DATA corresponding to the memory bank 1100 in the first merge group 1120, and output the latched compressed data C.DATA based on the output control signal OUTPUT_CTR, thereby outputting the first merged data 1 obtained by merging the compressed data C.DATA corresponding to the memory bank 1100 in the first merge group 1120.st M. DATA.

[0051] The first merge circuit 1300 may select and use any one of the output control signals OUTPUT_CTR output from the memory bank 1100 in the first merge group 1120. For example, when C.DATA0 and C.DATA2 are merged by the first merge circuit 1300, the first merge circuit 1300 may select and use the output control signal 0OUTPUT_CTR0 output from the memory bank 0BK0 and the output control signal 2 (not shown) output from the memory bank 2BK2. Thus, the first merged data 0 1 may be output in response to the output control signal 0OUTPUT_CTR0. st M.DATA0. A method of selecting the output control signal OUTPUT_CTR is not limited to a specific example.

[0052] The first combined data outputted from the first combining circuit 1300 is st The M.DATA may be merged in the second merge circuit 1400. The second merge circuit 1400 may merge the first merged data 1 outputted from different first merge circuits 1300. st More specifically, the second merge circuit 1400 may merge the first merged data 1 generated from the memory banks 1100 included in the same second merge group 1140. st That is, the second merge circuit 1400 may merge the first merged data 1 corresponding to the memory banks 1100 respectively included in the same second merge group 1140. st M.DATA. For example, the first merged data 0 1 can be merged in the second merge circuit 1400 st M.DATA0 and first merged data 1 1 st In another example, the first merged data 0 1 may be merged in the second merge circuit 1400 st M.DATA0 and first merged data 31 st In an embodiment, the first merged data 1 generated from the same plane group 1130 may be merged in the second merge circuit 1400. st M.DATA, more specifically, the first merged data 1 corresponding to the first merged groups 1120 respectively included in the same second merged group 1140 may be merged in the second merge circuit 1400. st M.DATA, and the number of the first merge groups 1120 corresponding to the first merged data merged in the second merge circuit 1400 is not limited to a specific example.

[0053] The second merging circuit 1400 can merge the first merged data 1 st M.DATA, thereby outputting the second merged data 2 nd M.DATA. can output the second merged data 2 nd M.DATA is latched to the output buffer circuit 1500. The second merged data 2 latched to the output buffer circuit 1500 may be output based on the output control signal OUTPUT_CTR. nd The output buffer circuit 1500 may select any one of the output control signals OUTPUT_CTR respectively corresponding to the second merge groups 1140, and output the second merged data 2 in response to the selected output control signal OUTPUT_CTR. nd M.DATA. For example, if the second merged data 0 2 nd M.DATA0 is the first merged data 0 by merging 1 st M.DATA0 and first merged data 1 1 st When the second merged data 0 and 2 are obtained by M.DATA1, the output buffer circuit 1500 selects and uses the output control signal 0OUTPUT_CTR0 from the output control signal 0OUTPUT_CTR0 and the output control signal 1OUTPUT_CTR1. Therefore, the second merged data 0 and 2 can be output from the output buffer circuit 1500 in response to the output control signal 0OUTPUT_CTR0. nd M.DATA0.

[0054] The output control signal OUTPUT_CTR can be output from the memory bank 1100. The output control signal OUTPUT_CTR can be used for outputting and merging data. For example, the memory bank 1100, the compression circuit 1200, etc. can output the read data R.DATA or the compressed data C.DATA in response to the output control signal OUTPUT_CTR. In addition, the first merging circuit 1300, the output buffer circuit 1500, etc. can align and output the latched data in response to the output control signal OUTPUT_CTR, so that the output control signal OUTPUT_CTR is used to merge the data.

[0055] Figure 2 It is shown Figure 1 A diagram of a first combining circuit is shown.

[0056] Reference Figure 1 and Figure 2, the memory bank 0BK0 and the memory bank 2BK2 may be memory banks 1100 included in the same first merge group 1120. The read data 0R.DATA0 read from the memory bank 0BK0 may be compressed by the compression circuit 1200, and the compressed data 0C.DATA0 may be output from the compression circuit 1200. In addition, the read data 2R.DATA2 read from the memory bank 2BK2 may be compressed by the compression circuit 1200, and the compressed data 2C.DATA2 may be output from the compression circuit 1200.

[0057] The output control signal OUTPUT_CTR may be output together with the read data R.DATA from each of the memory banks 1100, and the read data R.DATA may be output from each of the memory banks 1100 in response to the output control signal OUTPUT_CTR. Therefore, the read data 0R.DATA0 may be output in response to the output control signal 0OUTPUT_CTR0, and the read data 2R.DATA2 may be output in response to the output control signal 2OUTPUT_CTR2.

[0058] The compressed data 0C.DATA0 and the compressed data 2C.DATA2 may be merged by the first merge circuit 1300. In an embodiment, the first merge circuit 1300 may include a D flip-flop. The compressed data 0C.DATA0 and the compressed data 2C.DATA2 may be input to the D flip-flop for latching. In an embodiment, the first merge circuit 1300 may include a number of D flip-flops corresponding to the number of bits of the data read from the memory bank 1100, but the present disclosure is not limited thereto. For example, when it is assumed that 16-bit data is read from the memory bank 1100, the first merge circuit 1300 may include 16 flip-flops. In a normal read operation, 16-bit data may be read from the memory bank 1100 to be latched into the 16 flip-flops as is. In the compression read operation, when the read data R.DATA is compressed by the compression circuit 1200 at a compression ratio of 1:2 (i.e., 50%), the 8-bit compressed data 0C.DATA0 compressed and outputted in the memory bank 0BK0 and the 8-bit compressed data 2C.DATA2 compressed and outputted in the memory bank 2BK2 may be divided to be latched into 16 flip-flops. When the read data R.DATA is compressed by the compression circuit 1200 at a compression ratio of 1:4 (i.e., 25%), the 4-bit compressed data 0C.DATA0 compressed and outputted in the memory bank 0BK0 and the 4-bit compressed data 2C.DATA2 compressed and outputted in the memory bank 2BK2 may be divided to be latched into 8 flip-flops among the 16 flip-flops, and the other 8 flip-flops may not be used.

[0059] The latched compressed data 0C.DATA0 and the latched compressed data 1C.DATA1 can be aligned and output by the output control signal OUTPUT_CTR input to the D flip-flop, so as to output the first merged data 0 1 st M.DATA0. Figure 2 , it is shown that the output control signal 0 OUTPUT_CTR0 is used as a clock signal input to the D flip-flop. However, the present disclosure is not limited thereto, and the clock signal input to the D flip-flop may be selected from the output control signal 0 OUTPUT_CTR0 and the output control signal 2 OUTPUT_CTR2. Therefore, in an embodiment, the first merging circuit 1300 may further include a signal selector for selecting the clock signal input to the D flip-flop.

[0060] Figure 3 It is shown Figure 1 Schematic diagram of the second merging circuit and the output buffer circuit shown in .

[0061] Reference Figure 1 and Figure 3 , the second merging circuit 1400 may include a data merging circuit 1410 and a signal selecting circuit 1420 .

[0062] The data merging circuit 1410 may receive and merge the first merged data 1 outputted from the plurality of first merging circuits 1300. st In an embodiment, the data merging circuit 1410 may merge the first merged data 1 generated from the memory banks 1100 included in the same second merge group 1140. st That is, the data merging circuit 1410 may merge the first merged data 1 corresponding to the first merged groups 1120 respectively included in the same second merged group 1140. st M.DATA. For example, the data merging circuit 1410 may merge the first merged data 0 1 st M.DATA0 and first merged data 1 1 st M.DATA1, thereby outputting the second combined data 0 2 nd M.DATA0, and can merge the first merged data 2 1 st M.DATA2 and first merged data 3 1 st M.DATA3, thereby outputting the second combined data 1 2 nd M.DATA1.

[0063] In an embodiment, the data merging circuit 1410 may include one or more multiplexing circuits, and the first merged data 1 1 input to the data merging circuit 1410 stM.DATA can be combined by the multiplexing circuit to output as the second combined data 2 nd M. DATA.

[0064] The signal selection circuit 1420 may receive the output control signal OUTPUT_CTR outputted from the memory bank 1100. When the memory device 1000 performs a compression read operation, the signal selection circuit 1420 may select and output a portion of the received output control signal OUTPUT_CTR. In an embodiment, the signal selection circuit 1420 may select the first merged data 1 merged with the data merge circuit 1410. st One of the output control signals OUTPUT_CTR corresponding to M.DATA.

[0065] For example, Figure 3 As shown, the data merging circuit 1410 can merge the first merged data 0 1 st M.DATA0 and first merged data 1 1 st M.DATA1, thereby outputting the second combined data 0 2 nd M.DATA0, and can merge the first merged data 2 1 st M.DATA2 and first merged data 3 1 st M.DATA3, thereby outputting the second combined data 1 2 nd M.DATA1. First merged data 0 1 st M.DATA0 to first merged data 3 1 st M.DATA3 may be output from the first merging circuit 1300 in response to output control signals 0 OUTPUT_CTR0 , 0 ′ OUTPUT_CTR0 ′, 1 OUTPUT_CTR1 , and 1 ′ OUTPUT_CTR1 ′, respectively.

[0066] The signal selection circuit 1420 may receive the output control signals 0OUTPUT_CTR0, 0'OUTPUT_CTR0', 1OUTPUT_CTR1, and 1'OUTPUT_CTR1'. In an embodiment, the signal selection circuit 1420 may select and output any one of the output control signal 0OUTPUT_CTR0 and the output control signal 1OUTPUT_CTR1, and may select and output any one of the output control signal 0'OUTPUT_CTR0' and the output control signal 1'OUTPUT_CTR1'. For example, Figure 3As shown, output control signal 0 OUTPUT_CTR0 may be selected from output control signal 0 OUTPUT_CTR0 and output control signal 1 OUTPUT_CTR1, and output control signal 0 ' OUTPUT_CTR0 ' may be selected from output control signal 0 ' OUTPUT_CTR0 ' and output control signal 1 ' OUTPUT_CTR1 '.

[0067] When the memory device 1000 performs a normal read operation, the signal selection circuit 1420 does not simultaneously receive the output control signal 0 OUTPUT_CTR0 and the output control signal 1 OUTPUT_CTR1 or the output control signal 0 ' OUTPUT_CTR0 ' and the output control signal 1 ' OUTPUT_CTR1 '. Therefore, the signal selection circuit 1420 can output the received output control signal OUTPUT_CTR as it is. In addition, although Figure 3 Although not shown in the figure, the signal selection circuit 1420 may further receive an output control signal OUTPUT_CTR outputted from the bank 2, the bank 2', the bank 3, and the bank 3'.

[0068] The second merged data 2 merged and output by the data merging circuit 1410 may be nd M.DATA and the output control signal OUTPUT_CTR selected by the signal selection circuit 1420 are provided to the output buffer circuit 1500. The output buffer circuit 1500 may include an output control circuit 1510 and a latch group 1520.

[0069] The latch group 1520 may include a plurality of latches, and the second merged data 2 outputted from the second merge circuit 1400 may be nd M.DATA may be latched to a plurality of latches. The output control circuit 1510 may provide a data output control signal DOUT_CTR to the latch group 1520 based on the output control signal OUTPUT_CTR received from the second merge circuit 1400. More specifically, the output control circuit 1510 may provide a data output control signal DOUT_CTR to the latch group 1520 based on the output control signal OUTPUT_CTR selected by the signal selection circuit 1420. The second merged data latched to the latch group 1520 may be output in response to the data output control signal DOUT_CTR.

[0070] Figure 4 It shows the direction Figure 1 The illustrated memory device provides a diagram of a clock signal generator and a clock signal conditioner for a clock signal.

[0071] Reference Figure 1 and Figure 4, the memory device 1000 may further include a clock signal generator 1600 and a clock signal regulator 1700. The clock signal generator 1600 may output a clock signal CLK to be provided to the memory body 1100. In an embodiment, the clock signal generator 1600 may generate a clock signal by using an internal power supply of the memory device 1000 or a power supply external to the memory device 1000. In another embodiment, the clock signal generator 1600 may provide a clock signal provided from outside the memory device 1100 to the memory body 1100. Figure 4 , for convenience of description, it is shown that the clock signal CLK is provided to one plane group 1130. However, the clock signal CLK may be provided to all plane groups 1130 included in the memory device 1000. In an embodiment, the clock signal CLK provided to all plane groups 1130 may be the same clock signal CLK output from the same clock signal generator 1600. In another embodiment, the clock signals CLK provided to different plane groups 1130 may be clock signals CLK output from different clock signal generators 1600, respectively.

[0072] The clock signal adjuster 1700 may adjust the clock signal CLK output from the clock signal generator 1600 and provide the adjusted clock signal CLK′ to at least a portion of the memory bank 1100 .

[0073] Each of the memory banks 1100 may generate an output control signal OUTPUT_CTR based on the received clock signals CLK and CLK', and output the output control signal OUTPUT_CTR together with the read data R.DATA. When the clock signal CLK output from the clock signal generator 1600 is provided to each of the memory banks 1100, a phase difference is generated between the input clock signals according to the physical distance difference between the paths from the clock signal generator 1600 to the respective memory banks 1100, and therefore, a phase difference is also generated between the output control signals OUTPUT_CTR output from the respective memory banks 1100. When the phase difference between the output control signals OUTPUT_CTR is too large, a failure may occur when the data is merged, and therefore, the clock signal adjuster 1700 may adjust at least a portion of the clock signal CLK provided to the memory banks 1100 to reduce the phase difference between the output control signals OUTPUT_CTR. Therefore, the clock signal adjuster 1700 may provide the adjusted clock signal CLK' to the memory banks 1000.

[0074] In an embodiment, the clock signal adjuster 1700 may adjust the clock signal according to whether the compressed read operation is enabled. For example, when the compressed read operation is not enabled, that is, when a normal read operation is being performed, the clock signal adjuster 1700 may provide the clock signal CLK output from the clock signal generator 1600 to the memory bank 1100 as is. When the compressed read operation is enabled, the clock signal adjuster 1700 may adjust the clock signal CLK output from the clock signal generator 1600, and provide the adjusted clock signal to the memory bank 1100 to perform the compressed read operation. Therefore, the clock signal adjuster 1700 may receive a compressed read enable signal indicating whether the compressed read operation is enabled, and adjust the clock signal based on the compressed read enable signal.

[0075] Figure 5 It is shown by Figure 4 The clock signal generator and clock signal conditioner shown provide an illustration of an embodiment of a clock signal.

[0076] Reference Figure 4 and Figure 5 , the clock signal adjuster 1700 may adjust the clock signal provided to the memory bank 0BK0 among the plurality of memory banks 1100 based on the compression read mode enable signal ESS_EN. For example, when the compression read mode enable signal ESS_EN indicates that the compression read operation has not been enabled, the clock signal CLK0 output from the clock signal generator 1600 may be provided to the memory bank 0BK0 as is. When the compression read mode enable signal ESS_EN indicates that the compression read operation has been enabled, the clock signal CLK0′ adjusted by the clock signal adjuster 1700 may be provided to the memory bank 0BK0. In an embodiment, the clock signal adjuster 1700 may include a multiplexing circuit for selecting and outputting the clock signal CLK0 or the adjusted clock signal CLK0′ according to the compression read mode enable signal ESS_EN.

[0077] In an embodiment, in order to delay the clock signal provided to the memory bank 0BK0, the circuit in the clock signal regulator 1700 may be designed so that the clock signal CLK output from the clock signal generator 1600 is provided to the memory bank 0BK0 after passing through an additional path. Figure 5As shown, the circuit in the clock signal regulator 1700 can be designed so that the clock signal CLK0' output from the clock signal generator 1600 is transmitted in the direction toward the memory bank 1BK1, and then returned in the direction toward the memory bank 0BK0 and provided to the memory bank 0BK0. Therefore, the delayed clock signal CLK0' can be input to the multiplexing circuit, and the clock signal CLK0 or the delayed clock signal CLK0' can be provided to the memory bank 0BK0 according to the compressed read mode enable signal ESS_EN.

[0078] exist Figure 5 , it is shown that only the clock signal provided to the memory bank 0BK0 among the plurality of memory banks 1100 is adjusted. However, the present disclosure is not limited thereto, and if necessary, the number and position of the memory banks 1100 to which the clock signal adjuster 1700 can provide the adjusted clock signal may be appropriately changed.

[0079] Figure 6 It is shown by Figure 4 The clock signal generator and clock signal conditioner shown provide an illustration of another embodiment of a clock signal.

[0080] Reference Figure 4 and Figure 6 , the clock signal adjuster 1700 may adjust the clock signal provided to the memory bank 0BK0 among the plurality of memory banks 1100 based on the compression read mode enable signal ESS_EN. For example, when the compression read mode enable signal ESS_EN indicates that the compression read operation has not been enabled, the clock signal CLK0 output from the clock signal generator 1600 may be provided to the memory bank 0BK0 as is. When the compression read mode enable signal ESS_EN indicates that the compression read operation has been enabled, the clock signal CLK0′ adjusted by the clock signal adjuster 1700 may be provided to the memory bank 0BK0. In an embodiment, the clock signal adjuster 1700 may include a multiplexing circuit for selecting and outputting the clock signal CLK0 or the adjusted clock signal CLK0′ according to the compression read mode enable signal ESS_EN.

[0081] In an embodiment, in order to delay the clock signal provided to the memory bank 0BK0, the clock signal regulator 1700 may include a delay unit. The delay unit may receive the clock signal CLK output from the clock signal generator 1600, delay the received clock signal CLK for a certain time, and then output the delayed clock signal. Therefore, the delayed clock signal CLK0' may be input to the multiplexing circuit, and the clock signal CLK0 or the delayed clock signal CLK0' may be provided to the memory bank 0BK0 according to the compression read mode enable signal ESS_EN.

[0082] exist Figure 6 , it is shown that only the clock signal provided to the memory bank 0BK0 among the plurality of memory banks 1100 is adjusted. However, the present disclosure is not limited thereto, and if necessary, the number and position of the memory banks 1100 to which the clock signal adjuster 1700 can provide the adjusted clock signal may be appropriately changed.

[0083] Figure 7 is a timing diagram illustrating output of data when an unregulated clock signal is provided to a memory device according to an embodiment of the present disclosure.

[0084] Reference Figure 1 , Figure 4 and Figure 7 , clock signals 0CLK0 and 1CLK1 may be provided to the memory banks 0BK0 and 1BK1, respectively, and the memory banks 0BK0 and 1BK1 may generate output control signals OUTPUT_CTR0 and OUTPUT_CTR1 based on the clock signals 0CLK0 and 1CLK1. Read data R.DATA0 and R.DATA1 output from the memory banks 0BK0 and 1BK1 may be output in synchronization with the output control signals OUTPUT_CTR0 and OUTPUT_CTR1, respectively, and compressed data C.DATA0 and C.DATA1 output from the compression circuit 1200 connected to the memory banks 0BK0 and 1BK1 may also be output in synchronization with the output control signals OUTPUT_CTR0 and OUTPUT_CTR1, respectively.

[0085] Although the same clock signal CLK output from the clock signal generator 1600 is provided to each of the memory banks 1100, the phases of the clock signals CLK0 and CLK1 input to the respective memory banks 1100 may be different from each other according to the physical distance difference between the paths from the clock signal generator 1600 to the respective memory banks 1100. Since the memory bank 1100 generates the output control signal OUTPUT_CTR based on the clock signals CLK0 and CLK1 input to the respective memory banks 1100, a phase difference occurs between the output control signals OUTPUT_CTR0 and OUTPUT_CTR1 output from the memory bank 1100, and thus, a difference also occurs between the output timings of the compressed data C.DATA0 and C.DATA1. Therefore, the first merged data 1 obtained by merging the compressed data, respectively, st M.DATA0 and 1 st There may be output timing differences between M.DATA1. In particular, the first merged data 1 st M.DATA0 and 1 st The output timing difference between M.DATA1 may further increase according to the difference between the paths from the memory bank 1100 to the output unit, in which the first merged data 1st M.DATA0 and 1 st M.DATA1 is output to the second merging circuit 1400 .

[0086] Therefore, when the first merged data 1 st M.DATA0 and 1 st When the phase difference between M.DATA1 becomes larger, the second merger in the second merger circuit 1400 may fail. Therefore, the phase of the clock signal input to each memory bank 1100 is adjusted by the clock signal adjuster 1700, so that the first merger data 1 can be adjusted. st M.DATA0 and 1 st The output timing of M.DATA1 reduces the first merged data 1 st M.DATA0 and 1 st Phase difference between M.DATA1.

[0087] Figure 8 is a timing diagram illustrating output of data when an adjusted clock signal is provided to a memory device according to an embodiment of the present disclosure.

[0088] Reference Figures 4 to 6 and Figure 8 , the clock signal adjuster 1700 may delay the clock signal CLK0 output from the clock signal generator 1600 to provide the delayed clock signal CLK0′ to the memory bank 0BK0. The clock signal CLK1 output from the clock signal generator 1600 may be provided to the memory bank 1BK1 as it is.

[0089] The memory banks 0BK0 and 1BK1 may generate output control signals based on the clock signals 0'CLK0' and 1CLK1, and may output the read data R.DATA0 and R.DATA1 and the compressed data C.DATA0 and C.DATA1 in synchronization with the output control signals. The output timing of the compressed data C.DATA0 and C.DATA1 may have a difference corresponding to the phase difference between the clock signals 0'CLK0' and 1CLK1.

[0090] The first merging circuit 1300 may output the first merged data 1 by merging the compressed data C.DATA0 and C.DATA1 with other compressed data C.DATA2 and C.DATA3, respectively. st M.DATA0 and 1 st M.DATA1, and first merge data 1 st M.DATA0 and 1 stThe output timing of M.DATA1 may become the same according to the difference between the paths from the memory bank 1100 to the output unit, in which the first merged data 1 st M.DATA0 and 1 st M.DATA1 is output to the second merging circuit 1400 .

[0091] That is, when the phase of the clock signal input to each memory bank 1100 is adjusted by the clock signal adjuster 1700, the first merged data 1 st M.DATA0 and 1 st The phase difference between M.DATA1 is reduced, and thus, a second merging failure that may occur in the second merging circuit 1400 may be mitigated, reduced, or prevented.

[0092] Fig. 9 It is shown Figure 3 Schematic diagram of the data merging circuit shown.

[0093] Reference Figure 1 , Figure 3 and Fig. 9 , the data merging circuit 1410 may include a plurality of multiplexing circuits 1410a and 1410b. Each of the plurality of multiplexing circuits 1410a and 1410b may include a first channel unit CH1 or CH1' and a second channel unit CH2 or CH2', to which data generated from a plurality of first merging groups 1120 included in any one of the second merging groups 1140 in any one of the plane groups 1130 are input, respectively. In addition, each of the plurality of multiplexing circuits 1410a and 1410b may include a third channel unit CH3 or CH3', to which data generated from a first merging group 1120 included in any one of the second merging groups 1140 in another plane group 1130 are input. Each of the first channel unit CH1 or CH1', the second channel unit CH2 or CH2', and the third channel unit CH3 or CH3' may include one or more channels.

[0094] Each of the plurality of multiplexing circuits 1410a and 1410b may enable at least a portion selected from the group consisting of a first channel unit CH1 or CH1', a second channel unit CH2 or CH2', and a third channel unit CH3 or CH3' based on at least one signal selected from the group consisting of a compression read enable signal and a plane group selection signal. More specifically, each of the plurality of multiplexing circuits 1410a and 1410b may enable at least a portion of one or more channels included in the first channel unit CH1 or CH1', one or more channels included in the second channel unit CH2 or CH2', and one or more channels included in the third channel unit CH3 or CH3' based on at least one signal selected from the group consisting of a compression read enable signal and a plane group selection signal. In an embodiment, the compression read enable signal may indicate whether a compression read operation is enabled, and the plane group selection signal may be a plane group indicating a plane group to be selected among a plurality of plane groups.

[0095] In addition, each of the multiplexing circuits 1410a and 1410b can receive data input from an enabled channel and output data DATA0 or DATA1 based on the input data. Depending on whether the compression read operation is enabled, the output data DATA0 or DATA1 can be normal read data or second merged data 2 nd M. DATA.

[0096] In an embodiment, the first channel unit CH1 or CH1' may be a channel to which normal read data output from a plane group connected to the first channel unit CH1 or CH1' is input when the compression read operation is disabled, that is, in a normal read operation. Therefore, in a normal read operation, at least a portion of the channels included in the first channel unit CH1 or CH1' may be enabled according to a plane group selection signal.

[0097] In addition, the first channel unit CH1 or CH1′ may be a first merged data 1 generated from a plane group connected to the first channel unit CH1 or CH1′ when the compression read operation is enabled, that is, in the compression read operation. st The channel to which M.DATA is input. Therefore, in the compression read operation, at least a portion of the channels included in the first channel unit CH1 or CH1' may be enabled.

[0098] In an embodiment, the second channel unit CH2 or CH2′ may be a first merged data unit generated from a plane group connected to the second channel unit CH2 or CH2′ when the compression read operation is enabled, that is, in the compression read operation. st The channel to which M.DATA is input. Therefore, in the compression read operation, at least a portion of the channels included in the second channel unit CH2 or CH2' may be enabled.

[0099] In an embodiment, the channel unit CH3 or CH3' may be a channel to which normal read data output from a plane group connected to the third channel unit CH3 or CH3' is input when the compression read operation is disabled, that is, in a normal read operation. Therefore, in a normal read operation, at least a portion of the channels included in the channel unit CH3 or CH3' may be enabled according to a plane group selection signal.

[0100] For example, the multiplexing circuit 1410a may include a first channel unit CH1 connected to the zeroth plane group 1430, and the first channel unit CH1 may receive data generated from the first merge group 1120 including the memory banks 0BK0 and 2BK2. In addition, the multiplexing circuit 1410a may include a second channel unit CH2 connected to the zeroth plane group 1430, and the second channel unit CH2 may receive data generated from the first merge group 1120 including the memory banks 1BK1 and 3BK3. In addition, the multiplexing circuit 1410a may include a third channel unit CH3 connected to the first plane group 1430, and the third channel unit CH3 may receive data generated from the first merge group 1120 including the memory banks 0'BK0' and 2'BK2'.

[0101] For example, the multiplexing circuit 1410b may include a first channel unit CH1' connected to the first plane group 1430, and the first channel unit CH1' may receive data generated from the first merge group 1120 including the memory bank 1'BK1' and the memory bank 3'BK3'. In addition, the multiplexing circuit 1410b may include a second channel unit CH2' connected to the first plane group 1430, and the second channel unit CH2' may receive data generated from the first merge group 1120 including the memory bank 0'BK0' and the memory bank 2'BK2'. In addition, the multiplexing circuit 1410b may include a third channel unit CH3' connected to the zeroth plane group 1430, and the third channel unit CH3' may receive data generated from the first merge group 1120 including the memory bank 1BK1 and the memory bank 3BK3.

[0102] Fig.10 It is shown Fig. 9 A diagram of an example of a multiplexing circuit is shown.

[0103] Reference Figure 1 , Figure 3 , Fig. 9 and Fig.10, the multiplexing circuits 1410a and 1410b may include a plurality of multiplexers, and the multiplexers may select and output a portion of the input data based on signals ESS_EN, SEL_ESSO, and SEL_ESSX obtained by combining a compression read enable signal and a plane group selection signal.

[0104] In an embodiment, the multiplexing circuit 1410a may include a channel unit CH1 connected to the zeroth plane group 1430, and the first channel unit CH1 may include a channel GDL_B02[7:0] receiving 0-bit to 7-bit data from the first merge group 1120 including the memory banks 0BK0 and 2BK2, and a channel GDL_B02[15:8] receiving 8-bit to 15-bit data from the first merge group 1120 including the memory banks 0BK0 and 2BK2. In addition, the multiplexing circuit 1410a may include a second channel unit CH2 connected to the zeroth plane group 1430, and the second channel unit CH2 may include a channel GDL_B13[7:0] receiving 0-bit to 7-bit data from the first merge group 1120 including the memory banks 1BK1 and 3BK3. In addition, the multiplexing circuit 1410a may include a third channel unit CH3 connected to the first plane group 1430, and the third channel unit CH3 may include a channel GDL_B0'2'[7:0] receiving 0-bit to 7-bit data from the first merging group 1120 including the memory banks 0'BK0' and 2'BK2', and a channel GDL_B0'2'[15:8] receiving 8-bit to 15-bit data from the first merging group 1120 including the memory banks 0'BK0' and 2'BK2'.

[0105] In an embodiment, the multiplexing circuit 1410a may select and enable one channel from the channel GDL_B02[7:0] included in the first channel unit CH1 and the channel GDL_B0'2'[7:0] included in the third channel unit CH3 based on the compression read enable signal and the plane group selection signal. The data input from the enabled channel may be output through the 0th to 7th bit zero output line GDL0[7:0]. In addition, in an embodiment, the multiplexing circuit 1410a may select and enable one channel from the channel GDL_B02[15:8] included in the first channel unit CH1, the channel GDL_B0'2'[15:8] included in the third channel CH3, and the channel GDL_B13[7:0] included in the second channel unit CH2 based on the compression read enable signal and the plane group selection signal. The data input from the enabled channel may be output through the 8th to 15th bit zero output line GDL0[15:8].

[0106] In an embodiment, the multiplexing circuit 1410b may include a first channel unit CH1' connected to the first plane group 1430, and the first channel unit CH1' may include a channel GDL_B1'3'[7:0] receiving 0-bit to 7-bit data from the first merge group 1120 including the memory banks 1'BK1' and 3'BK3', and a channel GDL_B1'3'[15:8] receiving 8-bit to 15-bit data from the first merge group 1120 including the memory banks 1'BK1' and 3'BK3'. In addition, the multiplexing circuit 1410b may include a second channel unit CH2' connected to the first plane group 1430, and the second channel unit CH2' may include a channel GDL_B0'2'[7:0] receiving 0-bit to 7-bit data from the first merge group 1120 including the memory banks 0'BK0' and 2'BK2'. In addition, the multiplexing circuit 1410b may include a third channel unit CH3' connected to the zeroth plane group 1430, and the third channel unit CH3' may include a channel GDL_B13[7:0] receiving 0-bit to 7-bit data from the first merging group 1120 including the memory cells 1BK1 and 3BK3, and a channel GDL_B13[15:8] receiving 8-bit to 15-bit data from the first merging group 1120 including the memory cells 1BK1 and 3BK3.

[0107] In an embodiment, the multiplexing circuit 1410b may select and enable one channel from among the channel GDL_B1'3'[7:0] included in the first channel unit CH1' and the channel GDL_B13[7:0] included in the third channel unit CH3' based on the compression read enable signal and the plane group selection signal. The data input from the enabled channel may be output through the 0-bit to 7-bit first output line GDL1[7:0]. In addition, in an embodiment, the multiplexing circuit 1410b may select and enable one channel from among the channel GDL_B1'3'[15:8] included in the first channel unit CH1', the channel GDL_B1'3'[15:8] included in the third channel unit CH3', and the channel GDL_B0'2'[7:0] included in the second channel unit CH2' based on the compression read enable signal and the plane group selection signal. The data input from the enabled channel may be output through the 8-bit to 15-bit first output line GDL1[15:8].

[0108] Fig.11 It is shown Fig.10 Graph of an example of signals used in .

[0109] Reference Fig.10 and Fig.11, the compression read enable signal ESS_EN and the plane group selection signal SEL_PLG may be input to the multiplexing circuits 1410a and 1410b, or signals SEL_ESSO and SEL_ESSX obtained by combining the compression read enable signal ESS_EN and the plane group selection signal SEL_PLG may be input to the multiplexing circuits 1410a and 1410b.

[0110] For example, the signal SEL_ESSO may be a signal obtained by performing an AND operation on the compression read enable signal ESS_EN and the inverted value ESS_EN_N of the plane group selection signal SEL_PLG. In addition, the signal SEL_ESSX may be a signal obtained by performing an OR operation on the compression read enable signal ESS_EN and the plane group selection signal SEL_PLG.

[0111] For example, when the compressed read operation is enabled, the value of the compressed read enable signal ESS_EN may be 1. When the compressed read operation is disabled, the value of the compressed read enable signal ESS_EN may be 0. In addition, when the zeroth plane group is selected, the value of the plane group selection signal SEL_PLG may be 1. When the first plane group is selected, the value of the plane group selection signal SEL_PLG may be 1. Since no specific plane group is selected in the compressed read operation, both the first plane group and the second plane group are selected, and therefore, the value of the plane group selection signal SEL_PLG may be 1.

[0112] Fig.12 The present invention is a diagram showing an embodiment of the present invention. Fig. 9 A diagram of a normal read operation of the data merge circuit shown.

[0113] Reference Figure 1 , Fig. 9 and Fig.12 , the memory device 1000 may perform a normal read operation on the zeroth plane group 1130. Therefore, the compression read enable signal ESS_EN may indicate disabling the compression read operation (ie, indicating a normal read operation), and the plane group selection signal SEL_PLG may indicate the zeroth plane group 1130.

[0114] In an embodiment, based on the compression read enable signal ESS_EN and the plane group selection signal SEL_PLG, the multiplexing circuit 1410 a may enable at least a portion of channels included in the first channel unit CH1 and disable channels included in the second and third channel units CH2 and CH3 .

[0115] Therefore, normal data N.DATA0 (B02) may be input from the first merge group 1120 including the bank 0BK0 and the bank 2BK2 in the zeroth plane group through the enabled channel in the first channel unit CH1 and may be output from the multiplexing circuit 1410a.

[0116] In an embodiment, based on the compression read enable signal ESS_EN and the plane group selection signal SEL_PLG, the multiplexing circuit 1410 b may enable at least a portion of channels included in the third channel unit CH3 ′ and disable the first channel unit CH1 ′ and the second channel unit CH2 ′.

[0117] Therefore, normal data N.DATA1 (B13) may be input from the first merge group 1120 including the memory bank 1BK1 and the memory bank 3BK3 in the zeroth plane group through an enabled channel in the third channel unit CH3' and may be output from the multiplexing circuit 1410b.

[0118] Fig.13 It is shown Fig.12 A diagram of an example of a multiplexing circuit is shown.

[0119] Reference Figure 1 and Figures 9 to 13 In an embodiment, when a normal read operation is performed on the zeroth plane group 1130, the value of the compression read enable signal ESS_EN may be 0, and the value of the plane group selection signal SEL_PLG may be 0. Therefore, according to an AND operation of the compression read enable signal ESS_EN and the inverted value ESS_EN_N of the plane group selection signal SEL_PLG, the value of the signal SEL_ESSO may be 0. In addition, according to an OR operation of the compression read enable signal ESS_EN and the plane group selection signal SEL_PLG, the value of the signal SEL_ESSX may be 0.

[0120] In an embodiment, the multiplexing circuit 1410a may enable the channel GDL_B02[7:0] included in the first channel unit CH1 according to the signal SEL_ESSO. The data input from the enabled channel GDL_B02[7:0] may be output through the 0th to 7th bit zeroth output line GDL0[7:0]. In addition, in an embodiment, the multiplexing circuit 1410a may enable the channel GDL_B02[15:8] included in the first channel unit CH1 according to the compression read enable signal ESS_EN and the signal SEL_ESSO. The data input from the enabled channel GDL_B02[15:8] may be output through the 8th to 15th bit zeroth output line GDL0[15:8].

[0121] In an embodiment, the multiplexing circuit 1410b may enable the channel GDL_B13[7:0] included in the third channel unit CH3' according to the signal SEL_ESSX. The data input from the enabled channel GDL_B13[7:0] may be output through the 0th to 7th bit zeroth output line GDL1[7:0]. In addition, in an embodiment, the multiplexing circuit 1410b may enable the channel GDL_B13[15:8] included in the third channel unit CH3' according to the signal SEL_ESSX. The data input from the enabled channel GDL_B13[15:8] may be output through the 8th to 15th bit first output line GDL1[15:8].

[0122] Fig.14 Another embodiment of the present disclosure is shown in FIG. Fig. 9 A diagram of a normal read operation of the data merge circuit shown.

[0123] Reference Figure 1 , Fig. 9 and Fig.14 , the memory device 1000 may perform a normal read operation on the first plane group 1130. Therefore, the compression read enable signal ESS_EN may indicate disabling the compression read operation (ie, indicating a normal read operation), and the plane group selection signal SEL_PLG may indicate the first plane group 1130.

[0124] In an embodiment, based on the compression read enable signal ESS_EN and the plane group selection signal SEL_PLG, the multiplexing circuit 1410 a may enable at least a portion of channels included in the third channel unit CH3 and disable channels included in the first and second channel units CH1 and CH2 .

[0125] Therefore, normal data N.DATA2 (B0'2') may be input from the first merge group 1120 including memory banks 0'BK0' and 2'BK2' in the first plane group through an enabled channel in the third channel unit CH3 and may be output from the multiplexing circuit 1410a.

[0126] In an embodiment, based on the compression read enable signal ESS_EN and the plane group selection signal SEL_PLG, the multiplexing circuit 1410 b may enable at least a portion of channels included in the first channel unit CH1 ′ and disable the second channel unit CH2 ′ and the third channel unit CH3 ′.

[0127] Therefore, normal data N.DATA3 (B1'3') may be input from the first merge group 1120 including bank 1'BK1' and bank 3'BK3' in the first plane group through an enabled channel in the third channel unit CH3' and may be output from the multiplexing circuit 1410b.

[0128] Fig.15 It is shown Fig.14 A diagram of an example of a multiplexing circuit is shown.

[0129] Reference Figure 1 , 9 11, 14, and 15, in an embodiment, when a normal read operation is performed on the first plane group 1130, the value of the compression read enable signal ESS_EN may be 0, and the value of the plane group selection signal SEL_PLG may be 1. Therefore, according to an AND operation of the compression read enable signal ESS_EN and the inverted value ESS_EN_N of the plane group selection signal SEL_PLG, the value of the signal SEL_ESSO may be 1. In addition, according to an OR operation of the compression read enable signal ESS_EN and the plane group selection signal SEL_PLG, the value of the signal SEL_ESSX may be 1.

[0130] In an embodiment, the multiplexing circuit 1410a may enable the channel GDL_B0'2'[7:0] included in the third channel unit CH3 according to the signal SEL_ESSO. The data input from the enabled channel GDL_B0'2'[7:0] may be output through the 0th to 7th bit zeroth output line GDL0[7:0]. In addition, in an embodiment, the multiplexing circuit 1410a may enable the channel GDL_B0'2'[15:8] included in the third channel unit CH3 according to the compression read enable signal ESS_EN and the signal SEL_ESSO. The data input from the enabled channel GDL_B0'2'[15:8] may be output through the 8th to 15th bit zeroth output line GDL0[15:8].

[0131] In an embodiment, the multiplexing circuit 1410b may enable the channel GDL_B1'3'[7:0] included in the first channel unit CH1' according to the signal SEL_ESSX. The data input from the enabled channel GDL_B1'3'[7:0] may be output through the 0th to 7th bit zeroth output line GDL1[7:0]. In addition, in an embodiment, the multiplexing circuit 1410b may enable the channel GDL_B1'3'[15:8] included in the first channel unit CH1' according to the signal SEL_ESSX. The data input from the enabled channel GDL_B1'3'[15:8] may be output through the 8th to 15th bit first output line GDL1[15:8].

[0132] Fig.16 The present invention is a diagram showing an embodiment of the present invention. Fig. 9 A diagram of the compressed read operation of the data merge circuit shown.

[0133] Reference Figure 1 , Fig. 9 and Fig.16 , the memory device 1000 may perform a compression read operation on the first and second plane groups 1130. Therefore, the compression read enable signal ESS_EN may indicate that the compression read operation is enabled, and the plane group selection signal SEL_PLG may indicate that the first and second plane groups 1130 have been selected.

[0134] In an embodiment, based on the compression read enable signal ESS_EN and the plane group selection signal SEL_PLG, the multiplexing circuit 1410a may enable at least a portion of channels included in the first channel unit CH1 and at least a portion of channels included in the second channel unit CH2, and disable channels included in the third channel unit CH3.

[0135] Therefore, the first merged data 1 generated from the memory banks BK0 to BK3 in the zeroth plane group may be input through the enabled channels in the first channel unit CH1 and the second channel unit CH2, respectively. st M.DATA0 and 1 st M.DATA1. The first merged data 1 can be input st M.DATA0 and 1 st M.DATA1 is merged to form the second merged data 2 nd M.DATA0 is output from the multiplexing circuit 1410a.

[0136] In an embodiment, based on the compression read enable signal ESS_EN and the plane group selection signal SEL_PLG, the multiplexing circuit 1410b may enable at least a portion of channels included in the first channel unit CH1' and at least a portion of channels included in the second channel unit CH2', and disable channels included in the third channel unit CH3'.

[0137] Therefore, the first merged data 1 generated from the memory banks BK0′ to BK3′ in the first plane group may be input through the enabled channels in the first channel unit CH1′ and the second channel unit CH2′, respectively. st M.DATA2 and 1 st M.DATA3. The first merged data 1 can be input st M.DATA2 and 1 st M.DATA3 is merged to form the second merged data 2 ndM.DATA1 is output from the multiplexing circuit 1410b.

[0138] Fig.17 It is shown Fig.16 A diagram of an example of a multiplexing circuit is shown.

[0139] Reference Figure 1 , Figures 9 to 11 , Fig.14 , Fig.15 and Fig.17 In an embodiment, when a compression read operation is performed on a plurality of plane groups 1130, the value of the compression read enable signal ESS_EN may be 1, and the value of the plane group selection signal SEL_PLG may be 1. Therefore, according to an AND operation of the compression read enable signal ESS_EN and the inverted value ESS_EN_N of the plane group selection signal SEL_PLG, the value of the signal SEL_ESSO may be 0. In addition, according to an OR operation of the compression read enable signal ESS_EN and the plane group selection signal SEL_PLG, the value of the signal SEL_ESSX may be 1.

[0140] In an embodiment, the multiplexing circuit 1410a may enable the channel GDL_B02[7:0] included in the first channel unit CH1 according to the signal SEL_ESSO. The data input from the enabled channel GDL_B02[7:0] may be output through the 0th to 7th bit zeroth output line GDL0[7:0]. In addition, in an embodiment, the multiplexing circuit 1410a may enable the channel GDL_B13[7:0] included in the second channel unit CH2 according to the compression read enable signal ESS_EN and the signal SEL_ESSO. The data input from the enabled channel GDL_B13[7:0] may be output through the 8th to 15th bit zeroth output line GDL0[15:8].

[0141] In an embodiment, the multiplexing circuit 1410b may enable the channel GDL_B1'3'[7:0] included in the first channel unit CH1' according to SEL_ESSX. The data input from the enabled channel GDL_B1'3'[7:0] may be output through the 0-bit to 7-bit first output line GDL1[7:0]. In addition, in an embodiment, the multiplexing circuit 1410b may enable the channel GDL_B0'2'[15:8] included in the second channel unit CH2' according to the compression read enable signal ESS_EN and the signal SEL_ESSX. The data input from the enabled channel GDL_B0'2'[15:8] may be output through the 8-bit to 15-bit first output line GDL1[15:8].

[0142] Therefore, each of the multiplexing circuits 1410a and 1410b may merge and output the first merged data 1 corresponding to the different first merged groups 1120 included in the same plane group 1130. st More specifically, each of the multiplexing circuits 1410a and 1410b may merge and output first merged data 1 corresponding to different first merged groups 1120 included in the same second merged group 1140. st M. DATA.

[0143] As reference Figures 10 to 14 As described above, the memory device according to the embodiment of the present disclosure can perform a compressed read operation without significantly changing the design of an existing memory device that performs a normal read operation, and alleviate, reduce or minimize the merge failure that may occur during the data merge process when performing a compressed read operation.

[0144] Fig.18 It is shown Figure 1 A block diagram of another embodiment of a memory device is shown.

[0145] Reference Fig.18 , the memory device 100 may include a memory cell array 110 , a voltage generator 120 , an address decoder 130 , an input / output circuit 140 , and a control logic 150 .

[0146] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz may be connected to the address decoder 130 via row lines RL. The plurality of memory blocks BLK1 to BLKz may be connected to the input / output circuit 140 via column lines CL. In an embodiment, the row lines RL may include word lines, source selection lines, and drain selection lines. In an embodiment, the column lines may include bit lines.

[0147] Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells.

[0148] In any one of the plurality of memory blocks BLKi, a plurality of word lines arranged in parallel to each other may be connected between a first selection line and a second selection line. The first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. More specifically, the memory block BLKi may include a plurality of strings ST connected between the bit lines BL1 to BLn and the source line SL. The bit lines BL1 to BLn may be connected to the string ST, respectively, and the source line SL may be connected to the string ST in common. The strings ST may be configured identically to each other, and therefore, the string ST connected to the first bit line BL1 is described in detail as an example.

[0149] The string ST may include a source selection transistor SST, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST connected in series with each other between a source line SL and a first bit line BL1. At least one source selection transistor SST and at least one drain selection transistor DST may be included in one string ST, and the number of memory cells included in one string ST may be greater than the number of memory cells MC1 to MC16 shown in the figure.

[0150] The source of the source select transistor SST may be connected to the source line SL, and the drain of the drain select transistor DST may be connected to the first bit line BL1. The memory cells MC1 to MC16 may be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST may be connected to the source select line SSL, and the gates of the drain select transistors DST included in different strings ST may be connected to the drain select line DSL. The gates of the memory cells MC1 to MC16 may be connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings ST may be referred to as a physical page PPG. Therefore, a physical page PPG corresponding in number to the number of word lines WL1 to WL16 may be included in the memory block BLKi.

[0151] Each of the memory cells may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0152] The SLC can store one bit of data. One physical page PPG of the SLC can store one logical page of data. One logical page of data can include a number of data bits corresponding to the number of cells included in one physical page PPG.

[0153] MLC, TLC and QLC can store two or more bits of data. One physical page PPG can store two or more logical pages of data.

[0154] The memory cell array 110 may be configured with a plurality of memory banks including a plurality of memory blocks. Figure 1 The memory cell array 110 may include a plurality of memory planes, and each of the memory planes may include a plurality of memory banks.

[0155] In an embodiment, the voltage generator 120, the address decoder 130, and the input / output circuit 140 may be collectively referred to as a peripheral circuit. The peripheral circuit may drive the memory cell array 110 under the control of the control logic 150. The peripheral circuit may drive the memory cell array 110 to perform programming operations, read operations, and erase operations. Memory planes that share peripheral circuits among multiple planes may be grouped to form a plane group. In an embodiment, the plane group may include one or more second merged groups configured with adjacent storage bodies, and each of the second merged groups may include one or more first merged groups configured with adjacent storage bodies. In an embodiment, each of the first merged groups may include storage bodies included in different memory planes.

[0156] The voltage generator 120 may generate a plurality of operating voltages by using an external power supply voltage provided to the memory device 100. The voltage generator 120 may operate under the control of the control logic 150.

[0157] In an embodiment, the voltage generator 120 may generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generator 120 may be used as an operating voltage of the memory device 100.

[0158] In an embodiment, the voltage generator 120 may generate a plurality of operating voltages using an external power supply voltage or an internal power supply voltage. The voltage generator 120 may generate various voltages required in the memory device 100. For example, the voltage generator 120 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of non-select read voltages.

[0159] To generate a plurality of operating voltages having different voltage levels, the voltage generator 120 may include a plurality of pumping capacitors receiving an internal power supply voltage. The voltage generator 120 may generate a plurality of operating voltages by selectively enabling the plurality of pumping capacitors under the control of the control logic 150.

[0160] A plurality of operating voltages generated by the voltage generator 120 may be provided to the memory cell array 110 by the address decoder 130 .

[0161] The address decoder 130 may be connected to the memory cell array 110 through a row line RL. The address decoder 130 may operate under the control of the control logic 150. The address decoder 130 may receive an address ADDR from the control logic 150. The address decoder 130 may decode a block address in the received address ADDR. The address decoder 130 may select at least one memory block from among a plurality of memory blocks BLK1 to BLKi according to the decoded block address. The address decoder 130 may decode a row address in the received address ADDR. The address decoder 130 may select at least one word line from among the word lines of the selected memory block according to the decoded row address. In an embodiment, the address decoder 130 may decode a column address in the received address ADDR. The address decoder 130 may connect the input / output circuit 140 and the memory cell array 110 to each other according to the decoded column address.

[0162] The address decoder 130 may include components such as a row decoder, a column decoder, and an address decoder.

[0163] The input / output circuit 140 may include a plurality of page buffers. The plurality of page buffers may be connected to the memory cell array 110 through bit lines. In a programming operation, data may be stored in a selected memory cell according to data stored in the plurality of page buffers. In a read operation, data stored in a selected memory cell may be sensed through a bit line, and the sensed data may be stored in a page buffer.

[0164] The input / output circuit 140 may include a plurality of compression circuits. The compression circuits may be connected to a plurality of page buffers. More specifically, each of the compression circuits may be connected to a page buffer, which is connected to a memory bank corresponding thereto. The compression circuits may be connected to a plurality of page buffers. Figure 1 When a compression read operation is performed under the control of the control logic 150, the compression circuit may compress and output data read from the memory cell array 110.

[0165] The input / output circuit 140 may include a plurality of first merging circuits and a second merging circuit. The first merging circuit may be connected to two or more compression circuits, and the second merging circuit may be connected to two or more first merging circuits. The first merging circuit and the second merging circuit may be connected to Figure 1The first merging circuit 1300 and the second merging circuit 1400 described in the embodiment are the same. The first merging circuit may merge and output data output from the compression circuit, and the second merging circuit may merge and output data output from the first merging circuit. More specifically, the first merging circuit may merge compressed data corresponding to the memory banks grouped into the above-mentioned first merging group, and the second merging circuit may merge first merged data corresponding to the first merging group grouped into the above-mentioned second merging group.

[0166] The input / output circuit 140 may further include a clock signal generator and a clock signal regulator. In an embodiment, the clock signal generator may generate a clock signal using a voltage generated by the voltage generator 120, or may generate a clock signal using a voltage received from outside the memory device 100. Alternatively, in another embodiment, the clock signal generator may provide a clock signal received from outside the memory cell array 110. The clock signal regulator may regulate a clock signal output from the clock signal generator under the control of the control logic 150. In an embodiment, when a compression read operation is performed under the control of the control logic 150, the clock signal regulator may regulate a clock signal output from the clock signal generator. The clock signal generator and the clock signal regulator may be used together with Figure 4 The clock signal generator 1600 and the clock signal adjuster 1700 described in are the same.

[0167] The control logic 150 may control the address decoder 130, the voltage generator 120, and the input / output circuit 140. The control logic 150 may operate in response to a command CMD transmitted from an external device. The control logic 150 may control the peripheral circuit by generating various signals in response to the command CMD and the address ADDR. The control logic 150 may control the peripheral circuit so that the memory device 100 performs a normal read operation or a compressed read operation. The control logic 150 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 150 may be a control logic circuit operating according to an algorithm and / or a processor running a control logic code.

[0168] Fig.19 is a block diagram illustrating a storage device including a memory device according to an embodiment of the present disclosure.

[0169] Reference Fig.19, the storage device 50 may include a memory device 100 and a memory controller 200. The storage device 50 may be a device that stores data under the control of a host such as a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system. Alternatively, the storage device 50 may be a device that stores data under the control of a host that is used to store large amounts of data in one place (e.g., a server or a data center).

[0170] The memory device 50 may be manufactured as any of various types of memory devices according to a host interface as a communication scheme with a host. In addition, the memory device 50 may be manufactured as any of various package types.

[0171] The memory device 100 may store data. The memory device 100 may operate under the control of the memory controller 200. The memory device 100 may be Figure 1 or Fig.18 The memory device 1000 or 100 shown. Therefore, the memory device 100 may include: a memory cell array 110 including a plurality of memory cells; an input / output (I / O) circuit 140 connected to the memory cell array 110 and outputting data read from the memory cells; and a control logic 150 controlling a peripheral circuit. The memory cell array 110 may include a plurality of memory banks, each memory bank including a plurality of memory blocks. Each memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0172] In an embodiment, the memory device 100 may use any one of various types of volatile memory or nonvolatile memory. In this specification, for convenience of description, it is assumed and described that the memory device 100 uses a NAND flash memory.

[0173] The memory device 100 may receive a command and an address from the memory controller 200, and access an area selected by the address in the memory cell array. The memory device 100 may perform an operation indicated by a command on an area selected by an address. For example, the memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. In a programming operation, the memory device 100 may program data into an area selected by an address. In a read operation, the memory device 100 may read data from an area selected by an address. In an erase operation, the memory device 100 may erase data stored in an area selected by an address.

[0174] The memory controller 200 may control the overall operations of the memory device 50 .

[0175] The memory controller 200 may run firmware (FW) when power is supplied to the memory device 50. When the memory device 100 is a flash memory device, the memory controller 200 may run FW such as a flash translation layer (FTL) to control communication between the host and the memory device 100.

[0176] In an embodiment, the memory controller 200 may receive a logical address (LA) input from a host and convert the LA into a physical address (PA) indicating an address of a memory cell in the memory device 100 where data is to be stored or from which data is to be read.

[0177] The memory controller 200 may control the memory device 100 to perform a write operation, a read operation, an erase operation, etc. in response to a request from the host. In a program operation, the memory controller 200 may provide a write command, a PA, and data to the memory device 100. In a read operation, the memory controller 200 may provide a read command and a PA to the memory device 100. In an erase operation, the memory controller 200 may provide an erase command and a PA to the memory device 100.

[0178] In an embodiment, the memory controller 200 may autonomously generate commands, addresses, and data regardless of any request from the host, and send the commands, addresses, and data to the memory device 100. For example, the memory controller 200 may provide the memory device 100 with commands, addresses, and data for performing program operations, read operations, and erase operations accompanying when performing wear leveling, read recycling, garbage collection, etc.

[0179] In an embodiment, the memory controller 200 may control at least two memory devices 100. The memory controller 200 may control the memory devices according to an interleaving scheme to improve operation performance. The interleaving scheme may be a scheme for controlling operations on at least two memory devices 100 to overlap with each other.

[0180] In an embodiment, the memory controller 200 may include a read operation manager 210. The read operation manager 210 may control the memory device 100 to perform a compressed read operation or a normal read operation. For example, the read operation manager 210 may determine whether the memory device 100 is to perform a compressed read operation or a normal read operation, and provide a compressed read operation or a normal read operation command to the memory device 100 according to whether the memory device 100 is to perform a compressed read operation or a normal read operation. The control logic 150 may control the peripheral circuit including the I / O circuit 140 to perform a compressed read operation or a normal read operation in response to the received command. Therefore, the data read from the memory cell array 110 may be output to the memory controller 200 through the I / O circuit 140. When the memory device 100 receives a compressed read command, the I / O circuit 140 may provide the read data compressed by the compression operation to the memory controller 200. When the memory device 100 receives a normal read command, the I / O circuit 140 may provide the read data without the compression operation to the memory controller 200.

[0181] In an embodiment, a compression read operation may be performed using an efficient soft sensing (ESS) scheme. The ESS scheme may be a scheme that simultaneously compresses data of a plurality of regions in the memory cell array 110 and merges and outputs the compressed data together.

[0182] Fig. 20 It is shown Fig.19 A diagram of another embodiment of a memory controller is shown.

[0183] Reference Fig. 20 , the memory controller 2000 may include a processor 2010 , an internal memory 2020 , an error checking and correction (ECC) circuit 2030 , a host interface 2040 , a buffer memory interface 2050 , and a memory interface 2060 .

[0184] The processor 2010 may perform various calculations for controlling the memory device 100 or generate various commands. When the processor 2010 receives a request from the host 400, the processor 2010 may generate a command according to the received request and send the generated command to a queue controller (not shown). The processor 2010 may control the next operation of the memory device 100 based on the verification result received by the memory interface 2060 from the memory device 100. In an embodiment, the processor 2010 may generate a normal read command or a compressed read command.

[0185] The internal memory 2020 may store various information required for the operation of the memory controller 2000. For example, the internal memory 2020 may include a logical address and physical address mapping table.

[0186] The ECC circuit 2030 is configured to detect and correct errors of data received from the memory device 100 by using an error correction code. The processor 2010 may adjust a read voltage and control the memory device 100 to perform re-reading according to an error detection result of the ECC circuit 2030. In an embodiment, the error correction block may be provided as a component of the memory controller 2000.

[0187] The host interface 2040 may exchange commands, addresses, data, etc. between the memory controller 2000 and the host 400. For example, the host interface 2040 may receive a request, an address, data, etc. from the host 400, and output data read from the memory device 100 to the host 400. The host interface 2040 may communicate with the host 400 using various protocols.

[0188] The buffer memory interface 2050 may transfer data between the processor 2010 and the buffer memory. The buffer memory may be used as a working memory or cache memory of the memory controller 2000 and stores data used in the storage device. The buffer memory may be used by the processor 2010 as a read buffer, a write buffer, a mapping buffer, etc.

[0189] The memory interface 1060 may exchange commands, addresses, data, etc. between the memory controller 2000 and the memory device 100. For example, the memory interface 2060 may send commands, addresses, data, etc. to the memory device 100 through a channel, and may receive data, etc. from the memory device 100. The memory interface 2060 may provide a compressed read command or a normal read command to the memory device 100 according to an instruction of the processor 2010. Therefore, the memory interface 2060 may receive compressed read data or normal read data from the memory device 100.

[0190] Fig.21 is a flowchart illustrating an operating method of a memory device according to an embodiment of the present disclosure.

[0191] Reference Figure 1 and Fig.21 , in operation S2101 , the compression circuit 1200 of the memory device 1000 may compress the read data R.DATA provided from the memory bank 1100 , and thus, compressed data C.DATA may be generated from the compression circuit 1200 .

[0192] In operation S2103, the first merge circuit 1300 of the memory device 1000 may merge the compressed data C.DATA based on the output control signal OUTPUT_CTR output from the memory bank 1100, and the merging of the compressed data C.DATA by the first merge circuit 1300 may be referred to as a first merge. In the first merge, the compressed data corresponding to the memory banks grouped into the first merge group 1120 may be merged. In an embodiment, the first merge group may be configured with memory banks adjacent to each other. In an embodiment, the first merge group 1120 may be configured with memory banks 1100 included in different memory planes 1110. In an embodiment, the compressed data C.DATA output from the compression circuit 1200 may be latched to the first merge circuit 1300, and the first merge data C.DATA as the latched data may be latched in response to the output control signal OUTPUT_CTR. st M.DATA is output from the first merging circuit 1300 .

[0193] In operation S2105, the second merge circuit 1400 of the memory device 1000 may merge the first merged data 1 st M.DATA, and the second merging circuit 1400 performs the first merging data 1 st The merging of M.DATA may be referred to as a second merging. In the second merging, compressed data corresponding to the memory banks grouped into the second merging group 1140 may be merged. The second merging group 1140 may be configured with a plurality of memory banks 1100 included in the same plane group 1130. The plane group 1130 is configured with a memory plane 1110 that shares a peripheral circuit, and one plane group 1130 may include one or more second merging groups 1140. In an embodiment, the second merging group 1140 may be configured with memory banks 1100 that are physically adjacent to each other. More specifically, the second merging group 1140 may be configured with the first merging groups 1120 that are physically adjacent to each other. The second merging circuit 1140 may output the first merging data 1100 obtained by merging the first merging group 1120 to the output buffer circuit 1500. st The second merged data 2 obtained by M.DATA nd M. DATA.

[0194] In operation S2107, the output buffer circuit 1500 of the memory device may merge the first merged data 1 based on the output control signal OUTPUT_CTR output from the memory bank 1100. st M.DATA. In an embodiment, the second merged data 2 outputted from the second merge circuit 1400 is ndM.DATA may be latched to the output buffer circuit 1500 , and the latched data may be output from the output buffer circuit 1500 in response to at least some of the output control signals OUTPUT_CTR selected from among the output control signals OUTPUT_CTR output from the memory bank 1100 .

[0195] Fig. 22 is a flowchart illustrating a process of providing a clock signal to each of memory banks in an operating method of a memory device according to an embodiment of the present disclosure.

[0196] Reference Figure 1 , Figure 4 and Fig. 22 , in operation S2201, a clock signal may be output from the clock signal generator 1600 of the memory device 1000. In an embodiment, the clock signal generator 1600 may generate the clock signal by using an internal power supply of the memory device 1000 or a power supply external to the memory device 1000. In another embodiment, the clock signal generator 1600 may output a clock signal provided from outside the memory device 1000.

[0197] In operation S2203, the clock signal adjuster 1700 of the memory device 1000 may check whether the compression read operation has been enabled. When the compression read operation is enabled, in operation S2205, the clock signal adjuster 1700 may adjust at least a portion of the clock signals respectively provided to the memory banks 1100. In an embodiment, the clock signal adjuster 1700 may delay the clock signal to be provided to at least a portion of the memory banks 1100. In operation S2207, the clock signal adjusted by the clock signal adjuster 1700 may be provided to the memory banks 1100.

[0198] When the compression read operation is not enabled, the clock signal adjuster 1700 may not adjust the clock signal, and in operation S2207 , may provide the unadjusted clock signal to the memory bank 1100 .

[0199] Output control signals respectively corresponding to the memory banks 1100 may be generated based on the clock signal provided to the memory banks 1100 , and data may be output from the memory banks 1100 in response to the output control signals.

[0200] Fig.23 is a flowchart illustrating an operation of a second merging circuit in an operating method of a memory device according to an embodiment of the present disclosure.

[0201] Reference Figure 1 , Fig. 9 and Fig.23In operation S2301, the second merge circuit 1400 of the memory device 1000 may check whether the compression read operation has been enabled. In an embodiment, the second merge circuit 1400 may receive a compression read enable signal indicating whether the compression read operation has been enabled, and perform operation S2301 based on the compression read enable signal.

[0202] When the compression read operation is not enabled, that is, when the normal read operation is performed, in operation S2303, the second merging circuit 1400 may enable a channel corresponding to the normal read operation. In an embodiment, the second merging circuit 1400 may enable at least a portion of the channels connected to the plane group 1130 based on a plane group selection signal indicating a plane group 1130 to be selected from among a plurality of plane groups.

[0203] In operation S2305 , the second merge circuit 1400 may receive normal read data from the selected plane group 1130 through an enabled channel and output the received normal read data.

[0204] When the compressed read operation is enabled, that is, when the compressed read operation is performed, in operation S2307, the second merge circuit 1400 may enable a channel corresponding to the compressed read operation. In an embodiment, the second merge circuit 1400 may enable at least a portion of the channels connected to the one or more plane groups 1130 based on a selection signal indicating that one or more plane groups 1130 among the plurality of plane groups 1130 are to be selected.

[0205] In operation S2309, the second merge circuit 1400 may receive the first merged data 1 from the one or more plane groups 1130 by enabling the channels. st M.DATA, and by merging the received first merged data 1 st M.DATA to output the second merged data 2 nd In an embodiment, the second merge circuit 1400 may receive the first merged data 1 from the plurality of plane groups 1130. st M.DATA, but the present disclosure is not limited thereto. In an embodiment, the first merged data 1 may be received from a plane group 1130 st M. DATA.

[0206] According to the present disclosure, a memory device and a method for operating the memory device are provided, which can alleviate, reduce or prevent a merge failure that may occur during a data merge process when performing a compressed read operation.

[0207] Although the present disclosure has been shown and described with reference to certain embodiments of the present disclosure, it will be understood by those skilled in the art that various changes may be made in form and detail without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-mentioned embodiments, but should be determined not only by the appended claims, but also by their equivalents.

[0208] In the above-mentioned embodiments, all steps may be selectively performed or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described, and the steps may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are only examples for facilitating understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it is obvious to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0209] On the other hand, some embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only used to explain the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-mentioned embodiments, but there may be many changes within the spirit and scope of the present disclosure. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may also be made based on the technical scope of the present disclosure.

Claims

1. A memory device, comprising: a plurality of memory planes, each memory plane comprising a plurality of memory banks, the plurality of memory planes being grouped into memory planes that share at least one peripheral circuit to form one or more plane groups; a plurality of compression circuits connected to the plurality of memory banks, respectively, and outputting compressed data by respectively compressing data read from the plurality of memory banks in a compression read operation; a plurality of first merging circuits that receive compressed data corresponding to at least a portion of the memory banks and an output control signal, and output first merged data obtained by merging compressed data corresponding to the memory banks grouped into a first merge group based on the output control signal; a second merge circuit that receives the first merged data from the first merge circuit and outputs second merged data obtained by merging the first merged data generated from the memory banks included in the same plane group; as well as The output buffer circuit latches the second integrated data and outputs the second integrated data based on at least a portion of the output control signal.

2. The memory device according to claim 1, wherein: Each of the one or more plane groups includes at least one second coalescing group in which memory banks physically adjacent to each other are grouped.

3. The memory device according to claim 2, wherein: The second merge circuit merges first merge data generated from memory banks included in the same second merge group.

4. The memory device according to claim 2, wherein: In the first merge group, memory banks included in the same second merge group and included in different memory planes are grouped.

5. The memory device of claim 4, further comprising: A clock signal generator, outputting a clock signal to be provided to the memory bank; as well as a clock signal adjuster that adjusts at least a portion of the clock signal based on a compression read enable signal indicating whether the compression read operation has been enabled, Wherein, the output control signal is generated based on the clock signal.

6. The memory device according to claim 5, wherein: The clock signal adjuster delays a clock signal provided to at least a portion of memory banks included in the second merge group.

7. The memory device according to claim 3, wherein: The first merged data respectively generated from the first merged groups included in the same second merged group are output from the first merged circuit in synchronization with each other.

8. The memory device according to claim 4, wherein: The second merging circuit comprises: a data merging circuit that receives the first merged data from the first merging circuit and outputs the second merged data; and The signal selection circuit selects a part of the output control signals, thereby providing the output buffer circuit with output control signals respectively corresponding to the second merging groups.

9. The memory device according to claim 8, wherein: The data merging circuit comprises: a first channel unit and a second channel unit, to which data generated from a first merged group included in any one second merged group of a first plane group among a plurality of plane groups is inputted respectively; and A third pass unit to which data generated from a first merged group included in any one second merged group in a second plane group different from the first plane group is input.

10. The memory device according to claim 9, wherein: The data merging circuit: receiving a compression read enable signal and a plane group selection signal, wherein the compression read enable signal indicates whether the compression read operation has been enabled, and the plane group selection signal indicates a plane group to be selected among the plurality of plane groups; and At least one portion selected from the group consisting of the first channel unit, the second channel unit, and the third channel unit is enabled based on at least one selected from the group consisting of the compression read enable signal and the plane group selection signal.

11. The memory device according to claim 10, wherein: When the compression read enable signal indicates that the compression read operation is disabled and the plane group selection signal indicates that the first plane group is selected, the data merge circuit enables at least a portion of the channels included in the first channel unit.

12. The memory device according to claim 10, wherein: When the compression read enable signal indicates that the compression read operation is disabled and the plane group selection signal indicates that the first plane group is selected, the data merge circuit enables at least a portion of the channels included in the third channel unit.

13. The memory device according to claim 10, wherein: When the compression read enable signal indicates enabling the compression read operation, the data merge circuit enables at least a portion of the channels included in the first channel unit and at least a portion of the channels included in the second channel unit.

14. The memory device according to claim 8, wherein: The signal selection circuit selects an output control signal corresponding to any one memory bank included in the second merging group as an output control signal corresponding to the second merging group.

15. A method of operating a memory device, comprising: generating compressed data obtained by respectively compressing data read from a plurality of memory banks respectively included in a plurality of memory planes; performing a first merging of compressed data respectively corresponding to the memory banks grouped into a first merging group based on an output control signal corresponding to at least a portion of the memory banks; performing a second merge on the first merged data respectively generated from the memory banks included in the same second merge group among the first merged data obtained by performing the first merge; as well as outputting second combined data obtained by performing the second combination based on at least a part of the output control signal, wherein the plurality of memory planes are grouped into memory planes that share at least one peripheral circuit to form one or more plane groups, and The second coalescing group is grouped into memory banks included in the same plane group.

16. The method according to claim 15, wherein: The second coalescing group includes memory banks that are physically adjacent to each other.

17. The method according to claim 16, wherein: The first merging group includes memory banks included in the same second merging group and included in different memory planes.

18. The method according to claim 16, wherein: Each of the one or more plane groups includes one or more second merged groups.

19. The method according to claim 15, further comprising: before generating the compressed data, generating a clock signal to be provided to the plurality of memory planes; as well as A clock signal to be provided to at least a portion of the plurality of memory banks is adjusted.

20. The method according to claim 19, wherein: The first merged data generated from the memory banks included in the same second merge group are output in synchronization with each other.

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