Memory device and method of performing program operation

Abstract

A three-dimensional NAND memory device includes a memory array including blocks, each block including a first memory cell and a second memory cell connected in series to a bit line, a word line driver, a first memory cell, a second memory cell, a second memory cell, a third memory cell, a fourth memory cell, a fourth memory cell, and a third memory cell. And a controller configured to control the word line driver to perform a program operation on memory cells of the first memory cells, the memory cells being controlled by a selected word line of the first word lines corresponding to the first memory cells, the first word line includes a first unselected word line adjacent to the selected word line, and performing the program operation includes: applying a program voltage signal to the selected word line to program the memory cell to a target state; applying a first pass voltage to the first unselected word line; and applying a second pass voltage to a second word line corresponding to the second memory cell.

Description

Technical Field

[0001] The present disclosure relates to memory devices and methods for programming operations. In particular, the memory devices and methods reduce unintentional soft programming of adjacent memory cells during programming operations. Background Art

[0002] Currently, the demand for memory devices with higher storage capacity continues to increase. In order to meet the demand for higher storage capacity, the number of storage layers and the number of storage bits per unit of the memory device may continue to increase. The memory device may include a memory array including blocks. Each block may include one or more memory cells, and the memory device may perform an erase operation on a block-by-block basis. Summary of the invention

[0003] Some aspects of the present disclosure relate to memory devices and methods for programming operations. For example, the memory devices and methods are provided to reduce Vpass disturbance during programming operations.

[0004] Some aspects of the present disclosure relate to a method for programming a memory device having a memory array including blocks. Each block includes a first memory cell and a second memory cell. The first memory cell and the second memory cell are connected in series to a bit line. The method includes performing a programming operation on a memory cell in the first memory cell. The memory cell is controlled by a selected word line in a first word line corresponding to the first memory cell. The first word line includes a first unselected word line adjacent to the selected word line. Performing the programming operation includes: applying a programming voltage signal to the selected word line to program the memory cell to a target state. Performing the programming operation also includes: applying a first pass voltage to the first unselected word line. Performing the programming operation also includes: applying a second pass voltage to a second word line corresponding to the second memory cell.

[0005] According to some aspects, the second pass voltage can be lower than the first pass voltage.

[0006] According to some aspects, the program operation may be performed after performing an erase operation on the first group of memory cells.

[0007] According to some aspects, the first unselected word line can be adjacent to the second word line.

[0008] According to some aspects, the second pass voltage can be adjusted based on the location of the selected word line.

[0009] According to some aspects, the position of the selected word line may be determined by the number of the first unselected word lines between the selected word line and the second word line.

[0010] According to some aspects, when there are a first number of first unselected word lines between the selected word line and the second word line, the second pass voltage can be adjusted to a third pass voltage. When there are a second number of first unselected word lines between the selected word line and the second word line, the second pass voltage can be adjusted to a fourth pass voltage different from the third pass voltage. The second number can be different from the first number.

[0011] According to some aspects, the second number can be less than the first number.The fourth pass voltage can be greater than the third pass voltage.

[0012] According to some aspects, the first word line may further include a second unselected word line adjacent to the selected word line.

[0013] According to some aspects, the first unselected word line can be on a first side of the selected word line and the second unselected word line can be on a second side of the selected word line. The first side and the second side can be opposite sides of the selected word line.

[0014] According to some aspects, performing the program operation may further include applying a fifth pass voltage to the second unselected word line. The fifth pass voltage may be less than the first pass voltage.

[0015] According to some aspects, applying the program voltage signal, applying the first pass voltage, and applying the second pass voltage may be performed substantially simultaneously.

[0016] Some aspects of the present disclosure relate to a three-dimensional (3D) NAND memory device. The 3D NAND memory device may include a memory array including blocks. Each block includes a first memory cell and a second memory cell. The first memory cell and the second memory cell are connected in series to a bit line. The 3D NAND memory device may also include a word line driver; and a controller configured to control the word line driver to perform a programming operation on a memory cell in the first memory cell. The memory cell is controlled by a selected word line in a first word line corresponding to the first memory cell. The first word line includes a first unselected word line adjacent to the selected word line. Performing the programming operation includes: applying a programming voltage signal to the selected word line to program the memory cell to a target state. Performing the programming operation also includes applying a first pass voltage to the first unselected word line. Performing the programming operation also includes: applying a second pass voltage to a second word line corresponding to the second memory cell.

[0017] According to some aspects, the second pass voltage can be lower than the first pass voltage.

[0018] According to some aspects, the program operation may be performed after performing an erase operation on the first group of memory cells.

[0019] According to some aspects, the first unselected word line can be adjacent to the second word line.

[0020] According to some aspects, the second pass voltage can be adjusted based on the location of the selected word line.

[0021] According to some aspects, the position of the selected word line may be determined by the number of the first unselected word lines between the selected word line and the second word line.

[0022] According to some aspects, when there are a first number of first unselected word lines between the selected word line and the second word line, the second pass voltage can be adjusted to a third pass voltage. When there are a second number of first unselected word lines between the selected word line and the second word line, the second pass voltage can be adjusted to a fourth pass voltage different from the third pass voltage. The second number can be different from the first number.

[0023] According to some aspects, the second number can be less than the first number.The fourth pass voltage can be greater than the third pass voltage.

[0024] This summary of the invention is provided only to illustrate some aspects, to provide an understanding of the subject matter described herein. Accordingly, the features described above are only examples and should not be understood as limiting the scope or essence of the subject matter of the present disclosure. Other features, aspects and advantages of the present disclosure will become apparent through the following detailed description, drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate the present disclosure and together with the description further serve to explain the principles of the present disclosure and enable those skilled in the relevant art to make and use the present disclosure.

[0026] Figure 1 and Figure 2A-2B A memory system having one or more memory chips according to some embodiments of the present disclosure is shown.

[0027] Figure 3 A schematic diagram of a memory device according to some embodiments is shown.

[0028] Figure 4 A schematic diagram of a memory device according to some embodiments is shown.

[0029] Figure 5 Exemplary threshold voltage distributions for memory devices according to some aspects of the present disclosure are shown.

[0030] Figure 6 An exemplary schematic circuit diagram of a memory device according to some aspects of the present disclosure is shown.

[0031] Figure 7 An exemplary process flow for performing a programming operation according to aspects of the present disclosure is shown.

[0032] Fig. 8A An exemplary configuration of a plurality of pass voltage distributions and corresponding word lines is shown in accordance with some embodiments.

[0033] Figure 8B According to some embodiments, a Fig. 8A An exemplary voltage waveform timing diagram of a memory device configured in FIG.

[0034] Fig.9A An exemplary configuration of a plurality of pass voltage distributions and corresponding word lines is shown in accordance with some embodiments.

[0035] Fig. 9B According to some embodiments, Fig.9A An exemplary voltage waveform timing diagram of a memory device configured in FIG.

[0036] The features and advantages of the present disclosure will become more apparent from the detailed description set forth below when considered in conjunction with the accompanying drawings, in which like reference numerals identify corresponding elements throughout the drawings. In the drawings, like reference numerals generally indicate identical, functionally similar, and / or structurally similar elements.

[0037] Various aspects of the present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0038] Although specific configurations and arrangements have been discussed, it should be understood that this is done for exemplary purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. Those skilled in the art will obviously recognize that the present disclosure may also be used in a variety of other applications.

[0039] It should be noted that the references to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments" and the like in the specification indicate that the described embodiments may include specific features, structures or characteristics, but not every embodiment may include the specific features, structures or characteristics. In addition, such expressions do not necessarily refer to the same embodiment. In addition, when describing specific features, structures or characteristics in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such features, structures or characteristics in conjunction with other embodiments, whether explicitly or not explicitly described.

[0040] In general, terms may be understood at least in part from their use in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, at least in part, depending on the context. Similarly, the terms "one," "an," or "the" may also be understood to convey singular use or plural use, which may depend at least in part on the context. In addition, the term "based on" may be understood to not necessarily be intended to convey an exclusive set of factors, but may allow for the presence of other factors that may not be explicitly stated, which again may depend at least in part on the context.

[0041] It should be understood that the meanings of "on...", "above..." and "over..." in the present disclosure should be interpreted in the broadest manner, so that "on..." not only means being directly on something, but also includes the meaning of having intermediate features or layers therebetween when being on something. In addition, "above..." or "on..." not only means being "above" or "on" something, but may also contain the meaning of being "above" or "on" something without any intermediate features or layers therebetween (i.e., being directly on something).

[0042] In addition, spatially relative terms, such as "below", "beneath", "lower", "above", "upper", etc., may be used herein for ease of description to describe the relationship of one element or feature to other (multiple) elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or process steps in addition to the orientation shown in the figures. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly in a similar manner.

[0043] The term "substrate" as used herein refers to the material on which subsequent material layers are added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, so unless otherwise indicated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite the top surface, so the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, for example, silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be composed of non-conductive materials such as glass, plastic, or sapphire wafers.

[0044] As used herein, the term "layer" refers to a material portion including an area with a certain thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far away from the substrate. The layer can extend within the overall range of the underlying structure or the overlying structure, or can have a range smaller than the range of the underlying structure or the overlying structure. In addition, the layer can be a region of a homogeneous or non-homogeneous continuous structure, and its thickness is less than the thickness of the continuous structure. For example, the layer can be located between any set of horizontal planes between the top surface and the bottom surface of the continuous structure, or at the top surface and the bottom surface. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, can contain one or more layers therein, and / or can have one or more layers located thereon, above it and / or below it. The layer can include multiple layers. For example, the interconnect layer can include one or more conductive layers and contact layers (in which contacts, interconnect lines and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0045] In the present disclosure, for ease of description, "level" is used to refer to elements having substantially the same height in the vertical direction. For example, a word line and an underlying gate dielectric layer may be referred to as a "level", a word line and an underlying insulating layer may be referred to as a "level" together, and each word line having substantially the same height may be referred to as a "word line level", and so on.

[0046] As used herein, the term "nominal / nominal" refers to an expected or target value for a characteristic or parameter of a component or process step set during the design phase of a product or process, together with a certain range of values ​​above and / or below the expected value. The range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term "approximately" or "roughly" refers to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "approximately" or "roughly" may refer to a value of a given quantity that varies, for example, within 10-30% of a value (e.g., ±10%, ±20%, or ±30% of a value).

[0047] In the present disclosure, the terms “horizontal / horizontally / lateral / laterally” mean nominally parallel to a lateral surface of a substrate, and the terms “vertical” or “vertically” mean nominally perpendicular to a lateral surface of a substrate.

[0048] The term "3D memory" as used herein refers to a three-dimensional (3D) semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a "memory string", e.g., a NAND string) located on a substrate having a laterally orientation such that the memory string extends in a vertical direction relative to the substrate.

[0049] The memory device may include a memory array including blocks. Each block may include one or more memory cells, and the memory device may perform an erase operation of each block. However, due to a larger number of storage layers and unit storage bits, an erase operation based on a block of a memory device may not be able to achieve a high erase speed. The block may include a plurality of vertically stacked levels or decks, such as formed by a double stacking process. Each level may include a plurality of vertically stacked memory cells. In order to achieve efficient read, write, and erase operations in a memory device having a plurality of levels, each level may be able to implement an erase operation individually. In order to increase the erase speed, the memory device may perform an erase operation based on the level of the block. For example, the memory device may perform an erase operation to erase only the upper level unit or the lower level unit, or both.

[0050] A memory device can perform a programming operation by applying a voltage, such as a programming voltage, to the memory cell to program the memory cell of the memory device. In some aspects, memory cells in the same memory block of the memory device can share the same word line (WL) and can be programmed at the same time. During the programming operation, a row decoder can select the WL associated with the memory cell to send a programming voltage signal to program the memory cell to a target state. Unselected WLs in a memory block can typically be biased to a voltage level called "Vpass" to minimize program interference on unselected cells of the memory block.

[0051] A known problem called "Vpass interference" may occur when one or more unselected cells are accidentally "soft programmed" to be associated with an unselected WL. For example, during a programming operation, a Vpass voltage may be applied to the unselected WLs of the unprogrammed cells corresponding to the programming string. At this time, the potential difference between the gate and the channel of the unprogrammed cells can form an electric field. The magnitude of the electric field may not be large enough to allow electrons to easily enter the charge trapping layer. However, due to the electric field, a certain probability (e.g., number) of electrons entering the charge trapping layer may occur, especially when the isolation performance of the tunneling layer is poor or degraded. Therefore, the unprogrammed cells may be affected by the applied Vpass voltage, which is often referred to as Vpass interference. As a result, the performance of the memory device may be affected. The memory device may need to be tested or reprogrammed to resolve the Vpass interference problem.

[0052] As described above, in order to implement efficient read, write and erase operations in a memory device having multiple levels, each level may be able to implement erase operations individually. In order to increase the erase speed, the memory device may perform an erase operation based on the level of the block. For example, the memory device may perform an erase operation to erase only the first level or upper level cell, while not performing an erase operation on the second level or lower level cell. After the erase operation of the upper level cell, the upper level cell may be programmed. Due to the erase and / or programming operation of the upper level cell, the lower level cell in the programming state may be subjected to more severe Vpass interference.

[0053] Figure 1 A block diagram of an electronic device S1 having a memory system 10 according to some embodiments is shown. In some embodiments, the electronic device S1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other electronic device having a storage device located therein. The memory system 10 (e.g., a NAND memory system) may include a memory controller 20 and one or more semiconductor memory devices 25-1, 25-2, 25-3, ... 25-n. Each semiconductor memory device 25 (hereinafter referred to as "memory device") may be a NAND device (e.g., "flash memory", "NAND flash memory", or "NAND"). The memory system 10 may communicate with a host computer 15 through the memory controller 20, wherein the memory controller 20 may be connected to one or more memory chips 25-1, 25-2, 25-3, ... 25-n via one or more memory channels 30-1, 30-2, 30-3, ... 30-n. In some implementations, each memory device 25 may be managed by the memory controller 20 via one or more memory channels 30 - 1 , 30 - 2 , 30 - 3 . . . 30 - n .

[0054] In some embodiments, the host computer 15 may include a processor of an electronic device, such as a central processing unit (CPU), or may be a system on a chip (SoC), such as an application processor (AP). The host computer 15 may send data to be stored in the memory system 10 and / or may retrieve data stored in the memory system 10.

[0055] In some embodiments, the memory controller 20 can process I / O requests received from the host computer 15, ensure data integrity and efficient storage, and manage the memory device 25. To perform these tasks, the memory controller 20 can run firmware 21, which can be executed by one or more processors 22 (e.g., microcontroller unit, CPU) of the memory controller 20. For example, the memory controller 20 can map logical addresses (e.g., addresses associated with host data used by the host) to physical addresses in the memory device 25 (e.g., the actual location where the data is stored) by running the firmware 21. The memory controller 20 also manages defective memory blocks in the memory device 25 by running the firmware 21, wherein the firmware 21 can remap logical addresses to different physical addresses, that is, move data to different physical addresses. The memory controller 20 can also include one or more memories 23 (e.g., DRAM, SRAM, EPROM, etc.) that can be used to store various metadata used by the firmware 21. In some embodiments, the memory controller 20 can also perform error recovery through an error correction code (ECC) engine 29. ECC is used to detect and correct raw bit errors that occur in each memory device 25.

[0056] In some implementations, memory channel 30 may provide data and control communications between memory controller 20 and each memory device 25 via a data bus. Memory controller 20 may select one of memory devices 25 based on a chip enable signal.

[0057] In some embodiments, Figure 1 Each memory device 25 may include one or more memory devices 100, wherein each memory device may be a NAND memory.

[0058] In some embodiments, the memory controller 20 and one or more memory devices 25 can be integrated into various types of storage devices, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 10 can be implemented and packaged into different types of final electronic products. Figure 2A In one example shown, the memory controller 20 and the single memory device 25 may be integrated into a memory card 26. The memory card 26 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 26 may further include a processor that connects the memory card 26 to a host (e.g., Figure 1A memory card connector 24 is coupled to the host computer 15 in FIG. Figure 2B In another example shown, the memory controller 20 and the plurality of memory devices 25 may be integrated into a solid state drive (SSD) 27. The SSD 27 may further include a processor that interfaces the SSD 27 with a host (e.g., Figure 1 An SSD connector 28 coupled to a host computer 15).

[0059] Figure 3 A top view of a memory device 100 is shown in accordance with some embodiments. Figure 3 The exemplary configuration shown in is given as a non-limiting example, and it should be recognized that the memory is scalable. In some embodiments, the memory device 100 may include one or more memory planes 101, and each of the memory planes 101 may include multiple memory blocks 103. The same and parallel operations can be performed at each memory plane 101. The memory block 103, which may have a size of several megabytes (MB), is the minimum size for performing an erase operation. The memory device 100 may include (for example) four memory planes 101. Each memory plane 101 may include (for example) six memory blocks 103. Each memory block 103 may include multiple memory cells, wherein each memory cell can be addressed by interconnects such as bit lines and word lines. The bit lines and word lines may be arranged perpendicular to each other (for example, in rows and columns, respectively), thereby forming an array of metal lines. In Figure 3 In FIG. 1 , the directions of the bit lines and word lines are marked as “BL” and “WL”.

[0060] In some embodiments, the memory device 100 may further include a peripheral region 105, i.e., an area surrounding the memory plane 101. The peripheral region 105 may include many digital, analog, and / or mixed signal circuits to support the functions of the memory device, such as page buffers, row and column decoders, and sense amplifiers. The peripheral circuits use active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., which will be apparent to those of ordinary skill in the art.

[0061] In some embodiments, Figure 3 The illustrated arrangement of the memory planes 101 in the memory device 100 and the arrangement of the memory blocks 103 in each memory plane 101 are merely used as examples, which do not limit the scope of the present disclosure.

[0062] Figure 4A schematic diagram of a memory device 100 according to some embodiments is shown. In some embodiments, the memory device 100 may include one or more memory blocks 103. Each memory block 103 may include a plurality of memory strings 212. Each memory string 212 includes a plurality of memory cells 340. The memory cells 340 sharing the same word line form a memory page 432. The memory string 212 may also include at each end at least one field effect transistor (e.g., MOSFET) controlled by a lower select gate (LSG) 332 and a top select gate (TSG) 334, respectively. The lower select gate (LSG) may also be referred to as a bottom select gate (BSG). The drain terminal of the top select transistor 334-T may be connected to a bit line 341, and the source terminal of the lower select transistor 332-T may be connected to an array common source (ACS) 430. The ACS 430 may be shared by the memory strings 212 within the entire memory block, and is therefore also referred to as a common source line.

[0063] In some embodiments, the memory device 100 may also include peripheral circuits, which may include a number of digital, analog, and / or mixed signal circuits to support the functions of the memory block 103, such as page buffers 52, row decoders / word line drivers 40, column decoders / bit line drivers 50, controllers 70, voltage generators 65, and input / output buffers 55. The controller 70 may include one or more control circuits. In some aspects, the controller 70 may include one or more registers, buffers, and / or memories to store one or more fine-tuning settings, as described in the present disclosure. These circuits include active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., which will be apparent to those skilled in the art.

[0064] In some embodiments, the memory block 103 may be coupled to the row decoder / word line driver 40 via a word line (WL) 333, a lower select gate (LSG) 332, and a top select gate (TSG) 334. The memory block 103 may be coupled to the page buffer 52 via a bit line (BL) 341. The row decoder / word line driver 40 may select one of the memory blocks 103 on the memory device 100 in response to an X-path control signal provided by the controller 70. The row decoder / word line driver 40 may transfer a voltage provided from the voltage generator 65 to the word line according to the X-path control signal. During read and program operations, the row decoder / word line driver 40 may select a read voltage V according to the X-path control signal received from the controller 70. read and programming voltage V pgm is transmitted to the selected word line, and the pass voltage Vpass is transmitted to the unselected word lines.

[0065] In some embodiments, the column decoder / bit line driver 50 can transmit the inhibit voltage V to the unselected bit lines according to the Y path control signal received from the controller 70. inhibit And the selected bit line is connected to ground. In other words, the column decoder / bit line driver 50 can be configured to select or deselect one or more memory strings 212 according to the Y path control signal from the controller 70. The page buffer 52 can be configured to read data from the memory block 103 and write (write) data to the memory block 103 according to the Y path control signal from the controller 70. For example, the page buffer 52 can store a page of data to be programmed into a memory page 432. In another example, the page buffer 52 can perform a verification operation to ensure that the data has been correctly programmed into each memory cell 340. In yet another example, during a read operation, the page buffer 52 can sense the current flowing through the bit line 341 reflecting the logic state (i.e., data) of the memory cell 340 and amplify the small signal to a measurable amplification result.

[0066] In some embodiments, to improve the efficiency of the write operation, the column decoder / bit line driver 50 may transmit a bias voltage V to the selected bit line according to the Y path control signal from the controller 70 and the data to be programmed from the page buffer 52. bias .

[0067] In some embodiments, the input / output buffer 55 can transmit I / O data to and from the page buffer 52 and transmit addresses ADDR or commands CMD to the controller 70. In some embodiments, the input / output buffer 55 can function as a memory controller 20 ( Figure 1 The function of the interface between the memory device 100 on the memory device 25) and the memory device 100 on the memory device 25.

[0068] In some embodiments, the controller 70 can control the page buffer 52 and the row decoder / word line driver 40 in response to the command CMD transmitted by the input / output buffer 55. During a programming operation, the controller 70 can control the row decoder / word line driver 40 and the page buffer 52 to program the selected memory cell. During a read operation, the controller 70 can control the row decoder / word line driver 40 and the page buffer 52 to read the selected memory cell. The X-path control signal and the Y-path control signal include a row address X-ADDR and a column address Y-ADDR that can be used to locate the selected memory cell in the memory block 103. The row address X-ADDR may include a page index PD, a block index BD, and a plane index PL, thereby identifying the memory page 432, the memory block 103, and the memory plane 101 ( Figure 3 The column address Y-ADDR may identify a byte or word in the data of the memory page 432.

[0069] In some embodiments, the voltage generator 65 may generate voltages to be supplied to the word lines and the bit lines under the control of the controller 70. The voltages generated by the voltage generator 65 include a read voltage V read , programming voltage V pgm , through the voltage V pass , inhibit voltage Vinhibit, bit line bias voltage V bias wait.

[0070] It should be pointed out that Figure 1 , Figure 2A-2B as well as Figure 3-4 The arrangement of electronic components among the memory system 10 and the memory device 100 in FIG. 1 is shown as a non-limiting example. In some embodiments, the memory system 10 and the memory device 100 may have other layouts and may include additional components. Figure 4 The components shown on the memory device 100 (eg, the controller 70 , the I / O buffer 55 ) may also be moved outside the memory device 100 to function as independent electrical components in the memory system 10 . Figure 4 Components shown on memory device 100 (eg, controller 70, I / O buffer 55) may also be moved to other components in memory system 10, for example, portions of controller 70 may be combined with memory controller 20, and vice versa.

[0071] Figure 5 shows the threshold voltage V of a NAND flash memory programmed in SLC, MLC or TLC mode according to some embodiments th In some embodiments of the SLC mode, state P1 corresponds to state S1. In some embodiments of the MLC mode, states P1-P3 correspond to states M1-M3. In some embodiments of the TLC mode, states P1-P7 correspond to states T1-T7. In some embodiments, each state of the memory cell may correspond to a range of threshold voltages V th , where the threshold voltage of each state is V th The distribution can be represented by a probability density. In some embodiments, an incremental step pulse programming (ISPP) scheme can be used to program other states besides the erased state ER, so that the erased state ER can be programmed by increasing the step pulse V step The programming voltage V pgm For example, eight TLC states can be programmed from state ER having a lower threshold voltage to state T7 having a highest threshold voltage.

[0072] In some implementations, after programming, the read reference voltage V R1 -V R7 The eight TLC states ER and T1-T7 are verified. By applying a read reference voltage V R1 –V R7 One or more of the above can determine the threshold voltage V of the memory cell. th For example, to verify whether a memory cell is in state ER, a read reference voltage V R1 If the target memory cell is in state ER, then the threshold voltage V th Below the reading reference voltage V R1 The target memory cell can be turned on and form a conductive path in the channel. If the target memory cell is in any of the states T1-T7, the threshold voltage V th Higher than the reading reference voltage V R1 The target memory cell is thus turned off. By measuring or sensing the current through the target memory cell via the page buffer 52 at the corresponding bit line, the threshold voltage V th or status.

[0073] In some embodiments, as described above, to determine the two states ER and S1 stored in the SLC mode, only the reading reference voltage V R1 To determine the four states ER and M1-M3 in the MLC mode, the reference voltage V R1 、V R2 and V R3 To determine the eight states ER and T1-T7 of the TLC mode, the reference voltage V R1 -V R7 For example, in TLC mode, the threshold voltage of state ER is lower than V R1 , and the threshold voltage of state T7 is higher than V R7 , where the threshold voltage of state T1 is between V R1 and V R2 States T2-T6 can be determined similarly.

[0074] Figure 6 An exemplary circuit schematic 600 of a memory device according to aspects of the present disclosure is shown. The exemplary circuit schematic 600 includes a memory block 604 and a peripheral circuit 602.

[0075] In some aspects, the exemplary circuit schematic 600 includes a plurality of memory strings 610, each memory string 610 having a plurality of memory cells 608. The memory strings 610 also include at each end at least one field effect transistor (e.g., MOSFET) controlled by a lower select gate (LSG) 612 and a top select gate (TSG) 614, respectively. The memory cells 608 can be controlled by control gates, which can be connected to a word line 640 of the exemplary circuit schematic 600. The drain terminal of the TSG 614 can be connected to a bit line 618, and the source terminal of the LSG 612 can be connected to an array common source (ACS) 616. The ACS 616 can be shared by the memory strings 610 in the entire memory block, and is therefore also referred to as a common source line.

[0076] In some aspects, the exemplary circuit diagram 600 can be formed based on floating gate technology. In some aspects, the exemplary circuit diagram 600 can be formed based on charge trapping technology. NAND flash memory based on charge trapping can provide high storage density and high inherent reliability. The stored data or logic state (e.g., the threshold voltage V of the memory cell 608) th ) depends on the amount of charge trapped in the storage layer. In some aspects, the memory block 604 can be a three-dimensional (3D) memory device, and the exemplary circuit schematic 600 can be a 3D memory array, wherein the memory cells 608 can be arranged in a vertical stack one on top of another.

[0077] The memory block 604 may include multiple vertically stacked levels or layers, such as formed by a dual stacking process. Figure 6 As shown, the memory block 604 includes a first level 680 and a second level 690. Each level may include a plurality of vertically stacked memory cells. In addition, each level may be processed independently to achieve efficient read, write and / or erase operations. For example, each level may perform an erase operation independently of other levels. In addition, read operations and write operations may be performed in a memory page, wherein a memory page includes a plurality of memory cells sharing the same WL. Figure 6 An exemplary structure of a memory device including two levels is described in , however, the number of levels in the memory block 604 is not limited to two, and the memory block 604 may include three, four, or any other number of levels.

[0078] In NAND flash memory, read and write operations may be performed based on one or more logical pages, which may be associated with a memory block 604 and / or a memory page 622, which includes all memory cells 608 that share the same word line. In some aspects, a programming voltage may be sent to the control gates of all memory cells 608 via a selected word line (e.g., WL 640) in a memory page 622 to program at least one of the memory cells 608 that share the same word line. A row address X-ADDR of a memory page 622 may be selected by a row decoder / word line driver, e.g., Figure 4 The row address may include a page index PD, a block index BD, and a plane index PL, thereby identifying a memory page 622, a memory block 604, and a memory plane 101 ( Figure 3 The column address Y-ADDR may identify a byte or word in the data of the memory page 622.

[0079] In some aspects, while one or more memory cells in memory page 622 receive a programming voltage, other unselected memory cells may receive a pass voltage via one or more unselected word lines (e.g., WL 630 and WL 656) that is high enough to place the unselected memory cells in a conductive state but not high enough to program them.

[0080] In some aspects, one or more memory cells can be programmed in a word line programming order, one word line at a time, starting from one end of the NAND string and proceeding continuously to the other end of the NAND string. In some aspects, one or more memory cells can be programmed, starting from the WL with a low page index to the WL with a high page index, one word line at a time.

[0081] In a NAND memory, the memory cell 608 can be in an erased state ER or a programmed state. Initially, all memory cells 608 in the exemplary circuit diagram 600 can be reset to the erased state ER as a logic "1" by implementing a negative voltage difference between the control gate and the source terminal (e.g., the array common source 616) of the memory cell, thereby being able to eliminate all trapped charges in the storage layer of the memory cell 608. For example, the negative voltage difference can be induced by setting the control gate of the memory cell 608 to ground and applying a high positive voltage to the array common source 616. In the erased state ER ("state ER"), the threshold voltage V th may be reset to a minimum value and may be measured or sensed at bit line 618 .

[0082] During programming (i.e. writing), the programming voltage V pgmA positive voltage pulse (e.g., between 10 V and 20 V) may be applied to the control gate, so that charge (e.g., electrons) can be injected into the storage layer of the memory cell 608, thereby increasing the threshold voltage V of the memory cell 608. th Thus, memory cell 608 is programmed to a programmed state.

[0083] NAND flash memory can be configured to operate in single-level cell (SLC) mode. In order to increase storage capacity, NAND flash memory can also be configured to operate in multi-level cell (MLC) mode, triple-level cell (TLC) mode, quad-level cell (QLC) mode, or a combination of any of these modes. In SLC mode, a memory cell stores "1" bit and has two logical states ("states"), namely state ER and P1. In MLC mode, a memory cell stores 2 bits and has four states, namely states ER, P1, P2, and P3. In TLC mode, a memory cell stores 3 bits and has eight states, namely states P1–P7. In QLC mode, a memory cell stores 4 bits and has 16 states.

[0084] Figure 7 An exemplary process flow 700 for performing programming operations according to various aspects of the present disclosure is shown. Figure 1-6 The elements are used to describe Figure 7 Example 700 may be implemented by a memory system (e.g., Figure 1 10). It should be appreciated that process flow 700 is not exclusive, and other operation steps may be performed before, after, or between any of the illustrated operation steps. In some embodiments, some of the operation steps in process flow 700 may be omitted, or other operation steps may be included that are not described here for the purpose of brevity. In some embodiments, the operation steps in process flow 700 may be performed in a different order and / or there may be variations.

[0085] In some implementations, a programming operation is performed on a memory cell in the first memory cells at 702. In some aspects, the memory cell is controlled by a selected word line in the first word lines corresponding to the first memory cell. The first word lines may include a first unselected word line adjacent to the selected word line.

[0086] As described above, memory block 604 may include a first level 680 and a second level 690. Each level may include a plurality of vertically stacked memory cells. In some aspects, the first memory cell may correspond to a memory cell in first level 680. The second memory cell may correspond to a memory cell in second level 690. In some aspects, the first memory cell and the second memory cell may be connected in series to a bit line, such as bit line 618.

[0087] In some implementations, a programming operation is performed at 702 , including 704 , 706 , and 708 .

[0088] In some implementations, at 704, a program voltage signal is applied to a selected word line (eg, WL 640) to program the memory cells to a target state (eg, state P1).

[0089] In some implementations, at 706, a first pass voltage is applied to a first unselected word line (eg, WL 650, 652).

[0090] In some embodiments, a second pass voltage is applied to a second word line (eg, WL 654, 656) corresponding to a second memory cell at 708. In some embodiments, the second pass voltage can be lower than the first pass voltage.

[0091] In some embodiments, the programming operation can be performed after the erase operation is performed on the first memory cell. As described above, each level in the memory block can be processed independently to achieve efficient read, write and / or erase operations. For example, each level can perform an erase operation independently of other levels.

[0092] In some embodiments, the first unselected word line (e.g., WL 650, 652) can be adjacent to the second word line (e.g., WL 654, 656). In some embodiments, the second pass voltage can be adjusted based on the position of the selected word line (e.g., WL 640). In some embodiments, the position of the selected word line can be determined by the number of first unselected word lines (e.g., WL 650, 652) between the selected word line (e.g., WL 640) and the second word line (e.g., WL 654, 656).

[0093] In some embodiments, when there are a first number of first unselected word lines between the selected word line and the second word line, the second pass voltage can be adjusted to a third pass voltage. In some embodiments, when there are a second number of first unselected word lines between the selected word line and the second word line, the second pass voltage can be adjusted to a fourth pass voltage different from the third pass voltage. The second number can be different from the first number.

[0094] In some embodiments, the second number may be less than the first number, and the fourth pass voltage may be greater than the third pass voltage.

[0095] In some embodiments, the first word line may further include second unselected word lines (eg, WL 630 , 632 , 646 , 644 ) adjacent to the selected word line (eg, WL 640 ).

[0096] In some embodiments, the first unselected word line may be on a first side of a selected word line and the second unselected word line may be on a second side of a selected word line. The first side and the second side may be opposite sides of the selected word line.

[0097] In some embodiments, performing the program operation may further include applying a fifth pass voltage to the second unselected word line. The fifth pass voltage may be lower than the first pass voltage.

[0098] In some embodiments, applying the program voltage signal, applying the first pass voltage, and applying the second pass voltage can be performed substantially simultaneously.

[0099] Fig. 8A 1 shows an exemplary configuration of multiple pass voltage distributions and corresponding word lines according to some embodiments. Fig. 8A Without being limited to the specific aspects depicted in these figures, other configurations may be used, as will be appreciated by those skilled in the art.

[0100] exist Fig. 8A In Figure 7 6. After applying multiple pass voltages and programming voltages during a programming operation, a first configuration of multiple pass voltages applied and corresponding word lines are shown. In this configuration, a memory string (e.g., memory string 610) can include multiple memory cells (e.g., memory cell 608) in a first level 680 and a second level 690. The first level 680 performs an erase operation independently of the second level 690.

[0101] After the erase operation of the first stage 680, a programming operation may be performed in the first stage 680. The programming operation may be performed in the first stage 680 in a bit line precharge mode using forward programming. For example, the programming operation may be performed in an order from a source side or terminal to a drain side or terminal. The source side or terminal may be close to a bottom side of the second stage 690, and the drain side or terminal may be close to an upper side of the first stage 680 (e.g., WLx). The memory cells in the first stage 680 may correspond to a plurality of word lines, including Fig. 8A. In some aspects, WL0 to WLx may be arranged in a sequence starting from one end of the memory string and continuing to the other end of the memory string. In some aspects, the page indexes of WLx to WL0 may be in ascending order. In some aspects, WL0 to WLx may also correspond to different page index regions. A programming operation may be performed in the first level 680 in a sequence starting from WL0 and continuing to WLx.

[0102] In some aspects, in Figure 7 After applying a plurality of pass voltages and a program voltage during a programming operation as described in , a program voltage Vpgm may be applied to a selected word line WLn. Fig. 8A As shown, a plurality of pass voltages may be applied to the corresponding word line, including Vpass1, Vpass2, and Vpass3+ΔV. In some aspects, Vpass1, Vpass2, and Vpass3+ΔV may correspond to reference voltages 1, 2, 3, and 4, respectively. Figure 7 The fifth pass voltage, the first pass voltage, and the second pass voltage are described.

[0103] As reference Figure 7 As described, the second pass voltage (e.g., Vpass3+ΔV) can be adjusted based on the position of the selected word line. In some embodiments, the position of the selected word line can be determined by the number of first unselected word lines (e.g., WLn-1 to WL0) between the selected word line and the second word line (e.g., the word lines in the second level 690).

[0104] In some aspects, the second pass voltage (eg, Vpass3+ΔV) and the position of the selected word line may be shown in a dynamic setting table as shown in Table 1 below:

[0105] Selected WLn in stage 680 Section Vpass3+△V WLy-WLx Sec_x Vpass3+△V_sec x … … … … WL11-20 Sec_B Vpass3+△V_sec b WL0-10 Sec_A Vpass3+△V_sec a

[0106] Table 1. Dynamic settings table

[0107] As shown in Table 1, the second pass voltage (e.g., Vpass3+ΔV) may be adjusted based on the location of the selected word line WLn. For example, a segment in the first level 680 where the selected word line WLn is located may be determined. The magnitude of the second pass voltage may be adjusted based on the segment. For example, when the selected word line WLn is within WL0 to WL10, a first segment in the first level 680 may be determined. The magnitude of the second pass voltage may be adjusted based on the first segment. When the selected word line WLn is within WL11 to WL20, a second segment in the first level 680 may be determined. The magnitude of the second pass voltage may be adjusted based on the second segment.

[0108] Figure 8B According to some embodiments, Fig. 8A1 is an exemplary voltage waveform timing diagram of a memory device configured in FIG. Figure 8B Without being limited to the specific aspects depicted in these figures, other configurations may be used, as will be appreciated by those skilled in the art.

[0109] The time period from time T1 to time T2 may be referred to as a precharge cycle. In some aspects, one or more bit lines, such as bit line 618, may be precharged via page buffer 52. The time period from time T2 to time T3 may be referred to as a programming cycle. During the programming cycle, the voltage applied to the selected word line WLn may be ramped from a low level (e.g., ground level) to a high level (e.g., programming voltage Vpgm). The voltage applied to word lines WLn+1 to WLx may be ramped from a low level (e.g., ground level) to a high level (e.g., by voltage Vpass1). The voltage applied to word lines WLn-1 to WL0 may be ramped from a low level (e.g., ground level) to a high level (e.g., by voltage Vpass2). The voltage applied to the word lines in the second stage 690 may be ramped from a low level (e.g., ground level) to a high level (e.g., by voltage Vpass3+ΔV).

[0110] Fig.9A 1 shows an exemplary configuration of multiple pass voltage distributions and corresponding word lines according to some embodiments. Fig.9A Without being limited to the specific aspects depicted in these figures, other configurations may be used, as will be appreciated by those skilled in the art.

[0111] exist Fig.9A In Figure 7 After applying the multiple pass voltages and the program voltage during the programming operation as described in FIG. 8 , a second configuration of the applied multiple pass voltages and corresponding word lines are shown.

[0112] In this configuration, a memory string (eg, memory string 610) may include a plurality of memory cells (eg, memory cell 608) in a first level 680 and a second level 690. The first level 680 performs erase operations independently of the second level 690.

[0113] After the erase operation of the second stage 690, a programming operation may be performed in the second stage 690. The programming operation may be performed in the second stage 690 in an ACS precharge mode using reverse programming. For example, the programming operation may be performed in an order from the drain side or terminal to the source side or terminal. The source side or terminal may be close to the bottom side of the second stage 690, and the drain side or terminal may be close to the upper side of the first stage 680 (e.g., WLx). The memory cells in the second stage 690 may correspond to a plurality of word lines, including Fig.9A. In some aspects, WL0 to WLx may be arranged in a sequence starting from one end of the memory string and continuing to the other end of the memory string. In some aspects, the page indexes of WLx to WL0 may be in ascending order. In some aspects, WL0 to WLx may also correspond to different page index regions. A programming operation may be performed in the second level 690 in a sequence starting from WL0 and continuing to WLx.

[0114] In some aspects, in Figure 7 After applying a plurality of pass voltages and a program voltage during a programming operation as described in , a program voltage Vpgm may be applied to a selected word line WLn. Fig.9A As shown, a plurality of pass voltages may be applied to the corresponding word line, including Vpass1, Vpass2, and Vpass3+ΔV. In some aspects, Vpass1, Vpass2, and Vpass3+ΔV may correspond to reference voltages 1, 2, 3, and 4, respectively. Figure 7 The fifth pass voltage, the first pass voltage, and the second pass voltage are described.

[0115] As reference Figure 7 As described, the second pass voltage (e.g., Vpass3+ΔV) can be adjusted based on the position of the selected word line. In some embodiments, the position of the selected word line can be determined by the number of first unselected word lines (e.g., WL0 to WLn+1) between the selected word line and the second word line (e.g., the word lines in the first level 680).

[0116] In some aspects, the second pass voltage (eg, Vpass3+ΔV) and the position of the selected word line may be shown in a dynamic setting table as shown in Table 2 below:

[0117] Selected WLn in stage 690 Section Vpass3+△V WLy-WLx Sec_x Vpass3+△V_sec x … … … … WL11-20 Sec_B Vpass3+△V_sec b WL0-10 Sec_A Vpass3+△V_sec a

[0118] Table 2. Dynamic settings table

[0119] As described in Table 2, the second pass voltage (e.g., Vpass3+ΔV) may be adjusted based on the location of the selected word line WLn. For example, a segment in the second level 690 where the selected word line WLn is located may be determined. The magnitude of the second pass voltage may be adjusted based on the segment. For example, when the selected word line WLn is within WL0 to WL10, a first segment in the second level 690 may be determined. The magnitude of the second pass voltage may be adjusted based on the first segment. When the selected word line WLn is within WL11 to WL20, a second segment in the second level 690 may be determined. The magnitude of the second pass voltage may be adjusted based on the second segment.

[0120] Fig. 9B According to some embodiments, Fig.9A1 is an exemplary voltage waveform timing diagram of a memory device configured in FIG. Fig. 9B Without being limited to the specific aspects depicted in these figures, other configurations may be used, as will be appreciated by those skilled in the art.

[0121] The time period from time T1 to time T2 may be referred to as a precharge cycle. In some aspects, one or more bit lines, such as an array common source (e.g., ACS 430), may be precharged. The time period from time T2 to time T3 may be referred to as a programming cycle. During the programming cycle, the voltage applied to the selected word line WLn may be ramped from a low level (e.g., ground level) to a high level (e.g., programming voltage Vpgm). The voltage applied to word lines WLn+1 to WLx may be ramped from a low level (e.g., ground level) to a high level (e.g., by voltage Vpass1). The voltage applied to word lines WLn-1 to WL0 may be ramped from a low level (e.g., ground level) to a high level (e.g., by voltage Vpass2). The voltage applied to the word lines in the first stage 680 may be ramped from a low level (e.g., ground level) to a high level (e.g., by voltage Vpass3+ΔV).

[0122] In some examples, a memory system may include a controller and a memory device coupled to the controller, such as reference Figure 1 , Figure 2A-2B and Figure 3-6 The memory system may be configured to perform reference Figure 7 , Figures 8A-8B and Figures 9A-9B The operation described.

[0123] As described above, due to the erase and / or programming operation of the upper level cell, the lower level cell in the programming state may be subjected to more severe Vpass interference. Among other things, two advantages of the present disclosure may include: (1) Vpass interference may be improved in a memory system by providing independent or different pass voltages when performing a programming operation on a memory cell in a first memory cell. For example, a first pass voltage may be applied to a first unselected word line (e.g., WL 650, 652), and a first pass voltage may be applied to a first unselected word line (e.g., WL 650, 652) corresponding to a word line such as Figure 7 , Figures 8A-8B and Figures 9A-9B (2) applying a second pass voltage to a second word line (e.g., WL654, 656) of a second memory cell described in the embodiment; and (3) Vpass interference can be further improved in the memory system by adjusting the second pass voltage based on the position of the selected word line (e.g., WL 640), thereby improving one or more performance characteristics of the memory system.

[0124] The above description of specific embodiments will fully demonstrate the general nature of the present disclosure, so that others can easily modify and / or adjust various applications of such specific embodiments by applying knowledge within the technical scope of the art without excessive experimentation and without departing from the general concept of the present application. Therefore, according to the disclosure and guidance given herein, such adjustments and modifications are intended to be within the meaning and scope of the equivalents of the embodiments disclosed herein. It should be understood that the wording or terminology herein is for illustrative purposes, not for limitation, so the terms or wording of this specification will be interpreted by the technician according to the disclosure and guidance.

[0125] The above describes the embodiments of the present disclosure by means of functional building blocks that illustrate the embodiments of the specified functions and their relationships. For the convenience of description, the boundaries of these functional building blocks are arbitrarily defined. Alternative boundaries can be defined as long as the specified functions and relationships are appropriately performed.

[0126] The Summary and Abstract sections may set forth one or more, but not necessarily all exemplary embodiments of the present disclosure contemplated by the inventor(s), and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0127] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A method for programming a memory device having a memory array, the memory array comprising blocks, wherein: Each block includes a first memory cell and a second memory cell, wherein the first memory cell and the second memory cell are connected in series to a bit line, the method comprising: performing a programming operation on a memory cell in the first memory cell, wherein the memory cell is controlled by a selected word line among first word lines corresponding to the first memory cell, wherein the first word lines include a first unselected word line adjacent to the selected word line, and Wherein, executing the programming operation includes: applying a program voltage to the selected word line to program the memory cell to a target state; applying a first pass voltage to the first unselected word line; and A second pass voltage is applied to a second word line corresponding to the second memory cell.

2. The method according to claim 1, wherein: The second pass voltage is lower than the first pass voltage.

3. The method according to claim 1, wherein: The performing of the programming operation is performed after performing an erasing operation on the first memory cell.

4. The method according to claim 1, wherein: The first unselected word line is adjacent to the second word line.

5. The method according to claim 1, wherein: The second pass voltage is adjusted based on the location of the selected word line.

6. The method according to claim 5, wherein: The position of the selected word line is determined by the number of the first unselected word lines between the selected word line and the second word line.

7. The method according to claim 6, wherein: The second pass voltage is adjusted to a third pass voltage when there is a first number of the first unselected word lines between the selected word line and the second word line, wherein the second pass voltage is adjusted to a fourth pass voltage different from the third pass voltage when there is a second number of the first unselected word lines between the selected word line and the second word line, and wherein the second number is different from the first number.

8. The method according to claim 7, wherein: The second number is less than the first number, and wherein the fourth pass voltage is greater than the third pass voltage.

9. The method according to claim 1, wherein: The first word line further includes a second unselected word line adjacent to the selected word line.

10. The method according to claim 9, wherein: The first unselected word line is on a first side of the selected word line and the second unselected word line is on a second side of the selected word line, and wherein the first side and the second side are opposite sides of the selected word line.

11. The method according to claim 9, wherein: The performing the program operation further includes applying a fifth pass voltage to the second unselected word line, and wherein the fifth pass voltage is less than the first pass voltage.

12. The method according to claim 1, wherein: The applying the programming voltage, the applying the first pass voltage, and the applying the second pass voltage are performed substantially simultaneously.

13. A memory device comprising: a memory array comprising blocks, wherein each block comprises a first memory cell and a second memory cell, wherein the first memory cell and the second memory cell are connected in series to a bit line; word line driver; and A controller configured to control the word line driver to: performing a programming operation on a memory cell in the first memory cell, wherein the memory cell is controlled by a selected word line among first word lines corresponding to the first memory cell, wherein the first word lines include a first unselected word line adjacent to the selected word line, and Wherein, executing the programming operation includes: applying a program voltage signal to the selected word line to program the memory cell to a target state; applying a first pass voltage to the first unselected word line; and A second pass voltage is applied to a second word line corresponding to the second memory cell.

14. The memory device according to claim 13, wherein: The second pass voltage is lower than the first pass voltage.

15. The memory device of claim 13, wherein: The performing of the programming operation is performed after performing an erasing operation on the first memory cell.

16. The memory device of claim 13, wherein: The first unselected word line is adjacent to the second word line.

17. The memory device of claim 13, wherein: The second pass voltage is adjusted based on the location of the selected word line.

18. The memory device of claim 17, wherein: The position of the selected word line is determined by the number of the first unselected word lines between the selected word line and the second word line.

19. The memory device of claim 18, wherein: The second pass voltage is adjusted to a third pass voltage when there is a first number of the first unselected word lines between the selected word line and the second word line, wherein the second pass voltage is adjusted to a fourth pass voltage different from the third pass voltage when there is a second number of the first unselected word lines between the selected word line and the second word line, and wherein the second number is different from the first number.

20. The memory device of claim 19, wherein: The second number is less than the first number, and wherein the fourth pass voltage is greater than the third pass voltage.

21. A memory system comprising: Controller; as well as a memory device coupled to the controller, the memory device comprising: a memory array comprising blocks, wherein each block comprises a first memory cell and a second memory cell, wherein the first memory cell and the second memory cell are connected in series to a bit line; word line driver; and A controller configured to control the word line driver to: performing a program operation on memory cells in the first memory cells, wherein the memory cells are controlled by a selected word line in first word lines corresponding to the first memory cells, wherein the first word lines include a first unselected word line adjacent to the selected word line, and Wherein, executing the programming operation includes: applying a program voltage signal to the selected word line to program the memory cell to a target state; applying a first pass voltage to the first unselected word line; and A second pass voltage is applied to a second word line corresponding to the second memory cell.

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