Sharing bus type distributed MBIST system

Abstract

The invention relates to a shared bus type distributed MBIST system, and belongs to the technical field of MBIST architecture. According to the shared bus type distributed MBIST architecture, a Memory Interface module in a Tesent MBIST architecture is removed, an MBIST controller is reserved, and a shared bus controller is additionally arranged in the MBIST controller, so that a data path and a control path are built between the MBIST controller and Memory, and the data path and the control path comprise an address bus, a data bus, a read-write enable, a chip selection enable and other control buses which can be reused and are used for accessing the Memory. According to the shared bus type distributed MBIST architecture, a Memory Interface module is not needed, the problems that the chip area and power consumption are large due to the fact that multiple Memory Interfaces need to be adopted at present are solved, logic resources can be reduced to the maximum extent, the logic complexity can be reduced, and testing of Memory in a chip is achieved.

Description

Technical Field

[0001] The invention relates to a shared bus type distributed MBIST system, belonging to the technical field of MBIST architecture. Background Art

[0002] MBIST is the abbreviation of Memory Build-In-Self Test, which means memory built-in self-test. "Built-in" means that the test vectors for testing the memory are not generated by an external ATE (Auto Test Equipment) test machine, but are automatically generated by the memory test logic inside the chip, and the results are compared. In the MBIST test, the test machine only needs to issue the test instructions through the JTAG (Joint Test Action Group) standard interface to obtain the test results from the JTAG TDO (Test Data Output) interface.

[0003] The main significance of MBIST testing is:

[0004] (1) The memory integrates many storage units in a very small area, which makes the ATE test cost too high and is not suitable for externally injecting test vectors for the memory.

[0005] (2) Memory testing has its particularity. Memory has many units that need to be tested, but they are distributed in an orderly manner. Algorithms can be used to generate test vectors in batches.

[0006] (3) To meet the needs of online testing, MBIST testing does not rely on ATE testing machines. It can be integrated at the board level, in the chip, or called by software, so that testing can be carried out anytime and on demand, and possible faults can be eliminated at any time.

[0007] Currently, MBIST testing is performed in all chip designs that include memory, so the memory in the chip has two usage states, namely the Function work mode for normal operation and the MBIST TEST mode for MBIST testing.

[0008] Currently, the MBIST architecture used in the chip design process is mostly provided by chip EDA (Electronic Design Automation) manufacturers. Among the current EDA manufacturers, Mentor's Tessent MBIST architecture is the most widely used MBIST architecture in chip design. Take the Tessent MBIST architecture as an example. Figure 1The figure shows a simple functional block diagram of the Tessent MBIST architecture. The MBIST architecture used by Tessent MBIST consists of two parts: Tessent Memory BIST Controller and Memory Interface. Tessent Memory BIST Controller includes FSM (Finite-State Machine), SIGNAL GEN (Signal Generation) and COMP (Compare) modules. Memory Interface includes the input selector or COMP module of Memory signal. The number of Memory Interface is the same as the number of Memory in the chip. The location of COMP module is optional. It can be placed in Tessent Memory BIST Controller or Memory Interface. FSM module can generate a series of control signals according to the test signals transmitted from JTAG interface. These control signals are transmitted to SIGNAL GEN module. SIGNAL GEN module contains the relevant algorithms for MBIST test, which is used to generate address bus signal, data bus signal, read / write enable bus signal and chip select enable bus signal used in MBIST test.

[0009] Generally, dozens or even hundreds of memories are used in a chip project, and some large designs even use thousands of memories. According to the MBIST architecture of mentor company, it means that as many memory interfaces as memories will be used, which will undoubtedly cause huge chip area overhead, greatly increasing chip area and power consumption. Summary of the invention

[0010] The purpose of the present invention is to provide a shared bus type distributed MBIST system to solve the problem of large chip area and power consumption caused by the need to adopt multiple Memory Interfaces in the current MBIST architecture.

[0011] The present invention provides a shared bus type distributed MBIST system for solving the above-mentioned technical problems. The system comprises an MBIST Controller and a shared bus controller. The MBIST Controller is used for generating a control signal according to a test instruction, generating an address bus signal, a data bus signal, a read-write enable bus signal and a chip select enable bus signal used by the MBIST TEST based on the control signal, and transmitting the signals to the shared bus controller. The shared bus controller is used for distributing the received address bus signal, the data bus signal, the read-write enable bus signal and the chip select enable bus signal used by the MBIST TEST to each memory, so as to enable access to each memory.

[0012] Furthermore, the shared bus controller includes a selector array and a distributed bus distributor, and the distributed bus distributor includes a Function_work_controller and an MBIST_TEST_controller. The Function_work_controller is used to complete the access to each memory in the Function work stage; and the MBIST_TEST_controller is used to complete the access to each memory in the MBIST TEST stage.

[0013] Furthermore, the MBIST_TEST_controller includes a state machine of Distributed_FSM, and the state machine of the Distributed_FSM is used to implement serial access to each Memory in the MBIST TEST stage.

[0014] Further, described MBIST Controller includes Main_FSM module and SIGNAL_GEN module, described Main_FSM module is used for producing control signal under the driving of test signal, and the control signal that produces is sent to the SIGNAL_GEN module, and described SIGNAL_GEN module is used for producing address bus signal, data bus signal, read-write enable bus signal and the chip select enable bus signal that MBIST TEST uses according to received control signal.

[0015] Furthermore, the shared bus controller is also used to distribute the address bus signal, data bus signal, read / write enable bus signal and chip select enable bus signal used by the Function work to each Memory to enable access to each Memory.

[0016] Furthermore, in the Function work phase, the shared bus controller accesses each memory independently; in the MBIST TEST phase, the shared bus controller accesses each memory in chronological order.

[0017] The invention has the beneficial effects as follows: relative to traditional Tessent MBIST framework, shared bus type distributed MBIST framework of the present invention has removed the Memory Interface module in the Tessent MBIST framework, retained MBISTController, and in MBIST Controller, added shared bus controller, to build data path and control path between MBIST Controller and Memory, comprise the control buses such as address bus, data bus, read-write enable, chip select enable that can be reused to access Memory. As can be seen, shared bus type distributed MBIST framework of the present invention does not need the Memory Interface module, has solved the chip area and the large problem of power consumption that need to adopt multiple Memory Interface to cause at present, and can minimize logic resources, reduce logic complexity, realize the test of Memory in chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of Mentor's Tessent MBIST architecture;

[0019] Figure 2 It is a shared bus type distributed MBIST architecture schematic diagram of the present invention;

[0020] Figure 3 is a functional block diagram of a shared bus controller used in the present invention;

[0021] Figure 4 It is a flow chart of the Distributed_FSM adopted by the present invention. DETAILED DESCRIPTION

[0022] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0023] The present invention discloses a shared bus type distributed MBIST system, which comprises an MBIST Controller and a shared bus controller, wherein the MBIST Controller is used to generate a control signal according to a test instruction, and generates an address bus signal, a data bus signal, a read-write enable bus signal and a chip select enable bus signal used by MBISTTEST based on the control signal, and transmits the control signal to the shared bus controller; the shared bus controller is used to distribute each received bus signal to each memory to enable access to each memory. Relative to the traditional Tessent MBIST architecture, the shared bus type distributed MBIST architecture of the present invention removes the Memory Interface module in the Tessent MBIST architecture, retains the MBIST Controller, and adds a shared bus controller in the MBIST Controller to build a data path and a control path between the MBIST Controller and the memory. The following is a detailed description.

[0024] like Figure 2 Shown, shared bus type distributed MBIST framework of the present invention comprises MBIST Controller and shared bus controller, wherein MBIST Controller includes Main_FSM module and SIGNAL_GEN module, the Main_FSM module is used for producing control signal under the driving of test signal, and the control signal that produces is sent to the SIGNAL_GEN module, the SIGNAL_GEN module is used for utilizing address bus signal, data bus signal, read-write enable bus signal and the chip select enable bus signal that internal algorithm produces MBIST TEST to use according to the control signal received.

[0025] like Figure 3 As shown, the shared bus controller consists of a selector array and a distributed bus distributor. The selector array is used to select which memory to access according to the order in Main_FSM; the distributed bus distributor consists of Function_work_controller and MBIST_TEST_controller. MBIST_TEST_controller is responsible for completing the access to each memory in the MBIST TEST stage. MBIST_TEST_controller includes a state machine called Distributed_FSM. Figure 4As shown in the figure, the state machine is responsible for implementing serial access to each memory in the design during the MBIST TEST phase. Function_work_controller is responsible for completing the access to each memory during the Function work phase.

[0026] The process that the above-mentioned shared bus type distributed MBIST system carries out MBIST test is as follows:

[0027] When performing MBIST testing, the tester controls the BIST_SETUP and MBIST(PG)_EN signals through the JTAG interface to drive the Main_FSM in the MBIST Controller to start working. The Main_FSM module generates relevant control signals and transmits them to the SIGNAL_GEN module.

[0028] The SIGNAL_GEN module generates the address bus signals (MBIST_ADDR A to MBIST_ADDR X and other signals), data bus signals (MBIST_DATA_IN A to MBIST_DATA_IN X and other signals), read and write enable bus signals (MBIST_WEN A to MBIST_WEN X), and chip select enable bus signals (MBIST_CEN A to MBIST_CEN X) used by MBIST TEST according to the control signals generated by the Main_FSM module, and then passes the above bus signals to the shared bus controller.

[0029] The shared bus controller distributes the memory data and control bus signals through the distributed bus distributor inside the shared bus controller based on the address bus signals, data bus signals, read-write enable bus signals, and chip select enable bus signals of the memory in the Function work mode transmitted from inside the chip ("memory address bus signals, data bus signals, read-write enable bus signals, and chip select enable bus signals", all referred to as "memory data and control bus signals" in the afternoon) and the data and control bus signals of the memory in the MBIST TEST mode.

[0030] In MBIST TEST mode, the Distributed_FSM control state machine is used to enter the test state of each different Memory in turn (pulse). When entering the test state of a certain Memory, the distributed bus distributor transmits the data and control bus signal of the Memory to the corresponding Memory, triggering the Memory to start the MBIST test. The Distributed_FSM control state machine controls the order of the Memory. For example, if there are 8 memories, the control line can operate the first Memory, and then the second Memory after the operation. This order is set in the state. Then the Distributed_FSM enters the start state of the next Memory TEST. At this time, the previous Memory is still in the MBIST test process. That is to say, the role of the shared bus controller is to allocate the right to use the bus, drive the data and control bus signals of different memories at different times, and transmit them to the corresponding Memory to start the Memory test. From the perspective of time, each Memory TEST has a sequence, one after another, so the shared bus controller implements serial access to the Memory, and the tests performed by each Memory after the TEST is turned on do not affect each other, so it is a parallel test.

[0031] In the Function work mode, the access and operation of each memory are independent, and there is no problem of serial access to each memory. At this time, the memory address signal, data signal, and read / write enable signal in the Function work mode directly drive the corresponding memory.

Claims

1. a shared bus type distributed MBIST system, it is characterized in that, The system comprises an MBIST Controller and a shared bus controller. The MBIST Controller is used for generating a control signal according to a test instruction, generating an address bus signal, a data bus signal, a read-write enable bus signal and a chip select enable bus signal used by the MBIST TEST based on the control signal, and transmitting the signals to the shared bus controller. The shared bus controller is used for distributing the received address bus signal, data bus signal, read-write enable bus signal and chip select enable bus signal used by the MBIST TEST to each memory so as to enable access to each memory.

2. the distributed MBIST system of shared bus type according to claim 1 is characterized in that, The shared bus controller includes a selector array and a distributed bus distributor, and the distributed bus distributor includes a Function_work_controller and an MBIST_TEST_controller. The Function_work_controller is used to complete the access to each Memory in the Function work stage; and the MBIST_TEST_controller is used to complete the access to each Memory in the MBIST TEST stage.

3. the distributed MBIST system of shared bus type according to claim 2 is characterized in that, The MBIST_TEST_controller includes a state machine of Distributed_FSM, and the state machine of the Distributed_FSM is used to implement serial access to each Memory in the MBIST TEST stage.

4. according to each described shared bus type distributed MBIST system among the claim 1-3, it is characterized in that, Described MBIST Controller includes Main_FSM module and SIGNAL_GEN module, described Main_FSM module is used for producing control signal under the driving of test signal, and the control signal produced is sent to SIGNAL_GEN module, described SIGNAL_GEN module is used for producing address bus signal, data bus signal, read-write enable bus signal and chip select enable bus signal that MBIST TEST uses according to received control signal.

5. the distributed MBIST system of shared bus type according to claim 1 is characterized in that, The shared bus controller is also used to distribute the address bus signal, data bus signal, read / write enable bus signal and chip select enable bus signal used by the Function work to each Memory to enable access to each Memory.

6. the distributed MBIST system of shared bus type according to claim 5 is characterized in that, In the Function work phase, the shared bus controller accesses each memory independently; in the MBIST TEST phase, the shared bus controller accesses each memory in chronological order.

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