Capacitor and preparation method thereof, semiconductor assembly and electronic equipment

Abstract

The embodiment of the invention provides a capacitor and a preparation method thereof, a semiconductor assembly and electronic equipment, relates to the technical field of electronics, and is used for reducing the influence of capacitor vibration on a carrier plate. The semiconductor component includes a carrier plate and a capacitor disposed on the carrier plate. The capacitor comprises a capacitor body and first electrodes, and the first electrodes are arranged at the two opposite ends of the capacitor body respectively; the capacitor body comprises a plurality of dielectric layers and a plurality of second electrodes; the multiple dielectric layers are arranged in a stacked mode and intersect with the carrier plate; the second electrodes are arranged between the two adjacent dielectric layers, the two adjacent layers of second electrodes are arranged in a staggered mode, and the two adjacent layers of second electrodes are coupled with the first electrodes located on the different sides. By adjusting the shape of the first electrode, the dielectric layer in the capacitor is intersected with or vertical to the carrier plate. Therefore, the vibration direction of the capacitor is intersected with or perpendicular to the carrier plate, so that the resonance of the carrier plate is reduced, and the problem of plate vibration is suppressed.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a capacitor and a preparation method thereof, a semiconductor component, and an electronic device. Background Art

[0002] Multi-layer ceramic capacitors (MLCC) are one of the main passive chip components in electronic devices due to their high reliability, high precision, high frequency, low power consumption, large capacity, miniaturization and low cost.

[0003] The mainstream MLCC is formed by stacking the dielectric layers with the second electrode printed on them in an offset manner, and then sealing the first electrodes at both ends of the stack. During use, due to the inverse piezoelectric effect of the dielectric layer, when AC voltage is applied, the dielectric layer will expand and contract in the stacking direction, causing the MLCC to vibrate. The vibration of the MLCC will cause the carrier board carrying the MLCC to resonate, resulting in problems such as bending of the carrier board, breaking of leads, disconnection of coupling parts, etc., thus affecting the performance of the entire device. Summary of the invention

[0004] Embodiments of the present application provide a capacitor and a method for manufacturing the same, a semiconductor component, and an electronic device, which are used to reduce the impact of capacitor vibration on a carrier.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect of an embodiment of the present application, a semiconductor component is provided, the semiconductor component comprising a carrier and a capacitor arranged on the carrier. The capacitor comprises a capacitor body and a first electrode, and the first electrodes are respectively arranged at opposite ends of the capacitor body; the capacitor body comprises a plurality of dielectric layers and a plurality of second electrodes; the plurality of dielectric layers are stacked and arranged, and the dielectric layers intersect with the carrier; the second electrode is arranged between two adjacent dielectric layers, the two adjacent layers of second electrodes are staggered, and the two adjacent layers of second electrodes are coupled to the first electrodes located on different sides. The first electrode comprises a first surface and a second surface, the first surface intersects with the dielectric layer, is parallel to the carrier, and can be understood as the top and bottom surfaces of the first electrode, and the second surface is parallel to the dielectric layer, intersects with the carrier, and can be understood as the front and back of the first electrode. The capacitor is coupled to the carrier through the first surface; the area of ​​the first surface is greater than the area of ​​the second surface. That is, the surface with a larger area in the first electrode is used to couple with the carrier.

[0007] In the semiconductor assembly provided by the embodiment of the present application, the first surface of the first electrode intersects with the dielectric layer, and the second surface of the first electrode is parallel to the dielectric layer. By setting the area of ​​the first surface of the first electrode to be larger than the area of ​​the second surface, the first surface for coupling with the carrier can be clearly distinguished. Then, in the process of preparing the capacitor, each capacitor can be directly placed in the expected position, and there is no or little random placement phenomenon to limit the patch position of the capacitor. In this way, when the capacitor is assembled with the carrier, the shapes of the first surface and the second surface of the capacitor are different, and the capacitors are all placed in the expected position. Therefore, the first surface of the capacitor can be identified, so as to ensure that the dielectric layer and the stack of the second electrode of the capacitor are placed at an intersection (for example, vertically) with the carrier. In this way, even when an electric field is applied to the first electrode, the dielectric layer will expand in the direction of the applied electric field and shrink perpendicular to the direction of the applied electric field, and the capacitor will still vibrate during operation. However, the placement direction of the dielectric layer stack intersects with the carrier, and the vibration direction of the capacitor is parallel to the carrier, which can weaken the resonance of the carrier and reduce the influence of the capacitor vibration on the carrier to suppress the "plate vibration" problem of the carrier.

[0008] In one possible implementation, the first dimension of the first electrode along the first direction (capacitor width direction) is greater than the second dimension of the first electrode along the second direction (capacitor thickness direction or capacitor length direction); the first direction is the direction of stacking of multiple dielectric layers, and the second direction intersects with the first direction. By setting the first dimension of the first electrode to be greater than the second dimension of the first electrode, the long side and the short side of the capacitor (the stacking direction and the parallel direction of the dielectric layer) can be clearly distinguished, so that all capacitors are placed in the expected position to better suppress the "plate vibration" problem.

[0009] In a possible implementation, the second direction also intersects with the carrier. That is, the second direction is the thickness direction of the capacitor. In this way, the direction in which the dielectric layers are stacked and the direction in which the dielectric layers are parallel can be clearly distinguished.

[0010] In a possible implementation, the first size is more than twice the second size. Since the first surface and the second surface share the third size, setting the first size to be more than twice the second size can increase the difference between the first surface and the second surface, making it easier to place the capacitor in a desired orientation.

[0011] In a possible implementation, the first size is less than 0.5 mm. The structure of the capacitor provided in the embodiment of the present application is still applicable when the width of the capacitor is less than 0.5 mm, and is applicable to capacitors of various sizes.

[0012] In a possible implementation, the first surface is a rectangle, and the first size is the size of the long side of the rectangle. In this way, the long side and the short side of the capacitor can be clearly distinguished, so that all capacitors are placed in the expected position to better suppress the "board vibration" problem.

[0013] In a possible implementation, the dielectric layer is perpendicular to the carrier. In this arrangement, when the capacitor vibrates, the component parallel to the carrier is almost zero, which has a better effect on suppressing "plate vibration".

[0014] The second aspect of the embodiment of the present application provides a capacitor, including: a capacitor body and a first electrode; the first electrodes are respectively arranged at the opposite ends of the capacitor body; the capacitor body includes multiple dielectric layers and multiple second electrodes; the multiple dielectric layers are stacked along the first direction; the second electrode is arranged between two adjacent dielectric layers, the two adjacent layers of second electrodes are staggered, and the two adjacent layers of second electrodes are coupled to the first electrodes located on different sides; the first electrode includes a first surface and a second surface, the first surface intersects with the dielectric layer, and the first surfaces of the two first electrodes are located in the same plane, and the second surface is parallel to the dielectric layer; the area of ​​the first surface is greater than the area of ​​the second surface. The capacitor provided in the embodiment of the present application can clearly distinguish the stacking direction and parallel direction of the dielectric layer by setting the area of ​​the first surface in the first electrode to be greater than the area of ​​the second surface, so that all capacitors are patched in the expected position to better suppress the "plate vibration" problem.

[0015] In one possible implementation, the first dimension of the first electrode along the first direction is greater than the second dimension of the first electrode along the second direction, the second direction intersects with the first direction, and the second direction also intersects with the direction from one first electrode to another first electrode. The capacitor provided in the embodiment of the present application can clearly distinguish the stacking direction and the parallel direction of the dielectric layer by setting the first dimension of the first electrode along the dielectric layer stacking direction to be greater than the second dimension of the first electrode along the second direction, so that all capacitors are patched in the expected position to better suppress the "plate vibration" problem.

[0016] In a possible implementation, the first size is more than twice the second size, so that the difference between the first size and the second size can be widened, making it easier to place the capacitor in a desired position.

[0017] In a possible implementation, the first size is less than 0.5 mm. The structure of the capacitor provided in the embodiment of the present application is still applicable when the width of the capacitor is less than 0.5 mm, and is applicable to capacitors of various sizes.

[0018] In a third aspect of the embodiments of the present application, an electronic device is provided, comprising: a housing and a semiconductor component, the semiconductor component being disposed in the housing; the semiconductor component comprising any semiconductor component of the first aspect. Alternatively, a housing and a capacitor, the capacitor being disposed in the housing; the capacitor comprising the capacitor of the second aspect.

[0019] According to a fourth aspect of an embodiment of the present application, a method for preparing a capacitor is provided, comprising: forming a capacitor body stack, the capacitor body stack comprising a plurality of dielectric films with a second electrode printed on the surface; cutting the capacitor body stack to form a plurality of capacitor bodies; a fourth dimension of the capacitor body being greater than a fifth dimension of the capacitor body, the fourth dimension being a dimension in a dielectric film stacking direction, and the fifth dimension being a dimension in a second electrode width direction; forming a first electrode at both ends of the capacitor body in a direction parallel to a length of the second electrode to form a capacitor; positioning the capacitor on a carrier so that a surface where the fourth dimension of the capacitor is located is parallel to the carrier; and taping the capacitor.

[0020] By adopting the capacitor preparation method provided in the embodiment of the present application, the prepared capacitors are all placed according to the patch angle, so that the "plate vibration" problem can be suppressed after the capacitors are patched.

[0021] In a possible implementation, the capacitor is placed in position, including: the capacitor is vibrated and screened. This placement method has simple process, is easy to implement, and has low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 An architecture diagram of an electronic device provided in an embodiment of the present application;

[0023] Figure 2 A three-dimensional schematic diagram of a capacitor according to an embodiment of the present application;

[0024] Figure 3 A schematic diagram of the layout of a second electrode in a capacitor according to an embodiment of the present application;

[0025] Figure 4 A schematic diagram of the structure of a semiconductor component composed of a capacitor and a circuit board is shown in an embodiment of the present application;

[0026] Figure 5 A schematic diagram of the structure of a capacitor provided in an embodiment of the present application;

[0027] Figure 6 A schematic diagram of the layout of a second electrode in a capacitor provided in an embodiment of the present application;

[0028] Figure 7 A schematic diagram of a preparation process of a capacitor provided in an embodiment of the present application;

[0029] Figure 8 A schematic diagram of a partial preparation process of a capacitor provided in an embodiment of the present application;

[0030] Fig. 9 A schematic diagram of the structure of a semiconductor component provided in an embodiment of the present application;

[0031] Fig.10 An architecture diagram of a radio frequency front-end module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0033] In the following, the terms "second", "first", etc. are used only for convenience of description and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "second", "first", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0034] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0035] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. In addition, the term "coupled" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be a direct contact or an indirect contact through an intermediate medium.

[0036] In the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0037] An electronic device is provided in an embodiment of the present application. The electronic device is, for example, a consumer electronic product with a camera or display function, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product. Among them, consumer electronic products are such as mobile phones, tablet computers (pad), laptop computers, e-readers, personal computers (PC), personal digital assistants (PDA), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. Home electronic products are such as smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (e.g., soybean milk machines, sweeping robots), etc. Vehicle-mounted electronic products are such as vehicle-mounted navigation systems, vehicle-mounted high-density digital video discs (DVD), etc. Financial terminal products are such as automated teller machines (ATMs), self-service terminals, etc. Communication electronic products are such as communication equipment such as servers, non-volatile memories, radars, base stations, etc. The embodiments of the present application do not impose any special restrictions on the specific form of the above-mentioned electronic device.

[0038] Figure 1 An architectural diagram of an electronic device provided in an embodiment of the present application.

[0039] Taking the electronic device provided in the embodiment of the present application as a mobile phone as an example, for example, Figure 1 As shown, the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, a headphone interface 170D, a sensor module 180, a camera 190 and a display screen 191, etc.

[0040] It is to be understood that the structures illustrated in the embodiments of the present application do not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0041] In some embodiments, the electronic device 100 also includes a circuit board. Electronic components such as the processor 110, internal memory 121, power management module 141, microphone 170C, etc. in the electronic device 100 can be arranged on the circuit board. The circuit board is used to carry the above-mentioned electronic components and complete signal interaction with the above-mentioned electronic components.

[0042] In some embodiments, the electronic device 100 further includes a capacitor, which is mounted on a circuit board. For example, the capacitor can be fixed to the circuit board by welding. The capacitor is electrically connected to the circuit board to meet the functions of tuning, bypassing, coupling or filtering in the circuit. Of course, the capacitor can be integrated in other electronic devices arranged on the circuit board, and the capacitor can also be independently arranged on the circuit board.

[0043] Figure 2 A three-dimensional schematic diagram of a capacitor according to an embodiment of the present application is shown in FIG. Figure 3 This is a schematic diagram of the layout of a second electrode in a capacitor according to an embodiment of the present application.

[0044] Regarding the structure of the capacitor, in some embodiments, such as Figure 2 and Figure 3 As shown, the capacitor 10 includes a capacitor body 11 and a first electrode (or terminal electrode) 12, wherein a first dimension s1 of the first electrode 12 along a first direction X is equal to a second dimension s2 of the first electrode 12 along a second direction Z. The shape of the first surface a1 of the first electrode 12 is the same as the shape of the second surface a2.

[0045] The capacitor body 11 includes a multi-layer dielectric layer 111 and a multi-layer second electrode 112, and the multi-layer dielectric layer 111 and the multi-layer second electrode 112 are alternately arranged along the second direction Z. Then, the size of the first electrode 12 in the arrangement direction of the capacitor body 11 is equal to the width of the dielectric layer 111. In order to clearly illustrate the structure of the second electrode 112, Figure 3 The dielectric layer 111 is not shown in the figure. The arrangement of the dielectric layer 111 can be referred to Figure 2 shown.

[0046] Figure 4 A schematic structural diagram of a semiconductor component consisting of a capacitor and a circuit board according to an embodiment of the present application.

[0047] like Figure 4 As shown, the surface of the circuit board 20 for supporting the capacitor 10 is parallel to the plane formed by the first direction X and the third direction Y. The capacitor 10 is arranged on the surface of the circuit board 20, and the arrangement direction of the multi-layer dielectric layer 111 and the multi-layer second electrode 112 in the capacitor 10 is perpendicular to the circuit board 20.

[0048] During use, due to the inverse piezoelectric effect of the dielectric layer 111, when an AC voltage is applied, the dielectric layer 111 will expand and contract in the second direction Z, causing the capacitor 10 to vibrate in the second direction Z. The vibration of the capacitor 10 will cause the circuit board carrying the capacitor 10 to resonate, which is commonly referred to as the "board vibration" problem in the art.

[0049] At present, there are the following board-level countermeasures for the "board vibration" problem: first, simplify the capacitors, second, split the large package capacitors into multiple small package capacitors, third, control the periodic voltage drop across the capacitor 10, fourth, adjust the board-level layout position and placement direction of the capacitor 10, and fifth, prepare the capacitor 10 with a pad or a bracket.

[0050] However, the existing board-level countermeasures cannot completely solve the "board vibration" problem in various application scenarios and have limited effects. Moreover, these board-level countermeasures are difficult to process, expensive, and require large packages. For example, the current smallest packaging structure of a capacitor 10 with a pad has a metric size of length * width (the seventh dimension s7 * the first dimension s1 in the third direction Y) of 1.0mm * 0.5mm, which is commonly referred to in the art as the "04*02" specification, and cannot be further applied to capacitors 10 of smaller size.

[0051] Based on this, an embodiment of the present application provides a capacitor 10 for effectively improving the "board vibration" problem in various application scenarios.

[0052] The capacitor and the components including the capacitor provided in the embodiments of the present application are exemplarily described below.

[0053] Figure 5 A schematic diagram of the structure of a capacitor provided in an embodiment of the present application is shown in FIG. Figure 6 A schematic diagram of the layout of a second electrode in a capacitor provided in an embodiment of the present application.

[0054] like Figure 5 As shown, the embodiment of the present application provides a capacitor 10 , which is, for example, a chip-type multi-layer ceramic capacitor (MLCC). The capacitor 10 includes a capacitor body 11 and a first electrode 12 .

[0055] The first electrodes 12 are respectively provided at the opposite ends of the capacitor body 11. When the capacitor 10 is coupled to the circuit board 20, the capacitor 10 is coupled to the circuit board 20 through the first electrodes 12 to complete signal interaction. Then, the first electrode 12 can be used as a lead-out terminal of the capacitor body 11, so as to facilitate the electrical connection of the capacitor body 11 with an external circuit.

[0056] Combination Figure 5 and Figure 6As shown, the capacitor body 11 includes a multi-layer dielectric layer 111 and a multi-layer second electrode 112. The dielectric layer 111 and the second electrode 112 extend in a plane surrounded by the second direction Z and the third direction Y, and the multi-layer dielectric layer 111 and the multi-layer second electrode 112 are stacked along the first direction X. For example, along the first direction X, the multi-layer dielectric layer 111 is stacked, and the second electrode 112 is arranged between two adjacent dielectric layers 111. For example, along the first direction X, the dielectric layer 111 and the second electrode 112 are alternately arranged. That is, the second electrode 112 is arranged between any two dielectric layers 111. Or for example, along the first direction X, the second electrode 112 is arranged between some of the dielectric layers 111, and the second electrode 112 is not arranged between some of the dielectric layers 111. The embodiment of the present application is not limited to this, as long as the dielectric layer 111 is respectively arranged on both sides of any second electrode 112.

[0057] It should be understood that the embodiment of the present application does not limit the shape of the second electrode 112. The second electrode 112 can be Figure 6 The sheet-shaped electrode shown in the figure may also be an electrode of any other shape, which is only a schematic diagram. For example, the shape of the second electrode 112 is selected from at least one of a rectangle, a trapezoid, a triangle, a rhombus or a circle. The embodiment of the present application does not limit the number of layers of the second electrode 112. Figure 6 A total of four second electrodes 112 are shown in the figure. However, any number of second electrodes 112 can be used in the capacitor 10 to obtain the capacitance required by the application. In order to clearly illustrate the arrangement of the second electrodes 112, Figure 6 The dielectric layer 111 is not shown in the figure. The arrangement of the dielectric layer 111 can be referred to Figure 5 shown.

[0058] In addition, the staggered arrangement of two adjacent layers of second electrodes 112 in the capacitor body 11 can also be understood as the projections of the two adjacent layers of second electrodes 112 on the dielectric layer 111 overlap but do not overlap (overlap). Alternatively, it can be understood as that along the first direction X, the two adjacent layers of second electrodes 112 are staggered in a relative and separated manner.

[0059] On this basis, two adjacent layers of second electrodes 112 are coupled to the first electrodes 12 located on different sides. For example, along the third direction Y, two first electrodes 12 are arranged on the opposite first side (e.g., the left side) and second side (e.g., the right side) of the multilayer second electrodes 112, the second electrodes 112 of the odd-numbered layers are coupled to the first electrodes 12 on the first side, and the second electrodes 112 of the even-numbered layers are coupled to the first electrodes 12 on the second side.

[0060] In some embodiments, the spacing between the surfaces of the two first electrodes 12 coupled to the second electrode 112 is greater than the dimension of the second electrode 112 along the first direction X. Then, the second electrode 112 coupled to the first electrode 12 on the first side has a gap with the first electrode 12 on the second side. Similarly, the second electrode 112 coupled to the first electrode 12 on the second side has a gap with the first electrode 12 on the first side.

[0061] In the embodiment of the present application, the dielectric layer 111 may be formed of a specific type of material having a specific dielectric constant. For example, in some embodiments, the dielectric layer 111 may be formed of a material having a relatively high dielectric constant (K).

[0062] In some embodiments, the material of dielectric layer 111 may include ceramic. The ceramic may be provided in various forms, for example, as a pre-fired wafer or as a co-fired dielectric material within the device itself.

[0063] For example, the material of the dielectric layer 111 may include perovskite. For example, the material of the dielectric layer 111 may include barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), sodium bismuth titanate, etc.

[0064] In some other embodiments, the material of the dielectric layer 111 may include oxide.

[0065] For example, the material of the dielectric layer 111 may include zinc, zirconium, niobium, magnesium, tantalum, titanium, cobalt, strontium, neodymium, samarium, silicon, etc., or a mixture thereof.

[0066] In yet other embodiments, the material of the dielectric layer 111 may include a combination of titanate and oxide.

[0067] For example, the material of the dielectric layer 111 may include a combination of barium titanate and oxide.

[0068] In the embodiment of the present application, the first electrode 12 and the second electrode 112 may be formed of any conductive metal known in the art.

[0069] In some embodiments, the materials of the first electrode 12 and the second electrode 112 may include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, aluminum, zinc, etc.), alloys (e.g., titanium / tungsten alloy, chromium / nickel alloy, copper alloy), etc., and various combinations thereof.

[0070] The first electrode 12 is coupled to the second electrode 112, for example, the first electrode 12 may wrap the entire end of the capacitor body 11 where the second electrode 112 is exposed. In this way, the connection strength between the first electrode 12 and the capacitor body 11 can be improved, while ensuring reliable electrical connection between the first electrode 12 and each second electrode 112 exposed from the end of the capacitor body 11.

[0071] In some embodiments, the surface of the first electrode 12 may be plated with other conductive materials.

[0072] Of course, the embodiment of the present application does not limit the structural relationship between the first electrode 12 and the capacitor body 11. When identifying the size of the first electrode 12 in the capacitor 10 provided in the embodiment of the present application, the size of the first electrode 12 that can be directly seen from the appearance of the capacitor 10 without cutting open the capacitor 10 shall prevail.

[0073] In the embodiment of the present application, the first direction X is the direction in which the dielectric layer 111 is stacked, the third direction Y is the direction from one first electrode 12 to another first electrode 12 (or understood as the length direction of the second electrode 112), the second direction Z intersects with both the first direction X and the third direction Z, and the second direction Z is the width direction of the second electrode 112.

[0074] Please continue to refer to Figure 5 In some embodiments, the first electrode 12 includes two first surfaces a1 parallel to the first direction X and the third direction Y, two second surfaces a2 parallel to the second direction Z and the third direction Y, and two third surfaces a3 parallel to the first direction X and the second direction Z.

[0075] One of the two first surfaces a1 of the first electrode 12 is used to couple with the carrier, and the other first surface a1 intersects with the dielectric layer 111 and is parallel to the carrier. After the capacitor 10 is coupled with the carrier, the two second surfaces a2 of the first electrode 12 are parallel to the dielectric layer 111 and intersect with the carrier (e.g., perpendicularly), and the two third surfaces a3 of the first electrode 12 also intersect with the dielectric layer 111 and intersect with the carrier (e.g., perpendicularly). One of the two third surfaces a3 of the first electrode 12 (the inner surface) is coupled with the second electrode 112.

[0076] The first surfaces a1 of the two first electrodes 12 coupled to the carrier are located in the same plane, and the first surfaces a1 of the two first electrodes 12 not coupled to the carrier are located in the same plane. The second surfaces a2 of the two first electrodes 12 located on the same side are located in the same plane, and the third surfaces a3 of the two first electrodes 12 are located in different planes.

[0077] In some embodiments, from the appearance, the area of ​​the first surface a1 of the first electrode 12 is larger than the area of ​​the second surface a2.

[0078] For example, the first surface a1 and the second surface a2 are both rectangular, and a first dimension s1 of the first electrode 12 along the first direction X is greater than a second dimension s2 of the first electrode 12 along the second direction Z.

[0079] For example, the first dimension s1 is larger than the third dimension s3 of the first electrode 12 along the third direction Y. The first surface a1 is a rectangle, the first dimension s1 is the dimension of the long side of the rectangle, and the third dimension s3 is the dimension of the short side of the rectangle. The second surface a2 is a square.

[0080] Or, for example, the first size s1 is equal to the third size s3 of the first electrode 12 along the third direction Y, the first surface a1 is a square, and the second surface a2 is a rectangle.

[0081] Of course, in the above two cases, the first surface a1 and the second surface a2 may both be rectangular.

[0082] In some embodiments, from the appearance, the area of ​​the first surface a1 of the first electrode 12 is greater than or equal to the area of ​​the third surface a3.

[0083] For example, the first surface a1 and the third surface a3 are both rectangular. For example, the first surface a1 is a rectangle, and the third surface a3 is a rectangle.

[0084] In some embodiments, from the appearance, among the first size s1, the second size s2, and the third size s3 of the first electrode, the first size s1 is the largest, and the second size s2 and the third size s3 may be equal or unequal.

[0085] It should be noted that in the embodiment of the present application, the second direction may also be a direction from one first electrode 12 to another first electrode 12, and correspondingly, the third direction intersects both the first direction X and the second direction and is a width direction of the second electrode 112. The embodiment of the present application is only a schematic diagram and is not intended to be limiting.

[0086] By setting the first dimension s1 of the first electrode 12 along the first direction X to be larger than the second dimension s2 of the first electrode 12 along the second direction Z, the long side and the short side of the capacitor 10 can be clearly distinguished so that all capacitors 10 are placed in the expected position to better suppress the "plate vibration" problem.

[0087] In some embodiments, the first size s1 is more than twice the second size s2.

[0088] Since the first surface a1 and the second surface a2 share the third size s3, setting the first size s1 to be more than twice the second size s2 can increase the difference between the first surface a1 and the second surface a2, making it easier to place the capacitor 10 in a desired orientation when preparing the capacitor 10.

[0089] In some embodiments, the capacitor 10 provided in the embodiment of the present application is suitable for s7*s1 (length*width) of 2.5mm*2.0mm (metric "2520", imperial "1008"), s7*s1 of 2.0mm*1.25mm (metric "2012", imperial "0805"), s7*s1 of 1.6mm*0.8mm (metric "1608", imperial "0603"), s7*s1 of 1.0mm*0.5mm (metric "1005", imperial " 0402”), s7*s1 is 0.6mm*0.3mm (metric “0603”, imperial “0201”), s7*s1 is 0.4mm*0.2mm (metric “0402”, imperial “01005”), s7*s1 is 0.3mm*0.15mm (metric “03015”, imperial “009005”), s7*s1 is 0.25mm*0.125mm (metric “0201”, imperial “008004”) capacitors 10.

[0090] In some embodiments, the first dimension of the first electrode 12 is less than 0.5 mm.

[0091] The structure of the capacitor 10 provided in the embodiment of the present application is still applicable when the width of the capacitor 10 is less than 0.5 mm, and is applicable to capacitors 10 of various sizes.

[0092] Figure 7 A schematic diagram of a preparation process of a capacitor provided in an embodiment of the present application, Figure 8 A schematic diagram of a portion of the preparation process of the capacitor provided in an embodiment of the present application.

[0093] The present application also provides a method for preparing the capacitor 10. Figure 7 As shown, including:

[0094] S1. Ingredients.

[0095] Ceramic materials, adhesives, solvents, etc. are ball-milled in a certain proportion for a certain period of time to form ceramic slurry.

[0096] S2: Casting.

[0097] The ceramic slurry is passed through the pouring port of the casting machine and coated on the circulating polyethylene terephthalate (PET) film to form a uniform thin layer of slurry. It then passes through the hot air zone (to evaporate most of the solvent in the slurry) and is dried to obtain a dielectric film (ceramic diaphragm).

[0098] S3: Printing.

[0099] The second electrode 112 slurry is printed onto the dielectric film by a screen printing plate according to the process requirements.

[0100] S7: Lamination.

[0101] The dielectric films printed with the second electrode are stacked together according to the designed offset requirements, and upper and lower protective layer films are made to form a capacitor body stack (Bar), which includes multiple layers of dielectric films with the second electrode 112 printed on the surface.

[0102] S5: Lamination.

[0103] The capacitor body is stacked in a laminating bag, vacuum-encapsulated, and then pressurized by isostatic pressing to make the layers of the capacitor body stack more tightly and tightly bonded.

[0104] S6: Cutting.

[0105] The capacitor body stack is cut to form a plurality of independent capacitor embryos. Each capacitor embryo includes a stacked dielectric layer 111 and a second electrode 112 located on the surface of the dielectric layer 111. Figure 8 As shown, the fourth dimension s4 of the capacitor embryo is greater than the fifth dimension s5 of the capacitor embryo. The fourth dimension s4 is the dimension of the dielectric layer stacking direction in the capacitor embryo, and the fifth dimension s5 is the dimension of the second electrode 12 in the capacitor embryo in the width direction.

[0106] The length direction of the second electrode 112 is the direction from one second electrode 112 to another second electrode 112. After the first electrode 12 is formed, the length direction of the second electrode 112 is the direction from one first electrode 12 to another first electrode 12. The width direction of the second electrode 112 intersects with the length direction. In some embodiments, the length of the second electrode 112 may be equal to the width, but the length direction and the width direction are always as described above.

[0107] S7. Debonding.

[0108] The capacitor embryo is placed on a firing plate and baked at a high temperature according to a certain temperature curve (the highest temperature is generally around 400°C) to remove organic substances such as adhesives in the capacitor body 11, so as to avoid rapid volatilization of organic substances during firing, causing product stratification and cracking, to ensure that a good capacitor embryo with a desired shape is fired, and to eliminate the reducing effect of the adhesive during firing.

[0109] S8: Sintering.

[0110] The capacitor green body after debinding is subjected to high temperature treatment, and the sintering temperature is generally between 1140℃ and 1340℃, so as to improve the mechanical strength of the capacitor green body and optimize the electrical performance of the capacitor green body.

[0111] S9: Chamfer.

[0112] The sintered capacitor embryo is placed in a chamfering pot and moved by ball milling, planetary milling, etc. to form a smooth surface to ensure that the second electrode 112 is fully exposed at both ends of the capacitor embryo in a direction parallel to the length of the second electrode 112 to process the capacitor body 11.

[0113] S10: Capping (or termination).

[0114] The first electrode slurry is coated on the two ends of the exposed second electrode 112 of the capacitor body 11 along a direction parallel to the length of the second electrode 112, or the two ends of the exposed second electrode 112 of the capacitor body 11 are dipped into the first electrode slurry respectively, or the first electrode slurry is sputtered onto the two ends of the exposed second electrode 112 of the capacitor body 11 by a sputtering process to form the first electrode 12.

[0115] S11: Burning end.

[0116] The sealed product is sintered at a low temperature to ensure the connection between the second electrode 112 and the first electrode 12 , and to ensure that the first electrode 12 and the dielectric layer 111 in the capacitor body 11 have a certain bonding strength.

[0117] S12: End processing.

[0118] A nickel layer is plated on the first electrode 12 , and then a tin layer is plated on the nickel layer, so as to manufacture the capacitor 10 .

[0119] S13: Testing.

[0120] The electrical properties of the capacitor 10 are tested and defective products are removed.

[0121] S14: Positioning.

[0122] The capacitor 10 is placed on a carrier (such as a conveyor belt), such as Figure 8As shown, the surface where the fourth dimension s4 of the capacitor 10 is located is parallel to the carrier.

[0123] For example, the capacitor 10 is vibrated to make the capacitor 10 with its small surface in contact with the carrier (vertical) fall down and become the capacitor with its large surface in contact with the carrier (horizontal). The capacitor 10 with its large surface in contact with the carrier (horizontal) does not change its position.

[0124] The fourth size s4 of the capacitor green sheet is the fourth size s4 of the capacitor 10, which is the first size s1 of the capacitor 10. The fifth size s5 of the capacitor green sheet is the fifth size s5 of the capacitor 10, which is the second size s2 of the capacitor 10.

[0125] S15: Taping.

[0126] The capacitors 10 are packed in paper tape or plastic bags according to the size and quantity requirements.

[0127] S16: Packaging.

[0128] The taped capacitor 10 is placed in an outer package.

[0129] Of course, the processing technology of the capacitor 10 is not limited thereto. In other embodiments, step S7 to step S8 may be placed as a whole between steps S11 and S12.

[0130] Fig. 9 A schematic diagram of the structure of a semiconductor component provided in an embodiment of the present application.

[0131] The present application also provides a semiconductor component, such as Fig. 9 As shown, the semiconductor component includes a carrier and a capacitor 10 .

[0132] The carrier board can be any substrate having a signal transmission function, and for example, the carrier board is a circuit board. In the embodiment of the present application, the carrier board is a circuit board 20 as an example for illustration.

[0133] The circuit board can be a hard circuit board, a flexible circuit board, or a combination of hard and soft circuit boards. The circuit board can use FR-4 dielectric board, Rogers dielectric board, or a mixed dielectric board of FR-4 and Rogers, etc. Here, FR-4 is a code for a flame retardant material grade, and Rogers dielectric board is a high-frequency board.

[0134] The capacitor 10 is disposed on a circuit board 20, and the capacitor 10 is coupled to the circuit board 20. For example, a first surface a1 of a first electrode 12 in the capacitor 10 is coupled to the circuit board 20. The dielectric layer 111 and the second electrode 112 in the capacitor 10 both intersect with the circuit board 20. In some embodiments, the dielectric layer 111 and the second electrode 112 are both perpendicular to the circuit board 20.

[0135] In the embodiment of the present application, "vertical" means that the angle between the dielectric layer 111 and the circuit board 20 is within a preset range. For example, the preset range is [75°, 110°]. For example, the angle between the dielectric layer 111 and the circuit board 20 is 80°, 85°, 86°, 87°, 88°, 89°, 90°, 91°, 92°, 93°, 94°, 95°, 96°, 97°, 100° or 105°.

[0136] In the capacitor 10 provided in the embodiment of the present application, the first surface a1 of the first electrode 12 intersects with the dielectric layer 111, and the second surface a2 is parallel to the dielectric layer 111. By setting the area of ​​the first surface a1 of the first electrode 12 to be larger than the area of ​​the second surface a2, the first surface a1 for coupling with the carrier can be clearly distinguished. Then, in the process of preparing the capacitor 10, each capacitor 10 can be directly placed in the expected position, and there is no or little random placement phenomenon to limit the patch position of the capacitor 10. In this way, when the capacitor 10 is assembled with the carrier, the shapes of the first surface a1 and the second surface a2 of the capacitor 10 are different, and the capacitors 10 are placed in the expected position, so the first surface a1 of the capacitor 10 can be identified, thereby ensuring that the stack of the dielectric layer 111 and the second electrode 112 of the capacitor 10 is placed to intersect (for example, vertically) with the carrier. In this way, even when an electric field is applied to the first electrode 12, the dielectric layer 111 will expand in the direction of the applied electric field and shrink in a direction perpendicular to the applied electric field, and the capacitor 10 will still vibrate during operation. However, the stacking direction of the dielectric layer 111 intersects with the carrier, and the vibration direction of the capacitor 10 is parallel to the carrier, which can reduce the impact of the vibration of the capacitor 10 on the carrier, so as to suppress the "plate vibration" problem of the carrier.

[0137] It should be explained here that the electronic device provided in the embodiment of the present application includes any of the above-mentioned capacitors 10 and a shell. The capacitor 10 can be arranged in the shell after forming a semiconductor component with a carrier board. The capacitor 10 can also be arranged in the shell in other ways, and the embodiment of the present application is not limited to this.

[0138] Below, several application scenarios of the capacitor 10 provided in the embodiments of the present application are exemplified.

[0139] Fig.10An architecture diagram of a radio frequency front-end module provided in an embodiment of the present application.

[0140] In some application scenarios, the capacitor 10 can be used as Fig.10 The filter matching capacitor of the RF power supply in the RF front-end module in the 4G / 5G scenario shown. The capacitance of the capacitor 10 can be, for example, 1uF, and the size of the capacitor 10 can be, for example, British "0201". The RF front-end module illustrated in the embodiment of the present application can be applied to the mobile communication module 150 of the above-mentioned electronic device 100, for example.

[0141] The RF front-end module may include a transmitting channel and a receiving channel, wherein the transmitting channel includes a power amplifier (PA) and a transmitting channel filter, wherein the RF output of the PA is coupled to the input of the transmitting channel filter. The receiving channel includes a low noise amplifier (LNA) and a receiving channel filter, wherein the output of the receiving channel filter is coupled to the RF input of the LNA.

[0142] The duplexer is responsible for duplex switching of the frequency division duplex system and filtering of RF signals in the receiving channel / transmitting channel, and the RF switch is responsible for switching between the receiving channel and the transmitting channel.

[0143] The baseband signal is transmitted to the transmission channel through the transceiver. The transmission channel amplifies the received RF signal and outputs it to the antenna, which transmits it through the antenna. The PA is responsible for amplifying the RF signal of the transmission channel, and the transmission channel filter is responsible for filtering the RF signal of the transmission channel.

[0144] In the transmission phase, the PA needs to work and needs to be powered by an RF power supply to ensure the transmission power. In the reception phase or during the communication subframe gap, the PA does not need to work, so the RF power supply can be turned off to save power. Since the RF power supply is frequently turned on and off, the periodic large voltage difference will cause the external capacitor 10 to produce an inverse piezoelectric effect, thereby generating vibration and causing "plate vibration".

[0145] In other application scenarios, capacitor 10 can be used as an external filter matching capacitor for battery power supply (VBAT) and main power supply (VBAT_SYS) in 2G scenarios. The capacitance of capacitor 10 can be, for example, 4.7uF or 10uF, and the size of capacitor 10 can be, for example, British "0402". Or the capacitance of capacitor 10 can be, for example, 22uF, and the size of capacitor 10 can be, for example, British "0603". Battery power supply (VBAT) and main power supply (VBAT_SYS) can be applied to the power management module 141 of the above-mentioned electronic device 100, for example.

[0146] The time division multiple access (TDMA) of the global system for mobile communications (GSM) has a time slot of 577uS, and each frame has 8 time slots. The length of each frame is 577us×8=4.616ms, that is, the frequency is 216.6HZ. Due to the working principle of the GSM standard, the PA will have a burst of large current demand (about 1.5A-2A) every time it transmits. The power circuit of the electronic device will transmit this noise to the entire circuit board, resulting in a voltage drop on VBAT and VBAT_SYS, and all the filter matching capacitors externally mounted on the power supply will produce "board vibration".

[0147] In some other application scenarios, the capacitor 10 can be used as a filter capacitor for the rectified voltage (Vrect) in wireless charging. The capacitance of the capacitor 10 can be, for example, 10uF, and the size of the capacitor 10 can be, for example, British "0603". The rectified voltage (Vrect) can be applied to the charging management module 140 of the electronic device 100.

[0148] During wireless charging, the voltage received by the electronic device is the power voltage of electromagnetic induction superimposed on the voltage obtained (polling) by the wireless charging communication protocol. After full-bridge rectification, the power voltage is rectified into DC, but the voltage polled by the wireless charging communication protocol is not rectified, resulting in "board vibration".

[0149] The capacitor 10 provided in the embodiment of the present application can be applied to a variety of scenarios. Since the dielectric layer 111 of the capacitor 10 provided in the embodiment of the present application is perpendicular to the circuit board in the electronic device, the vibration direction of the capacitor 10 is also perpendicular to the circuit board. Therefore, the resonance of the circuit board is small, which can effectively suppress the "board vibration" problem caused by the vibration of the capacitor 10, and can effectively improve the performance of the electronic device.

[0150] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor component, characterized in that: include: Carrier board; A capacitor, the capacitor comprising a capacitor body and a first electrode, wherein the first electrodes are respectively disposed at two opposite ends of the capacitor body; The capacitor body comprises a plurality of dielectric layers and a plurality of second electrodes; the plurality of dielectric layers are stacked and intersect with the carrier; the second electrode is arranged between two adjacent dielectric layers, the second electrodes of two adjacent layers are staggered, and the second electrodes of two adjacent layers are coupled to the first electrodes located on different sides; The first electrode includes a first surface and a second surface, the first surface intersects with the dielectric layer and is parallel to the carrier, the second surface is parallel to the dielectric layer, and the capacitor is coupled to the carrier through the first surface; the area of ​​the first surface is greater than the area of ​​the second surface.

2. The semiconductor component according to claim 1, characterized in that A first dimension of the first electrode along a first direction is greater than a second dimension of the first electrode along a second direction; the first direction is a direction in which the multi-layer dielectric layers are stacked, and the second direction intersects with the first direction.

3. The semiconductor component according to claim 2, characterized in that The second direction also intersects the carrier.

4. The semiconductor component according to claim 2 or 3, characterized in that The first size is more than twice the second size.

5. The semiconductor component according to any one of claims 2 to 4, characterized in that: The first dimension is less than 0.5 mm.

6. The semiconductor component according to any one of claims 1 to 5, characterized in that: The first surface is a rectangle, and the first size is the size of a long side of the rectangle.

7. The semiconductor component according to any one of claims 1 to 6, characterized in that: The dielectric layer is perpendicular to the carrier board.

8. A capacitor, characterized in that: include: A capacitor body and a first electrode; the first electrodes are respectively disposed at two opposite ends of the capacitor body; The capacitor body comprises a plurality of dielectric layers and a plurality of second electrodes; the plurality of dielectric layers are stacked along a first direction; the second electrode is arranged between two adjacent dielectric layers, the second electrodes of two adjacent layers are staggered, and the second electrodes of two adjacent layers are coupled to the first electrodes located on different sides; The first electrode comprises a first surface and a second surface, the first surface intersects with the dielectric layer, the first surfaces of the two first electrodes are located in the same plane, and the second surface is parallel to the dielectric layer; An area of ​​the first surface is greater than an area of ​​the second surface.

9. An electronic device, characterized in that: include: A housing and a semiconductor component, wherein the semiconductor component is arranged in the housing; the semiconductor component comprises the semiconductor component according to any one of claims 1 to 7; or, A shell and a capacitor, wherein the capacitor is arranged in the shell; the capacitor comprises the capacitor according to claim 8.

10. A method for preparing a capacitor, characterized in that: include: Forming a capacitor body stack, wherein the capacitor body stack includes a plurality of dielectric films with second electrodes printed on the surface; The capacitor body stack is cut to form a plurality of capacitor bodies; the fourth dimension of the capacitor body is greater than the fifth dimension of the capacitor body, the fourth dimension is the dimension in the dielectric film stacking direction, and the fifth dimension is the dimension in the second electrode width direction; forming first electrodes at two ends of the capacitor body in a direction parallel to the length of the second electrode to form a capacitor; Positioning the capacitor on a carrier so that a surface of the capacitor where the fourth dimension is located is parallel to the carrier; The capacitor is subjected to a taping process.

11. The preparation method according to claim 10, characterized in that: Performing a positioning process on the capacitor includes: performing a vibration screening process on the capacitor.

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