Semiconductor device and forming method thereof

Abstract

In one embodiment, a method of forming a semiconductor device includes forming a first opening in a semiconductor substrate, the first opening having an annular shape in a plan view; forming a dielectric protection ring in the first opening; forming an active device along the first surface of the semiconductor substrate; forming a first metallization layer over the active device; forming a second opening through the semiconductor substrate, the second opening being adjacent to the annular shape of the dielectric guard ring; forming a conductive through hole in the second opening; and forming a second metallization layer over the first metallization layer. The embodiment of the invention also relates to a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and more specifically, to semiconductor devices and methods for forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the increase in integration density comes from iterative reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, the need for smaller and more creative manufacturing technologies for semiconductor dies has emerged. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a first opening in a semiconductor substrate, wherein the first opening has an annular shape in a plan view; forming a dielectric protection ring in the first opening; forming an active device along a first surface of the semiconductor substrate; forming a first metallization layer above the active device; forming a second opening through the semiconductor substrate, wherein the second opening is adjacent to the annular shape of the dielectric protection ring; forming a conductive through-hole in the second opening; and forming a second metallization layer above the first metallization layer.

[0004] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: an active device along a first surface of a semiconductor substrate; a first metallization layer located above the active device and electrically connected to the active device, the first metallization layer comprising a conductive component embedded in a first dielectric layer; a through via extending through the semiconductor substrate; a second metallization layer located above the first metallization layer and the through via and electrically connected to the first metallization layer and the through via; and a dielectric guard ring embedded in the semiconductor substrate, wherein in a plan view, the dielectric guard ring surrounds the through via.

[0005] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: an active device along the front side of a semiconductor substrate, the semiconductor substrate having a thickness; a through via embedded in the semiconductor substrate, the through via having a first width at the front side, and the through via having a first height within the semiconductor substrate; a dielectric guard ring embedded in the semiconductor substrate and surrounding the through via, the dielectric guard ring having a second width at a position closest to the front side or at the front side, and the dielectric guard ring having a second height; and a metallization layer located above the semiconductor substrate, the metallization layer being electrically connected to the active device and the through via. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6 , Figure 7 , Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 9A , Fig. 9B , Fig. 9C ,and Fig.9D are cross-sectional and plan views of intermediate steps during a process of forming a semiconductor structure according to various embodiments;

[0008] Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig. 15C ,and Fig.15D are cross-sectional and plan views of intermediate steps during a process of forming a semiconductor structure according to various embodiments;

[0009] Fig.16 is a cross-sectional view of an intermediate stage during a process of forming a semiconductor structure according to various embodiments;

[0010] Fig.17 is a cross-sectional view of an intermediate stage during a process of forming a semiconductor structure according to various embodiments. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," etc. may be used herein to easily describe the relationship of one element or component to another (or additional) elements or components as shown in the drawings. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0013] According to some embodiments, a semiconductor die or wafer is formed, and one or more through-holes are formed through the die or wafer, for example, through the semiconductor substrate of the die or wafer. The through-holes can be used to electrically connect components on opposite sides of the semiconductor substrate, and allow multiple dies to be stacked to form a 3D package or a 3D integrated circuit (3DIC). A dielectric protection ring is formed in the semiconductor substrate to surround the through-holes. The dielectric protection ring provides a buffer between the through-holes and the active devices formed along the semiconductor substrate. In particular, the dielectric protection ring is used to absorb heat that may be dissipated from the through-holes to the active devices. The large difference in the coefficient of thermal expansion (CTE) between the material of the through-hole and the material of the semiconductor substrate may affect or violate the performance of proximal active devices and circuits. However, the dielectric protection ring can alleviate these problems by making the CTE of the material of the dielectric protection ring closer to the CTE of the material of the semiconductor substrate. The resulting semiconductor die has improved performance and reliability.

[0014] According to some embodiments, Figure 1A and Figure 1BA cross-sectional view and a plan view of a semiconductor substrate 60 at an intermediate stage of forming a semiconductor structure 50 are provided, respectively. The semiconductor substrate 60 may be doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 60 may include other semiconductor materials, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates, such as multilayer substrates or gradient substrates, may also be used. The semiconductor structure 50 may be manufactured at the wafer level. For example, the semiconductor structure 50 shown may represent a single integrated circuit die or semiconductor device within a wafer (e.g., among many integrated circuit dies or semiconductor devices).

[0015] According to various embodiments, a guard ring 52 is formed in a semiconductor substrate 60. The guard ring 52 will surround a through via (see FIG. 3A to FIG. 5B ). According to various embodiments, the guard ring includes a dielectric material and may be referred to as a dielectric guard ring or an insulating guard ring. Note that Figure 1A and Figure 1B and the subsequent FIG. 2A to FIG. 8D , Figures 10 to 17 One guard ring 52 is shown (eg, surrounding one through via), however, any number of guard rings 52 and through vias may be used in the semiconductor structure 50 .

[0016] As described and illustrated in more detail below, the guard ring 52 is located in an area that will be around the through via that is subsequently formed. This area can remain free of electronic components. Additionally, this area can be referred to as a shielding zone (KOZ) 102K that surrounds the through via (e.g., currently indicated as through via zone 102R). According to various embodiments, the shielding zone can have a width W0 (e.g., spaced apart by a shielding distance) by which the closest device 62 is spaced apart from the through via zone 102R (e.g., where the through via is subsequently formed).

[0017] The semiconductor substrate 60 may be etched using appropriate photolithography and etching techniques (e.g., anisotropic reactive ion etching (RIE) using fluorocarbons) to form an opening for the guard ring 52. A dielectric material may be deposited to fill the opening. For example, the dielectric material may include an oxide or a nitride, such as silicon oxide, silicon oxycarbide, silicon oxynitride, silicon nitride, etc., or a combination thereof. Any excess dielectric material above the semiconductor substrate 60 outside the opening may be removed by a planarization process, such as a chemical mechanical polishing (CMP) process, thereby forming a top surface of the guard ring 52 that is substantially coplanar with the semiconductor substrate 60.

[0018] refer to Figure 1B , a top plan view shows the semiconductor structure 50 at the uppermost portion of the semiconductor substrate 60. As shown, the guard ring 52 forms concentric rings around the through-hole region 102R within the shielding region 102K. The guard ring 52 is shown as a rectangle (e.g., a square). However, the guard ring 52 can be any suitable polygon (e.g., a square, a hexagon, an octagon, etc.) or elliptical (e.g., a circle) (see FIG. 8B to FIG. 8D ). In addition, the shielding region 102K is shown as a concentric circle surrounding the through via region 102R. However, the shielding region 102K may be any suitable shape, such as a rectangular shape (eg, a square).

[0019] exist Figure 2A and Figure 2B In the embodiment of the present invention, the device 62 is formed at the active surface of the semiconductor substrate 60. The device 62 can be an electronic component such as an active device and a passive device. For example, the device 62 can be a transistor, a diode, a capacitor, a resistor, etc. formed by any suitable formation method. The devices 62 can be interconnected to form, for example, a memory device or a logic device on the semiconductor structure 50. In some embodiments, the guard ring 52 can be formed during various steps of forming the device 62 or between various steps of forming the device 62. For example, the opening for the guard ring 52 can be etched during or after forming the isolation region or the source / drain region of the transistor.

[0020] One or more interlayer dielectric (ILD) layers 64 are formed on the semiconductor substrate 60, and conductive features, such as contact plugs 66, are formed to be physically and electrically connected to the device 62. The ILD layer 64 may be formed by any suitable dielectric material, such as an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc., a nitride such as silicon nitride, or the like. The ILD layer 64 may be formed by any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, and / or the like, or a combination thereof. The conductive features in the ILD layer 64 may be formed by any suitable process, such as deposition, damascene (e.g., single damascene, dual damascene, etc.), etc., or a combination thereof.

[0021] In addition, a first metallization layer M1 is formed over the semiconductor substrate 60 and over the ILD layer 64. The first metallization layer M1 is the lower portion of the interconnect structure 68, wherein the second metallization layer M2 is subsequently formed (see Figure 6). The interconnect structure 68 electrically connects the devices 62 to form an integrated circuit. The first metallization layer M1 includes conductive components 72 (e.g., conductive vias 72V and conductive lines 72L) embedded in an inter-metal dielectric (IMD) layer 74 (not shown separately). In addition to providing insulation between the various conductive elements, the IMD layer 74 may also include one or more dielectric etch stop layers (not shown separately) to control the etching process for forming openings in the IMD layer 74. Typically, the via 72V conducts current vertically and is used to electrically connect two other conductive components 72 (e.g., conductive lines 72L) located at vertically adjacent levels, while the conductive lines 72L conduct current laterally and are used to distribute electrical signals and power within a level.

[0022] Although two layers of conductive components 72 (e.g., two layers of wires 72L) are shown in the first metallization layer M1, it should be understood that more or fewer layers may be formed. Each first metallization layer M1 includes a metallization pattern of a wire 72L in a corresponding IMD layer 74. The conductive component 72 is electrically connected to the device 62 along the semiconductor substrate 60. The first metallization layer M1 of the interconnect structure 68 may be formed by a damascene process such as a single damascene process, a dual damascene process, etc. In the illustrated embodiment, the wire 72L at the bottom of the conductive component 72 connects the contact plug 66 to the other conductive components 72, and the via 72V connects the wire 72L at the level below the via 72V to the wire 72L above the via 72V (e.g., a pair of wires 72L may be connected by the via 72V). Some embodiments may adopt different schemes. For example, the conductive via 72V may be in the first metallization layer M1 between the contact plug 66 and the conductive component 72. In some embodiments, contact plugs 66 are formed through the ILD layer 64 before or during the formation of the metallization layer M1 .

[0023] Still reference Figure 2A and Figure 2B, the first metallization layer M1 can be formed using, for example, a damascene process flow. The technique for depositing the dielectric stack for the IMD layer 74 can be the same or similar to the technique for forming the ILD layer 64. Each of the IMD layers 74 can be patterned using appropriate photolithography and etching techniques (e.g., anisotropic RIE using fluorocarbons) to form openings for each of the wires 72L and / or vias 72V. A number of conductive materials can be deposited to fill the trenches of the conductive features 72 forming the first metallization layer M1. For example, the openings can first be lined with one or more pads and then filled with a conductive filling layer. A conductive diffusion barrier liner can be formed over the sidewalls and bottom surface of the trench. Any excess conductive material above the IMD layer 74 outside the opening can be removed by a planarization process (e.g., CMP) to form a top surface including a dielectric region of the IMD layer 74, the dielectric region of the IMD layer 74 being substantially coplanar with the conductive features 72. As a result, the first metallization layer M1 includes conductive features 72 (eg, conductive lines 72L and vias 72V) embedded in the IMD layer 74 .

[0024] In some embodiments, one or more layers of the first metallization layer M1 may be formed using, for example, a dual damascene process flow. First, a dielectric stack is formed to form the IMD layer 74 using materials and methods similar to those described above. Next, openings for vias and wires are formed in the IMD layer 74 using appropriate photolithography and etching techniques. The openings for the vias may be vertical holes extending through the IMD layer 74 to expose the top surface of the lower conductive component 72 (e.g., the wire 72L at the bottom of the first metallization layer M1), while the openings for the wire 72L may be longitudinal grooves formed in the upper portion of the IMD layer 74. The openings may be formed using a via first process or a via last process.

[0025] Several conductive materials may be deposited to fill the holes and trenches to simultaneously form a layer of conductive lines 72L and vias 72V of the first metallization layer M1. The conductive lines 72L and vias 72V may be formed using materials and methods similar to those described above. Any excess conductive material above the IMD 74 outside the openings may be removed by a planarization process (e.g., CMP) to form a top surface including a dielectric region of the IMD layer 74 that is substantially coplanar with the conductive features 72 of the first metallization layer M1. As a result, the first metallization layer M1 includes a layer of multiple conductive features 72 embedded in multiple IMD layers 74.

[0026] refer to Figure 2B, a top plan view shows the semiconductor structure 50 at the uppermost portion of the semiconductor substrate 60. As shown, the guard ring 52 forms concentric rings around the through-hole region 102R within the shielding region 102K. In addition, the device 62 is located outside the shielding region 102K. Although the first metallization layer M1 is not in the Figure 2B , but it should be understood that the conductive member 72 may also be located outside the shielding area 102.

[0027] Although a specific number of devices 62 and the first metallization layer M1 of the interconnect structure 68 for making connections within the semiconductor structure 50 are described and shown, it should be understood that those skilled in the art will understand that the above examples are provided only for illustrative purposes to further explain the application of the present embodiment. These descriptions and illustrations are not meant to limit the present embodiment in any way.

[0028] FIG. 3A to FIG. 5B The formation of a through via 102 (e.g., a conductive through via) using a through-hole process according to various embodiments is shown. As shown, the through via 102 can extend through the first metallization layer M1 (e.g., the IMD layer 74), the ILD layer 64, and at least a portion of the semiconductor substrate 60. The through via 102 may also be referred to as a through-substrate via, a through-semiconductor via, or a through-silicon via (TSV). The through via 102 can be used for electrical connection of a device that is subsequently connected to the semiconductor structure 50 (e.g., a component located or to be located on an opposite side of the semiconductor substrate 60). For example, the through via 102 can be formed through multiple layers for electrical connection of components formed or connected outside the semiconductor structure 50. Although only one through via 102 is shown for exemplary purposes, any appropriate number of through vias 102 may be formed. In addition, although only a single through via 102 is shown within a single guard ring 52, in some embodiments, multiple through vias 102 may be located within a single shielding guard ring 52. In addition, for illustrative purposes, FIG. 3A to FIG. 5B The through via 102 is shown extending through the first metallization layer M1. In some embodiments, the through via 102 may be formed after forming additional metallization layers, for example, after forming the second metallization layer M2 (see Figure 6 In particular, the through via 102 may be formed to pass through any suitable number of metallization layers.

[0029] exist Figure 3A and Figure 3BIn the embodiment of the present invention, a recess 80 is formed through the IMD layer 74 (e.g., the first metallization layer M1), the ILD layer 64, and into the semiconductor substrate 60. The recess 80 can be formed by applying, exposing, and developing a suitable photoresist (not shown) over the first metallization layer M1 to define a desired pattern of through-holes. One or more etching processes can be used to remove the IMD layer 74, the ILD 64, and the portion of the semiconductor substrate 60 exposed to the desired depth. Other techniques, such as milling, laser techniques, combinations thereof, and / or the like can also be used. The recess 80 can be formed to extend into the semiconductor substrate 60, at least further than the device 62 formed within and / or on the semiconductor substrate 60. In some embodiments, the recess 80 extends to a depth that is less than the entire thickness of the semiconductor substrate 60. In addition, the recess 80 can extend to a depth that is greater than the final desired thickness of the semiconductor substrate 60 (see Fig. 8A ).

[0030] refer to Figure 3B , the top view shows the semiconductor structure 50 at the uppermost portion of the semiconductor substrate 60. As shown, the recess 80 is the location of the through-hole region 102R. Figure 3B In the embodiment of the present invention, the recess 80 may be smaller than the through via region 102 to account for the greater width of the recess 80 in a different cross section (eg, near the top surface of the IMD layer 74 ).

[0031] exist Figure 4A and Figure 4B , after the recess 80 is formed in the semiconductor substrate 60, the recess 80 can be lined with a liner layer. The liner layer can be a plurality of layers, including an adhesion layer 102A and a barrier layer 102B. The adhesion layer 102A can be an oxide formed, for example, from tetraethyl orthosilicate (TEOS) or silicon nitride, although any suitable dielectric material can be used. In some embodiments, a suitable conductive material can be used. The adhesion layer 102A can be conformally deposited and formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other suitable processes, such as physical vapor deposition or thermal processes, can be used alternatively. The adhesion layer 102A can have a thickness in the range of 5nm to 500nm.

[0032] Once the adhesion layer 102A is formed along the sidewalls and bottom of the recess 80, the barrier layer 102B can be conformally deposited in the recess 80 and formed by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, etc., or a combination thereof. The barrier layer 102B can be formed by an oxide, a nitride, or an oxynitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, a combination thereof, and / or the like. However, any suitable material for the barrier layer 102B can be used. In some embodiments, the barrier layer 102B is formed directly along the sidewalls and bottom of the recess 80. The barrier layer 102B can have a thickness in the range of 5nm to 500nm. As described above, the adhesion layer 102A and the barrier layer 102B can be collectively referred to as a liner layer.

[0033] refer to Figure 4B , a top view shows semiconductor structure 50 at the uppermost portion of semiconductor substrate 60. As shown, recess 80 is lined by adhesion layer 102A and barrier layer 102B.

[0034] exist Figure 5A and Figure 5B In the embodiment of the present invention, after forming the liner layer (e.g., the adhesion layer 102A and the barrier layer 102B), the remaining portion of the recess 80 can be filled with a conductive material 102C. The conductive material 102C may include copper, tungsten, cobalt, aluminum, silver, gold, alloys, doped polysilicon, etc., or a combination thereof. The conductive material 102C may be formed by depositing or electroplating copper on a seed layer (not shown), filling and overfilling the recess 80. However, any suitable process such as CVD, PVD, etc. may be used. Once the recess 80 is filled, the excess liner layer, seed layer (if present), and conductive material 102C outside the recess 80 may be removed by a planarization process such as CMP, although any suitable removal process may be used. The remaining portion of the liner layer 102A / 102B and the conductive material 102C forms a through via 102. In some cases, only the conductive material remaining in the recess 80 may be referred to as a through via 102. Thus, the through via 102 may include only the conductive material 102C, or include the conductive material 102C and the barrier layer 102B. In some embodiments, each of the adhesive layer 102A and the barrier layer 102B is a single continuous material extending from the bottom surface of the through via 102 to the top surface of the through via 102. In an embodiment (not specifically shown), the adhesive layer 102A and the barrier layer 102B may be processed to form a hybrid bilayer that may be considered as part of the through via 102.

[0035] As shown, in some embodiments, the through via 102 is not yet exposed at the back side of the semiconductor substrate 60. Instead, the through via 102 is buried in the semiconductor substrate 60. As discussed in more detail below, the through via 102 will be exposed at the back side of the semiconductor substrate 60 in subsequent processing. In other embodiments, the through via 102 is formed through the semiconductor substrate 60.

[0036] exist Figure 6 , a second metallization layer M2 is formed over the first metallization layer M1 to form an upper portion of the interconnect structure 68. Although two layers of the second metallization layer M2 are shown, for simplicity of illustration, the second metallization layer M2 represents any number of layers. Any suitable number of metallization layers may be formed in the interconnect structure 68, such as four to twenty metallization layers in the combined first metallization layer M1 and second metallization layer M2. The second metallization layer M2 includes an IMD layer 78 and a conductive component 76 (e.g., a wire 76L and a via 76V). The materials and processing techniques described above in the context of the first metallization layer M1 may be used to form the second metallization layer M2 (e.g., including similar features).

[0037] In various embodiments, the conductive features 76 of the second metallization layer M2 are electrically connected to the through-via 102. For example, the lowermost conductive feature 76 (e.g., the lowermost conductive line 76L) can be formed along the top surface of the through-via 102 to make an electrical connection. In other embodiments (not specifically shown), the second metallization layer M2 can be electrically connected to the through-via through the conductive via 76V. Similarly, as stated above, a dual damascene process (or a combination of a single damascene process and a dual damascene process) can be used to form the conductive features 76. In some embodiments, the first of these dual damascene processes can include: forming the uppermost via 72V of the first metallization layer M1 (e.g., through the uppermost IMD layer 74) simultaneously with the lowermost conductive line 76L of the second metallization layer M2 (e.g., through the lowermost IMD layer 78).

[0038] exist Figure 7 , the semiconductor structure 50 is connected to the carrier 22 and the release film 24. The carrier 22 may be a glass carrier, a silicon wafer, an organic carrier, etc. According to some embodiments, the carrier 22 may have a circular top view shape. The release film 24 may be a glue and may be formed of a polymer-based material and / or an epoxy-based thermal release material (e.g., a light-to-heat conversion (LTHC) material), which is capable of decomposing under radiation such as a laser beam, so that the carrier 22 can be subsequently disengaged from the overlying structure. According to some embodiments, before the carrier 22 is connected to the semiconductor structure 50, the release film 24 is applied to the carrier 22 by coating.

[0039] exist FIG. 8A to FIG. 8DIn the embodiment, a backside thinning process is performed on the backside of the semiconductor structure 50, wherein the semiconductor substrate 60 is thinned. The backside thinning process may be a grinding process and is performed by a CMP process or a mechanical polishing process. In some embodiments, after the backside thinning process, the through via 102 (e.g., the barrier layer 102B and / or the conductive material 102C) is exposed.

[0040] Benefits may be obtained by the guard ring 52 surrounding the through via 102. In particular, the layout and size of the guard ring 52 relative to the corresponding through via 102 provide advantages for the performance of the resulting semiconductor structure 50. In various embodiments, the height H1 of the through via 102 within the semiconductor substrate 60 (e.g., the thickness of the semiconductor substrate 60 after thinning) may be greater than the total height H2 of the guard ring 52 (e.g., within the semiconductor substrate 60). For example, the height H1 may be greater than or equal to 5 μm, and the height H2 may be greater than or equal to 0.5 μm. In addition, the ratio H2 / H1 may be in the range of 0.15 to almost 1 (or substantially 1). Note that in embodiments where the ratio is substantially 1, the guard ring 52 may be exposed or nearly exposed by the backside thinning process. In addition, the through via 102 may have a taper angle α1 less than 90°. In addition, the guard ring 52 may have a taper angle α2 less than 90°. In some embodiments, the through via and / or the guard ring are substantially vertical (e.g., a taper angle of 90°). However, any suitable shapes for through vias 102 and guard rings 52 may be used.

[0041] As mentioned above, the shielding region can have a width W0 by which the nearest device 62 is separated from the through-via 102. In addition, the through-via 102 and the guard ring 52 can have similar proportions. For example, the ratio of the height H1 to the width W1 of the through-via 102 can be in the range of 2 to 20, and the ratio of the height H2 to the width W2 of the guard ring 52 can be in the range of 2 to 20. In addition, the guard ring 52 can be separated from the through-via 102 by a width W3. In this way, the ratio W0 / W1 can be in the range of 0.2 to 1.2, the ratio W3 / W0 can be greater than 0 (e.g., in the range of 0.05 to 0.2), and the ratio W2 / W0 can be in the range of 0.1 to 0.5. These dimensions ensure a sufficiently large distance between various features to reduce expansion issues associated with various CTE mismatches (e.g., CTE gaps between adjacent components). In turn, these dimensions ensure close enough distances between the various features to allow the guard ring 52 to act as a buffer and mitigate issues particularly associated with CTE mismatch between the through via 102 and the semiconductor substrate 60. For example, the through via 102 (e.g., copper) may have a CTE of 17.3, while the semiconductor substrate 60 (e.g., silicon) may have a CTE of 2.8. However, the guard ring 52 (e.g., silicon oxide) may have a CTE of 0.6. Thus, the smaller thermal expansion of the guard ring 52 compared to the semiconductor substrate 60 also helps to balance the larger thermal expansion of the through via 102 compared to the semiconductor substrate 60.

[0042] refer to FIG. 8B to FIG. 8D , a top view shows the semiconductor structure 50 at the uppermost portion of the semiconductor substrate 60 according to various embodiments where the guard ring 52 concentrically surrounds the through via 102 while being located within the shielding region 102K. As shown, the recess 80 is filled with the adhesive layer 102A, the barrier layer 102B, and the conductive material 102C. For exemplary reasons, Figure 8B A protective ring 52 having a square shape is shown, Figure 8C A guard ring 52 having a hexagonal shape is shown, Fig.8D A guard ring 52 having a circular shape is shown. Note that the dimensions described previously may refer to the position of the guard ring 52 on these embodiments being closest to the through via 102 (e.g., an edge of a polygon), or farthest from the through via 102 (e.g., a corner of a polygon), or in between.

[0043] 9A to 9DA multiple guard ring 52 including an inner guard ring 52A and an outer guard ring 52B according to various embodiments is shown. The multiple guard ring 52 structure can provide similar advantages as described above, although it is particularly useful for through-holes 102 that are at the higher end of the size range or larger. Although two rings of the multiple guard ring 52 are shown, any feasible number of rings can be used. In some embodiments, each ring can have dimensions (e.g., height H2 and width W2) within the ranges described above. For example, the inner guard ring 52A can have a larger value than the value of the outer guard ring 52B. In other embodiments, the inner guard ring 52A and the outer guard ring 52B can have substantially similar values ​​for those dimensions.

[0044] refer to FIG. 9B to FIG. 9D , a top view shows the semiconductor structure 50 at the uppermost portion of the semiconductor substrate 60 according to various embodiments in which multiple guard rings 52 concentrically surround the through via 102 while being located within the shielding region 102K. For exemplary reasons, Fig. 9B A multiple guard ring 52 having a square shape is shown, Fig. 9C A multiple guard ring 52 having a hexagonal shape is shown, Fig.9D Multiple guard rings 52 are shown having circular shapes. Additionally, any combination of these shapes may be used with respect to the inner guard rings 52A and the outer guard rings 52B.

[0045] Figures 10 to 15D 1 shows an intermediate step in a via extension process for forming a semiconductor structure 50 including a through via 102 and a guard ring 52 according to various embodiments. Please note that similar features may be combined as above unless otherwise specified. FIG. 1A to FIG. 9D The described manner is similarly formed.

[0046] exist Fig.10 In the embodiment of the present invention, device 62 is formed at the active surface of semiconductor substrate 60. Device 62 can be an electronic component such as an active device and a passive device. For example, device 62 can be a transistor, a diode, a capacitor, a resistor, etc. formed by any suitable formation method. Device 62 can be interconnected to form, for example, a memory device or a logic device on semiconductor structure 50.

[0047] An ILD layer 64 is formed on the semiconductor substrate 60, and conductive features, such as contact plugs 66, are formed to be physically and electrically connected to the device 62. The ILD layer 64 may be formed by any suitable dielectric material, such as an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc., a nitride such as silicon nitride, or the like. The ILD layer 64 may be formed by any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, and / or the like, or a combination thereof. The conductive features in the ILD layer 64 may be formed by any suitable process, such as deposition, damascene (e.g., single damascene, dual damascene, etc.), etc., or a combination thereof.

[0048] In addition, a first metallization layer M1 is formed over the semiconductor substrate 60 and over the ILD layer 64. The first metallization layer M1 is the lower portion of the interconnect structure 68, wherein the second metallization layer M2 is subsequently formed (see Fig.11 ). The interconnect structure 68 electrically connects the devices 62 to form an integrated circuit. The first metallization layer M1 includes conductive components 72 (e.g., conductive vias 72V and conductive lines 72L) embedded in an inter-metal dielectric (IMD) layer 74 (not shown separately). In addition to providing insulation between the various conductive elements, the IMD layer 74 may also include one or more dielectric etch stop layers (not shown separately) to control the etching process for forming openings in the IMD layer 74. Typically, the via 72V conducts current vertically and is used to electrically connect two other conductive components 72 (e.g., conductive lines 72L) located at vertically adjacent levels, while the conductive lines 72L conduct current laterally and are used to distribute electrical signals and power within a level.

[0049] Although two layers of conductive components 72 (e.g., two layers of wires 72L) are shown in the first metallization layer M1, it should be understood that more or fewer layers may be formed. Each first metallization layer M1 includes a metallization pattern of a wire 72L in a corresponding IMD layer 74. The conductive component 72 is electrically connected to the device 62 along the semiconductor substrate 60. The first metallization layer M1 of the interconnect structure 68 may be formed by a damascene process such as a single damascene process, a dual damascene process, etc. In the illustrated embodiment, the wire 72L at the bottom of the conductive component 72 connects the contact plug 66 to the other conductive components 72, and the via 72V connects the wire 72L at the level below the via 72V to the wire 72L above the via 72V (e.g., a pair of wires 72L may be connected by the via 72V). Some embodiments may adopt different schemes. For example, the conductive via 72V may be in the first metallization layer M1 between the contact plug 66 and the conductive component 72. In some embodiments, contact plugs 66 are formed through the ILD layer 64 before or during the formation of the metallization layer M1 .

[0050] Still reference Fig.10 , the first metallization layer M1 can be formed using, for example, a damascene process flow. The technique for depositing the dielectric stack for the IMD layer 74 can be the same or similar to the technique for forming the ILD layer 64. Each of the IMD layers 74 can be patterned using appropriate photolithography and etching techniques (e.g., anisotropic RIE using fluorocarbons) to form openings for each of the wires 72L and / or vias 72V. A number of conductive materials can be deposited to fill the trenches of the conductive features 72 forming the first metallization layer M1. For example, the openings can first be lined with one or more pads and then filled with a conductive filling layer. A conductive diffusion barrier liner can be formed over the sidewalls and bottom surface of the trench. Any excess conductive material above the IMD layer 74 outside the opening can be removed by a planarization process (e.g., CMP) to form a top surface including a dielectric region of the IMD layer 74, the dielectric region of the IMD layer 74 being substantially coplanar with the conductive features 72. As a result, the first metallization layer M1 includes conductive features 72 (eg, conductive lines 72L and vias 72V) embedded in the IMD layer 74 .

[0051] In some embodiments, one or more layers of the first metallization layer M1 may be formed using, for example, a dual damascene process flow. First, a dielectric stack is formed to form the IMD layer 74 using materials and methods similar to those described above. Next, openings for vias and wires are formed in the IMD layer 74 using appropriate photolithography and etching techniques. The openings for the vias may be vertical holes extending through the IMD layer 74 to expose the top surface of the lower conductive component 72 (e.g., the wire 72L at the bottom of the first metallization layer M1), while the openings for the wire 72L may be longitudinal grooves formed in the upper portion of the IMD layer 74. The openings may be formed using a via first process or a via last process.

[0052] Several conductive materials may be deposited to fill the holes and trenches to simultaneously form a layer of conductive lines 72L and vias 72V of the first metallization layer M1. The conductive lines 72L and vias 72V may be formed using materials and methods similar to those described above. Any excess conductive material above the IMD 74 outside the openings may be removed by a planarization process (e.g., CMP) to form a top surface including a dielectric region of the IMD layer 74 that is substantially coplanar with the conductive features 72 of the first metallization layer M1. As a result, the first metallization layer M1 includes a layer of multiple conductive features 72 embedded in multiple IMD layers 74.

[0053] Although the guard ring 52 (and the through via 102) will be formed later through the back side of the semiconductor substrate 60, the through via region 102R, the shielding region 102K, and the device region 62R are marked. Although there are different methods of manufacturing and different orientations of certain components, the components of the present embodiment will follow a similar configuration as described above. For example, the first metallization layer M1 can remain free of conductive features 72 in the through via region 102R and the shielding region 102K. In some embodiments (not specifically shown), the first metallization layer M1 can include conductive features 72 in the through via region 102R to electrically connect to the back through via 102 formed later.

[0054] exist Fig.11 , a second metallization layer M2 is formed over the first metallization layer M1 to form an upper portion of the interconnect structure 68. Although two layers of the second metallization layer M2 are shown, for simplicity of illustration, the second metallization layer M2 represents any number of layers. Any suitable number of metallization layers may be formed in the interconnect structure 68, such as four to twenty metallization layers in the combined first metallization layer M1 and second metallization layer M2. The second metallization layer M2 includes an IMD layer 78 and a conductive component 76 (e.g., a wire 76L and a via 76V). The materials and processing techniques described above in the context of the first metallization layer M1 may be used to form the second metallization layer M2 (e.g., including similar features).

[0055] In various embodiments, the conductive features 76 of the second metallization layer M2 will be electrically connected to the subsequently formed through-via 102. For example, the lowermost conductive feature 76 (e.g., the lowermost conductive line 76L) can be formed along the top surface of the through-via 102 to make an electrical connection. In other embodiments (not specifically shown), the second metallization layer M2 can be electrically connected to the through-via through the conductive via 76V. Similarly, as stated above, a dual damascene process (or a combination of a single damascene process and a dual damascene process) can be used to form the conductive features 76. In some embodiments, the first of these dual damascene processes can include: forming the uppermost via 72V of the first metallization layer M1 (e.g., through the uppermost IMD layer 74) simultaneously with the lowermost conductive line 76L of the second metallization layer M2 (e.g., through the lowermost IMD layer 78).

[0056] exist Fig.12 , the semiconductor structure 50 is connected to the carrier 22 and the release film 24. The carrier 22 may be a glass carrier, a silicon wafer, an organic carrier, etc. According to some embodiments, the carrier 22 may have a circular top view shape. The release film 24 may be glue, and may be formed of a polymer-based material and / or an epoxy-based thermal release material (e.g., a LTHC material), which can be decomposed under radiation such as a laser beam, so that the carrier 22 can be subsequently disengaged from the overlying structure. According to some embodiments, before the carrier 22 is connected to the semiconductor structure 50, the release film 24 is applied to the carrier 22 by coating.

[0057] exist Fig.13 In the embodiment, a backside thinning process is performed on the backside of the semiconductor structure 50, wherein the semiconductor substrate 60 is thinned to a desired thickness. The backside thinning process may be a grinding process, and is performed by a CMP process or a mechanical polishing process.

[0058] exist Fig.14A and Fig. 14B In the embodiment, a guard ring 52 (eg, a backside guard ring) is formed in a semiconductor substrate 60. The guard ring 52 will surround a through-hole via that is subsequently formed. According to various embodiments, the guard ring 52 includes a dielectric material and may be referred to as a dielectric guard ring or an insulating guard ring. Fig.14A and Fig. 14B and the subsequent FIG. 15A to FIG. 17 One guard ring 52 is shown (eg, surrounding one through via), however, any number of guard rings 52 and through vias 102 may be used in the semiconductor structure 50 .

[0059] As previously discussed, the guard ring 52 is located in a region (e.g., shielding zone (KOZ) 102K) that will be around the subsequently formed through via 102, which surrounds the through via 102 (e.g., currently indicated as through via zone 102R). According to various embodiments, the shielding zone may have a width W0 by which the nearest device 62 is spaced apart from the through via zone 102R (e.g., the subsequently formed through via 102).

[0060] The semiconductor substrate 60 may be etched using appropriate photolithography and etching techniques (e.g., RIE using fluorocarbons) to form an opening for the guard ring 52. A dielectric material may be deposited to fill the opening. For example, the dielectric material may include an oxide or a nitride, such as silicon oxide, silicon oxycarbide, silicon oxynitride, silicon nitride, etc., or a combination thereof. Any excess dielectric material above the semiconductor substrate 60 outside the opening may be removed by a planarization process, such as a CMP process, to form a top surface of the guard ring 52 that is substantially coplanar with the semiconductor substrate 60.

[0061] Although guard ring 52 is shown extending to a depth that is the same thickness as semiconductor substrate 60, other depths may be used. For example, guard ring 52 may extend to less than this thickness (see FIG. Fig. 15B ) or greater than this thickness (see Fig. 15C ).

[0062] refer to Fig. 14B , the plan view shows the semiconductor structure 50, although not necessarily at any particular cross-section of the semiconductor substrate 60. Instead, the plan view (and subsequent plan views of this embodiment) show the lateral relationships between various components. The components shown can be in the same horizontal cross-section, or they can be in different cross-sections. As shown, the guard ring 52 forms concentric rings around the through-hole via region 102R within the shielding region 102K. The guard ring 52 is shown as a rectangle (e.g., a square). However, the guard ring 52 can be any suitable polygon (e.g., a square, a hexagon, an octagon, etc.) or elliptical (e.g., a circle) (see FIG. 8B to FIG. 8D ). In addition, the shielding region 102K is shown as a concentric circle surrounding the through via region 102R. However, the shielding region 102K may be any suitable shape, such as a rectangular shape (eg, a square).

[0063] exist Fig.15A and Fig. 15B, a through via 102 is formed using a via post process according to various embodiments. As shown, the through via 102 extends through the back side of the semiconductor substrate 60 and the ILD layer 64, and may further extend through the first metallization layer M1 (e.g., the IMD layer 74) to be electrically connected to the second metallization layer M2. Similar to what is described above, the through via 102 may be used for electrical connection of a device (e.g., a component located or to be located on the opposite side of the semiconductor substrate 60) that is subsequently connected to the semiconductor structure 50. For example, the through via 102 may be formed through multiple layers for electrical connection of components formed or connected outside the semiconductor structure 50. Although only one through via 102 is shown for exemplary purposes, any suitable number of through vias 102 may be formed. In addition, although only a single through via 102 is shown within a single guard ring 52, in some embodiments, multiple through vias 102 may be located within a single shielding guard ring 52. In addition, for illustrative purposes, the through via 102 is shown as extending through the first metallization layer M1. In some embodiments, the through via 102 may be formed to be directly connected to the first metallization layer M1. In particular, the through via 102 may be formed to pass through any suitable number of metallization layers.

[0064] For example, a back recess is formed through the back side of the semiconductor substrate 60. The recess can be formed by applying, exposing, and developing a suitable photoresist (not shown) over the semiconductor substrate 60 to define a desired pattern of through-holes. A first etching process can be used to remove a portion of the semiconductor substrate 60 to expose the ILD layer 64. One or more additional etching processes can be used to extend the recess to a desired depth. Other techniques, such as milling, laser techniques, combinations thereof, and / or the like can also be used. The recess can be formed to extend through the semiconductor substrate 60 and beyond the device 62 (e.g., exposing the wire 72L of the second metallization layer M2).

[0065] In addition, barrier layer 102B may be conformally deposited in the recess without first forming adhesion layer 102A. For example, barrier layer 102B may be formed by CVD, ALD, PVD, thermal oxidation, etc., or a combination thereof. Barrier layer 102B may be formed by oxide, nitride, or oxynitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, a combination thereof, and / or the like. However, any suitable material for barrier layer 102B may be used. In some embodiments, barrier layer 102B is formed directly along the sidewalls and bottom of the recess. Barrier layer 102B may have a thickness in the range of 5 nm to 500 nm. Thus, barrier layer 102B may be the only liner layer. However, any suitable number and type of liner layers may be used for back-side through-hole 102.

[0066] Finally, after forming the liner layer (e.g., barrier layer 102B), the remaining portion of the recess can be filled with conductive material 102C. Conductive material 102C may include copper, tungsten, cobalt, aluminum, silver, gold, alloys, doped polysilicon, etc., or a combination thereof. Conductive material 102C may be formed by depositing or electroplating copper on a seed layer (not shown), filling and overfilling the recess. However, any suitable process such as CVD, PVD, etc. may be used. Once the recess is filled, excess barrier layer 102B, seed layer (if present), and conductive material 102C outside the recess may be removed by a planarization process such as CMP, although any suitable removal process may be used. The remaining portion of barrier layer 102B and conductive material 102C forms a back through-hole via 102. In some cases, only the conductive material remaining in the recess may be referred to as a through-hole via 102. As such, the through via 102 may include only the conductive material 102C, or include the conductive material 102C and the barrier layer 102B.

[0067] Benefits may be obtained by the guard ring 52 surrounding the through via 102, similar to those described above in connection with the previous embodiments. In particular, the layout and size of the guard ring 52 relative to the corresponding through via 102 provide advantages to the performance of the resulting semiconductor structure 50. In various embodiments, the height H1 of the through via 102 within the semiconductor substrate 60 (e.g., the thickness of the semiconductor substrate 60) may be greater than the total height H2 of the guard ring 52 within the semiconductor substrate 60.

[0068] According to various embodiments, the height H1 may be greater than or equal to 5 μm, and the height H2 may be greater than or equal to 0.5 μm. In addition, the ratio H2 / H1 may be in the range of 0.5 to about 1.2 (or substantially 1). For example, Fig.15A An embodiment is shown in which the ratio is substantially 1, Fig. 15B An embodiment is shown in which the ratio is greater than or equal to 0.5 and less than 1, Fig. 15C An embodiment is shown in which the ratio is greater than 1 and less than or equal to 1.2. Similar to the previous embodiment, the through via 102 can have a taper angle α1 less than 90°. In addition, the guard ring 52 can have a taper angle α2 less than 90°. Note that since these features are formed from the back side of the semiconductor substrate 60, the taper angles α1 and α2 are opposite to the previous embodiment. In some embodiments, the through via and / or the guard ring are substantially vertical (e.g., a taper angle of 90°). However, any suitable shape can be used for the through via 102 and the guard ring 52.

[0069] As mentioned above, the shielding region can have a width W0 by which the nearest device 62 is spaced apart from the through via 102. In addition, the through via 102 and the guard ring 52 can have similar proportions. For example, the ratio of the height H1 to the width W1 of the through via 102 can be in the range of 2 to 20, and the ratio of the height H2 to the width W2 of the guard ring 52 can be in the range of 2 to 20. In addition, the guard ring 52 can be spaced apart from the through via 102 by a width W3. In this way, the ratio W0 / W1 can be in the range of 0.2 to 1.2, the ratio W3 / W0 can be greater than 0 (e.g., in the range of 0.05 to 0.2), and the ratio W2 / W0 can be in the range of 0.1 to 0.5. These dimensions ensure a sufficiently large distance between various features to reduce expansion issues associated with various CTE mismatches. In turn, these dimensions ensure close enough distances between the various features to allow the guard ring 52 to act as a buffer and mitigate issues particularly associated with CTE mismatch between the through via 102 and the semiconductor substrate 60 .

[0070] refer to Fig.15D , a plan view shows the semiconductor structure 50, although not necessarily at any particular cross section of the semiconductor substrate 60. Instead, the plan view shows the lateral relationship between the various components. The components shown can be in the same horizontal cross section, or they can be in different cross sections. As shown, the guard ring 52 forms concentric rings around the through-hole area 102R within the shielding area 102K. The guard ring 52 is shown as a rectangle (e.g., a square). However, the guard ring 52 can be any suitable polygon (e.g., a square, a hexagon, an octagon, etc.) or an elliptical shape (e.g., a circle) (see above FIG. 8B to FIG. 8D ). In addition, the shielding region 102K is shown as a concentric circle surrounding the through via region 102R. However, the shielding region 102K may be any suitable shape, such as a rectangular shape (eg, a square).

[0071] In addition, the above FIG. 9B to FIG. 9D A plan view of the present embodiment using multiple guard rings 52 is depicted. FIG. 9B to FIG. 9D Represents the current embodiment, except that the features shown are not necessarily in the same horizontal cross-section.

[0072] Fig.16 and Fig.17 A further embodiment of a semiconductor structure 50 including a through via 102 surrounded by a dielectric guard ring 52 is shown. Fig.16 An embodiment is shown in which the guard ring 52 is formed through the front side of the semiconductor substrate 60 (eg, guard ring first process), while the through via 102 is formed through the back side of the semiconductor substrate 60 (eg, via last process). Fig.17An embodiment is shown in which the through via 102 is formed through the front side of the semiconductor substrate (e.g., a via middle process), while the guard ring 52 is formed through the back side of the semiconductor substrate 60 (e.g., a guard ring later process). The various sizes and configurations for each of these features in these embodiments can follow similar sizes and configurations described above with respect to the previous embodiments.

[0073] Although not specifically shown, the semiconductor structure 50 of any embodiment may be subsequently processed for incorporation into a semiconductor package. For example, any suitable method may be used to form an under-bump metallization layer (UBM) and / or a conductive connector on either side or both sides of the semiconductor structure 50. In some such embodiments, a redistribution structure may be formed before forming the conductive connector. Any suitable method may be used, such as a method similar to those described above in conjunction with forming the interconnect structure 68, to form the redistribution structure. In addition, a singulation process may be implemented by sawing along a scribe line area (not specifically indicated) (e.g., between the die areas of adjacent integrated circuit dies). Sawing causes the die areas to be singulated from one another.

[0074] Embodiments can achieve advantages. In particular, when the CTE mismatch between the through via 102 and the semiconductor substrate 60 may cause performance degradation, forming a dielectric guard ring 52 around the through via 102 according to the disclosed embodiments can improve the performance of the semiconductor structure 50. For example, the guard ring 52 is formed of a dielectric material having a CTE closer to that of the semiconductor substrate 60. In this way, the guard ring 52 provides an insulation barrier and expansion buffer between the through via 102 and the device 62.

[0075] In one embodiment, a method of forming a semiconductor device includes: forming a first opening in a semiconductor substrate, the first opening having an annular shape in a plan view; forming a dielectric guard ring in the first opening; forming an active device along a first surface of the semiconductor substrate; forming a first metallization layer above the active device; forming a second opening through the semiconductor substrate, the second opening being adjacent to the annular shape of the dielectric guard ring; forming a conductive through via in the second opening; and forming a second metallization layer above the first metallization layer. In another embodiment, the first opening is formed through the first surface of the semiconductor substrate. In another embodiment, the second opening is formed through the first surface of the semiconductor substrate. In another embodiment, the first opening is formed through the second surface of the semiconductor substrate, and wherein the second surface is opposite to the first surface. In another embodiment, the second opening is formed through the second surface of the semiconductor substrate, and wherein the second opening exposes the second metallization layer. In another embodiment, after forming the second metallization layer, a first height of the dielectric guard ring within the semiconductor substrate is less than a second height of the through via within the semiconductor substrate. In another embodiment, the first height is greater than two times a first width of the dielectric guard ring, wherein the first width is measured at the first surface of the semiconductor substrate, wherein the second height is greater than two times a second width of the through via, and wherein the second width is measured at the first surface of the semiconductor substrate. In another embodiment, the semiconductor substrate includes a shielding region based on the through via, and wherein the entire dielectric guard ring is located within the shielding region.

[0076] In one embodiment, a semiconductor device includes: an active device along a first surface of a semiconductor substrate; a first metallization layer located above the active device and electrically connected to the active device, the first metallization layer including a conductive feature embedded in a first dielectric layer; a through via extending through the semiconductor substrate; a second metallization layer located above the first metallization layer and the through via and electrically connected to the first metallization layer and the through via; and a dielectric guard ring embedded in the semiconductor substrate, wherein in a plan view, the dielectric guard ring surrounds the through via. In another embodiment, the width of the through via at the first surface is greater than the width of the through via at the second surface of the semiconductor substrate. In another embodiment, the width of the through via at the first surface is less than the width of the through via at the second surface of the semiconductor substrate. In another embodiment, in a plan view, the dielectric guard ring has a polygonal shape. In another embodiment, in a plan view, the dielectric guard ring has a circular shape. In another embodiment, the semiconductor device further includes an additional dielectric guard ring, wherein in a plan view, the additional dielectric guard ring surrounds the dielectric guard ring.

[0077] In one embodiment, a semiconductor device includes: an active device along a front side of a semiconductor substrate, the semiconductor substrate having a thickness; a through-hole via embedded in the semiconductor substrate, the through-hole via having a first width at the front side, and the through-hole via having a first height within the semiconductor substrate; a dielectric guard ring embedded in the semiconductor substrate and surrounding the through-hole via, the dielectric guard ring having a second width at a position closest to the front side or at the front side, and the dielectric guard ring having a second height; and a metallization layer located above the semiconductor substrate, the metallization layer being electrically connected to the active device and the through-hole via. In another embodiment, the second height is greater than the first height. In another embodiment, the first height is equal to the second height. In another embodiment, the first end of the dielectric guard ring is flush with the back side of the semiconductor substrate, and wherein the second height is less than the thickness of the semiconductor substrate. In another embodiment, the active device is a first distance from the through-hole via measured along the front side of the semiconductor substrate, wherein the dielectric guard ring is a second distance from the through-hole via, and wherein the ratio of the second distance to the first distance is between 0.05 and 0.2. In another embodiment, the first ratio of the first height to the first width is substantially the same as the second ratio of the second height to the second width.

[0078] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as the present disclosure. Those skilled in the art should also be aware that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a first opening in a semiconductor substrate, the first opening having a ring shape in a plan view; forming a dielectric guard ring in the first opening; forming active devices along a first surface of the semiconductor substrate; forming a first metallization layer over the active device; forming a second opening through the semiconductor substrate, the second opening being adjacent to the annular shape of the dielectric guard ring; forming a conductive through via in the second opening; as well as A second metallization layer is formed over the first metallization layer.

2. The method according to claim 1, wherein: The first opening is formed through the first surface of the semiconductor substrate.

3. The method according to claim 2, wherein: The second opening is formed through the first surface of the semiconductor substrate.

4. The method according to claim 1, wherein: The first opening is formed through a second surface of the semiconductor substrate, and wherein the second surface is opposite to the first surface.

5. The method according to claim 4, wherein: The second opening is formed through the second surface of the semiconductor substrate, and wherein the second opening exposes the second metallization layer.

6. A semiconductor device comprising: an active device along a first surface of the semiconductor substrate; a first metallization layer located above the active device and electrically connected to the active device, the first metallization layer comprising conductive features embedded in a first dielectric layer; a through via extending through the semiconductor substrate; a second metallization layer located above the first metallization layer and the through via and electrically connected to the first metallization layer and the through via; as well as A dielectric guard ring is embedded in the semiconductor substrate, and in a plan view, the dielectric guard ring surrounds the through via.

7. The semiconductor device according to claim 6, wherein: A width of the through via at the first surface is greater than a width of the through via at the second surface of the semiconductor substrate.

8. The semiconductor device according to claim 6, wherein: A width of the through via at the first surface is smaller than a width of the through via at the second surface of the semiconductor substrate.

9. A semiconductor device comprising: an active device along a front surface of a semiconductor substrate, the semiconductor substrate having a thickness; a through via embedded in the semiconductor substrate, the through via having a first width at the front surface and a first height within the semiconductor substrate; a dielectric guard ring embedded in the semiconductor substrate and surrounding the through-hole, the dielectric guard ring having a second width at a position closest to the front surface or at the front surface, and the dielectric guard ring having a second height; as well as A metallization layer is located above the semiconductor substrate, and the metallization layer is electrically connected to the active device and the through via.

10. The semiconductor device according to claim 9, wherein The active device is a first distance from the through via measured along the front side of the semiconductor substrate, wherein the dielectric guard ring is a second distance from the through via, and wherein a ratio of the second distance to the first distance is between 0.05 and 0.2.

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