Semiconductor test equipment and power supply method thereof

Abstract

A semiconductor test apparatus for simultaneously testing a maximum number of semiconductor chips and a power supply method of the semiconductor test apparatus are provided. The semiconductor test apparatus includes a tester including a power source configured to simultaneously supply power to a plurality of devices under test (DUTs) during a test; and a test board disposed between the tester and the plurality of DUTs, and transmitting power from the power source to the tester, in which the power source includes a plurality of power channels, and each of the plurality of DUTs receives two or more types of power from the power channels, each type of power being power supplied at a corresponding power supply voltage for the DUT, and each type of power being power supplied at a corresponding power supply voltage for the DUT. The power supply shares current among the plurality of power channels and supplies the shared amount of current to each of the plurality of DUTs.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0102290 filed on August 4, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to testing equipment, and more particularly, to a semiconductor testing equipment for simultaneously testing a plurality of semiconductor devices and a power supply method thereof. Background Art

[0004] Typically, the semiconductor manufacturing process includes a fabrication (FAB) process to form multiple semiconductor chips on a wafer and an electrical die sorting (EDS) process to test the electrical characteristics of each semiconductor chip formed on the wafer. The EDS process determines and discards poor / average quality semiconductor chips. This is followed by an assembly process of high-quality semiconductor chip packaging devices determined by the EDS process, where the packaging protects the device from external mechanical, physical and chemical influences.

[0005] Using the EDS process, chips of average / poor quality may be determined by signals output in response to electrical signals received after power and electrical signals are sent to respective chips on a wafer. Summary of the invention

[0006] Embodiments of the inventive concept provide a semiconductor testing apparatus for simultaneously testing a maximum number of semiconductor chips and a power supply method of the semiconductor testing apparatus.

[0007] According to an aspect of the inventive concept, there is provided a semiconductor testing device, comprising:

[0008] A tester circuit, comprising a power supply configured to simultaneously supply power to a plurality of devices under test (DUTs) during testing; and a test board arranged between the tester and the plurality of DUTs and transmitting power from the power supply to the tester, wherein the power supply comprises a plurality of power channels, each of the plurality of DUTs receives two or more types of power from the power channels, each type of power being power supplied to the DUT at a corresponding power supply voltage, and the power supply shares current between the plurality of power channels and supplies the shared current to each of the plurality of DUTs.

[0009] According to another aspect of the inventive concept, there is provided a semiconductor test apparatus, comprising: a tester circuit including a power supply configured to simultaneously supply power to a plurality of devices under test (DUTs) during a test, a test signal transmitter configured to input a test signal to the plurality of DUTs and receive a response signal from the plurality of DUTs, a logic generation determiner circuit configured to generate a test signal and determine a failure of the plurality of DUTs based on the response signal, and a controller configured to control the power supply and the logic generation determiner; and a test board arranged between the tester and the plurality of DUTs, transmitting power of the power supply and a test signal of the test signal transmitter to the plurality of DUTs, and transmitting a response signal from the plurality of DUTs to the test signal transmitter, wherein the power supply includes a plurality of power channels, the plurality of power channels are divided into a plurality of groups, each of the plurality of groups includes a set number of power channels, and each of the plurality of DUTs receives two or more types of power from the power channels, each type of power being power supplied at a corresponding power supply voltage for the DUT, and each of the plurality of groups shares current between the plurality of power channels and supplies the shared current to each of the plurality of DUTs.

[0010] According to another aspect of the inventive concept, there is provided a semiconductor testing device, including: a power supply configured to simultaneously supply power to a plurality of DUTs during testing; a test signal transmitter configured to input test signals to the plurality of DUTs and receive response signals from the plurality of DUTs; a logic generation determiner configured to generate test signals and determine failures of the plurality of DUTs based on the response signals; and a controller configured to control the power supply and the logic generation determiner, wherein the power supply includes a plurality of power channels, the plurality of power channels are divided into a plurality of groups, each of the plurality of groups includes a set number of power channels, and when each of the plurality of DUTs receives two or more types of power from the power channels, each type of power is power supplied to the DUT at a corresponding power supply voltage, each of the plurality of groups shares current between the plurality of power channels and supplies the shared current to each of the plurality of DUTs.

[0011] According to another aspect of the inventive concept, a power supply method for a semiconductor test device is provided, comprising: in a tester including a power supply configured to simultaneously supply power to a plurality of DUTs during testing, when the power supply includes a plurality of power channels, the plurality of power channels are divided into a plurality of groups, each of the plurality of groups includes a set number of power channels, and the power supply is configured to supply two or more types of power to each of the plurality of DUTs, each type of power being power supplied to the DUT at a corresponding power supply voltage; supplying a first current amount to each of the plurality of groups; dividingly inputting the first current amount to the plurality of power channels; and supplying a corresponding current amount to each of the plurality of DUTs through the plurality of power channels, wherein each of the plurality of groups shares current between the plurality of power channels and supplies the shared current to each of the plurality of DUTs. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments will be more clearly understood from the detailed description below in conjunction with the accompanying drawings. Various elements of the same or similar type can be distinguished by appending an underscore / dash to the reference label and a second label (e.g., -1, -2) to distinguish between the same / similar elements, or by appending the second label directly to the reference label. However, if a given description uses only the first reference label, it applies to any of the same / similar elements with the same first reference label, regardless of the second label.

[0013] Figure 1A is a block diagram of a semiconductor testing apparatus according to an embodiment;

[0014] Figure 1B Is used to describe Figure 1A A conceptual diagram of the operation of a power supply of a semiconductor test equipment;

[0015] Figure 2A and Figure 2B is a conceptual diagram for describing the operation of power supply of the semiconductor test equipment of the comparative example;

[0016] Figure 3A , Figure 3B and Figure 3C It is shown Figure 1A A graph showing the number of devices under test (DUT) that can be tested simultaneously according to the amount of current in the semiconductor test apparatus of the embodiment and the semiconductor test apparatus of the comparative example;

[0017] Figure 4A , Figure 4B and Figure 4C It is a specific implementation Figure 1B Circuit diagram of the power supply;

[0018] Figure 5A and Figure 5B It is a specific implementation Figure 1BCircuit diagram of the power supply and conceptual diagram of the switch matrix;

[0019] Fig. 6A , Figure 6B and Figure 6C It is a specific implementation Figure 1B Circuit diagram of the power supply;

[0020] Figure 7 is a flowchart of a power supply method for a semiconductor test device according to an embodiment; and

[0021] Fig. 8A , Figure 8B , Figure 8C , Fig.8D and Fig. 8E A semiconductor test device is shown in detail according to various embodiments Figure 7 Flowchart of a power supply method. DETAILED DESCRIPTION

[0022] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same elements, and redundant descriptions thereof will be omitted.

[0023] Figure 1A is a block diagram of a semiconductor testing apparatus 1000 according to an embodiment, Figure 1B Is used to describe Figure 1A A conceptual diagram of an operation of supplying power to the power supply 110 of the semiconductor testing apparatus 1000.

[0024] Reference Figure 1A and Figure 1B , semiconductor test equipment 1000 (hereinafter, interchangeably referred to as "test equipment 1000") may be referred to as automatic test equipment (ATE), which may operate based on automatic test operations. Test equipment 1000 may basically test logical faults and parameter faults. Logical faults may include faults such as open / short, hard / soft, etc., and parameter faults may include faults such as Icc (e.g., bias current draw), current leakage, setup / hold time, voltage, refresh, etc., out-of-range results.

[0025] The test apparatus 1000 may include a tester circuit ("tester") 100 and a test board 200. The tester 100 may include a power supply 110, a test signal transmitter 120, a logic generation determiner circuit ("determinator") 130, and a controller 140. The power supply 110, the test signal transmitter 120, the logic generation determiner 130, and the controller 140 may correspond to functional classifications of components of the tester 100. For example, the tester 100 may include a test body and a test head as physical components, which may be connected to each other by wiring, etc.

[0026] The power supply 110 can supply power to a plurality of devices under test (DUTs) simultaneously during testing. The DUT can represent a semiconductor device actually tested. The power supply 110 may include a plurality of power channels 112. For example, the power supply 110 may include hundreds to thousands of power channels 112 to supply power to the DUTs simultaneously. However, the number of power channels 112 of the power supply 110 is not limited to the above numerical range. At the same time, the power from the power supply 110 can be supplied to the DUTs through the test board 200.

[0027] In terms of function, the power channel 112 may also be referred to as a digital power supply (DPS) or a programmable power supply (PPS). Figure 1B , for illustration purposes, DPS_1, DPS_2, DPS_3, and DPS_4 are indicated for the first power channel 112-1 to the fourth power channel 112-4 (eg, among hundreds or thousands of power channels 112 in the power supply 110). Figure 1A and Figure 1B The operation of the power supply 110 is described in detail.

[0028] The test signal transmitter 120 may receive a test signal TS from the logic generation determiner 130 and input the test signal TS to the DUT; receive a corresponding response signal RS (e.g., RS_1, RS_2) from the DUT; and transmit the response signal RS to the logic generation determiner 130. The input of the test signal TS and the reception of the response signal RS by the test signal transmitter 120 are performed by the test board 200.

[0029] The logic generation determiner 130 may generate and transmit a test signal TS to the DUT and determine a fault of the DUT based on a response signal RS received from the DUT. The logic generation determiner 130 may transmit the test signal TS to the DUT through the test signal transmitter 120 and receive the response signal RS.

[0030] The controller 140 may control the operations of the power supply 110 and the logic generation determiner 130. In addition, the controller 140 may control the operations of some or all other components in the test apparatus 1000.

[0031] The test board 200 may be arranged between the tester 100 and the DUT and route power from the power supply 110 to the DUT. In addition, the test board 200 may route test signals and response signals from the test signal transmitter 120 and the DUT and route test signals and response signals to the test signal transmitter 120 and the DUT. For example, the test board 200 may include a probe card for testing semiconductor devices in a wafer state. For example, the probe card may be used for wafer aging tests and bare core sorting tests. In addition, the probe card may be used by being mounted on a test head portion of the tester 100. The test board 200 may include an interface board for testing semiconductor devices in a packaged state.

[0032] One aspect of the test equipment 1000 may be its technique for efficiently using the power supply 110. In the following, it is assumed that other resources of the tester 100 are not particularly limited or at least sufficient for the limitation caused by insufficient power channels to power the DUT.

[0033] In the test device 1000, the power supply 110 of the tester 100 may include a power channel 112. The power channel 112 may be divided into a plurality of groups. Each group may include a set number of power channels 112. The number of power channels 112 included in each group may be set according to various standards. For example, when two or more "types of power" are supplied to the DUT, each group may include a number of power channels 112 corresponding to the two or more types of power. Herein, "power type" may be power supplied at a specific voltage level for the DUT. The first type of power may be power supplied at a first power supply voltage of VDD1 (the power supplied is VDD1×I1, where I1 is a current supplied to a DUT terminal providing the voltage VDD1), and the second type of power may be power supplied at a different second power supply voltage of VDD2 (the power supplied is VDD2×I2, where I2 is a current supplied to a DUT terminal providing the voltage VDD2). Below, for the convenience of description, an example in which the power supply 110 includes four power channels 112 and supplies two different types of power to the DUT will be described.

[0034] For example, Figure 1B As shown, the power supply 110 may include first to fourth power channels 112-1 to 112-4. In addition, based on supplying two different types of power to the DUT, the first to fourth power channels 112-1 to 112-4 may be divided into two groups, namely, a first group Group_A and a second group Group_B. In detail, the first group Group_A may include the first power channel 112-1 and the second power channel 112-2, and the second group Group_B may include the third power channel 112-3 and the fourth power channel 112-4.

[0035] In the semiconductor testing device 1000, the power supply 110 can share current output between the power channels 112 in the group. For example, the first power channel 112-1 and the second power channel 112-2 can share the current output by the first group Group_A, and the third power channel 112-3 and the fourth power channel 112-4 can share the current output by the second group Group_B. For example, if the group having the first power channel and the second power channel outputs the maximum current (current limit) Imax, the first power channel in the group can output some of the maximum current, and the second power channel can output the remaining current of the maximum current. Therefore, the power channels 112 "share current" in the group, and therefore, can effectively respond to two different types of power supplied to the DUT. Another type of sharing disclosed herein is "unidirectional sharing" of a specific amount of current in the group shared by two power channels (for example, as Figure 4B In an embodiment), the first power channel draws and uses the current of the second power channel, but the second power channel cannot use the current of the first power channel.

[0036] For example, the first power supply voltage VDD1 of the DUT may require a current of 0.3A, and the second power supply voltage VDD2 may require a current of 1.3A. The power supply voltages VDD1 and VDD2 may be different voltage levels in some embodiments, or the same voltage in other embodiments (for example, in the latter case, different types of loads are supplied). Herein, each power supply voltage VDD1 and VDD2 may be loosely and interchangeably referred to as a "power supply". Each power channel may be powered by providing both the required / desired power supply voltage VDD1 or VDD2 and the associated current level. For example, each power channel may supply a maximum current of 0.8A. When current is not shared between power channels (in conventional test equipment), neither of the two power channels supplies a current of 1.3A with the second power supply voltage VDD2, and therefore, the power required by one DUT cannot be supplied by two power channels. As a result, in order to test one DUT, in addition to the two power channels, a separate power channel may need to be added.

[0037] On the other hand, in the semiconductor test device 1000, in each of the first group Group_A and the second group Group_B of the power supply 110, the power channel 112 may share current. For example, in the first group Group_A, the first power channel 112-1 and the second power channel 112-2 may share current, and thus, the first power channel 112-1 may output a current of 0.3A, and the second power channel 112-2 may output a current of 1.3A. (It should be noted here that the specific current level examples herein are understood to cover levels within a tolerance range of, for example, + / -10%.) Therefore, the first power channel 112-1 may supply a current of 0.3A at the first power supply voltage VDD1 of the DUT, and the second power channel 112-2 may supply a current of 1.3A at the second power supply voltage VDD2 of the DUT. As a result, in the test device 1000, one DUT may be tested using two power channels 112.

[0038] In the test apparatus 1000, the maximum supplyable current amount may be limited based on the number of power channels 112 in each group. For example, the first group Group_A and the second group Group_B each include two power channels 112, and thus, the maximum current may be limited to 1.6 A. Therefore, the maximum current supplied by each group is limited based on the number of power channels 112, and thus, the entire current supplied by the power supply 110 may not increase.

[0039] Figure 2A and Figure 2B 1 is a conceptual diagram for describing the operation of power supply of the semiconductor testing equipment of the comparative example.

[0040] Reference Figure 2A and Figure 2B In the semiconductor test equipment of the comparative example, the power supply P / S may include a plurality of power channels, for example, four power channels DPS_1 to DPS_4. The four power channels DPS_1 to DPS_4 may independently supply power to the DUT. In addition, each of the power channels DPS_1 to DPS_4 may supply a current of 0.8 A or less. Figure 2A As shown, two DUTs DUT1 and DUT2 receive two different types of power, wherein when the first power supply VDD1 receives a current of 0.2A and the second power supply VDD2 receives a current of 0.8A, the two DUTs DUT1 and DUT2 can each receive sufficient power through two power channels. In other words, the two DUTs DUT1 and DUT2 can receive sufficient power through four power channels. Here, T / B can represent a test board.

[0041] However, if Figure 2BAs shown, when the DUT receives two different types of power, where the first power supply VDD1 is to receive a current of 0.2A and the second power supply VDD2 is to receive a current of 1.4A, the first power supply VDD1 may receive a current from one power channel (e.g., the first power channel DPS_1), but the second power supply VDD2 cannot receive the required / desired current through one power channel. Therefore, two power channels (e.g., the second power channel DPS_2 and the third power channel DPS_3) may supply current to the second power supply VDD2. Therefore, the fourth power channel DPS_4 may not be used for power supply. Therefore, the power supply P / S including four power channels DPS_1 to DPS_4 may supply power to one DUT, and one power channel may be wasted, thereby greatly reducing the efficiency of simultaneous testing.

[0042] Therefore, when two or more types of power are used according to the design purpose and operation of various areas in the internal circuit of the semiconductor device to be tested (i.e., DUT), the operating voltage and current consumption specifications of the two or more types of power are independent, and the current consumption in a specific power supply exceeds the maximum supplyable current of the power channel, problems may occur in the semiconductor testing equipment of the comparative example.

[0043] On the other hand, in the test device 1000, as shown in FIG. Figure 1B As described, the four power channels DPS_1 to DPS_4 are divided into two groups in the first group Group_A and the second group Group_B, and the current amount of the power channels DPS_1 to DPS_4 is shared in each of the first group Group_A and the second group Group_B to increase the efficiency of the power supply. For example, the four power channels can supply power to two DUTs at the same time without wasting the power channels. Therefore, the efficiency of simultaneous testing can be greatly improved.

[0044] For reference, regarding the problem of the semiconductor test equipment of the comparative example, the case where the number of power channels increases will be described. There may be a power supply including 1024 power channels capable of supplying up to 800mA, and for two types of power supply voltages (i.e., VDD1 and VDD2), the peak current of the DUT is 250mA and 1.2A. Here, there are a sufficient number of signal channels, so the number of DUTs that can be tested simultaneously can be limited only by the number of power channels. In this case, when only one power channel is connected to VDD2, the current level is insufficient, so it is necessary to assign two power channels to configure an environment for supplying 1.6A. For VDD1, even when only 250mA is consumed, one power channel is assigned, so a total of three power channels are assigned per DUT, and only 341 DUTs are tested simultaneously according to simple calculations.

[0045] Obviously, when the maximum current that can be supplied by the power channel increases to 1.2A or more, only one power channel can be assigned to VDD2, and therefore, the number of DUTs that can be tested simultaneously can be increased to 512, but in this case, the maximum power supplied by the semiconductor test equipment to all components also increases by the same amount, and therefore, the circuit of the power system may need to adopt high-priced components. In addition, the number of components may need to be increased, and the heat dissipation-related components may need to be strengthened. Therefore, the price or size of the semiconductor test equipment may be potentially adversely affected, and the energy consumption may also increase. The method of increasing the number of power channels may also cause similar problems.

[0046] On the other hand, in the test device 1000, as shown in FIG. Figure 1B As described, the power channels are divided and included in a plurality of groups, and the power channels in each group share current, thereby optimizing power efficiency, thereby increasing the efficiency of simultaneous testing of the test apparatus 1000 .

[0047] FIG. 3A to FIG. 3C It is shown in Figure 1A Graph showing the number of DUTs that can be tested simultaneously according to the amount of current in the semiconductor test apparatus 1000 of the embodiment and the semiconductor test apparatus of the comparative example.

[0048] exist FIG. 3A to FIG. 3C In the graph of , two different types of power can be supplied to the DUT, and the power supply may include 1024 power channels. In addition, in the semiconductor test device Com. of the comparative example, each power channel of the power supply P / S outputs a current of 800mA or less. In the semiconductor test device Emb. of the present embodiment, the power channels 112 of the power supply 110 are divided into two groups, each power channel 112 outputs a current of 1600mA or less, and each group supplies 1600mA. FIG. 3A to FIG. 3C In each of the graphs of FIG. 1 , the x-axis represents the amount of current supplied to the second power supply VDD2 , and the y-axis represents the number of DUTs that can be tested simultaneously.

[0049] Reference FIG. 3A to FIG. 3C , when the first power supply VDD1 is Figure 3A When receiving a current of 100 mA as shown, the number of DUTs that can be tested simultaneously by the semiconductor test apparatus Com. of the comparative example may be smaller than that of the semiconductor test apparatus Emb. of the present embodiment when the current required by the second power supply VDD2 increases.

[0050] In detail, when the second power supply VDD2 receives a current of 800 mA, both the semiconductor test device Com. of the comparative example and the semiconductor test device Emb. of the present embodiment can test 512 DUTs simultaneously. However, when the second power supply VDD2 receives a current greater than 800 mA but less than 1600 mA, the semiconductor test device Com. of the comparative example requires three power channels for one DUT, and thus can test 341 DUTs simultaneously. On the other hand, the semiconductor test device Emb. of the present embodiment still requires two power channels for one DUT, and thus can test 512 DUTs simultaneously.

[0051] When the second power supply VDD2 receives a current greater than 1600 mA, the semiconductor test device Com. of the comparative example requires four power channels for one DUT, so 256 DUTs can be tested simultaneously. On the other hand, the semiconductor test device Emb. of the present embodiment still only requires three power channels for one DUT, so 341 DUTs can be tested simultaneously.

[0052] Figure 3B is a graph showing the number of DUTs that can be tested simultaneously according to the current level required by the second power supply VDD2 for a case where the first power supply VDD1 receives a current amount of 500 mA, Figure 3C is a graph showing the number of DUTs that can be tested simultaneously according to the current level required by the second power supply VDD2 for the case where the first power supply VDD1 receives a current of 1A. Figure 3B and Figure 3C As shown in the curve graph, when the current required by the second power supply VDD2 increases, the number of DUTs that can be simultaneously tested by the semiconductor test device Com. of the comparative example may be smaller than the number of DUTs that can be simultaneously tested by the semiconductor test device Emb. of the present embodiment.

[0053] In detail, Figure 3B In the curve diagram, when the second power supply VDD2 receives a current of 800mA, both the semiconductor test device Com. of the comparative example and the semiconductor test device Emb. of the present embodiment can test 512 DUTs simultaneously. However, when the second power supply VDD2 receives a current greater than 800mA but less than 1600mA, the semiconductor test device Com. of the comparative example requires three power channels for one DUT, and thus can test 341 DUTs simultaneously. On the other hand, for a current of 1100mA, the semiconductor test device Emb. of the present embodiment still requires two power channels for one DUT, and thus can test 512 DUTs simultaneously.

[0054] When the second power supply VDD2 receives a current greater than 1600 mA, the semiconductor test device Com. of the comparative example requires four power channels for one DUT, and thus 256 DUTs can be tested simultaneously. On the other hand, for a current greater than 1100 mA, the semiconductor test device Emb. of the present embodiment requires three power channels for one DUT, and thus 341 DUTs can be tested simultaneously.

[0055] exist Figure 3C In the graph of , until the current output of 800mA required for the second power supply VDD2, the semiconductor test device Com. of the comparative example may require three power channels for one DUT, so 341 DUTs can be tested simultaneously. On the other hand, for the semiconductor test device Emb. of the present embodiment, each group supplies up to 1600mA of current output, so until the current amount of 600mA required for the second power supply VDD2, one DUT only requires two power channels. Therefore, 512 DUTs can be tested simultaneously.

[0056] When the current amount required by the second power supply VDD2 is greater than 800mA but less than 1600mA, the semiconductor test device Com. of the comparative example may require four power channels for one DUT, and thus 256 DUTs may be tested simultaneously. On the other hand, for the semiconductor test device Emb. of the present embodiment, for the current amount required by the second power supply VDD2 greater than 600mA but less than 1400mA, only one power channel may be added, and thus three power channels are required for one DUT, and thus 341 DUTs may be tested simultaneously.

[0057] Finally, when the second power supply VDD2 receives a current greater than 1600 mA, the semiconductor test device Com. of the comparative example requires five power channels for one DUT, and thus 204 DUTs can be tested simultaneously. On the other hand, for the semiconductor test device Emb. of the present embodiment, when the second power supply VDD2 receives a current greater than 1400 mA, four power channels are required for one DUT, and thus 256 DUTs can be tested simultaneously.

[0058] FIG. 4A to FIG. 4C yes Figure 1B 1 and 2 are circuit diagrams of various examples of the power supply 110 , and a circuit diagram of the power channel 112 in one group is shown. FIG. 4A to FIG. 4C Will refer to Figure 1B Describe together, briefly describe or omit the referenced Figures 1A to 3C Describe the details.

[0059] Reference Figure 4A, the power supply 110a of the test device 1000 may include a plurality of groups, and each group may include two power channels 112a. For example, the first group Group_Aa may include a first power channel 112a-1 and a second power channel 112a-2. The first power channel 112a-1 and the second power channel 112a-2 may each output a maximum current of 1.6A. In other words, the first power channel 112a-1 and the second power channel 112a-2 may each output a current amount between about 0A and about 1.6A. At the same time, the maximum current amount of the power channel 112a may be limited by the current limiter (clamp) 114. For example, the maximum current of the first power channel 112a-1 may be limited to 1.6A by the first current clamp 114-1, and the maximum current of the second power channel 112a-2 may be limited to 1.6A by the second current clamp 114-2. Information about the maximum current may be stored in the mode register 116, and the current clamp 114 may limit the maximum current of the power channel 112a based on the information of the mode register 116. In addition, the circuit in the power channel 112a may be changed so that each of the first power channel 112a-1 and the second power channel 112a-2 may supply a maximum current of 1.6 A. In other words, the circuit may be designed so that the capacity of the first power channel 112a-1 and the second power channel 112a-2 increases.

[0060] At the same time, the maximum current output by each group of the power supply 110a may be limited. For example, the maximum current output from the first group Group_Aa may be limited to 1.6A. In detail, the sum of the maximum currents of the first power channel 112a-1 and the second power channel 112a-2 does not exceed 1.6A. For example, when the first power channel 112a-1 outputs a current of 1.6A, the second power channel 112a-2 outputs a current of 0A; when the first power channel 112a-1 outputs a current of 0.8A, the second power channel 112a-2 outputs a maximum current of 0.8A; when the first power channel 112a-1 outputs a current of 0A, the second power channel 112a-2 outputs a maximum current of 1.6A.

[0061] Therefore, in the power supply 110a of the present embodiment, the two power channels 112a in the group share and collectively use 1.6 A. Therefore, a group of power G / P may be substantially the same as the power of the two power channels, and no additional power may be consumed. Therefore, the entire power of the power supply 110a may be substantially the same as the entire power of the power supply P / S of the comparative example including the same number of power channels.

[0062] exist Figure 4AIn the power supply 110a of FIG. 1 , a case where the maximum current Imax of each power channel 112a in the group is increased by two times by 0.8A is described, but the increase in the maximum current Imax of the power channel 112a in the group is not limited to two times. For example, the power channel can be designed by partially limiting the current level that can be shared so that a smaller maximum current Imax is supplied. In detail, when the power channel can share current only within the range of 0.4A, each power channel can be designed to supply a maximum current Imax of 1.2A, and the current clamp can be adjusted within an additional range of 0.4A.

[0063] In addition, a case where one group includes two power channels is described, but the same principle of sharing the current amount can be applied to a case where the number of power channels is generalized and each group includes n power channels (n is an integer of 2 or more). The concept of generalizing the number of power channels included in each group to n can also be applied to other embodiments below.

[0064] Reference Figure 4B , the power supply 110b of the test device 1000 and Figure 4A The power supply 110a of the test device 1000 is different in that the maximum current amounts of the two power channels 112b in the group are different from each other. In detail, the first group Group_Ab may include a first power channel 112b-1 and a second power channel 112b-2. The first power channel 112b-1 may output a maximum current of 1.6A, and the second power channel 112b-2 may output a maximum current Iref of 0.8A. In other words, the first power channel 112b-1 may output a current between approximately 0A and approximately 1.6A, and the second power channel 112b-2 may output a current between approximately 0A and approximately 0.8A. Similar Figure 4A In the power supply 110a of the present embodiment, the maximum current of the power channel 112b may be limited by the current clamp 114, and information about the maximum current may be stored in the mode register 116. In the power supply 110b of the present embodiment, the capacity of the first power channel 112b-1 needs to be increased so that a maximum current of 1.6A can be supplied, but the second power channel 112b-2 supplies a maximum current of 0.8A, so the existing power channels can be used without increasing the capacity.

[0065] Therefore, when sharing current between two power channels in a group, symmetry can be abandoned; the maximum current of only one power channel (e.g., the first power channel 112b-1) can be increased; the maximum current of the remaining power channel (e.g., the second power channel 112b-2) can be maintained as it is. In addition, each of the power channels 112b can be freely connected to any power supply (e.g., VDD1 or VDD2) of the DUT through the test board 200, so a considerable current sharing effect can be achieved while minimizing circuit changes.

[0066] The maximum current output of each group of the power supply 110b may be limited. For example, the maximum current output of the first group Group_Ab may be limited to 1.6A. In detail, the sum of the maximum currents of the first power channel 112b-1 and the second power channel 112b-2 does not exceed 1.6A. For example, when the first power channel 112b-1 outputs a current of 1.6A, the second power channel 112b-2 outputs a current of 0A; when the first power channel 112b-1 outputs a current of 0.8A, the second power channel 112b-2 outputs a maximum current of 0.8A. However, in the power supply 110b of the present embodiment, the maximum current output of the second power channel 112b-2 is limited to 0.8A. Therefore, even when the first power channel 112b-1 outputs a current of 0A, the second power channel 112b-2 only outputs a maximum current of 0.8A.

[0067] Therefore, the power supply 110b of the present embodiment can realize the concept of unidirectional sharing, in which two power channels 112b in the group share 0.8A, in which one power channel (e.g., the first power channel 112b-2) draws and uses the current of another power channel (e.g., the second power channel 112b-2), and the second power channel 112b-2 cannot use the current of the first power channel 112b-1. However, also in the power supply 110b of the present embodiment, a group of power G / P can be substantially the same as the power of the two power channels, and as a result, the entire power of the power supply 110b can be substantially the same as the entire power of the power supply P / S of the comparative example including the same number of power channels.

[0068] Reference Figure 4C , the power supply 110c of the test device 1000 and Figure 4A The power supply 110a of the test device 1000 is different in that three power channels are included in one group. In detail, the first group Group_Ac may include a first power channel 112c-1, a second power channel 112c-2, and an additional power channel 112c-s. Each of the first power channel 112c-1, the second power channel 112c-2, and the additional power channel 112c-s may output a maximum current of 0.8A. Figure 4A In the power supply 110a of the embodiment, the maximum current of the power channel 112c may be limited by the current clamp 114, and information about the maximum current may be stored in the mode register 116. In the power supply 110c of the present embodiment, since all three power channels 112c only need to supply a maximum current of 0.8A, existing power channels may be used without increasing capacity.

[0069] In the power supply 110c of the present embodiment, the power channels 112c in the group may be divided into supply channels and additional channels. In detail, in the first group Group_Ac, the first power channel 112c-1 and the second power channel 112c-2 may correspond to supply channels for supplying power to two power supplies of the DUT, and the additional power channel 112c-s may correspond to an additional channel for adding a current amount to the first power channel 112c-1. Therefore, as a result, the first power channel 112c-1 may supply a maximum current amount of 1.6A to the DUT by adding the current amount of the additional power channel 112c-s, and the second power channel 112c-2 may supply a maximum current of 0.8A to the DUT.

[0070] In the power supply 110c of the present embodiment, the maximum current output from each group may be the sum of the maximum currents of the three power channels 112c. For example, the maximum current amount of the first group Group_Ac may be 2.4A. In other words, the capacity of the three power channels 112c is not increased, and therefore, there is no need to limit the maximum current output from the group. Therefore, the power supply 110c of the present embodiment may use the concept in which the first power channel 112c-1 and the second power channel 112c-2 as the supply channel are shared and the additional power channel 112c-s is used, rather than the concept in which the power channel 112c shares the current amount in the group. Therefore, in the power supply 110c of the present embodiment, a group of power G / P may be substantially the same as the power of the three power channels, and as a result, the entire power of the power supply 110c of the present embodiment may be substantially the same as the entire power of the power supply P / S of the comparative example including the same number of power channels.

[0071] Figure 5A 1 is a circuit diagram depicting a group "Group_Ad" of power channels 112 forming a power supply 110d. The power supply 110d is Figure 1B Although one group of power channels is shown, the power supply 110d may include multiple groups of similar configurations. The power supply 110d includes a switch matrix 115, an example of which is shown in FIG. Figure 5B middle. Figure 5A and Figure 5B Will refer to Figure 1B Describe together, briefly describe or omit the referenced Figures 1A to 3C Describe the details.

[0072] Reference Figure 5A and Figure 5B, in addition to the two power channels (the first power channel 112-1 and the second power channel 112-2) in one group, the power source 110d may further include a plurality of sub-power channels 118 and a switch matrix 115. In one example discussed below for ease of understanding, the group Group_Ad may include 16 sub-power channels 118, a switch matrix 115, and the first power channel 112-1 and the second power channel 112-2.

[0073] The 16 sub-power channels 118 can be connected to corresponding power channels among the first power channel 112-1 and the second power channel 112-2 through a switching combination implemented by the switch matrix 115. Figure 5B As shown, the switch matrix 115 may include 16 switches 117 corresponding to the 16 sub-power channels 118, respectively, and each of the switches 117 may connect the corresponding sub-power channel 118 to the first power channel 112-1 or the second power channel 112-2. The connection information of the switches 117 may be stored in the mode register 116a. For example, there are 16 switches 117, so 16 bits of connection information may be stored in the mode register 116a, and each bit is used to control the switching signal state S / W of the corresponding switch 117.

[0074] In this embodiment, each of the 16 sub-power channels 118 may output the same maximum current. In one example, the maximum current output by each sub-power channel is 100 mA. Therefore, the first power channel 112-1 and the second power channel 112-2 may each output a maximum current of 16 A through the combination of the switch matrix 115. Therefore, when all 16 sub-power channels 118 are connected to the first power channel 112-1, the first power channel 112-1 may output a maximum current of 1.6 A, and the second power channel 112-2 may output a current of 0 A. In another case, when 8 sub-power channels 118 are connected to the first power channel 112-1 and 8 sub-power channels 118 are connected to the second power channel 112-2, each of the first power channel 112-1 and the second power channel 112-2 may output a maximum current of 0.8 A.

[0075] The maximum current output of each group of the power supply 110d may be limited by the number of sub-power channels 118 and the maximum current of each sub-power channel. For example, in the group Group_Ad, there are 16 sub-power channels 118, and each maximum current output is 100mA, so the maximum current output of the first group Group_Ad may be limited to 1.6A. In addition, the maximum current output of each of the first power channel 112-1 and the second power channel 112-2 may be determined by the number of connected sub-power channels 118 and the respective maximum current output. Therefore, each of the first power channel 112-1 and the second power channel 112-2 may require a separate current clamp.

[0076] When the number of sub-power channels 118 and the power channels 112 is generalized to represent the maximum current output of each of the group and the power channels 112, based on the number of sub-power channels 118 being m (m being an integer greater than the number n of power channels 112 in the group) and the maximum current output of each sub-power channel 118 being Isub, the maximum current output of each of the group and the power channels 112 can be represented as m*Isub.

[0077] Therefore, the power supply 110d can utilize the concept of sharing the maximum available current of 1.6A by using the sub-power channel 118 and the switch matrix 115 for the first power channel 112-1 and the second power channel 112-2 in the group. Therefore, one group of power G / P may be substantially the same as the power of the two power channels, and no additional power may be consumed. Therefore, the entire power of the power supply 110d may be substantially the same as the entire power of the power supply P / S of the comparative example including the same number of power channels.

[0078] against Figure 5A The power supply 110d of FIG. 1 describes a case where each of the sub-power channels 118 outputs a maximum current of 100 mA, but the maximum current output by each of the sub-power channels 118 is not limited to 100 mA. For example, each of the sub-power channels 118 may output a maximum current of 200 mA. In this case, eight sub-power channels 118 may be arranged in one group, the switch matrix 115 may include eight switches, and the mode register 116a may store 8 bits of connection information.

[0079] FIG. 6A to FIG. 6C It is a specific implementation Figure 1B 1 is a circuit diagram of a power supply 110, and a circuit diagram of a power channel 112 in one group is shown. FIG. 6A to FIG. 6C Will refer to Figure 1B , Figure 5A and Figure 5B together, and will briefly describe or omit the referenced Figure 3C , Figure 5A and Figure 5B Describe the details.

[0080] Reference Fig. 6A , the power supply 110e of the test device 1000 and Figure 5A The power supply 110d of the embodiment of the present invention may be different in that the sub-power channels 118a in the group are divided into two channel categories: a first channel category 118a-1 and a second channel category 118a-2. The maximum current outputs of the sub-power channels of the first channel category 118a-1 and the second channel category 118a-2 are different from each other. The first group Group_Ae may include eight sub-power channels 118a. The eight sub-power channels 118a may be distributed among the first channel category 118a-1 and the second channel category 118a-2.

[0081] The first channel category 118a-1 may include two first sub-power channels 118a-1a, one second sub-power channel 118a-1b, and one third sub-power channel 118a-1c. The second channel category 118a-2 may include two first sub-power channels 118a-2a, one second sub-power channel 118a-2b, and one third sub-power channel 118a-2c. In addition, each of the four first sub-power channels 118a-1a and 118a-2a may output a maximum current of 100mA, each of the two second sub-power channels 118-1b and 118-2b may output a maximum current of 200mA, and each of the two third sub-power channels 118-1c and 118-2c may output a maximum current of 400mA.

[0082] According to the number of sub power channels 118a, the switch matrix 115 may include eight switches, and the mode register 116a may store 8-bit connection information. In addition, the first power channel 112-1 and the second power channel 112-2 may each output a maximum current of 1.6A through the combination of the switch matrix 115.

[0083] The maximum current output of each group of the power source 110e may be limited by the sum of the maximum current outputs of the sub-power channels 118a. For example, in the first group Group_Ae, the sum of the maximum current outputs of the sub-power channels 118a is 1.6 A, and therefore, the maximum current output of the first group Group_Ae may be limited to 1.6 A. The maximum current output of each of the first power channel 112-1 and the second power channel 112-2 is also determined by the sum of the maximum current outputs of the connected sub-power channels 118a, and therefore, each of the first power channel 112-1 and the second power channel 112-2 does not require a separate current clamp.

[0084] Therefore, the power supply 110e can utilize the concept in which two power channels 112 in a group share 1.6A by using the sub-power channel 118a and the switch matrix 115. Therefore, one group of power G / P can be substantially the same as the power of the two power channels, and no additional power can be consumed. Therefore, the entire power output of the power supply 110e can be substantially the same as the entire power output of the power supply P / S of the comparative example including the same number of power channels. In addition, compared with Figure 5A Compared to the power supply 110d, the power supply 110e may have half the number of sub-power channels 118a and half the number of switches 117 included in the switch matrix 115. In addition, the connection information stored in the mode register 116a may be reduced to 8 bits.

[0085] When the number of sub-power channels 118a and the power channels 112 is generalized to represent the maximum current output of each of the sub-power channels 118a, the corresponding group, and the power channels 112, based on the number of channel categories being equal to the number n of power channels 112 and each channel category including m sub-power channels 118a (where m is an integer of 3 or greater), the m sub-power channels 118a can collectively output 2x2 0 *Isub (e.g., the current collectively output by the two power sub-channels 118a-1a), plus 2 1 *Isub (eg, the current output by the power sub-channels 118a-1b), ..., plus 2 m-2 *Isub (e.g., the maximum current level of the sub-power channels 118a-1c), and Isub may represent the maximum current amount of the sub-power channel 118a having the smallest capacity among the sub-power channels 118a. Therefore, the maximum current output of each of the groups and power channels 112 may be represented as 2*2 0 *I sub+2 1 *Isub, ..., +2 m-2 *Isub. (Note that the maximum current supplied by any given power channel in the group is for the case where the other power channels in the group supply zero current.)

[0086] Reference Figure 6B , the power supply 110f of the test device 1000 and Figure 5A The power supply 110d of the embodiment of the present invention may be different in that the maximum current output of the sub-power channels 118b in the group is different from each other. Fig. 6A The power supply 110 e may differ in that the sub-power channels 118 b are not divided into a plurality of channel categories.

[0087] In the power supply 110f, the first group Group_Af may include five sub-power channels 118b. The five sub-power channels 118a may include two first sub-power channels 118b-1a, one second sub-power channel 118b-1b, one third sub-power channel 118b-1c, and one fourth sub-power channel 118b-1d. Each of the two first sub-power channels 118b-1a may output a maximum current of 100mA, the second sub-power channel 118b-1b may output a maximum current of 200mA, the third sub-power channel 118b-1c may output a maximum current of 400mA, and the fourth sub-power channel 118b-1d may output a maximum current of 800mA.

[0088] According to the number of sub-power channels 118a, the switch matrix 115 may include five switches, and the mode register 116b may store 5-bit connection information. In addition, the first power channel 112-1 and the second power channel 112-2 may each output a maximum current of 1.6A through a switching combination implemented by the switch matrix 115. Here, the fourth sub-power channel 118-1d may be fixedly connected to the first power channel 112-1 or the second power channel 112-2, and the first power channel 112-1 and the second power channel 112-2 may be connected to the corresponding power supply of the DUT through the test board 200. In this case, the switch matrix 115 may include four switches to perform desired switching between the two first sub-power channels 118b-1a, the second sub-power channel 118b-1b, and the third sub-power channel 118b-1c and the power channel 112; and the mode register 116b may store only 4-bit connection information.

[0089] The maximum current output from each group of the power source 110f may be limited by the sum of the maximum currents of the sub-power channels 118b. For example, in the first group Group_Af, the sum of the maximum currents of the sub-power channels 118b is 1.6A, and therefore, the maximum current of the first group Group_Af may be limited to 1.6A. The maximum current of each of the first power channel 112-1 and the second power channel 112-2 is also determined by the sum of the maximum currents of the connected sub-power channels 118b. Therefore, each of the first power channel 112-1 and the second power channel 112-2 does not require a separate current clamp.

[0090] Therefore, the power supply 110f can also utilize the concept in which two power channels 112 in a group are shared by using the sub-power channel 118b and the switch matrix 115 and using 1.6A. Therefore, one group of power G / P can be substantially the same as the power of the two power channels, and no additional power can be consumed. Therefore, the entire power of the power supply 110f of the present embodiment can be substantially the same as the entire power of the power supply P / S of the comparative example including the same number of power channels. In addition, compared with Fig. 6A Compared with the power supply 110e of the present embodiment, the power supply 110f of the present embodiment may include three fewer sub-power channels 118b, and the number of switches 117 included in the switch matrix 115 may be halved. In addition, the connection information stored in the mode register 116b may be reduced to 4 bits.

[0091] When the number of sub-power channels 118b and the power channel 112 is generalized to represent the maximum current amount of each of the sub-power channels 118b, the group, and the power channel 112, based on each group including m+1 sub-power channels 118b (where m is an integer of 3 or greater), the m+1 sub-power channels 118b can output 2x2 0 *I sub, add 2 1 *I sub, ..., plus 2 m-1 *The maximum current of Isub. In addition, the maximum current of each of the groups and power channels 112 can be expressed as 2*2 0 *Isub+2 1 *Isub, ..., +2 m-1 *Isub. Here, Isub may represent a maximum current amount of the sub-power channel 118b having the smallest capacity among the sub-power channels 118b.

[0092] Reference Figure 6C , the power supply 110g of the test device 1000 and Figure 5A The power supply 110d of the embodiment of the present invention may be different in that the maximum current amounts of the sub-power channels 118c in the group are different from each other. Fig. 6A or Figure 6B The power supply 110 e or 110 f may differ in that the number of the sub-power channels 118 c in the group is greater than the number of the power channels 112 by one.

[0093] In detail, in the power supply 110g, the first group Group_Ag may include three sub-power channels 118c. The three sub-power channels 118c may include a first sub-power channel 118-1, a second sub-power channel 118-2, and an additional sub-power channel 118-s. In addition, the first sub-power channel 118-1 and the additional sub-power channel 118-s may each output a maximum current of 400mA, and the second sub-power channel 118-2 may output a maximum current of 800mA.

[0094] The switch matrix 115 may include one switch 117 connected to the additional sub-power channel 118-s, and the mode register 116c may store 1-bit connection information. The second power channel 112-2 may output a maximum current of 1.2A when connected to the additional sub-power channel 118-s through the switch 117, and output a maximum current of 0.8A when not connected to the additional sub-power channel 118-s. In addition, the first power channel 112-1 may output a maximum current of 0.8A when connected to the additional sub-power channel 118-s through the switch 117, and output a maximum current of 0.4A when not connected to the additional sub-power channel 118-s.

[0095] The maximum current output from each group of the power source 110g may be limited by the sum of the maximum current amounts of the sub-power channels 118c. For example, in the first group Group_Ag, the sum of the maximum current amounts of the sub-power channels 118c is 1.6 A, and therefore, the maximum current amount of the first group Group_Ag may be limited to 1.6 A. The maximum current amount of each of the first power channel 112-1 and the second power channel 112-2 is also determined by the sum of the maximum current amounts of the connected sub-power channels 118c, and therefore, there is no need to provide a separate current clamp for each of the first power channel 112-1 and the second power channel 112-2.

[0096] Therefore, the power supply 110g may use a concept that the first power channel 112-1 and the second power channel 112-2 in the group are shared and use 0.4A by using the sub-power channel 118c and the switch matrix 115. Therefore, one group of power G / P may be substantially the same as the power of the two power channels, and no additional power may be consumed. Therefore, the entire power of the power supply 110g may be substantially the same as the entire power of the power supply P / S of the comparative example including the same number of power channels. In addition, compared with Fig. 6A Compared to the power supply 110e, the power supply 110g may include a significantly reduced number of sub-power channels 118c and one switch 117 included in the switch matrix 115. In addition, the connection information stored in the mode register 116c may also be reduced to 1 bit.

[0097] When the number of sub-power channels 118c and power channels 112 is generalized to represent the maximum current amount of each of the sub-power channels 118c, the group, and the power channels 112, based on each group including n power channels 112 and n+1 sub-power channels 118c (where n is an integer of 2 or more), one of the n+1 sub-power channels 118c may output the maximum current Iref, and the remaining n sub-power channels 118c may output the maximum current Isub. In addition, one of the power channels 112 may output the maximum current Iref+Isub, the maximum current output of each of the remaining power channels 112 may be 2*Isub, and the maximum current output of the group may be Iref+n*Isub. Here, Iref may represent the maximum current amount assigned to one sub-power channel 118c (e.g., the second sub-power channel 118-2), and may be 0.8A (the maximum current amount of the reference power channel). In addition, Isub may represent the maximum current amount assigned to each sub-power channel 118c.

[0098] Figure 7 is a flow chart of a power supply method 700 of a semiconductor test device according to an embodiment. Figure 7 Will refer to Figure 1A and Figure 1B together, and will briefly describe or omit the referenced Figures 1A to 6C Describe the details.

[0099] Reference Figure 7 , the power supply method 700 may be Figure 1A In operation S110, the power supply method 700 may first supply a first current amount to each of the plurality of groups. The first current amount may correspond to a maximum current amount that all power channels 112 included in each group can supply to the DUT.

[0100] Then, in operation S120, the first current amount is dividedly input to the power channels 112 included in each group. The first current amount may be uniformly or non-uniformly input to the power channels 112 included in the group.

[0101] Next, in operation S130, the power channels 112 in the group may share the current amount to supply the corresponding current amount to each of the DUTs. Based on the sharing of the current, each of the power channels 112 may output the maximum current of the group. According to some embodiments, some of the power channels 112 may output the maximum current of the group, and the remaining power channels 112 may output a current less than the maximum current of the group based on the sharing of the available current. According to some embodiments, based on the sharing of the current, the power channels 112 may all output a current amount less than the maximum current of the group. Hereinafter, the specific concept of current sharing of the power channels 112 will be described.

[0102] FIG. 8A to FIG. 8E Semiconductor test equipment Figure 7 Flowcharts of various examples of power supply method 700. FIG. 8A to FIG. 8E Will refer to FIG. 4A to FIG. 4C , Figure 5A and FIG. 6A to FIG. 6C together, and will briefly describe or omit the referenced Figures 1A to 7 Describe the details.

[0103] Reference Fig. 8A , the power supply method 800A is by Figure 4A The power supply method 800A is a power supply method performed by the power supply 110a of the embodiment of the present invention, and may correspond to a case where the number of power channels 112 included in the group is generalized to n, where n is an integer of 2 or more. In operation S110, the power supply method 800A may supply a first current amount to each of the plurality of groups. Then, in operation S120a, the first current amount is dividedly input to the n power channels 112 included in the group. The first current amount may be uniformly or unevenly input to the n power channels 112.

[0104] Thereafter, in operation S130a, each of the n power channels 112 outputs a current of Imax or less to supply a corresponding current to each of the DUTs. Here, Imax is a maximum current that the group can supply and may be substantially the same as a first current input to the group.

[0105] Reference Figure 8B , the power supply method 800B is composed of Figure 4B The power supply method 800B is a power supply method performed by the power supply 110b of the embodiment of the present invention, and may correspond to a case where the number of power channels 112 included in the group is generalized to n, where n is an integer of 2 or more. In operation S110, the power supply method 800B may supply a first current amount to each of the groups. Then, in operation S120a, the first current amount is dividedly input to the n power channels 112 included in the group. The first current amount may be uniformly or unevenly input to the n power channels 112.

[0106] Thereafter, in operation S130b, some of the n power channels may output a current of Imax or less, and the remaining power channels may output a current of Iref or less (Iref is less than Imax) to supply a corresponding current to each of the DUTs. Here, Imax is the maximum current that the group can supply, and may be substantially the same as the first current input to the group. In addition, Iref is the maximum current assigned to one power channel 112, and may represent 0.8A (the maximum current of the reference power channel).

[0107] Reference Figure 8C , the power supply method 800C is composed of Figure 4C The power supply method 800C is a power supply method performed by the power supply 110c of the embodiment of the present invention, and may correspond to a case where the number of power channels 112 included in the group is generalized to n, where n is an integer of 2 or more. In operation S110, the power supply method 800C may supply a first current amount to each of the plurality of groups. Then, in operation S120a, the first current amount is dividedly input to the n power channels 112 included in the group. The first current amount may be uniformly or unevenly input to the n power channels 112.

[0108] Thereafter, in operation S130c, each of the n power channels 112 may output a current amount of Iref or less, wherein only some of the n power channels 112 supply a corresponding current amount to each of the DUTs. Here, the power channels 112 supplying the current amount to the DUT may correspond to supply channels, and the remaining power channels 112 may correspond to additional channels that add the corresponding current amount to the supply channels. The first current amount, which is the maximum current amount that the group can supply, may be expressed as n*Iref.

[0109] Reference Fig.8D , power supply method 800D may correspond to Figure 5A and FIG. 6A to FIG. 6C A case where the power supply methods of the power supplies 110d to 110g are combined.

[0110] In operation S110, the power supply method 800D may supply a first current amount to each of the plurality of groups. Then, in operation S115, the first current amount is dividedly input to the sub-power channels included in the group. Then, in operation S120b, the outputs of the sub-power channels are input to the power channel 112 through the switching combination implemented by the switch matrix 115.

[0111] Thereafter, in operation S130d, each of the power channels 112 outputs a current amount of the output of one of the sub-power channels or the sum of the outputs of at least two sub-power channels to supply a corresponding current amount to each of the DUTs. The outputs of the current amounts of the sub-power channels and the power channels 112 may be different from each other, such as Figure 5A and FIG. 6A to FIG. 6C The power supply 110d to 110g is shown below. Fig. 8E As a representative example, only Figure 5A power supply method.

[0112] Reference Fig. 8E , the power supply method for 800E is Figure 5A The power supply method of the power supply 110d may correspond to a case where each group includes n power channels 112 and m sub-power channels 118, where n is an integer of 2 or more and m is an integer greater than n.

[0113] In operation S110, the power supply method 800E may supply a first current amount to each of the plurality of groups. Then, in operation S115a, the first current amount is dividedly input to the m sub-power channels 118 included in the group. Next, in operation S120c, the outputs of the m sub-power channels 118 are input to the power channel 112 through the combination of the switch matrix 115.

[0114] Thereafter, in operation S130e, each of the n power channels 112 outputs a current amount of m*Isub or less to supply a corresponding current amount to each of the DUTs. In addition, Isub may represent a maximum current output of each of the sub-power channels 118. The first current, which is the maximum current amount that the group can supply, may be represented as m*Isub.

[0115] In the above, the inventive concept is described with reference to the embodiments shown in the drawings, but these embodiments are only examples, and those skilled in the art will appreciate that various modifications and equivalent embodiments are possible. Therefore, the scope of the inventive concept will be defined by the appended claims.

Claims

1. A semiconductor testing device, comprising: a tester circuit comprising a power supply configured to simultaneously power a plurality of devices under test during testing; as well as a test board disposed between the tester circuit and the plurality of devices under test and routing power from the power supply to the tester circuit, The power supply includes a plurality of power channels, each of the plurality of devices under test receives two or more types of power from the plurality of power channels, each type of power is power supplied to the device under test at a corresponding power supply voltage, and the power supply shares current between the plurality of power channels and supplies the shared current to each of the plurality of devices under test.

2. The semiconductor testing device according to claim 1, wherein: The plurality of power channels are divided into a plurality of groups, Each of the plurality of groups includes a set number of power channels, and Each of the plurality of groups shares current among the plurality of power channels.

3. The semiconductor testing device according to claim 2, wherein: Each of the plurality of groups includes n power channels, wherein n is an integer of 2 or greater, Each of the n power channels outputs a current of Imax or less, and The maximum current supplied by each of the plurality of groups is Imax.

4. The semiconductor testing device according to claim 3, wherein: The maximum current of each of the n power channels is limited by a current clamp, and The current clamp limits the maximum current based on information stored in the mode register.

5. The semiconductor testing device according to claim 2, wherein: Each of the plurality of groups includes n power channels, wherein n is an integer of 2 or greater, Some of the n power channels output a current of Imax or less, and each of the remaining power channels of the n power channels outputs a current of Iref or less, wherein Iref is less than Imax, and The maximum current supplied by each of the plurality of groups is Imax.

6. The semiconductor testing device according to claim 2, wherein: Each of the plurality of groups includes n power channels, wherein n is an integer of 2 or greater, Each of the n power channels outputs a current of Iref or less, The n power channels are divided into supply channels for supplying current to the plurality of devices under test and additional channels for adding current to the supply channels, and The maximum amount of current supplied by each of the plurality of groups is n*Iref.

7. The semiconductor testing device according to claim 2, wherein: Each of the plurality of groups includes n power channels arranged on the output side, wherein n is an integer of 2 or more, and m sub-power channels arranged on the input side, wherein m is an integer greater than n, The m sub-power channels are connected to the n power channels through a switching combination implemented by a switch matrix, Each of the m sub-power channels outputs a current of Isub or less, Each of the n power channels outputs a current of m*Isub or less, and The maximum current supplied by each of the plurality of groups is m*Isub.

8. The semiconductor testing device according to claim 2, wherein: Each of the plurality of groups includes n power channels arranged on the output side and n+1 sub-power channels arranged on the input side, wherein n is an integer of 2 or more, The n+1 sub-power channels are connected to the n power channels through a switching combination implemented by a switch matrix, One of the n+1 sub-power channels outputs a current of Iref or less, and each of the remaining n sub-power channels outputs a current of Isub or less, One of the n power channels outputs a current of Iref+Isub or less, and each of the remaining n-1 power channels outputs a current of 2*Isub or less, and The maximum current supplied by each of the plurality of groups is Iref+n*Isub.

9. The semiconductor testing device according to claim 2, wherein: Each of the plurality of groups includes n power channels arranged on the output side and m*n sub-power channels arranged on the input side, wherein n is an integer of 2 or more, and m is an integer of 3 or more, The m*n sub-power channels are connected to the n power channels through a switching combination implemented by a switch matrix, The m sub-power channels output two 2 0 *Isub or less current, and 2 1 *Isub or less current to 2 m-2 *Isub or smaller current, Each of the n power channels outputs 2*2 0 *Isub+2 1 *Isub+,...,+2 m-2 *Isub or less current, and The maximum current supplied by each of the plurality of groups is 2*2 0 *Isub+2 1 *Isub+,...,+2 m-2 *Isub.

10. The semiconductor testing device according to claim 2, wherein: Each of the plurality of groups includes n power channels arranged on the output side and m+1 sub-power channels arranged on the input side, wherein n is an integer of 2 or more, and m is an integer of 3 or more, The m+1 sub-power channels are connected to the n power channels through a combination of switch matrices, The m+1 sub-power channels output two 2 0 *Isub or less current, and 2 1 *Isub or less current to 2 m -1 *Isub or smaller current, Each of the n power channels outputs 2*2 0 *Isub+2 1 *Isub+,...,+2 m-1 *Isub or less current, and The maximum current supplied by each of the plurality of groups is 2*2 0 *Isub+2 1 *Isub+,...,+2 m-1 *Isub.

11. A semiconductor testing device comprising: A tester circuit comprising a power supply configured to simultaneously supply power to a plurality of devices under test during testing, a test signal transmitter configured to input a test signal to the plurality of devices under test and to receive a response signal from the plurality of devices under test, a logic generation determiner circuit configured to generate the test signal and determine a failure of the plurality of devices under test based on the response signal, and a controller configured to control the power supply and the logic generation determiner; as well as a test board disposed between the tester circuit and the plurality of devices under test, the test board routing the power of the power supply and the test signal of the test signal transmitter to the plurality of devices under test, and routing the response signal from the plurality of devices under test to the test signal transmitter, Wherein, the power supply includes a plurality of power channels, The plurality of power channels are divided into a plurality of groups, Each of the plurality of groups includes a set number of power channels, and Each of the plurality of devices under test receives two or more types of power from the plurality of power channels, each type of power being power supplied at a corresponding power supply voltage for the device under test, and each of the plurality of groups shares current between the plurality of power channels and supplies the shared current to each of the plurality of devices under test.

12. The semiconductor testing device according to claim 11, wherein: Each of the plurality of groups includes n power channels, wherein n is an integer of 2 or greater, Each of the n power channels outputs a current of Imax or less, or Some of the n power channels output a current of Imax or less, and the remaining power channels of the n power channels output a current of Iref or less, wherein Iref is less than Imax, and The maximum current supplied by each of the plurality of groups is Imax.

13. The semiconductor testing device according to claim 11, wherein: Each of the plurality of groups includes a sub-power channel arranged on the input side, a power channel arranged on the output side, and a switch matrix arranged between the power channel on the output side and the sub-power channel, The number of the sub-power channels is greater than the number of the power channels on the output side, The currents output by the sub-power channels are all equal, or at least one of the currents output by the sub-power channels is different from the other currents, The sub-power channels are connected to the power channels on the output side through a switching combination implemented by the switch matrix, and A maximum current supplied by each of the plurality of groups is a sum of maximum currents output by the sub-power channels.

14. A semiconductor testing device comprising: a power supply configured to simultaneously supply power to the plurality of devices under test during testing; a test signal transmitter configured to input test signals to the plurality of devices under test and receive response signals from the plurality of devices under test; a logic generation determiner circuit configured to generate the test signal and determine failures of the plurality of devices under test based on the response signal; as well as a controller configured to control the power supply and the logic generation determiner circuit; wherein the power supply includes a plurality of power channels, The plurality of power channels are divided into a plurality of groups, Each of the plurality of groups includes a set number of power channels, and Each of the plurality of devices under test receives two or more types of power, each type of power being power supplied to the device under test at a corresponding power supply voltage, and each of the plurality of groups shares current between the plurality of power channels and supplies the shared current to each of the plurality of devices under test.

15. The semiconductor testing device according to claim 14, wherein: Each of the plurality of groups includes n power channels, wherein n is an integer of 2 or greater, Each of the n power channels outputs a current of Imax or less, or Some of the n power channels output a current of Imax or less, and the remaining power channels output a current of Iref or less, wherein Iref is less than Imax, and The maximum amount of current supplied by each of the plurality of groups is Imax.

16. The semiconductor testing device according to claim 14, wherein: Each of the plurality of groups includes a sub-power channel arranged on the input side, a power channel arranged on the output side, and a switch matrix arranged between the power channel on the output side and the sub-power channel, The number of the sub-power channels is greater than the number of the power channels on the output side, The currents output by the sub-power channels are all equal, or at least one of the currents output by the sub-power channels is different from the other currents, The sub-power channels are connected to the power channels on the output side through a switching combination implemented by the switch matrix, and A maximum current supplied by each of the plurality of groups is a sum of maximum currents of the sub-power channels.

17. A power supply method for a semiconductor test device, the semiconductor test device comprising a tester circuit, the tester circuit comprising a power supply configured to simultaneously supply power to a plurality of devices under test during testing, the power supply comprising a plurality of power channels, the plurality of power channels being divided into a plurality of groups, each of the plurality of groups comprising a set number of power channels, and the power supply being configured to supply two or more types of power to each of the plurality of devices under test, each type of power being power supplied to the device under test at a corresponding power supply voltage, the power supply method comprising: supplying a first current to each of the plurality of groups; inputting the first current into the plurality of power channels in a divided manner; and supplying a corresponding current to each of the plurality of devices under test through the plurality of power channels, Each of the plurality of groups shares current among the plurality of power channels and supplies the shared current to each of the plurality of devices under test.

18. The power supply method according to claim 17, wherein: Each of the plurality of groups includes n power channels, wherein n is an integer of 2 or greater, The step of dividing and inputting the first current into the plurality of power channels comprises: dividing and inputting the first current into the n power channels, Supplying a corresponding current to each of the plurality of devices under test includes: outputting a current of Imax or less through each of the n power channels, or outputting a current of Imax or less through some of the n power channels and outputting a current of Iref or less through the remaining power channels, wherein Iref is less than Imax, and The first current is Imax.

19. The power supply method according to claim 17, wherein: Each of the plurality of groups includes n power channels, wherein n is an integer of 2 or greater, The step of dividing and inputting the first current into the plurality of power channels comprises: dividing and inputting the first current into the n power channels, supplying a corresponding current to each of the plurality of devices under test comprises: outputting a current of Iref or less through each of the n power channels, wherein the n power channels are divided into a supply channel for supplying current to the plurality of devices under test and an additional channel for adding current to the supply channel, and The first current is n*Iref.

20. The power supply method according to claim 17, wherein: Each of the plurality of groups includes a sub-power channel arranged on the input side, a power channel arranged on the output side, and a switch matrix arranged between the power channel on the output side and the sub-power channel, The number of the sub-power channels is greater than the number of the power channels on the output side, The currents output by the sub-power channels are all equal, or at least one of the currents output by the sub-power channels is different from the other currents, The power supply method further includes: before being dividedly input into the plurality of power channels, inputting the first current into the sub-power channels in a divided manner, The divided input to the plurality of power channels comprises: inputting the output from the sub-power channels to the plurality of power channels through a switching combination of the switch matrix, wherein the currents output by the sub-power channels are all equal, or at least one of the currents output by the sub-power channels is different from the other currents, Supplying a corresponding current to each of the plurality of devices under test comprises: outputting a current from one output of the sub-power channels or a current of a sum of at least two outputs of the sub-current channels through each of the plurality of power channels, and The first current is the sum of maximum currents of the sub-power channels.

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