Method, device and equipment for controlling three-level interleaving direct-current converter

Abstract

The invention discloses a control method, device and equipment for a three-level interleaving direct-current converter, and relates to the technical field of power electronics, and the method comprises the steps: determining a voltage-sharing control compensation value of a high-voltage side and a current-sharing control compensation value of each phase according to a control sampling parameter of an n-phase three-level interleaving direct-current converter; determining two modulation signals corresponding to each phase according to the voltage-sharing control compensation value and the current-sharing control compensation value of the high-voltage side; determining an upper unit switch tube driving signal and a lower unit switch tube driving signal of each phase in the n-phase three-level interleaved parallel DC converter according to two phase shift signals of each phase and two modulation signals of each phase corresponding to the input carrier signal, so as to control switch tubes in respective upper units and lower units of n three-level bridge arms in the converter; according to the invention, the non-voltage-sharing condition of the high-voltage side capacitor of the converter can be conveniently suppressed, the circulating current of the converter is suppressed, and the output current balance degree of each phase is improved, so that the precision and stability of the system are improved.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and in particular to a control method, device and equipment for a three-level staggered parallel DC converter. Background Art

[0002] Each phase of the three-level staggered parallel DC converter (DC-DC converter) adopts an independent PWM (Pulse Width Modulation) control strategy, which can effectively reduce the current ripple of the DC-DC converter output. However, due to the differences in the converter hardware design, there are different component parameters and inconsistent equivalent resistance, which leads to uneven voltage on the high-voltage side capacitor and uneven current on each phase of the three-level staggered parallel DC converter, reducing the control accuracy and stability of the system.

[0003] At present, the optimization modulation technology is generally used to reduce the interphase circulation current and achieve the balance of each phase current by screening in the vector selection, but the algorithm of the optimization modulation technology has the problem of high algorithm complexity in vector selection. Although there are also solutions in the related technology that use power balance control algorithms to achieve the effect of balancing each phase by adding a power control loop and correcting the duty cycle of each phase; however, due to the ripple of the DC-DC converter output current in parallel, the power calculation is inaccurate, which affects the control effect. Therefore, how to conveniently improve the voltage balancing capability of the high-voltage side of the DC converter, achieve the balance of each phase current, and thus improve the control accuracy and stability of the system is a problem that needs to be solved urgently. Summary of the invention

[0004] The purpose of the present invention is to provide a control method, device and equipment for a three-level staggered parallel DC converter, so as to conveniently improve the voltage balancing capability of the high-voltage side of the DC converter, achieve the balance of the current of each phase, and thus improve the control accuracy and stability of the system.

[0005] In order to solve the above technical problems, the present invention provides a control method of a three-level staggered parallel DC converter, comprising:

[0006] According to the control sampling parameters of the n-phase three-level staggered parallel DC converter, the high-voltage side voltage sharing control compensation value and the current sharing control compensation value of each phase are determined; wherein n is a positive integer greater than or equal to 2, and the control sampling parameters include the upper unit capacitor voltage and the lower unit capacitor voltage on the high-voltage side of the n-phase three-level staggered parallel DC converter and the upper unit current and / or lower unit current of each phase on the low-voltage side;

[0007] Determine two modulation signals corresponding to each phase according to the high-voltage side voltage sharing control compensation value and the current sharing control compensation value;

[0008] According to the two phase-shifted signals of each phase and the two modulation signals of each phase corresponding to the input carrier signal, the upper unit switch tube drive signal and the lower unit switch tube drive signal of each phase in the n-phase three-level interleaved parallel DC converter are determined; wherein the first phase-shifted signal and the second phase-shifted signal of each phase differ by 180 degrees, and the first phase-shifted signals of two adjacent phases differ by a preset angle clockwise or counterclockwise, and the preset angle is the quotient of 360 degrees and n;

[0009] The upper unit switch tube driving signal and the lower unit switch tube driving signal are used to control the switch tubes in the upper unit and the lower unit of the n three-level bridge arms in the n-phase three-level staggered parallel DC converter to complete the DC-to-DC conversion.

[0010] On the other hand, the method of determining the high-voltage side voltage sharing control compensation value and the current sharing control compensation value of each phase according to the control sampling parameters of the n-phase three-level staggered parallel DC converter includes:

[0011] According to the control sampling parameters, the high-voltage side voltage sharing control compensation value, the current sharing control compensation value and the low-voltage side voltage stabilization control compensation value are determined; wherein the control sampling parameters also include the capacitor voltage on the low-voltage side of the n-phase three-level interleaved parallel DC converter;

[0012] Correspondingly, the two modulation signals corresponding to each phase are determined according to the high-voltage side voltage sharing control compensation value and the current sharing control compensation value, including:

[0013] According to the high-voltage side voltage sharing control compensation value, the current sharing control compensation value and the low-voltage side voltage stabilization control compensation value, two modulation signals corresponding to each phase are determined.

[0014] On the other hand, determining the high-voltage side voltage sharing control compensation value, the current sharing control compensation value and the low-voltage side voltage stabilization control compensation value according to the control sampling parameter includes:

[0015] Determining the high-side voltage sharing control compensation value according to the upper unit capacitor voltage and the lower unit capacitor voltage;

[0016] Determine the current sharing control compensation value of each phase according to the upper unit current or the lower unit current of each phase;

[0017] According to the capacitor voltage and the target sampling current on the low-voltage side, a low-voltage side voltage stabilization control compensation value of each phase is determined; wherein the target sampling current includes an upper unit current or a lower unit current of each phase.

[0018] On the other hand, determining the high-side voltage sharing control compensation value according to the upper unit capacitor voltage and the lower unit capacitor voltage includes:

[0019] Calculating an average voltage of the upper unit capacitor voltage and the lower unit capacitor voltage;

[0020] Calculating a difference between the average voltage and the upper unit capacitor voltage to obtain a first error;

[0021] A proportional-integral calculation is performed on the first error to obtain the high-pressure side equalizing pressure control compensation value.

[0022] On the other hand, determining the current sharing control compensation value according to the upper unit current or the lower unit current of each phase includes:

[0023] Calculate the average lower unit current of the lower unit currents of the n phases;

[0024] Calculating the difference between the average lower unit current and the lower unit current of each phase, to obtain a second error of each phase;

[0025] Proportional integral calculation is performed on the second error of each phase respectively to obtain a current sharing control compensation value of each phase.

[0026] On the other hand, the target sampling current includes an upper unit current of each phase; and determining the low-voltage side voltage stabilization control compensation value of each phase according to the capacitor voltage on the low-voltage side and the target sampling current includes:

[0027] Calculating a difference between a target output voltage on the low voltage side and a capacitor voltage on the low voltage side to obtain a third error;

[0028] Performing proportional integral calculation on the third error to obtain a total current reference value for voltage stabilization control;

[0029] Calculating the quotient of the total current reference value and n to obtain an average current reference value for voltage stabilization control;

[0030] Calculating the sum of the voltage stabilization control average current reference value and the feedforward current to obtain a current control amount;

[0031] Calculating the difference between the current control amount and the upper unit current of each phase, to obtain a fourth error of each phase;

[0032] Proportional integral calculation is performed on the fourth error of each phase respectively to obtain a low-voltage side voltage stabilization control compensation value of each phase.

[0033] On the other hand, the determining of two modulation signals corresponding to each phase according to the high-voltage side voltage sharing control compensation value, the current sharing control compensation value and the low-voltage side voltage stabilization control compensation value includes:

[0034] Calculate the difference between the low-voltage side voltage stabilization control compensation value and the high-voltage side voltage balancing control compensation value of each phase to obtain a first modulation signal of each phase;

[0035] The sum of the low-voltage side voltage stabilization control compensation value, the current sharing control compensation value and the high-voltage side voltage sharing control compensation value of each phase is calculated respectively to obtain a second modulation signal of each phase.

[0036] On the other hand, the method of determining the upper unit switch tube drive signal and the lower unit switch tube drive signal of each phase in the n-phase three-level interleaved parallel DC converter according to the two phase-shifted signals of each phase and the two modulation signals of each phase corresponding to the input carrier signal includes:

[0037] Determine the driving signal of the first switch tube in the upper unit switch tube driving signal of each phase according to the comparison between the first phase-shifted signal of each phase and the first modulation signal;

[0038] According to the comparison between the second phase-shifted signal and the second modulation signal of each phase, the driving signal of the fourth switch tube in the lower unit switch tube driving signal of each phase is determined; wherein the three-level bridge arm of each phase includes an upper unit switch tube and a lower unit switch tube connected in series; the upper unit switch tube of each phase includes a first switch tube and a second switch tube connected in series, and the lower unit switch tube of each phase includes a third switch tube and a fourth switch tube connected in series; the driving signal of the second switch tube of each phase is in antiphase with the driving signal of the first switch tube, and the driving signal of the third switch tube of each phase is in antiphase with the driving signal of the fourth switch tube.

[0039] In another aspect, n is 3.

[0040] The present invention also provides a control device for a three-level staggered parallel DC converter, comprising:

[0041] A compensation determination module, used to determine a high-voltage side voltage sharing control compensation value and a current sharing control compensation value of each phase according to control sampling parameters of an n-phase three-level interleaved parallel DC converter; wherein n is a positive integer greater than or equal to 2, and the control sampling parameters include an upper unit capacitor voltage and a lower unit capacitor voltage on the high-voltage side of the n-phase three-level interleaved parallel DC converter and an upper unit current and / or a lower unit current of each phase on the low-voltage side;

[0042] A modulation determination module, used to determine two modulation signals corresponding to each phase according to the high-voltage side voltage sharing control compensation value and the current sharing control compensation value;

[0043] A drive determination module, used to determine the upper unit switch tube drive signal and the lower unit switch tube drive signal of each phase in the n-phase three-level interleaved parallel DC converter according to the two phase-shifted signals of each phase and the two modulation signals of each phase corresponding to the input carrier signal; wherein the first phase-shifted signal and the second phase-shifted signal of each phase differ by 180 degrees, and the first phase-shifted signals of two adjacent phases differ by a preset clockwise or counterclockwise angle, and the preset angle is the quotient of 360 degrees and n;

[0044] The drive control module is used to control the switch tubes in the upper unit and the lower unit of the n three-level bridge arms in the n-phase three-level staggered parallel DC converter by using the upper unit switch tube drive signal and the lower unit switch tube drive signal to complete the DC-to-DC conversion.

[0045] In addition, the present invention also provides a control device for a three-level staggered parallel DC converter, comprising:

[0046] Memory for storing computer programs;

[0047] A processor is used to implement the steps of the control method of the three-level staggered parallel DC converter as described above when executing the computer program.

[0048] A control method for a three-level interleaved parallel DC converter provided by the present invention comprises: determining a high-voltage side voltage-sharing control compensation value and a current-sharing control compensation value for each phase according to control sampling parameters of an n-phase three-level interleaved parallel DC converter; wherein n is a positive integer greater than or equal to 2, and the control sampling parameters include an upper unit capacitor voltage and a lower unit capacitor voltage on the high-voltage side of the n-phase three-level interleaved parallel DC converter and an upper unit current and / or a lower unit current of each phase on the low-voltage side; determining two modulation signals corresponding to each phase according to the voltage-sharing control compensation value and the current-sharing control compensation value on the high-voltage side; and determining two modulation signals corresponding to each phase according to the input carrier signal corresponding to the input carrier signal. The two phase-shifted signals of each phase and the two modulation signals of each phase are used to determine the upper unit switch tube driving signal and the lower unit switch tube driving signal of each phase in the n-phase three-level interleaved parallel DC converter; wherein the first phase-shifted signal and the second phase-shifted signal of each phase differ by 180 degrees, and the first phase-shifted signals of two adjacent phases differ by a preset angle clockwise or counterclockwise, and the preset angle is the quotient of 360 degrees and n; the upper unit switch tube driving signal and the lower unit switch tube driving signal are used to control the switch tubes in the upper unit and the lower unit of each of the n three-level bridge arms in the n-phase three-level interleaved parallel DC converter to complete the DC-to-DC conversion.

[0049] It can be seen that the present invention determines the high-voltage side voltage-balanced control compensation value and the current-balanced control compensation value of each phase according to the control sampling parameters of the n-phase three-level staggered parallel DC converter, and can conveniently suppress the uneven voltage of the high-voltage side capacitor of the converter through compensation, and suppress the circulating current of the converter, improve the balance of the output current of each phase, thereby improving the control accuracy and stability of the system; and according to the two phase-shifted signals of each phase and the two modulation signals of each phase corresponding to the input carrier signal, determine the upper unit switch tube drive signal and the lower unit switch tube drive signal of each phase in the n-phase three-level staggered parallel DC converter, adopt the carrier phase-shifted modulation technology, realize the independent PWM control of each phase, improve the applicability, and thus realize the application of higher power level. In addition, the present invention also provides a control device and equipment for a three-level staggered parallel DC converter, which also has the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0051] Figure 1 A flow chart of a control method for a three-level staggered parallel DC converter provided by an embodiment of the present invention;

[0052] Figure 2 A schematic diagram of the circuit structure of a three-phase three-level interleaved parallel DC converter provided by an embodiment of the present invention;

[0053] Figure 3 A flow chart of another control method of a three-level interleaved parallel DC converter provided by an embodiment of the present invention;

[0054] Figure 4 A control schematic block diagram of a three-phase three-level interleaved parallel DC converter provided by an embodiment of the present invention;

[0055] Figure 5 A schematic block diagram of a carrier phase shift control method provided by an embodiment of the present invention;

[0056] Figure 6 A schematic diagram of a carrier phase-shift switch tube drive provided by an embodiment of the present invention;

[0057] Figure 7 It is a schematic diagram of a switch tube driving state of the three-level bridge arm of the u phase;

[0058] Figure 8Schematic diagram of another switch tube driving state of the three-level bridge arm of the u phase;

[0059] Fig. 9 Schematic diagram of another switch tube driving state of the three-level bridge arm of the u phase;

[0060] Fig.10 The voltage waveforms of the high and low voltage sides are shown when the voltage equalization control is not started;

[0061] Fig.11 The voltage waveforms of the high and low voltage sides are shown when the voltage equalization control is started;

[0062] Fig.12 The waveform diagram of the output current of the lower unit when the current sharing control is not started;

[0063] Fig.13 The waveform diagram of the output current of the lower unit when the current sharing control is started;

[0064] Fig.14 A structural block diagram of a control device for a three-level staggered parallel DC converter provided by an embodiment of the present invention;

[0065] Fig.15 A schematic structural diagram of a control device for a three-level interleaved parallel DC converter provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0067] Please refer to Figure 1 , Figure 1 A flow chart of a control method for a three-level staggered parallel DC converter provided by an embodiment of the present invention. The method may include:

[0068] Step 101: Determine a high-side voltage sharing control compensation value and a current sharing control compensation value for each phase according to control sampling parameters of an n-phase three-level interleaved parallel DC converter.

[0069] Wherein, n is a positive integer greater than or equal to 2, and the control sampling parameters include the upper unit capacitor voltage and the lower unit capacitor voltage on the high voltage side of the n-phase three-level staggered parallel DC converter and the upper unit current and / or lower unit current of each phase on the low voltage side.

[0070] It should be noted that the control method provided in this embodiment can be used to control the on and off of the switch tubes (such as insulated gate bipolar transistors IGBT tubes or field effect transistors MOS tubes) in n three-level bridge arms in an n-phase three-level staggered parallel DC converter, thereby completing the DC-to-DC conversion. In this embodiment, the number n can be greater than or equal to 2, that is, the number of three-level bridge arms in the three-level staggered parallel DC converter can be greater than or equal to 2; Figure 2 As shown, n can be 3, and the control method provided in this embodiment can be used to control a three-phase three-level staggered parallel DC converter; n can also be 2 or a value greater than 3, and this embodiment does not impose any limitation on this.

[0071] Correspondingly, the specific circuit structure of the n-phase three-level interleaved parallel DC converter in this embodiment can be set by the designer, such as by adopting the same or similar method as the structure of the three-level interleaved parallel DC converter in the prior art. Figure 3 As shown, the n-phase three-level interleaved parallel DC converter may include n parallel three-level bridge arms, each of which may include two switch tubes of an upper unit (i.e., the upper unit switch tube) and two switch tubes of a lower unit (i.e., the lower unit switch tube), that is, each three-level bridge arm may include four switch tubes connected in series (i.e., the first switch tube to the fourth switch tube), the two switch tubes of the upper unit of each three-level bridge arm may include a first switch tube and a second switch tube, and the two switch tubes of the lower unit of each three-level bridge arm may include a third switch tube and a fourth switch tube; the common end connected to the first end of the first switch tube in all the three-level bridge arms may be connected to the first end of the upper unit capacitor (C1) on the high voltage side, and the second switch tubes of all the three-level bridge arms may be connected to the first end of the upper unit capacitor (C1) on the high voltage side. The common end connected to the second end of the first switch tube and the first end of the third switch tube can be respectively connected to the second end of the upper unit capacitor on the high voltage side and the first end of the lower unit capacitor (C2) on the high voltage side, and the common end connected to the second end of the fourth switch tube in all three-level bridge arms can be connected to the second end of the lower unit capacitor on the high voltage side; the common end connected to the second end of the first switch tube of each three-level bridge arm and the first end of the second switch tube can be connected to the first end of the low voltage side capacitor (C3) through their respective inductors (such as L1, L2 or L3), and the common end connected to the second end of the third switch tube of each three-level bridge arm and the first end of the fourth switch tube can be connected to the second end of the low voltage side capacitor (C3) through their respective inductors (such as L4, L5 or L6).

[0072] Accordingly, the control sampling parameters in this embodiment can be obtained by sampling from the n-phase three-level interleaved parallel DC converter to control the switch tubes in the upper unit and the lower unit of each of the n three-level bridge arms. The specific number and type of control sampling parameters in this embodiment can be set by the designer according to practical scenarios and user needs. For example, the control sampling parameters may include the upper unit capacitor voltage and the lower unit capacitor voltage on the high-voltage side of the n-phase three-level interleaved parallel DC converter required for the voltage equalization control on the high-voltage side, such as Figure 2 The voltage v at the upper cell capacitor C1 is shown H1 and the voltage v at the lower unit capacitor C2 H2 The control sampling parameters may also include the upper unit current and / or lower unit current of each phase on the low voltage side of the n-phase three-level interleaved parallel DC converter required for current sharing control, such as Figure 2 The current i of the inductors L1, L2 and L3 is shown L1 、i L2 and i L3 and / or the current i of each of the inductors L4, L5 and L6 L4 、i L5 and i L6 The control sampling parameters may also include the capacitor voltage on the low voltage side of the n-phase three-level interleaved parallel DC converter required for overall voltage control (ie, voltage regulation control) (eg Figure 2 The voltage v at the capacitor C3 on the medium and low voltage sides dc ) and the upper unit current or lower unit current of each phase. This embodiment does not impose any restriction on this.

[0073] It can be understood that in this step, the processor can use the control sampling parameters of the n-phase three-level staggered parallel DC converter to determine the compensation value of the voltage control on the high-voltage side (i.e., the voltage control compensation value on the high-voltage side) and the compensation value of each phase of the current control (i.e., the current control compensation value) through PI (proportional integral) control. The specific method of determining the voltage control compensation value on the high-voltage side and the current control compensation value of each phase according to the control sampling parameters of the n-phase three-level staggered parallel DC converter in this step can be set by the designer according to the usage scenario and user needs. For example, the processor can determine the voltage control compensation value on the high-voltage side according to the upper unit capacitor voltage and the lower unit capacitor voltage; and determine the current control compensation value of each phase according to the upper unit current or the lower unit current of each phase. The processor can also determine the high-voltage side voltage-equalizing control compensation value, the current-equalizing control compensation value, and the low-voltage side voltage-stabilizing control compensation value according to the control sampling parameters; wherein the control sampling parameters also include the capacitor voltage on the low-voltage side of the n-phase three-level staggered parallel DC converter; that is, the processor can determine the high-voltage side voltage-equalizing control compensation value, the current-equalizing control compensation value, and the low-voltage side voltage-stabilizing control compensation value through PI control according to the control sampling parameters, so that in this embodiment, not only the high-voltage side voltage-equalizing control and current-equalizing control can be performed on the n-phase three-level staggered parallel DC converter, but also the low-voltage side voltage-stabilizing control can be performed. For example, the processor can determine the high-voltage side voltage-equalizing control compensation value according to the upper unit capacitor voltage and the lower unit capacitor voltage; determine the current-equalizing control compensation value of each phase according to the upper unit current or the lower unit current of each phase; determine the low-voltage side voltage-stabilizing control compensation value of each phase according to the capacitor voltage on the low-voltage side and the target sampling current; wherein the target sampling current includes the upper unit current or the lower unit current of each phase.

[0074] Step 102: Determine two modulation signals corresponding to each phase according to the voltage sharing control compensation value and the current sharing control compensation value on the high-voltage side.

[0075] It can be understood that in this embodiment, the processor can determine the two modulation signals (i.e., the first modulation signal and the second modulation signal) required for the carrier phase shift control modulation corresponding to each phase based on the determined high-voltage side voltage equalization control compensation value and the current equalization control compensation value of each phase, such as the driving signals of the first switch tube and the fourth switch tube in the three-level bridge arm of each phase each determine the required modulation signal.

[0076] Correspondingly, the specific method of determining the two modulation signals corresponding to each phase according to the high-voltage side voltage equalization control compensation value and the current equalization control compensation value in this step can be set by the designer according to practical scenarios and user needs. Taking the working mode of the n-phase three-level staggered parallel DC converter as converting the input voltage on the high-voltage side into the voltage output on the low-voltage side as an example, the processor can directly calculate the difference between the target output voltage on the low-voltage side and the voltage equalization control compensation value on the high-voltage side to obtain the first modulation signal of each phase; respectively calculate the low-voltage side target output voltage and the sum of the current equalization control compensation value and the voltage equalization compensation value on the high-voltage side to obtain the second modulation signal of each phase. The processor can also determine the two modulation signals corresponding to each phase according to the high-voltage side voltage balancing control compensation value, the current balancing control compensation value and the low-voltage side voltage stabilization control compensation value; for example, when the low-voltage side of the n-phase three-level staggered parallel DC converter outputs voltage to the external load, the processor can calculate the difference between the low-voltage side voltage stabilization control compensation value and the high-voltage side voltage balancing control compensation value of each phase, and obtain the first modulation signal of each phase; calculate the sum of the low-voltage side voltage stabilization control compensation value and the current balancing control compensation value and the high-voltage side voltage balancing control compensation value of each phase, and obtain the second modulation signal of each phase. This embodiment does not impose any restrictions on this.

[0077] Step 103: Determine an upper unit switch tube driving signal and a lower unit switch tube driving signal of each phase in the n-phase three-level interleaved parallel DC converter according to two phase shift signals of each phase and two modulation signals of each phase corresponding to the input carrier signal.

[0078] The first phase-shifted signal and the second phase-shifted signal of each phase differ by 180 degrees, and the first phase-shifted signals of two adjacent phases differ by a preset clockwise or counterclockwise angle, which is the quotient of 360 degrees and n.

[0079] It should be noted that in this embodiment, a carrier phase-shift control modulation strategy can be adopted for the n-phase three-level interleaved parallel DC converter. Through a multi-phase PWM generation method, the two phase-shifted signals of each phase obtained by phase-shifting the input carrier signal (i.e., the first phase-shifted signal and the second phase-shifted signal) are compared with the two modulation signals of each phase to determine the upper unit switch tube drive signal and the lower unit switch tube drive signal of each phase in the converter, thereby realizing independent PWM control of each phase.

[0080] Correspondingly, in this embodiment, the first phase shift signal and the second phase shift signal of each phase differ by 180 degrees, that is, the upper and lower unit driving waveforms differ by 180 degrees in each phase, so as to realize the phase shift control of the upper and lower units; the first phase shift signals of adjacent two phases differ by 180 degrees clockwise or counterclockwise. (i.e. preset angle), , that is, the phase difference of each phase in the phase-to-phase drive waveform angle.

[0081] The upper unit switch tube driving signal in this embodiment may be the driving signal of the two switch tubes (i.e., the first switch tube and the second switch tube) of the upper unit in the three-level bridge arm of each phase in the n-phase three-level interleaved parallel DC converter, and the driving signals of the two switch tubes may be inverted, i.e., when the driving signal of the first switch tube of a certain phase is at a high level, the driving signal of the second switch tube of the phase is at a low level. The lower unit switch tube driving signal in this embodiment may be the driving signal of the two switch tubes (i.e., the third switch tube and the fourth switch tube) of the lower unit in the three-level bridge arm of each phase in the n-phase three-level interleaved parallel DC converter, and the driving signals of the two switch tubes may be inverted, i.e., when the driving signal of the third switch tube of a certain phase is at a high level, the driving signal of the fourth switch tube of the phase is at a low level.

[0082] For example, in this embodiment, the processor can determine the drive signal of the first switch tube in the upper unit switch tube drive signal of each phase based on the comparison between the first phase-shifted signal and the first modulation signal of each phase, such as when the first modulation signal of a phase is greater than the first phase-shifted signal, the drive signal of the first switch tube of the phase is determined to be a high level, otherwise it is a low level; according to the comparison between the second phase-shifted signal and the second modulation signal of each phase, the drive signal of the fourth switch tube in the lower unit switch tube drive signal of each phase is determined, such as when the second modulation signal of a phase is greater than the second phase-shifted signal, the drive signal of the fourth switch tube of the phase is determined to be a high level, otherwise it is a low level; wherein the three-level bridge arm of each phase includes an upper unit switch tube and a lower unit switch tube connected in series; the upper unit switch tube of each phase includes a first switch tube and a second switch tube connected in series, and the lower unit switch tube of each phase includes a third switch tube and a fourth switch tube connected in series; the drive signal of the second switch tube of each phase is inverted with the drive signal of the first switch tube, and the drive signal of the third switch tube of each phase is inverted with the drive signal of the fourth switch tube.

[0083] Step 104: Using the upper unit switch tube driving signal and the lower unit switch tube driving signal, control the switch tubes in the upper unit and the lower unit of the n three-level bridge arms in the n-phase three-level staggered parallel DC converter to complete the DC-to-DC conversion.

[0084] It can be understood that in this step, the processor can use the upper unit switch tube drive signal and the lower unit switch tube drive signal of each phase to respectively control the switch tubes connected in series in the three-level bridge arm of each phase to complete the DC-to-DC conversion of the n-phase three-level interleaved parallel DC converter.

[0085] In this embodiment, the embodiment of the present invention determines the high-voltage side voltage equalization control compensation value and the current equalization control compensation value of each phase according to the control sampling parameters of the n-phase three-level staggered parallel DC converter, and can conveniently suppress the uneven voltage of the high-voltage side capacitor of the converter and suppress the circulating current of the converter through compensation, thereby improving the balance of the output current of each phase, thereby improving the control accuracy and stability of the system; and according to the two phase-shifted signals of each phase and the two modulation signals of each phase corresponding to the input carrier signal, the upper unit switch tube drive signal and the lower unit switch tube drive signal of each phase in the n-phase three-level staggered parallel DC converter are determined, and the carrier phase-shift modulation technology is adopted to realize independent PWM control of each phase, thereby improving applicability, thereby realizing applications with higher power levels.

[0086] Based on the above embodiment, the present invention also provides another control method for a three-level staggered parallel DC converter to further achieve overall voltage stabilization control. Figure 3 , Figure 3 A flow chart of another control method of a three-level interleaved parallel DC converter provided by an embodiment of the present invention. The method may include:

[0087] Step 201: Obtain control sampling parameters of an n-phase three-level interleaved parallel DC converter; wherein the control sampling parameters may include an upper unit capacitor voltage and a lower unit capacitor voltage on a high voltage side of the n-phase three-level interleaved parallel DC converter, an upper unit current and a lower unit current of each phase on a low voltage side, and a capacitor voltage on the low voltage side.

[0088] Step 202: Determine a high-side voltage sharing control compensation value according to the upper unit capacitor voltage and the lower unit capacitor voltage.

[0089] Among them, in this step, the processor can determine the compensation value of the voltage equalization control on the high-voltage side (i.e., the high-voltage side voltage equalization control compensation value) through PI control operation based on the upper unit capacitor voltage and the lower unit capacitor voltage on the high-voltage side sampled from the n-phase three-level interleaved parallel DC converter.

[0090] Correspondingly, the specific method of determining the high-voltage side voltage equalization control compensation value according to the upper unit capacitor voltage and the lower unit capacitor voltage in this step can be set by the designer according to the usage scenario and user needs. For example, in this step, the processor can calculate the average voltage of the upper unit capacitor voltage and the lower unit capacitor voltage; calculate the difference between the average voltage and the upper unit capacitor voltage (or the lower unit capacitor voltage) to obtain a first error; and perform proportional integral calculation on the first error to obtain the high-voltage side voltage equalization control compensation value.

[0091] like Figure 4 As shown, in the voltage balancing control on the high-voltage side, the processor can calculate the upper unit capacitor voltage (u H1 ) and the lower unit capacitor voltage (uH2 ) is the average voltage, ; Calculate the average voltage and u H1 The difference between the first error and the second error is obtained; the first error is subjected to proportional integral (PI) calculation to obtain the high-pressure side equalizing pressure control compensation value (u av ), such as by calculating the product of the first error and the preset voltage balancing control proportional gain and the preset voltage balancing control integral gain, the sum of the two products is determined as the high-voltage side voltage balancing control compensation value. In other words, the processor can perform midpoint potential balance control on the high-voltage bus voltage and calculate the voltage reference value of the voltage balancing control. , that is, the average voltage; the upper unit capacitor voltage u on the high voltage side H1 As the voltage control object of the voltage equalization control method, the difference between the two is obtained to obtain the first error. After proportional integral operation, the voltage compensation value u of the voltage equalization control is output. av (i.e., the high-pressure side equalizing control compensation value).

[0092] Step 203: Determine the current sharing control compensation value of each phase according to the upper unit current or the lower unit current of each phase.

[0093] It can be understood that in this step, the processor can determine the compensation value of the current sharing control of each phase (i.e., the current sharing control compensation value) through PI control operation based on the upper unit current or lower unit current of each phase sampled from the n-phase three-level staggered parallel DC converter; since the control object of the current sharing control is DC, there is no need for a coordinate transformation link after sampling the three-phase current, and PI proportional integral operation control is used, which can achieve an ideal suppression effect and reduce the amount of control operations.

[0094] Correspondingly, for the specific method of determining the current sharing control compensation value of each phase according to the upper unit current or lower unit current of each phase in this step, the designer can set it according to the usage scenario and user needs. For example, when the processor uses the upper unit current of each phase for voltage stabilization control, the processor can use the lower unit current of each phase to determine the current sharing control compensation value of each phase to achieve current sharing control of each phase; for example, the processor can calculate the average lower unit current of the lower unit current of n phases; calculate the difference between the average lower unit current and the lower unit current of each phase, respectively, to obtain the second error of each phase; perform proportional integral calculation on the second error of each phase, respectively, to obtain the current sharing control compensation value of each phase. Correspondingly, when the processor uses the lower unit current of each phase for voltage stabilization control, the processor can also adopt a method corresponding to the above process, using the upper unit current of each phase to determine the current sharing control compensation value of each phase, so as to achieve current sharing control of each phase, and this embodiment does not impose any restrictions on this.

[0095] For example, when n is 3, Figure 4As shown, during the current sharing control process, the processor can calculate the lower unit current of the three phases (i L4 、i L5 and i L6 ) of the average lower unit current ( ); Calculate the difference between the average lower unit current and the lower unit current of each phase to obtain the second error of each phase; Perform proportional integral calculation on the second error of each phase to obtain the current sharing control compensation value (u) of each phase aiu 、u aiv and u aiw ), such as by calculating the product of the second error of a certain phase and the preset current sharing control proportional gain and the preset current sharing control integral gain of the phase, and determining the sum of the two products as the current sharing control compensation value of the phase. In other words, the processor can perform current sharing control on each phase of the six output currents of the three phases, and calculate the current sharing control current reference value , that is, the average lower unit current; the current control current reference value i Lref The three-phase current sampling feedback value i is output by the lower unit respectively L4 、i L5 and i L6 The three-way current sharing control current error (i.e., the second error) is obtained by subtracting the three-way current sharing control current error. After the three-way error is acted upon by independent PI controllers, the current sharing control output modulation signal compensation value u is obtained. aiu 、u aiv and u aiw .

[0096] Step 204: Determine the low-voltage side voltage regulation control compensation value of each phase according to the capacitor voltage and the target sampling current on the low-voltage side; wherein the target sampling current includes the upper unit current or the lower unit current of each phase.

[0097] It can be understood that in this step, the processor can determine the compensation value of the overall voltage control of each phase (i.e., the low-voltage side voltage regulation control compensation value) through PI control operation based on the capacitor voltage on the low-voltage side and the upper unit current or lower unit current of each phase sampled from the n-phase three-level interleaved parallel DC converter.

[0098] Correspondingly, the specific method for determining the low-voltage side voltage stabilization control compensation value of each phase according to the capacitor voltage and the target sampling current on the low-voltage side in this step can be set by the designer according to the usage scenario and user needs. For example, the processor can determine the low-voltage side voltage stabilization control compensation value of each phase through a dual-loop PI control operation based on the capacitor voltage on the low-voltage side and the upper unit current of each phase; or it can determine the low-voltage side voltage stabilization control compensation value of each phase through a dual-loop PI control operation based on the capacitor voltage on the low-voltage side and the lower unit current of each phase. This embodiment does not impose any restrictions on this.

[0099] For example, when the processor determines the low-voltage side voltage regulation control compensation value of each phase through a dual-loop PI control operation based on the capacitor voltage on the low-voltage side and the upper unit current of each phase, when the low-voltage side of the n-phase three-level staggered parallel DC converter outputs a voltage to an external load, the processor can determine the low-voltage side voltage regulation control compensation value of each phase based on the capacitor voltage on the low-voltage side, the upper unit current of each phase and the low-voltage side target output voltage (that is, the target value of the low-voltage side output voltage to the external load); for example, the processor can calculate the low-voltage side target output voltage and the low-voltage side The difference of capacitor voltage is obtained to obtain the third error; the third error is calculated by proportional integral (i.e., the first loop PI calculation) to obtain the total current reference value of voltage stabilization control; the quotient of the total current reference value and n is calculated to obtain the average current reference value of voltage stabilization control; the sum of the average current reference value of voltage stabilization control and the feedforward current is calculated to obtain the current control amount; the difference between the current control amount and the upper unit current of each phase is calculated to obtain the fourth error of each phase; the fourth error of each phase is calculated by proportional integral (i.e., the second loop PI calculation) to obtain the low-voltage side voltage stabilization control compensation value of each phase. Correspondingly, when the processor determines the low-voltage side voltage stabilization control compensation value of each phase according to the capacitor voltage on the low-voltage side and the lower unit current of each phase through the dual-loop PI control operation, the processor can determine the low-voltage side voltage stabilization control compensation value of each phase according to the capacitor voltage on the low-voltage side, the lower unit current of each phase and the target output voltage on the low-voltage side; if it can be set in a manner corresponding to the above process, this embodiment does not impose any restrictions on this.

[0100] Correspondingly, the above process is demonstrated by taking the output voltage of the low-voltage side of the n-phase three-level interleaved parallel DC converter to the external load as an example. For the case where the high-voltage side of the n-phase three-level interleaved parallel DC converter outputs the voltage to the outside, a corresponding method can be used for setting, that is, the n-phase three-level interleaved parallel DC converter controlled in this embodiment can complete the DC-to-DC output from the high-voltage side to the low-voltage side, and can also complete the DC-to-DC output from the low-voltage side to the high-voltage side. This embodiment does not impose any restrictions on this.

[0101] like Figure 4 As shown, when n is 3, the processor can calculate the low-voltage side target output voltage ( ) and the capacitor voltage on the low voltage side (V dc ) to obtain the third error; perform proportional integral calculation on the third error to obtain the total current reference value for voltage regulation control; calculate the quotient of the total current reference value and 3 to obtain the average current reference value for voltage regulation control (i ref ); Calculate the average current reference value and feedforward current value of voltage regulation control (i D ) and obtain the current control quantity ( ); Calculate the current control quantity and the upper unit current of each phase (iL1 、i L2 and i L3 ) to obtain the fourth error of each phase; perform proportional integral calculation on the fourth error of each phase respectively to obtain the low-voltage side voltage regulation control compensation value of each phase. Among them, the feedforward current can be the current of the upper unit capacitor C1 on the high-voltage side, the current of the lower unit capacitor C2 or the current of the low-voltage side capacitor C3, or the product of the current of C1, C2 or C3 and the preset parameter. In other words, the processor does not need to perform a coordinate transformation link to sample the voltage V dc And the output current i of the three-phase unit L1 、i L2 and i L3 Perform dual-loop proportional-integral operation and superimpose the feedforward current i D Then the three-phase modulation signal u of the overall voltage control is obtained u 、u v and u w .

[0102] Among them, the target sampling current used in the calculation of the low-voltage side voltage regulation control compensation value in this embodiment may be different from the sampling current value (i.e., the upper unit current or the lower unit current of each phase) used in the calculation of the current sharing control compensation value. For example, in some embodiments, step 203 may determine the current sharing control compensation value of each phase according to the lower unit current of each phase; step 204 may determine the low-voltage side voltage regulation control compensation value of each phase according to the capacitor voltage on the low-voltage side and the upper unit current of each phase. In other embodiments, step 203 may determine the current sharing control compensation value of each phase according to the upper unit current of each phase; step 204 may determine the low-voltage side voltage regulation control compensation value of each phase according to the capacitor voltage on the low-voltage side and the lower unit current of each phase.

[0103] Step 205: Determine two modulation signals corresponding to each phase according to the high-voltage side voltage sharing control compensation value, the current sharing control compensation value and the low-voltage side voltage stabilization control compensation value.

[0104] It can be understood that in this embodiment, the processor can determine the two modulation signals (i.e., the first modulation signal and the second modulation signal) required for the carrier phase shift control modulation corresponding to each phase based on the determined high-voltage side voltage equalization control compensation value, the current equalization control compensation value of each phase, and the low-voltage side voltage regulation control compensation value, such as the driving signals of the first switch tube and the fourth switch tube in the three-level bridge arm of each phase each determine the required modulation signal.

[0105] Correspondingly, in this step, the processor determines the specific method of the two modulation signals corresponding to each phase according to the high-voltage side voltage equalization control compensation value, the current equalization control compensation value and the low-voltage side voltage stabilization control compensation value. The method can be set by the designer according to the usage scenario and user needs. For example, the processor can calculate the difference between the low-voltage side voltage stabilization control compensation value and the high-voltage side voltage equalization control compensation value of each phase to obtain the first modulation signal of each phase; calculate the sum of the low-voltage side voltage stabilization control compensation value and the current equalization control compensation value and the high-voltage side voltage equalization control compensation value of each phase to obtain the second modulation signal of each phase. Taking the output u phase as an example, the high-voltage side voltage equalization control compensation value u av The low voltage side voltage regulation control compensation value u of phase u u Calculate, that is and , can realize the balanced control of the upper and lower bus capacitor voltages on the high-voltage side; on this basis, the u-phase current control compensation value u aiu And add calculation, that is and , we can get two modulation signals of phase u, namely the first modulation signal u uup and the second modulation signal u udowm .

[0106] Correspondingly, the processor may also calculate the product of the difference between the low-voltage side voltage stabilization control compensation value and the high-voltage side voltage equalization control compensation value of each phase and the respective first additional compensation parameter to obtain the first modulation signal of each phase; calculate the product of the low-voltage side voltage stabilization control compensation value of each phase and the respective current equalization control compensation value and the high-voltage side voltage equalization control compensation value and the respective second additional compensation parameter to obtain the second modulation signal of each phase. This embodiment does not impose any limitation on this.

[0107] Step 206: Determine an upper unit switch tube driving signal and a lower unit switch tube driving signal for each phase in the n-phase three-level interleaved parallel DC converter according to two phase-shifted signals for each phase and two modulation signals for each phase corresponding to the input carrier signal.

[0108] The first phase-shifted signal and the second phase-shifted signal of each phase differ by 180 degrees, and the first phase-shifted signals of two adjacent phases may differ by a preset clockwise angle, which is the quotient of 360 degrees and n.

[0109] Correspondingly, in this step, the processor determines the specific method of the upper unit switch tube drive signal and the lower unit switch tube drive signal of each phase in the n-phase three-level interleaved parallel DC converter according to the two phase-shifted signals of each phase corresponding to the input carrier signal and the two modulation signals of each phase. The method can be set by the designer according to the usage scenario and user needs. For example, the processor can determine the drive signal of the first switch tube in the upper unit switch tube drive signal of each phase according to the comparison between the first phase-shifted signal of each phase and the first modulation signal; and determine the drive signal of the fourth switch tube in the lower unit switch tube drive signal of each phase according to the comparison between the second phase-shifted signal of each phase and the second modulation signal. Among them, the three-level bridge arm of each phase includes an upper unit switch tube and a lower unit switch tube connected in series; the upper unit switch tube of each phase includes a first switch tube and a second switch tube connected in series, and the lower unit switch tube of each phase includes a third switch tube and a fourth switch tube connected in series; the driving signal of the second switch tube of each phase is inverted with the driving signal of the first switch tube, and the driving signal of the third switch tube of each phase is inverted with the driving signal of the fourth switch tube; the upper unit switch tube driving signal of each phase may include the driving signal of the first switch tube and the driving signal of the second switch tube of the phase; the lower unit switch tube driving signal of each phase may include the driving signal of the third switch tube and the driving signal of the fourth switch tube of the phase.

[0110] For example, when n is 3, Figure 5 As shown, the first phase-shifted signal and the second phase-shifted signal of each phase may differ by 180 degrees, and the first phase-shifted signals of two adjacent phases may differ by 120 degrees clockwise. The first phase-shifted signal of the u-phase may be the input carrier signal, and the second phase-shifted signal may be the input carrier signal shifted by 180 degrees; the first phase-shifted signal of the v-phase may be the first phase-shifted signal of the u-phase shifted by 120 degrees clockwise, and the second phase-shifted signal may be the first phase-shifted signal of the v-phase shifted by 180 degrees; the first phase-shifted signal of the w-phase may be the first phase-shifted signal of the v-phase shifted by 120 degrees clockwise, and the second phase-shifted signal may be the first phase-shifted signal of the w-phase shifted by 180 degrees. Figure 6 As shown, taking phase u as an example, the processor can up carrier) is less than the first modulation signal of the u phase, the driving signal of the first switch tube of the u phase is determined to be high level, and the driving signal of the second switch tube of the u phase is low level; when the first phase shift signal of the u phase is not less than the first modulation signal of the u phase, the driving signal of the first switch tube of the u phase is determined to be low level, and the driving signal of the second switch tube of the u phase is high level; the processor can downcarrier) is less than the second modulation signal of the u phase, the drive signal of the fourth switch tube of the u phase is determined to be high level, and the drive signal of the third switch tube of the u phase is determined to be low level; when the second phase-shifted signal of the u phase is not less than the second modulation signal of the u phase, the drive signal of the fourth switch tube of the u phase is determined to be low level, and the drive signal of the third switch tube of the u phase is determined to be high level; accordingly, by U up Carrier, U down The carrier participates in the modulation and drives the first switch tube S of the u phase a1 , the second switch tube S a2 , the third switch tube S a3 and the fourth switch tube S a4 , we can get Figure 7-Figure 9 The u-phase current flow direction is shown.

[0111] Step 206: Using the upper unit switch tube driving signal and the lower unit switch tube driving signal, control the switch tubes in the upper unit and the lower unit of the n three-level bridge arms in the n-phase three-level staggered parallel DC converter to complete the DC-to-DC conversion.

[0112] It can be understood that in this step, the processor can use the upper unit switch tube drive signal and the lower unit switch tube drive signal of each phase to respectively control the switch tubes connected in series in the three-level bridge arm of each phase to complete the DC-to-DC conversion of the n-phase three-level interleaved parallel DC converter.

[0113] Through simulation, it can be determined that the pressure equalization control method provided by this embodiment can Fig.10 The upper half bus voltage (i.e., upper unit capacitor voltage) and the lower half bus voltage (i.e., lower unit capacitor voltage) of the high voltage side above and below the low voltage side are balanced to Fig.11 The state shown in the figure makes the capacitor voltage of the upper and lower busbar units balanced; and the current sharing control method provided by this embodiment can Fig.12 The lower unit output current (i L4 、i L5 and i L6 ) waveform is equalized to Fig.13 The state shown in the figure achieves output current balance.

[0114] In this embodiment, the embodiment of the present invention adopts three-level control strategies of voltage equalization control, current equalization control and overall voltage control to achieve complete decoupling and independence from each other, realizes voltage stabilization through overall voltage control, realizes voltage balance of upper and lower bus unit capacitors through voltage equalization control, and realizes current balance of upper and lower units of each phase through current equalization control.

[0115] Corresponding to the above method embodiments, an embodiment of the present invention further provides a control device for a three-level interleaved parallel DC converter. The control device for a three-level interleaved parallel DC converter described below and the control method for a three-level interleaved parallel DC converter described above can be referred to each other.

[0116] Please refer to Fig.14 , Fig.14 A structural block diagram of a control device for a three-level staggered parallel DC converter provided by an embodiment of the present invention. The device may include:

[0117] A compensation determination module 10 is used to determine a high-voltage side voltage sharing control compensation value and a current sharing control compensation value of each phase according to control sampling parameters of an n-phase three-level interleaved parallel DC converter; wherein n is a positive integer greater than or equal to 2, and the control sampling parameters include an upper unit capacitor voltage and a lower unit capacitor voltage on the high-voltage side of the n-phase three-level interleaved parallel DC converter and an upper unit current and / or a lower unit current of each phase on the low-voltage side;

[0118] A modulation determination module 20, for determining two modulation signals corresponding to each phase according to a high-voltage side voltage sharing control compensation value and a current sharing control compensation value;

[0119] The drive determination module 30 is used to determine the upper unit switch tube drive signal and the lower unit switch tube drive signal of each phase in the n-phase three-level interleaved parallel DC converter according to the two phase-shifted signals of each phase corresponding to the input carrier signal and the two modulation signals of each phase; wherein the first phase-shifted signal and the second phase-shifted signal of each phase differ by 180 degrees, and the first phase-shifted signals of two adjacent phases differ by a preset angle clockwise or counterclockwise, and the preset angle is the quotient of 360 degrees and n;

[0120] The drive control module 40 is used to control the switch tubes in the upper unit and the lower unit of the n three-level bridge arms in the n-phase three-level staggered parallel DC converter using the upper unit switch tube drive signal and the lower unit switch tube drive signal to complete the DC-to-DC conversion.

[0121] In some embodiments, the compensation determination module 10 can be specifically used to determine the high-voltage side voltage sharing control compensation value, the current sharing control compensation value and the low-voltage side voltage stabilization control compensation value according to the control sampling parameters; wherein the control sampling parameters also include the capacitor voltage on the low-voltage side of the n-phase three-level interleaved parallel DC converter;

[0122] Correspondingly, the modulation determination module 20 can be specifically used to determine two modulation signals corresponding to each phase according to the high-voltage side voltage sharing control compensation value, the current sharing control compensation value and the low-voltage side voltage stabilization control compensation value.

[0123] In some embodiments, the compensation determination module 10 may include:

[0124] The voltage balancing compensation submodule is used to determine the high-voltage side voltage balancing control compensation value according to the upper unit capacitor voltage and the lower unit capacitor voltage;

[0125] The current sharing compensation submodule is used to determine the current sharing control compensation value of each phase according to the upper unit current or the lower unit current of each phase;

[0126] The voltage stabilization compensation submodule is used to determine the low-voltage side voltage stabilization control compensation value of each phase according to the capacitor voltage and the target sampling current on the low-voltage side; wherein the target sampling current includes the upper unit current or the lower unit current of each phase.

[0127] In some embodiments, the voltage balance compensation submodule may include:

[0128] A first calculation unit, used for calculating an average voltage of an upper unit capacitor voltage and a lower unit capacitor voltage;

[0129] A second calculation unit, used for calculating the difference between the average voltage and the upper unit capacitor voltage to obtain a first error;

[0130] The first PI unit is used to perform proportional integral calculation on the first error to obtain a high-voltage side equalizing pressure control compensation value.

[0131] In some embodiments, the current sharing compensation submodule may include:

[0132] A third calculation unit is used to calculate an average lower unit current of the lower unit currents of the n phases;

[0133] a fourth calculation unit, used for calculating the difference between the average lower unit current and the lower unit current of each phase, to obtain a second error of each phase;

[0134] The second PI unit is used to perform proportional integral calculation on the second error of each phase respectively to obtain a current sharing control compensation value of each phase.

[0135] In some embodiments, the voltage stabilization compensation submodule may include:

[0136] a fifth calculation unit, configured to calculate a difference between a target output voltage on the low voltage side and a capacitor voltage on the low voltage side to obtain a third error;

[0137] A third PI unit is used to perform proportional integral calculation on the third error to obtain a total current reference value for voltage stabilization control;

[0138] a sixth calculation unit, used for calculating the quotient of the total current reference value and n to obtain an average current reference value for voltage stabilization control;

[0139] A seventh calculation unit, used for calculating the sum of the voltage stabilization control average current reference value and the feedforward current amount to obtain a current control amount;

[0140] an eighth calculation unit, used for calculating the difference between the current control amount and the upper unit current of each phase, to obtain a fourth error of each phase;

[0141] The fourth PI unit is used to perform proportional integral calculation on the fourth error of each phase respectively to obtain a low-voltage side voltage stabilization control compensation value of each phase.

[0142] In some embodiments, the modulation determination module 20 may include:

[0143] A first modulation determination submodule is used to calculate the difference between the low-voltage side voltage stabilization control compensation value and the high-voltage side voltage sharing control compensation value of each phase, and obtain a first modulation signal of each phase;

[0144] The second modulation determination submodule is used to calculate the sum of the low-voltage side voltage stabilization control compensation value of each phase and the respective current sharing control compensation value and high-voltage side voltage sharing control compensation value to obtain the second modulation signal of each phase.

[0145] In some embodiments, the drive determination module 30 may include:

[0146] A first drive determination submodule, used to determine the drive signal of the first switch tube in the upper unit switch tube drive signal of each phase according to the comparison between the first phase-shifted signal of each phase and the first modulation signal;

[0147] The first drive determination submodule is used to determine the drive signal of the fourth switch tube in the lower unit switch tube drive signal of each phase according to the comparison between the second phase-shifted signal of each phase and the second modulation signal; wherein the three-level bridge arm of each phase includes an upper unit switch tube and a lower unit switch tube connected in series; the upper unit switch tube of each phase includes a first switch tube and a second switch tube connected in series, and the lower unit switch tube of each phase includes a third switch tube and a fourth switch tube connected in series; the drive signal of the second switch tube of each phase is inverted with the drive signal of the first switch tube, and the drive signal of the third switch tube of each phase is inverted with the drive signal of the fourth switch tube.

[0148] In some embodiments, n is 3.

[0149] In this embodiment, the embodiment of the present invention determines the high-voltage side voltage equalization control compensation value and the current equalization control compensation value of each phase according to the control sampling parameters of the n-phase three-level staggered parallel DC converter through the compensation determination module 10, and can conveniently suppress the uneven voltage of the high-voltage side capacitor of the converter and suppress the circulating current of the converter through compensation, thereby improving the output current balance of each phase, thereby improving the control accuracy and stability of the system; and through the drive determination module 30, according to the two phase-shifted signals of each phase and the two modulation signals of each phase corresponding to the input carrier signal, the upper unit switch tube drive signal and the lower unit switch tube drive signal of each phase in the n-phase three-level staggered parallel DC converter are determined, and the carrier phase-shift modulation technology is adopted to realize independent PWM control of each phase, thereby improving applicability, thereby realizing applications with higher power levels.

[0150] Corresponding to the above method embodiments, an embodiment of the present invention further provides a control device for a three-level interleaved parallel DC converter. The control device for a three-level interleaved parallel DC converter described below and the control method for a three-level interleaved parallel DC converter described above can be referred to each other.

[0151] Please refer to Fig.15 , Fig.15 A schematic diagram of the structure of a control device for a three-level staggered parallel DC converter provided by an embodiment of the present invention. The control device may include:

[0152] A memory D1, for storing computer programs;

[0153] The processor D2 is used to implement the steps of the control method of the three-level staggered parallel DC converter provided by the above method embodiment when executing the computer program.

[0154] The control device of the three-level interleaved parallel DC converter in this embodiment may specifically be an MCU (single chip microcomputer) or a CPU (central processing unit).

[0155] The steps in the control method of the three-level interleaved parallel DC converter described above can be implemented by the structure of a control device of the three-level interleaved parallel DC converter.

[0156] Corresponding to the above method embodiment, the embodiment of the present invention further provides a computer program product. The computer program product described below and the control method of the three-level staggered parallel DC converter described above can refer to each other.

[0157] A computer program product includes a computer program / instruction, which, when executed by a processor, implements the steps of the control method for a three-level staggered parallel DC converter provided in the above method embodiment.

[0158] Corresponding to the above method embodiment, the embodiment of the present invention further provides a computer storage medium. The computer storage medium described below and the control method of a three-level staggered parallel DC converter described above can refer to each other.

[0159] A computer storage medium stores a computer program, which, when executed by a processor, implements the steps of the control method of the three-level staggered parallel DC converter of the above method embodiment.

[0160] The computer storage medium may specifically be a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, or other storage medium that can store program codes.

[0161] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the devices, equipment, computer program products and computer storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0162] The above is a detailed introduction to the control method, device and equipment of a three-level staggered parallel DC converter provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A control method for a three-level staggered parallel DC converter, characterized in that: include: According to the control sampling parameters of the n-phase three-level staggered parallel DC converter, the high-voltage side voltage sharing control compensation value and the current sharing control compensation value of each phase are determined; wherein n is a positive integer greater than or equal to 2, and the control sampling parameters include the upper unit capacitor voltage and the lower unit capacitor voltage on the high-voltage side of the n-phase three-level staggered parallel DC converter and the upper unit current and / or lower unit current of each phase on the low-voltage side; Determine two modulation signals corresponding to each phase according to the high-voltage side voltage sharing control compensation value and the current sharing control compensation value; According to the two phase-shifted signals of each phase and the two modulation signals of each phase corresponding to the input carrier signal, the upper unit switch tube drive signal and the lower unit switch tube drive signal of each phase in the n-phase three-level interleaved parallel DC converter are determined; wherein the first phase-shifted signal and the second phase-shifted signal of each phase differ by 180 degrees, and the first phase-shifted signals of two adjacent phases differ by a preset angle clockwise or counterclockwise, and the preset angle is the quotient of 360 degrees and n; The upper unit switch tube driving signal and the lower unit switch tube driving signal are used to control the switch tubes in the upper unit and the lower unit of the n three-level bridge arms in the n-phase three-level staggered parallel DC converter to complete the DC-to-DC conversion.

2. The control method of the three-level interleaved parallel DC converter according to claim 1, characterized in that: The method of determining the high-voltage side voltage sharing control compensation value and the current sharing control compensation value of each phase according to the control sampling parameters of the n-phase three-level staggered parallel DC converter includes: According to the control sampling parameters, the high-voltage side voltage sharing control compensation value, the current sharing control compensation value and the low-voltage side voltage stabilization control compensation value are determined; wherein the control sampling parameters also include the capacitor voltage on the low-voltage side of the n-phase three-level interleaved parallel DC converter; Correspondingly, the two modulation signals corresponding to each phase are determined according to the high-voltage side voltage sharing control compensation value and the current sharing control compensation value, including: According to the high-voltage side voltage sharing control compensation value, the current sharing control compensation value and the low-voltage side voltage stabilization control compensation value, two modulation signals corresponding to each phase are determined.

3. The control method of the three-level interleaved parallel DC converter according to claim 2, characterized in that: The step of determining the high-side voltage sharing control compensation value, the current sharing control compensation value and the low-side voltage stabilization control compensation value according to the control sampling parameters includes: Determining the high-side voltage sharing control compensation value according to the upper unit capacitor voltage and the lower unit capacitor voltage; Determine the current sharing control compensation value of each phase according to the upper unit current or the lower unit current of each phase; According to the capacitor voltage and the target sampling current on the low-voltage side, a low-voltage side voltage stabilization control compensation value of each phase is determined; wherein the target sampling current includes an upper unit current or a lower unit current of each phase.

4. The control method of the three-level interleaved parallel DC converter according to claim 3, characterized in that: The step of determining the high-side voltage sharing control compensation value according to the upper unit capacitor voltage and the lower unit capacitor voltage includes: Calculating an average voltage of the upper unit capacitor voltage and the lower unit capacitor voltage; Calculating a difference between the average voltage and the upper unit capacitor voltage to obtain a first error; A proportional-integral calculation is performed on the first error to obtain the high-pressure side equalizing pressure control compensation value.

5. The control method of the three-level interleaved parallel DC converter according to claim 3, characterized in that: The determining the current sharing control compensation value according to the upper unit current or the lower unit current of each phase includes: Calculate the average lower unit current of the lower unit currents of the n phases; Calculating the difference between the average lower unit current and the lower unit current of each phase, to obtain a second error of each phase; Proportional integral calculation is performed on the second error of each phase respectively to obtain a current sharing control compensation value of each phase.

6. The control method of the three-level interleaved parallel DC converter according to claim 3, characterized in that: The target sampling current includes the upper unit current of each phase; and determining the low-voltage side voltage stabilization control compensation value of each phase according to the capacitor voltage on the low-voltage side and the target sampling current includes: Calculating a difference between a target output voltage on the low voltage side and a capacitor voltage on the low voltage side to obtain a third error; Performing proportional integral calculation on the third error to obtain a total current reference value for voltage stabilization control; Calculating the quotient of the total current reference value and n to obtain an average current reference value for voltage stabilization control; Calculating the sum of the voltage stabilization control average current reference value and the feedforward current to obtain a current control amount; Calculating the difference between the current control amount and the upper unit current of each phase, to obtain a fourth error of each phase; Proportional integral calculation is performed on the fourth error of each phase respectively to obtain a low-voltage side voltage stabilization control compensation value of each phase.

7. The control method of the three-level interleaved parallel DC converter according to claim 3, characterized in that: Determining two modulation signals corresponding to each phase according to the high-voltage side voltage sharing control compensation value, the current sharing control compensation value and the low-voltage side voltage stabilization control compensation value includes: Calculate the difference between the low-voltage side voltage stabilization control compensation value and the high-voltage side voltage balancing control compensation value of each phase to obtain a first modulation signal of each phase; The sum of the low-voltage side voltage stabilization control compensation value, the current sharing control compensation value and the high-voltage side voltage sharing control compensation value of each phase is calculated respectively to obtain a second modulation signal of each phase.

8. The control method of the three-level interleaved parallel DC converter according to claim 7, characterized in that: The method of determining the upper unit switch tube driving signal and the lower unit switch tube driving signal of each phase in the n-phase three-level interleaved parallel DC converter according to the two phase-shifted signals of each phase and the two modulation signals of each phase corresponding to the input carrier signal comprises: Determine the driving signal of the first switch tube in the upper unit switch tube driving signal of each phase according to the comparison between the first phase-shifted signal of each phase and the first modulation signal; According to the comparison between the second phase-shifted signal and the second modulation signal of each phase, the driving signal of the fourth switch tube in the lower unit switch tube driving signal of each phase is determined; wherein the three-level bridge arm of each phase includes an upper unit switch tube and a lower unit switch tube connected in series; the upper unit switch tube of each phase includes a first switch tube and a second switch tube connected in series, and the lower unit switch tube of each phase includes a third switch tube and a fourth switch tube connected in series; the driving signal of the second switch tube of each phase is in antiphase with the driving signal of the first switch tube, and the driving signal of the third switch tube of each phase is in antiphase with the driving signal of the fourth switch tube.

9. The control method of a three-level interleaved parallel DC converter according to claim 1, characterized in that: n is 3.

10. A control device for a three-level staggered parallel DC converter, characterized in that: include: A compensation determination module, used to determine a high-voltage side voltage sharing control compensation value and a current sharing control compensation value of each phase according to control sampling parameters of an n-phase three-level interleaved parallel DC converter; wherein n is a positive integer greater than or equal to 2, and the control sampling parameters include an upper unit capacitor voltage and a lower unit capacitor voltage on the high-voltage side of the n-phase three-level interleaved parallel DC converter and an upper unit current and / or a lower unit current of each phase on the low-voltage side; A modulation determination module, used to determine two modulation signals corresponding to each phase according to the high-voltage side voltage sharing control compensation value and the current sharing control compensation value; A drive determination module, used to determine the upper unit switch tube drive signal and the lower unit switch tube drive signal of each phase in the n-phase three-level interleaved parallel DC converter according to the two phase-shifted signals of each phase and the two modulation signals of each phase corresponding to the input carrier signal; wherein the first phase-shifted signal and the second phase-shifted signal of each phase differ by 180 degrees, and the first phase-shifted signals of two adjacent phases differ by a preset clockwise or counterclockwise angle, and the preset angle is the quotient of 360 degrees and n; The drive control module is used to control the switch tubes in the upper unit and the lower unit of the n three-level bridge arms in the n-phase three-level staggered parallel DC converter by using the upper unit switch tube drive signal and the lower unit switch tube drive signal to complete the DC-to-DC conversion.

11. A control device for a three-level staggered parallel DC converter, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the control method for a three-level interleaved parallel DC converter as claimed in any one of claims 1 to 9 when executing the computer program.

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