A hybrid control DC conversion circuit

Abstract

The present invention discloses a hybrid control DC conversion circuit, including a main power topology circuit, a switch control timing, a voltage feedforward hybrid control and a startup pre-bias strategy; the main power topology circuit includes an input voltage source, an input capacitor, a switch tube, a flying capacitor, an inductor, an output capacitor and an output load, etc.; the voltage feedforward hybrid control circuit is a hybrid control circuit with input voltage adaptive capability and peak current limiting capability; the startup pre-bias strategy mainly includes an input voltage series voltage-dividing sampling resistor network, whose resistance values ​​should be the same to ensure that the voltage-dividing ratio is linear; a current source with enable control, a hysteresis comparator and an AND gate device, etc. The present invention not only improves the step-down capability of the hybrid converter but also solves the inherent startup surge problem, and has a high application value in extremely high step-down ratio, low voltage and high current occasions.

Description

Technical Field

[0001] The present invention belongs to the technical field of direct current converters of electric energy conversion devices, and in particular relates to a hybrid controlled direct current conversion circuit. Background Art

[0002] Nowadays, with the widespread application of technologies such as artificial intelligence, big data and cloud computing, the computing power they need to provide is growing. Since a large number of CPU or GPU processors are usually used in these computing systems to provide computing power, the power transmitted by their power supply systems increases accordingly, resulting in a large amount of power transmission losses. In most power supply systems, since the power supply bus is 48V, and the power supply voltage of processors such as CPUs and GPUs is 1V or even lower, their power processing chain usually adopts a two-stage converter architecture. The first stage is a 48V to 12V converter for providing a 12V bus, and the second stage is a 12V to 1.xV load point converter. However, the two-stage conversion architecture at this extremely high conversion ratio is usually low in efficiency and power density, because each converter in the two-stage power conversion system needs to process and transmit all the power, so there is an urgent need for a single-stage high-efficiency, high-power-density, high-step-down ratio switching conversion circuit.

[0003] Switched capacitor circuits have been widely studied in recent years due to their extremely high conversion efficiency and power density. However, their open-loop gain characteristics and large startup surge current have limited the application of this circuit. In response to this, many studies have integrated switched capacitor circuits with traditional inductive switching conversion circuits to form single-stage high-step-down circuits such as series capacitor hybrid converters and ladder-type switched capacitor hybrid converters. However, this type of hybrid conversion circuit provides limited step-down capability and does not solve the inherent startup surge problem of the switched capacitor circuit, so it is still not applicable to 48V-1V, an extremely high step-down ratio, low voltage, and high current occasion. Therefore, improving the step-down ratio and solving the startup surge problem are necessary measures to improve the application value of this type of hybrid circuit. Summary of the invention

[0004] In order to solve the above problems, the present invention comprehensively considers the respective advantages of the switched capacitor converter and the inductor converter, complements each other's advantages and disadvantages, and proposes a hybrid control DC conversion circuit.

[0005] A hybrid control DC conversion circuit of the present invention includes a main power topology circuit. The main power topology circuit includes an input voltage source U in , input capacitor C in , switch tube S 1- S6, flying capacitor C 1- C3, inductor L 1- L2, output capacitor C o and output load R L .

[0006] Among them, the input capacitor C in Connect in parallel to the input voltage source U in The drain of the switch tube S1 is connected to one end of the input capacitor, the source of the switch tube S1 is connected to the drain of the switch tube S2 and one end of the flying capacitor C1; the source of the switch tube S2 is connected to the drain of the switch tube S3 and one end of the flying capacitor C2, the source of the switch tube S3 is connected to the drain of the switch tube S4 and one end of the flying capacitor C3; the source of the switch tube S4, the drain of the switch tube S5, the other end of the flying capacitor C2 and one end of the inductor L1 are connected together, the other end of the flying capacitor C1, the other end of the flying capacitor C3, the drain of the switch tube S6 and one end of the inductor L2 are connected together; the other end of the inductor L1, the other end of the inductor L2, the output capacitor C o One end and output load R L One end of the capacitor is connected together to form the positive electrode of the output voltage; the input capacitor C in The other end of the switch tube S5, the source of the switch tube S6, the output capacitor C o The cathode and output load R L The other end is connected to form the reference potential point of the main power topology circuit.

[0007] The switch control timing of the present invention is the on and off state of each switch tube in the circuit in different circuit working modes. The present invention can only achieve a stable high step-down ratio and low voltage stress characteristics of the switch tube by following a specific switch tube action timing. The switch timing is divided into two groups of PWM (Pulse Width Modulation, PWM) drive signals, namely VH1&VL1 and VH2&VL2; VH1 and VL1 are a group of complementary PWM square wave signals, wherein the duty cycle of VH1 is D and the duty cycle of VL1 is 1-D; VH2 and VL2 are another group of complementary PWM square wave signals, wherein the duty cycle of VH2 is D and the phase difference with the VH1 signal is 180°, and the duty cycle of VL2 is 1-D and the phase difference with the VL1 signal is 180°. The switch tubes S2 and S4 perform switching operations according to the VH1 signal, the switch tube S5 performs switching operations according to the VL1 signal, the switch tubes S1 and S3 perform switching operations according to the VH2 signal, and the switch tube S6 performs switching operations according to the VL2 signal.

[0008] A hybrid control DC conversion circuit of the present invention also includes a voltage feedforward hybrid control circuit. The voltage feedforward hybrid control circuit of the present invention is a hybrid control circuit with input voltage adaptive capability and peak current limiting capability, and includes R fb1 and R fb2The voltage sampling structure is composed of the operational amplifier EA and the three-type compensation network composed of R1, C1, R2, C2 and R3, which outputs the error signal v e ; R f1 , R f2 , Q SAW1 , Q SAW2 , C f1 and C f2 The two input voltage feedforward structures are composed of the switch tube Q SAW1 and Q SAW2 The driving signals of the two feedforward structures are respectively synchronized with the driving signals of the switch tubes S6 and S5, and the two feedforward structures respectively output sawtooth wave control signals v saw1 and v saw2 ; The inverting input of comparator COMP1 is connected to v e signal, its non-inverting input terminal is connected to v saw1 signal; the inverting input of comparator COMP3 is connected to v e signal, its non-inverting input terminal is connected to v saw2 signal; the inverting input of the peak current limiting comparator COMP2 is connected to the set peak current threshold signal v current_limit Its non-inverting input terminal is connected to the current sampling signal ki of the inductor L1. L1 The inverting input of the peak current limiting comparator COMP4 is connected to the set peak current threshold signal v current_limit Its non-inverting input terminal is connected to the current sampling signal ki of the inductor L2. L2 ; After the output signals of comparator COMP1 and comparator COMP2 pass through the "OR" logic OR1, the logic operation result is sent to the R input terminal of RS flip-flop RS Flip-flop1, and the switch clock signal Clock is sent to the S input terminal of RS Flip-flop1; the inverting output terminal nQ of RS Flip-flop1 passes through a dead zone generation module to generate the PWM drive signal V of the switch tube S6 GS6 , which is the logic signal VL2; the output terminal Q of RS Flip-flop1 generates the PWM drive signal V of the switch tubes S1 and S3 after passing through a dead zone generation module. GS1，3 , which is the logic signal VH2; similarly, the output signals of comparator COMP3 and comparator COMP4 are sent to the R input terminal of RS flip-flop RS Flip-flop2 after the "OR" logic OR2, and a clock signal Clock2 with a phase shift of 180° relative to the Clock signal is sent to the S input terminal of RS Flip-flop2; the inverting output terminal nQ of RS Flip-flop2 is generated through a dead zone generation module to generate the PWM drive signal V of the switch tube S5. GS5, which is the logic signal VL1; the output terminal Q of RS Flip-flop2 generates the PWM drive signal V of the switch tubes S2 and S4 after passing through a dead zone generation module. GS2，4 , that is, the logic signal VH1.

[0009] The present invention also includes a startup pre-bias strategy circuit; the startup pre-bias strategy of the present invention is a startup strategy for solving the problem of excessive switch tube voltage and surge current when the switch capacitor starts the circuit because the initial value of the capacitor voltage is zero, and the startup pre-bias strategy mainly includes an input voltage series voltage-dividing sampling resistor network R4, R5, R6 and R7, whose resistance values ​​should be the same to ensure that the voltage-dividing ratio is in a linear relationship; current sources CS1, CS2 and CS3 with enable control; hysteresis comparators COMP5, COMP6 and COMP7; and "AND" gate devices AND1, AND2 and AND3.

[0010] Among them, resistors R4, R5, R6 and R7 are connected in series in sequence, one end of R4 is connected to the positive pole of the input power supply, and one end of R7 is connected to the reference potential point; the voltage at the node connecting R4 and R5 is the reference pre-bias control voltage v of the series capacitor C1 1_reg The voltage at the node connecting R5 and R6 is the reference pre-bias control voltage v of the series capacitor C2. 2_reg The voltage at the node connecting R6 and R7 is the reference pre-bias control voltage v of the series capacitor C3. 3_reg ; The inflow end of the current source CS1 is connected to the positive electrode of the input power supply, and the outflow end is connected to the connection node of the switch tube S1, the switch tube S2 and C1, and the potential of the node is v1; the inflow end of the current source CS2 is connected to the positive electrode of the input power supply, and the outflow end is connected to the connection node of the switch tube S2, the switch tube S3 and C2, and the potential of the node is v2; the inflow end of the current source CS3 is connected to the positive electrode of the input power supply, and the outflow end is connected to the connection node of the switch tube S3, the switch tube S4 and C3, and the potential of the node is v3; it is necessary to ensure that the drive signals of the switch tubes S5 and S6 always maintain a high level during the pre-bias startup phase, so as to control the pre-bias voltage of each series capacitor; the voltage sampling signal v1 of the series capacitor C1 is sent to the input end of the hysteresis comparator COMP5 after passing through the proportional link K1, and the reference pre-bias control voltage v 1_reg Add or subtract a hysteresis v _hyst The voltage sampling signal v2 of the series capacitor C2 is sent to the input terminal of the hysteresis comparator COMP6 after passing through the proportional link K2, and the reference pre-bias control voltage v 2_reg Add or subtract a hysteresis v _hystThe voltage sampling signal v3 of the series capacitor C3 is sent to the input terminal of the hysteresis comparator COMP7 after passing through the proportional link K3, and the reference pre-bias control voltage v 3_reg Add or subtract a hysteresis v _hyst Then they are sent to the positive input terminal and the negative input terminal of COMP7 respectively, and then the negative output of COMP7 and the pre-bias flag signal Flag_prebias are sent to the "AND" logic to generate the enable signal EN3 of the current source CS3.

[0011] The two control strategies in the present invention are respectively used in the two working states of the circuit. After the circuit is initially powered on, the pre-bias flag signal Flag_prebias is set high to enter the pre-bias mode. After the bias voltage of each series capacitor is established, Flag_prebias is set low to exit the pre-bias mode, and then the voltage feedforward hybrid control is switched on to allow the circuit to enter a stable working state.

[0012] The present invention has the following beneficial technical effects:

[0013] 1. The main power circuit of the present invention integrates the switch capacitor and the inductor converter, which can further improve the voltage reduction capability of the circuit. In addition, the advantage of low voltage stress of the circuit can also provide a wider optimization space for conversion efficiency.

[0014] 2. The startup pre-bias strategy in the present invention can solve the inherent surge problem of the switched capacitor circuit at startup, thereby improving the application value of such hybrid converters.

[0015] 3. The voltage feedforward hybrid control circuit in the present invention has input voltage adaptive capability and peak current limiting capability. The input voltage adaptive capability can improve the voltage regulation rate and dynamic response of input jump of traditional voltage type control, and the peak current limiting capability can make the voltage type control have a certain overcurrent and overload protection mechanism to ensure the safety of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a main power topology circuit structure diagram of a hybrid control DC conversion circuit of the present invention.

[0017] Figure 2 It is the key waveform diagram of the switching timing and each mode of the present invention.

[0018] Figure 3 This is a voltage feedforward hybrid control circuit diagram of the present invention.

[0019] Figure 4 This is a startup pre-bias strategy diagram provided by the present invention.

[0020] Figure 5 FIG. 1 is an equivalent circuit diagram of an embodiment of the present invention in mode 1.

[0021] Figure 6 FIG. 2 is an equivalent circuit diagram of an embodiment of the present invention in mode 2.

[0022] Figure 7 FIG. 3 is an equivalent circuit diagram of an embodiment of the present invention in mode 3.

[0023] Figure 8 FIG. 4 is an equivalent circuit diagram of an embodiment of the present invention in mode 4. DETAILED DESCRIPTION

[0024] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0025] A hybrid control DC conversion circuit of the present invention includes a main power topology circuit. The main power topology circuit is as follows Figure 1 As shown, including the input voltage source U in , input capacitor C in , switch tube S 1- S6, flying capacitor C 1- C3, inductor L 1- L2, output capacitor C o and output load R L .

[0026] Among them, the input capacitor C in Connect in parallel to the input voltage source U in The drain of the switch tube S1 is connected to one end of the input capacitor, the source of the switch tube S1 is connected to the drain of the switch tube S2 and one end of the flying capacitor C1; the source of the switch tube S2 is connected to the drain of the switch tube S3 and one end of the flying capacitor C2, the source of the switch tube S3 is connected to the drain of the switch tube S4 and one end of the flying capacitor C3; the source of the switch tube S4, the drain of the switch tube S5, the other end of the flying capacitor C2 and one end of the inductor L1 are connected together, the other end of the flying capacitor C1, the other end of the flying capacitor C3, the drain of the switch tube S6 and one end of the inductor L2 are connected together; the other end of the inductor L1, the other end of the inductor L2, the output capacitor C o One end and output load R L One end of the capacitor is connected together to form the positive electrode of the output voltage; the input capacitor C in The other end of the switch tube S5, the source of the switch tube S6, the output capacitor C o The cathode and output load R L The other end is connected to form the reference potential point of the main power topology circuit.

[0027] The switch control timing of the present invention and the special waveform under steady-state operation are as follows: Figure 2 As shown, the switch control timing is VH1&VL1 and VH2&VL2 respectively; VH1 and VL1 are a set of complementary PWM square wave signals, where the duty cycle of VH1 is D and the duty cycle of VL1 is 1-D; VH2 and VL2 are another set of complementary PWM square wave signals, where the duty cycle of VH2 is D and the phase difference with the VH1 signal is 180°, and the duty cycle of VL2 is 1-D and the phase difference with the VL1 signal is 180°. Switches S2 and S4 follow the VH1 signal to perform switching actions, switch S5 follows the VL1 signal to perform switching actions, switch S1 and S3 follow the VH2 signal to perform switching actions, and switch S6 follows the VL2 signal to perform switching actions.

[0028] The present invention also includes a voltage feedforward hybrid control circuit. The voltage feedforward hybrid control circuit of the present invention is as follows Figure 3 As shown, it includes R fb1 and R fb2 The voltage sampling structure is composed of the operational amplifier EA and the three-type compensation network composed of R1, C1, R2, C2 and R3, which outputs the error signal v e ; R f1 , R f2 , Q SAW1 , Q SAW2 , C f1 and C f2 The two input voltage feedforward structures are composed of the switch tube Q SAW1 and Q SAW2 The driving signals of the two feedforward structures are respectively synchronized with the driving signals of the switch tubes S6 and S5, and the two feedforward structures respectively output sawtooth wave control signals v saw1 and v saw2 ; The inverting input of comparator COMP1 is connected to v e signal, its non-inverting input terminal is connected to v saw1 signal; the inverting input of comparator COMP3 is connected to v e signal, its non-inverting input terminal is connected to v saw2 signal; the inverting input of the peak current limiting comparator COMP2 is connected to the set peak current threshold signal v current_limit Its non-inverting input terminal is connected to the current sampling signal ki of the inductor L1. L1 The inverting input of the peak current limiting comparator COMP4 is connected to the set peak current threshold signal v current_limit Its non-inverting input terminal is connected to the current sampling signal ki of the inductor L2. L2; After the output signals of comparator COMP1 and comparator COMP2 pass through the "OR" logic OR1, the logic operation result is sent to the R input terminal of RS flip-flop RS Flip-flop1, and the switch clock signal Clock is sent to the S input terminal of RS Flip-flop1; the inverting output terminal nQ of RS Flip-flop1 passes through a dead zone generation module to generate the PWM drive signal V of the switch tube S6 GS6 , which is the logic signal VL2; the output terminal Q of RS Flip-flop1 generates the PWM drive signal V of the switch tubes S1 and S3 after passing through a dead zone generation module. GS1，3 , which is the logic signal VH2; similarly, the output signals of comparator COMP3 and comparator COMP4 are sent to the R input terminal of RS flip-flop RS Flip-flop2 after the "OR" logic OR2, and a clock signal Clock2 with a phase shift of 180° relative to the Clock signal is sent to the S input terminal of RS Flip-flop2; the inverting output terminal nQ of RS Flip-flop2 is generated through a dead zone generation module to generate the PWM drive signal V of the switch tube S5. GS5 , which is the logic signal VL1; the output terminal Q of RS Flip-flop2 generates the PWM drive signal V of the switch tubes S2 and S4 after passing through a dead zone generation module. GS2，4 , that is, the logic signal VH1.

[0029] The startup pre-bias strategy of the present invention is as follows Figure 4 As shown, it includes an input voltage series voltage-dividing sampling resistor network R4, R5, R6 and R7, whose resistance values ​​should be the same to ensure that the voltage-dividing ratio is linear; current sources CS1, CS2 and CS3 with enable control; hysteresis comparators COMP5, COMP6 and COMP7; and AND gate devices AND1, AND2 and AND3.

[0030] Among them, resistors R4, R5, R6 and R7 are connected in series in sequence, one end of R4 is connected to the positive pole of the input power supply, and one end of R7 is connected to the reference potential point; the voltage at the node connecting R4 and R5 is the reference pre-bias control voltage v of the series capacitor C1 1_reg The voltage at the node connecting R5 and R6 is the reference pre-bias control voltage v of the series capacitor C2. 2_reg The voltage at the node connecting R6 and R7 is the reference pre-bias control voltage v of the series capacitor C3. 3_reg; The inflow end of the current source CS1 is connected to the positive electrode of the input power supply, and the outflow end is connected to the connection node of the switch tube S1, the switch tube S2 and C1, and the potential of the node is v1; the inflow end of the current source CS2 is connected to the positive electrode of the input power supply, and the outflow end is connected to the connection node of the switch tube S2, the switch tube S3 and C2, and the potential of the node is v2; the inflow end of the current source CS3 is connected to the positive electrode of the input power supply, and the outflow end is connected to the connection node of the switch tube S3, the switch tube S4 and C3, and the potential of the node is v3; it is necessary to ensure that the drive signals of the switch tubes S5 and S6 always maintain a high level during the pre-bias startup phase, so as to control the pre-bias voltage of each series capacitor; the voltage sampling signal v1 of the series capacitor C1 is sent to the input end of the hysteresis comparator COMP5 after passing through the proportional link K1, and the reference pre-bias control voltage v 1_reg Add or subtract a hysteresis v _hyst The voltage sampling signal v2 of the series capacitor C2 is sent to the input terminal of the hysteresis comparator COMP6 after passing through the proportional link K2, and the reference pre-bias control voltage v 2_reg Add or subtract a hysteresis v _hyst The voltage sampling signal v3 of the series capacitor C3 is sent to the input terminal of the hysteresis comparator COMP7 after passing through the proportional link K3, and the reference pre-bias control voltage v 3_reg Add or subtract a hysteresis v _hyst Then they are sent to the positive input terminal and the negative input terminal of COMP7 respectively, and then the negative output of COMP7 and the pre-bias flag signal Flag_prebias are sent to the "AND" logic to generate the enable signal EN3 of the current source CS3.

[0031] Working principle of the present invention:

[0032] In order to analyze the working principle of the circuit provided by the present invention, based on Figure 1 The circuit of an embodiment shown in the figure first makes the following assumptions: 1) All switch tubes have the same parasitic diode D and parasitic capacitor C oss 2) All physical quantities are expressed in Figure 2 The reference direction shown is the positive direction.

[0033] Considering steady-state operation, there are four modes in a switching cycle. The waveform and equivalent circuit corresponding to each mode are as follows: Figure 2 and Figures 5 to 8 shown.

[0034] Mode 1 [t0-t1]: At time t0, the VH1 and VL2 signals are set high, and the switches S2, S4 and S6 are turned on. Figure 5 As shown. The flying capacitor C1 is connected in series with C2 and then in parallel with C3 to provide energy for the inductor and output. During this period, capacitors C1 and C3 are in a discharging state, capacitor C2 is in a charging state, and inductor L1 is in the excitation stage. Its current i L1 It starts to rise linearly, L2 is in the freewheeling stage at this time, i L2 It shows a linear downward trend. The working process of this mode can be summarized as follows:

[0035]

[0036] Where V C1 (t), V C2 (t), V C3 (t) and V o (t) represent the flying capacitors C1, C2, C3 and the output capacitor C o The capacitor voltage on the capacitor, L1 and L2 represent the inductance of inductor L1 and inductor L2 respectively, i L1 (t) and i L2 (t) represent the inductor current on inductor L1 and inductor L2 respectively.

[0037] Mode 2 [t1-t2]: At t1, the VL1 and VL2 signals are set high, and the switches S5 and S6 are turned on. Figure 6 As shown. In this mode, the synchronous freewheeling tubes are all turned on, and the inductors L1 and L2 are in the freewheeling stage, and the inductor current shows a linear downward trend. The working process of this mode can be summarized as:

[0038]

[0039] Where V o Represents the steady-state average value of the output voltage.

[0040] Mode 3 [t2-t3]: At t2, the VH2 and VL1 signals are at high level, and the switches S1, S3 and S5 are turned on. Figure 7 In this mode, the input power supply provides energy to capacitor C1 and inductor L2 through switch tube S1. Capacitors C2 and C3 are connected in series and also provide energy to inductor L2. During this period, capacitors C1 and C3 are in a charging state, capacitor C2 is in a discharging state, and L2 is in the excitation stage. The excitation current i L2 It shows a linear upward trend. L1 is in the continuous flow stage at this time. L1 It shows a linear downward trend. The working process of this mode can be summarized as follows:

[0041]

[0042] Where V in (t) represents the input voltage.

[0043] Mode 4 [t3-t4]: At t3, the VL1 and VL2 signals are set high, and the switches S5 and S6 are turned on. Figure 6 As shown. In this mode, the synchronous freewheeling tubes are all turned on, and the inductors L1 and L2 are in the freewheeling stage, and the inductor current shows a linear downward trend. The working process of this mode can be summarized as:

[0044]

[0045] Voltage gain and capacitor voltage stress analysis:

[0046] In steady-state operation, the flying capacitors C1, C2 and C3 are considered to be in a charge balance state, that is, the flying capacitor voltage is the average voltage plus the ripple voltage. The series-parallel relationship of the flying capacitors in mode 1 and mode 3 can be obtained respectively:

[0047]

[0048] Where V C1 、V C2 and V C3 Represents the steady-state average value of the capacitor voltage on the flying capacitors C1, C2, and C3, V in Represents the steady-state average value of the input voltage.

[0049] Simplifying formula (5) we can get:

[0050]

[0051] Let the duty cycle of VH1 and VL1 be D and the period be T S , according to the volt-second balance equation of inductors L1 and L2, it can be listed as:

[0052]

[0053] Solving (7) yields:

[0054] V in =V C1 +V C3 (8)

[0055] Combining equations (6) and (8) further derives:

[0056]

[0057] Finally, substituting equation (9) back into the volt-second balance equation (7), we can obtain the input-output voltage relationship of the converter as

[0058]

[0059] From formula (9), it can be seen that the voltage stress of the flying capacitor decreases successively. From formula (10), it can be seen that the voltage gain is D / 4. Compared with the voltage gain of D / 2 of the series capacitor hybrid converter, the main power circuit in the present invention has a higher voltage reduction capability at the same duty cycle.

[0060] Switching device stress analysis:

[0061] In the initial startup phase of the circuit, if the startup pre-bias strategy of the present invention is not used, the initial voltage of the flying capacitors C1, C2 and C3 is zero. When the circuit is started, the flying capacitors will be charged by the input voltage. The capacitor charging process is similar to a short-circuit state, which will bring a large surge current, and the switch tube S 1-6 The startup transient voltage stress is V in After adopting the startup pre-bias strategy of the present invention, the flying capacitor will be pre-charged to a specific voltage by the current source before starting. This strategy can reduce the voltage stress of the switch tube when the circuit starts and suppress the surge current caused by the charging of the flying capacitor.

[0062] In the steady-state operation stage of the circuit, the switches S1, S3 and S5 in mode 1 are subjected to the turn-off reverse voltage. The voltage stress of the switch S1 in this mode is the difference between the input voltage and the voltage of the capacitor C1, that is, V in / 4; the voltage stress of the switch tube S3 in this mode is the voltage value on the capacitor C2, which is 2V in / 4; the voltage stress of the switch tube S5 in this mode is the voltage value on the capacitor C3, that is, V in / 4. In mode 2, the switches S1, S2, S3 and S4 are subjected to the turn-off reverse voltage. The voltage stress of the switch S1 in this mode is still the difference between the input voltage and the voltage of the capacitor C1, that is, V in / 4; the voltage stress of the switch tube S2 in this mode is the difference between the voltage of capacitor C1 and the voltage of capacitor C2, that is, V in / 4; the voltage stress of the switch tube S3 in this mode is the difference between the voltage of capacitor C2 and the voltage of capacitor C3, that is, V in / 4; the voltage stress of the switch tube S3 in this mode is the voltage value of the capacitor C1, that is, V in / 4. In mode 3, the switches S2, S4 and S6 are subjected to the turn-off reverse voltage. The voltage stress of the switch S2 in this mode is the difference between the voltage of the capacitor C1 and the voltage of the capacitor C3, which is 2V. in / 4; the voltage stress of the switch tube S4 in this mode is the voltage value of the capacitor C2, which is 2V in / 4; the voltage stress of the switch tube S6 in this mode is the difference between the input voltage and the voltage of the capacitor C1, that is, V in / 4; because mode 4 and mode 2 work in the same way, the voltage stress is the same as mode 2.

[0063] In summary, the maximum voltage stress of each switch tube after adopting the startup pre-bias strategy is:

[0064]

[0065] Where V DS1 、V DS2 、V DS3 、V DS4 、V DS5 and V DS6 They represent the drain-source voltage differences on the switch tubes S1, S2, S3, S4, S5 and S6 respectively.

[0066] It can be seen from this that the stress of the switch tubes is much lower than the input voltage, so there is a wider choice space when optimizing the selection of the switch tubes.

[0067] Automatic balancing analysis of two-phase inductor current:

[0068] During the steady-state operation of the circuit, the flying capacitor will continuously charge and discharge to keep its voltage stable. In circuit working mode 1, the current flowing through the inductor L1 is the flying capacitor series-parallel charging and discharging current. The flying capacitor C1 discharges and C2 charges, but because C1 and C2 are connected in series, the current between them can be i trans , the amount of charge transferred is Q trans The flying capacitor C3 is discharged, and its discharge current can be i C3 , the discharge charge is Q C3_dischg Therefore, the relationship between the charging and discharging charge of the flying capacitor and the current of the inductor L1 can be specifically expressed as:

[0069]

[0070] Among them I L1 represents the average current flowing through the inductor L1, i C3 (t) is the current flowing through the flying capacitor C3.

[0071] Similarly, in mode 2, the current flowing through the inductor L1 is also the flying capacitor series-parallel charging and discharging current. However, in this mode, the flying capacitor C1 is charged by the input, and its charging current is i C1 , the charge is Q C1_chgC2 and C3 are connected in series, C2 discharges, and C3 charges, so that the current between them is i trans2 , the amount of charge transferred is Q trans2 Therefore, the relationship between the charging and discharging charge of the flying capacitor and the current of the inductor L2 can be specifically expressed as:

[0072]

[0073] Among them I L2 represents the average current flowing through the inductor L2, i C1 (t) is the current flowing through the flying capacitor C1.

[0074] According to the principle of conservation of capacitor charge in steady state, we can get:

[0075]

[0076] Substituting (14) into (12) and (13) we can further deduce:

[0077] I L1 =I L2 (15)

[0078] It can be seen that when the duty cycles of VH1 and VH2 are the same, the average current flowing through inductor L1 is the same as the average current flowing through inductor L2. This is due to the charge balance of the flying capacitor, so it has nothing to do with the control method. The natural automatic balance of inductor current reduces the dependence on external balance algorithms, further improving its application value.

[0079] Although the specific implementation of the present invention is described above in conjunction with the accompanying drawings, this is only a preferred implementation of the present invention. The protection scope of the present invention is not limited to the above embodiments, and all technical solutions under this idea belong to the protection scope of the present invention. It should be pointed out that for those skilled in the art, several improvements and changes without departing from the principle of the present invention, or equivalent changes or replacements of related technical features, such as replacing the switch tubes S5 and S6 with diodes or making simple changes to the startup pre-bias strategy and the voltage feedforward hybrid control circuit, should be within the protection scope of the present invention as long as they do not exceed the protection scope described in the claims of the present invention.

Claims

1. A hybrid control DC conversion circuit, characterized in that: Including main power topology circuit; The main power topology circuit includes an input voltage source U in , input capacitor C in , switch tube S 1- S6, flying capacitor C 1- C3, inductor L 1- L2, output capacitor C o and output load R L ; Among them, the input capacitor C in Connect in parallel to the input voltage source U in The drain of the switch tube S1 is connected to one end of the input capacitor, the source of the switch tube S1 is connected to the drain of the switch tube S2 and one end of the flying capacitor C1; the source of the switch tube S2 is connected to the drain of the switch tube S3 and one end of the flying capacitor C2, the source of the switch tube S3 is connected to the drain of the switch tube S4 and one end of the flying capacitor C3; the source of the switch tube S4, the drain of the switch tube S5, the other end of the flying capacitor C2 and one end of the inductor L1 are connected together, the other end of the flying capacitor C1, the other end of the flying capacitor C3, the drain of the switch tube S6 and one end of the inductor L2 are connected together; the other end of the inductor L1, the other end of the inductor L2, the output capacitor C o One end and output load R L One end of the capacitor is connected together to form the positive electrode of the output voltage; the input capacitor C in The other end of the switch tube S5, the source of the switch tube S6, the output capacitor C o The cathode and output load R L The other end is connected to form a reference potential point of the main power topology circuit; Also included is a voltage feed-forward hybrid control circuit; The voltage feedforward hybrid control circuit includes R fb1 and R fb2 The voltage sampling structure is composed of the operational amplifier EA and the three-type compensation network composed of R1, C1, R2, C2 and R3, which outputs the error signal v e ; R f1 , R f2 , Q SAW1 , Q SAW2 , C f1 and C f2 The two input voltage feedforward structures are composed of the switch tube Q SAW1 and Q SAW2 The driving signals of the two feedforward structures are respectively synchronized with the driving signals of the switch tubes S6 and S5, and the two feedforward structures respectively output sawtooth wave control signals v saw1 and v saw2 ; The inverting input of comparator COMP1 is connected to v e signal, its non-inverting input terminal is connected to v saw1 signal; the inverting input of comparator COMP3 is connected to v e signal, its non-inverting input terminal is connected to v saw2 signal; the inverting input of the peak current limiting comparator COMP2 is connected to the set peak current threshold signal v current_limit Its non-inverting input terminal is connected to the current sampling signal ki of the inductor L1. L1 The inverting input of the peak current limiting comparator COMP4 is connected to the set peak current threshold signal v current_limit Its non-inverting input terminal is connected to the current sampling signal ki of the inductor L2. L2 The output signals of comparator COMP1 and comparator COMP2 are sent to the R input of RS flip-flop RS Flip-flop1 after the "OR" logic OR1, and the switch clock signal Clock is sent to the S input of RS Flip-flop1; the inverting output nQ of RS Flip-flop1 is sent to a dead zone generation module to generate the PWM drive signal V of switch tube S6. GS6 , which is the logic signal VL2; the output terminal Q of RS Flip-flop1 generates the PWM drive signal V of the switch tubes S1 and S3 after passing through a dead zone generation module. GS1，3 , which is the logic signal VH2; similarly, the output signals of comparator COMP3 and comparator COMP4 are sent to the R input terminal of RS flip-flop RS Flip-flop2 after the "OR" logic OR2, and a clock signal Clock2 with a phase shift of 180° relative to the Clock signal is sent to the S input terminal of RS Flip-flop2; the inverting output terminal nQ of RS Flip-flop2 generates the PWM drive signal V of switch tube S5 after passing through a dead zone generation module. GS5 , which is the logic signal VL1; the output terminal Q of RS Flip-flop2 generates the PWM drive signal V of the switch tubes S2 and S4 after passing through a dead zone generation module. GS2，4 , that is, the logic signal VH1.

2. A hybrid control DC conversion circuit according to claim 1, characterized in that: The switch control timing adopted by the DC conversion circuit is divided into two groups of PWM drive signals, namely VH1&VL1 and VH2&VL2; VH1 and VL1 are a group of complementary PWM square wave signals, wherein the duty cycle of VH1 is D and the duty cycle of VL1 is 1-D; VH2 and VL2 are another group of complementary PWM square wave signals, wherein the duty cycle of VH2 is D and the phase difference with the VH1 signal is 180°, and the duty cycle of VL2 is 1-D and the phase difference with the VL1 signal is 180°; the switch tubes S2 and S4 follow the VH1 signal to perform the switch tube action, the switch tube S5 follows the VL1 signal to perform the switch tube action, the switch tubes S1 and S3 follow the VH2 signal to perform the switch tube action, and the switch tube S6 follows the VL2 signal to perform the switch tube action.

3. A hybrid control DC conversion circuit according to claim 1, characterized in that: Also included is a startup pre-bias strategy circuit; The startup pre-bias strategy circuit includes an input voltage series voltage-dividing sampling resistor network R4, R5, R6 and R7, whose resistance values ​​should be the same to ensure that the voltage-dividing ratio is linear; current sources CS1, CS2 and CS3 with enable control; hysteresis comparators COMP5, COMP6 and COMP7; and AND gate devices AND1, AND2 and AND3; Among them, resistors R4, R5, R6 and R7 are connected in series in sequence, one end of R4 is connected to the positive pole of the input power supply, and one end of R7 is connected to the reference potential point; the voltage at the node connecting R4 and R5 is the reference pre-bias control voltage v of the series capacitor C1 1_reg The voltage at the node connecting R5 and R6 is the reference pre-bias control voltage v of the series capacitor C2. 2_reg The voltage at the node connecting R6 and R7 is the reference pre-bias control voltage v of the series capacitor C3. 3_reg ; The inflow end of the current source CS1 is connected to the positive electrode of the input power supply, and the outflow end is connected to the connection node of the switch tube S1, the switch tube S2 and C1, and the potential of the node is v1; the inflow end of the current source CS2 is connected to the positive electrode of the input power supply, and the outflow end is connected to the connection node of the switch tube S2, the switch tube S3 and C2, and the potential of the node is v2; the inflow end of the current source CS3 is connected to the positive electrode of the input power supply, and the outflow end is connected to the connection node of the switch tube S3, the switch tube S4 and C3, and the potential of the node is v3; it is necessary to ensure that the drive signals of the switch tubes S5 and S6 always maintain a high level during the pre-bias startup phase, so as to control the pre-bias voltage of each series capacitor; the voltage sampling signal v1 of the series capacitor C1 is sent to the input end of the hysteresis comparator COMP5 after passing through the proportional link K1, and the reference pre-bias control voltage v 1_reg Add or subtract a hysteresis v _hyst The voltage sampling signal v2 of the series capacitor C2 is sent to the input terminal of the hysteresis comparator COMP6 after passing through the proportional link K2, and the reference pre-bias control voltage v 2_reg Add or subtract a hysteresis v _hyst The voltage sampling signal v3 of the series capacitor C3 is sent to the input terminal of the hysteresis comparator COMP7 after passing through the proportional link K3, and the reference pre-bias control voltage v 3_reg Add or subtract a hysteresis v _hyst Then, they are sent to the positive input terminal and the negative input terminal of COMP7 respectively. Then, the negative output of COMP7 and the pre-bias flag signal Flag_prebias are sent to the "AND" logic to generate the enable signal EN3 of the current source CS3.

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