A folded cascode operational amplifier circuit with low power consumption and large slew rate

Abstract

The present invention belongs to the field of integrated circuits, and provides a folded cascode operational amplifier circuit with low power consumption and large slew rate to solve the problems of low slew rate and high power consumption existing in the prior art. The present invention includes current sources I0 to I4, transistors M1 to M14, a resistor R1, and a load capacitor CL. On the basis of the traditional folded cascode structure, a differential structure of a flip voltage follower (DFVF) composed of transistors M4, M7, and M8, a flip voltage follower current sensor (FVFCS) composed of transistors M3, M4, and M8, and a source follower composed of transistor M14 and current source I4 are introduced. The DFVF is used to increase the discharge current of the load capacitor in the negative conversion stage. At the same time, the FVFCS is used to increase the charging current of the load capacitor in the positive conversion stage, thereby greatly increasing the slew rate of the operational amplifier circuit. In this case, the magnitude of the tail current of the differential input can reach more than one hundred times the magnitude of the intermediate-stage current at most, thereby significantly reducing the power consumption of the operational amplifier circuit.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits, relates to an operational amplifier circuit, and specifically provides a folded cascode structure operational amplifier circuit with low power consumption and large slew rate. Background Art

[0002] During the signal processing, usually an operational amplifier is used to collect signals, and then the signals are handed over to an ADC (Analog-to-Digital Converter) circuit to convert the analog signals into digital signals for processing; the slew rate refers to the response speed of the operational amplifier to a large step signal, that is, when a large step signal is input to the operational amplifier, the conversion rate of the operational amplifier from the initial state to the final steady state.

[0003] Currently, a commonly used folded cascode structure operational amplifier circuit is as Figure 1 shown. For such an operational amplifier, the calculation formula for its slew rate is SR = I0 / CL, where I0 is the current of the input stage tail current source, and CL is the load capacitance; however, the slew rate is limited by the magnitude of the intermediate stage static current. When the intermediate stage static current is much smaller than the current of the input stage tail current source I0, the slew rate no longer satisfies SR = I0 / CL; specifically:

[0004] During the positive conversion stage, i.e., when VIN+ is much greater than VIN-; assume that the static current of metal-oxide-semiconductor field-effect transistor M17 is equal to the static current of metal-oxide-semiconductor field-effect transistor M18, which is Im, the static current of metal-oxide-semiconductor field-effect transistor M21 is Im21, and the static current flowing through the branch of metal-oxide-semiconductor field-effect transistor M6 is Im22, and Im21 is equal to Im22; at the moment when the positive conversion starts, almost all of the current I0 in the input tail current source flows through metal-oxide-semiconductor field-effect transistor M16 and into metal-oxide-semiconductor field-effect transistor M18. At this time, the drain voltage of metal-oxide-semiconductor field-effect transistor M18 rises sharply, causing metal-oxide-semiconductor field-effect transistor M20 to turn off. At the same time, the excessively high drain voltage of metal-oxide-semiconductor field-effect transistor M18 will cause metal-oxide-semiconductor field-effect transistor M16 to enter the linear region, thereby causing the input differential pair transistors to lose the ability to control the current; as a result, the current flowing through metal-oxide-semiconductor field-effect transistor M16 is actually generated by metal-oxide-semiconductor field-effect transistor M18. At this time, due to the effective channel length modulation effect, the current generated by metal-oxide-semiconductor field-effect transistor M18 is greater than its static current Im. For the convenience of analysis, it is approximately considered that the current flowing through metal-oxide-semiconductor field-effect transistor M18 is still Im at this time; although at the moment when the positive conversion starts, almost no current in the input tail current source flows through metal-oxide-semiconductor field-effect transistor M15 and into metal-oxide-semiconductor field-effect transistor M17, and metal-oxide-semiconductor field-effect transistor M17 enters the linear region at the beginning moment, but afterwards, only a current of Im magnitude is drawn away by metal-oxide-semiconductor field-effect transistor M16, resulting in a current of I0 - Im magnitude flowing through metal-oxide-semiconductor field-effect transistor M15 and into metal-oxide-semiconductor field-effect transistor M17. At this time, metal-oxide-semiconductor field-effect transistor M17 enters the saturation region; in this case, the magnitude of the current flowing through metal-oxide-semiconductor field-effect transistor M19 is Im - (I0 - Im), which is Im21 + Im22; this current enters the branch of metal-oxide-semiconductor field-effect transistor M22 and metal-oxide-semiconductor field-effect transistor M24 through the current mirror formed by metal-oxide-semiconductor field-effect transistor M21 and metal-oxide-semiconductor field-effect transistor M22, thereby providing current for the charging of the load capacitor CL.

[0005] During the negative conversion stage, i.e., when VIN+ is much smaller than VIN-; assume that the static current of metal-oxide-semiconductor field-effect transistor M17 is equal to the static current of metal-oxide-semiconductor field-effect transistor M18, which is Im, the static current of metal-oxide-semiconductor field-effect transistor M21 is Im21, and the static current flowing through the branch of metal-oxide-semiconductor field-effect transistor M6 is Im22, and Im21 is equal to Im22; at the moment when the negative conversion starts, almost all the current in the input tail current source flows through metal-oxide-semiconductor field-effect transistor M15 into metal-oxide-semiconductor field-effect transistor M17. At this time, the drain voltage of metal-oxide-semiconductor field-effect transistor M17 rises sharply, causing metal-oxide-semiconductor field-effect transistor M19 to turn off, so that no current flows through metal-oxide-semiconductor field-effect transistor M21. Metal-oxide-semiconductor field-effect transistor M21 and metal-oxide-semiconductor field-effect transistor M22 form a current mirror, and the current flowing through metal-oxide-semiconductor field-effect transistor M22 and metal-oxide-semiconductor field-effect transistor M24 is also 0; at the same time, the too high drain voltage of metal-oxide-semiconductor field-effect transistor M17 will cause metal-oxide-semiconductor field-effect transistor M15 to enter the linear region, thus making the input differential pair lose the ability to control the current; furthermore, the current flowing through metal-oxide-semiconductor field-effect transistor M1 is actually generated by metal-oxide-semiconductor field-effect transistor M17. At this time, due to the effective channel length modulation effect, the current generated by metal-oxide-semiconductor field-effect transistor M17 is greater than its static current Im. For the convenience of analysis, it is approximately considered that the current flowing through metal-oxide-semiconductor field-effect transistor M17 is still Im; although at the moment when the negative conversion starts, almost no current in the input tail current source flows through metal-oxide-semiconductor field-effect transistor M16 into metal-oxide-semiconductor field-effect transistor M18, and metal-oxide-semiconductor field-effect transistor M18 enters the linear region at the beginning moment, but then only Im-sized current is diverted by metal-oxide-semiconductor field-effect transistor M15, resulting in (I0 - Im)-sized current flowing through metal-oxide-semiconductor field-effect transistor M16 into metal-oxide-semiconductor field-effect transistor M18. At this time, metal-oxide-semiconductor field-effect transistor M18 enters the saturation region; in this case, the current flowing through metal-oxide-semiconductor field-effect transistor M20 is Im - (I0 - Im), that is, Im21 + Im22, and this current provides current for the discharge of the load capacitor CL.

[0006] It can be seen that when the current of the intermediate stage is much smaller than the tail current source of the input stage, the slew rate is limited by the current of the intermediate stage and thus greatly reduced. Therefore, in the usual circuit design, to ensure that the slew rate meets the requirements, the current of the intermediate stage and the tail current of the differential input are generally set to the same order of magnitude, so as to get rid of the limitation of the intermediate stage current and make the slew rate meet the calculation formula SR = I0 / CL. However, in the conventional case, the tail current of the input stage of the operational amplifier is usually very large. If the current of the intermediate stage and the tail current of the input stage are set to the same order of magnitude, it will cause a large amount of static current consumption. Summary of the Invention

[0007] The purpose of the present invention is to provide a folded cascode structure operational amplifier circuit with low power consumption and large slew rate to solve the problems of low slew rate and high power consumption existing in the existing folded cascode structure operational amplifier circuit. The present invention is designed based on the folded cascode structure, and uses the differential structure of the flip voltage follower (DFVF) to increase the discharge current of the load capacitor in the negative conversion stage, and at the same time uses the flip voltage follower current sensor (FVFCS) to increase the charging current of the load capacitor in the positive conversion stage, thereby greatly increasing the slew rate of the operational amplifier circuit. In this case, the magnitude of the tail current of the differential input can reach more than a hundred times that of the intermediate stage current, thereby significantly reducing the power consumption of the operational amplifier circuit.

[0008] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0009] A folded cascode structure operational amplifier circuit with low power consumption and large slew rate, including: current sources I0 to I4, transistors M1 to M14, thin film resistor R1, load capacitor CL; where:

[0010] The gate of transistor M1 is connected to the non-inverting input terminal VIN+, and the gate of transistor M2 is connected to the inverting input terminal VIN-. The sources of transistor M1 and transistor M2 are connected, and current source I0 is connected between the source of transistor M1 and the positive power supply rail. The drains of transistor M1, transistor M3, the source of transistor M5, and the source of transistor M6 are connected.

[0011] The drains of transistor M2, transistor M4, the source of transistor M7, and the source of transistor M8 are connected. The sources of transistor M3 and transistor M4 are both connected to the negative power supply rail. The gates of transistor M3, transistor M4, and the drain of transistor M8 are connected, and current source I3 is connected between the drain of transistor M8 and the positive power supply rail.

[0012] The gates of transistor M5, transistor M8, and transistor M9 are connected together. The drain of transistor M9 is connected to its gate. Current source I1 is connected between the drain of transistor M9 and the positive power supply rail. Thin film resistor R1 is connected between the gate of transistor M9 and the negative power supply rail. The drains of transistor M5, the gates of transistor M10, transistor M11, the drain of transistor M12, and the gate of transistor M14 are connected together.

[0013] The gates of transistor M12, transistor M13, and the source of transistor M14 are connected together. Current source I4 is connected between the source of transistor M14 and the negative power supply rail. The sources of transistor M10, transistor M11, and the drain of transistor M14 are all connected to the positive power supply rail. The drain of transistor M10 is connected to the source of transistor M12. The drain of transistor M11 is connected to the source of transistor M13.

[0014] The gates of transistor M6 and transistor M7 are connected together. The drain of transistor M6 is connected to its gate. Current source I1 is connected between the gate of transistor M6 and the positive power supply rail. The drains of transistor M7 and transistor M13 are connected together and connected to the output voltage terminal Vout. Load capacitor CL is connected between the output voltage terminal Vout and the negative power supply rail.

[0015] Furthermore, transistor M4, transistor M7, and transistor M8 form a differential flip voltage follower (DFVF) structure.

[0016] Furthermore, transistor M3, transistor M4, and transistor M8 form a flip voltage follower current sensor (FVFCS).

[0017] Furthermore, transistor M14 and current source I4 form a source follower.

[0018] Furthermore, current sources I0 to I4 all adopt cascode current sources.

[0019] Furthermore, transistors M1 to M14 all adopt metal oxide semiconductor field effect transistors.

[0020] Based on the above technical solutions, the beneficial effects of the present invention are as follows:

[0021] The present invention provides a folded cascode operational amplifier circuit with low power consumption and large slew rate. On the basis of the traditional folded cascode structure, a differential structure of a flip voltage follower (DFVF) composed of transistor M4, transistor M7, and transistor M8 is introduced. A flip voltage follower current sensor (FVFCS) composed of transistor M3, transistor M4, and transistor M8, and a source follower composed of transistor M14 and current source I4 are provided. The differential structure of the flip voltage follower (DFVF) is used to increase the discharge current of the load capacitor in the negative conversion stage. At the same time, the flip voltage follower current sensor (FVFCS) is used to increase the charging current of the load capacitor in the positive conversion stage, thereby significantly increasing the slew rate of the operational amplifier circuit. In this case, the magnitude of the differential input tail current can reach more than one hundred times the magnitude of the intermediate stage current, thereby significantly reducing the power consumption of the operational amplifier circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 FIG. is a schematic circuit diagram of a traditional folded cascode operational amplifier circuit.

[0023] Figure 2 FIG. is a schematic circuit diagram of a folded cascode operational amplifier circuit with low power consumption and large slew rate in the present invention.

[0024] Figure 3 FIG. is a schematic circuit diagram of a cascode current source in the present invention.

[0025] Figure 4 FIG. is a schematic circuit diagram of the differential structure of a flip voltage follower (DFVF) in the present invention and a schematic diagram of its current-voltage relationship.

[0026] Figure 5 FIG. is a schematic circuit diagram of the flip voltage follower current sensor structure (FVFCS) in the present invention and a schematic diagram of its current-voltage relationship.

[0027] Figure 6 FIG. is a comparison chart of the slew rates of folded cascode operational amplifier circuits in the embodiment and the comparative example of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] In order to make the objectives, technical solutions, and beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments.

[0029] This embodiment provides a folded cascode operational amplifier circuit with low power consumption and large slew rate. Its circuit structure is as Figure 2 shown, where VIN+ is the non-inverting input terminal of the operational amplifier circuit, VIN- is the inverting input terminal of the operational amplifier circuit, VOUT is the output voltage terminal of the input stage of the operational amplifier circuit, AVDD is the positive power supply, and AVSS is the negative power supply.

[0030] Specifically, the folded cascode operational amplifier circuit includes: cascode current sources I0, I1, I2, I3, I4, metal-oxide-semiconductor field-effect transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, M13, M14, thin film resistor R1, and load capacitor CL; where:

[0031] The gate of metal-oxide-semiconductor field-effect transistor M1 is connected to the non-inverting input terminal VIN+, and the gate of metal-oxide-semiconductor field-effect transistor M2 is connected to the inverting input terminal VIN-.

[0032] The sources of metal-oxide-semiconductor field-effect transistors M1 and M2 are connected together, and cascode current source I0 is connected between the source of metal-oxide-semiconductor field-effect transistor M1 and the positive power supply rail.

[0033] The drains of metal-oxide-semiconductor field-effect transistors M1, M3, the sources of metal-oxide-semiconductor field-effect transistors M5 and M6 are connected together.

[0034] The drains of metal-oxide-semiconductor field-effect transistors M2, M4, the sources of metal-oxide-semiconductor field-effect transistors M7 and M8 are connected together.

[0035] The sources of metal-oxide-semiconductor field-effect transistors M3 and M4 are both connected to the negative power supply rail.

[0036] The gates of metal-oxide-semiconductor field-effect transistors M3, M4, and the drain of metal-oxide-semiconductor field-effect transistor M8 are connected together, and cascode current source I3 is connected between the drain of metal-oxide-semiconductor field-effect transistor M8 and the positive power supply rail.

[0037] The gates of metal-oxide-semiconductor field-effect transistor M5, metal-oxide-semiconductor field-effect transistor M8, and metal-oxide-semiconductor field-effect transistor M9 are connected (the connection point is Vcon). The drain of metal-oxide-semiconductor field-effect transistor M9 is connected to its gate. The cascode current source I1 is connected between the drain of metal-oxide-semiconductor field-effect transistor M9 and the positive power supply rail. The thin-film resistor R1 is connected between the gate of metal-oxide-semiconductor field-effect transistor M9 and the negative power supply rail;

[0038] The drains of metal-oxide-semiconductor field-effect transistor M5, the gates of metal-oxide-semiconductor field-effect transistor M10, the gates of metal-oxide-semiconductor field-effect transistor M11, the drain of metal-oxide-semiconductor field-effect transistor M12, and the gate of metal-oxide-semiconductor field-effect transistor M14 are connected;

[0039] The gates of metal-oxide-semiconductor field-effect transistor M12, the gates of metal-oxide-semiconductor field-effect transistor M13, and the source of metal-oxide-semiconductor field-effect transistor M14 are connected. The cascode current source I4 is connected between the source of metal-oxide-semiconductor field-effect transistor M14 and the negative power supply rail;

[0040] The sources of metal-oxide-semiconductor field-effect transistor M10, the sources of metal-oxide-semiconductor field-effect transistor M11, and the drain of metal-oxide-semiconductor field-effect transistor M14 are all connected to the positive power supply rail;

[0041] The drain of metal-oxide-semiconductor field-effect transistor M10 is connected to the source of metal-oxide-semiconductor field-effect transistor M12. The drain of metal-oxide-semiconductor field-effect transistor M11 is connected to the source of metal-oxide-semiconductor field-effect transistor M13;

[0042] The gates of metal-oxide-semiconductor field-effect transistor M6 and metal-oxide-semiconductor field-effect transistor M7. The drain of metal-oxide-semiconductor field-effect transistor M6 is connected to its gate. The cascode current source I1 is connected between the gate of metal-oxide-semiconductor field-effect transistor M6 and the positive power supply rail;

[0043] The drains of metal-oxide-semiconductor field-effect transistor M7 and metal-oxide-semiconductor field-effect transistor M13 are connected and connected to the output voltage terminal Vout. The load capacitor CL is connected between the output voltage terminal Vout and the negative power supply rail.

[0044] Further, the circuit structure of the cascode current source is as Figure 3As shown, where Vb1, Vb2, Vb3, and Vb4 are bias voltage terminals, I is the output current of the cascode current source, AVDD is the positive power supply, and AVSS is the negative power supply.

[0045] Furthermore, the metal-oxide-semiconductor field-effect transistors M4, M7, and M8 form a differential structure of a flip voltage follower (DFVF). The schematic diagram of its circuit structure and the schematic diagram of the current-voltage relationship are as Figure 4 shown, where V1 and V2 are voltage input terminals, Ib is the bias current of the differential structure of the flip voltage follower, IDM3 is the output current of the differential structure of the flip voltage follower, AVDD is the positive power supply, and AVSS is the negative power supply; in the normal operating state, the current-voltage relationship of the differential structure of the flip voltage follower is as Figure 4 shown.

[0046] Furthermore, the metal-oxide-semiconductor field-effect transistors M3, M4, and M8 form a flip voltage follower current sensor (FVFCS). The schematic diagram of its circuit structure and the schematic diagram of the current-voltage relationship are as Figure 5 shown, where V1 is the bias voltage terminal, Iin is the current input terminal, Ib is the bias current of the flip voltage follower current sensor, Iout is the output current of the flip voltage follower current sensor, AVDD is the positive power supply, and AVSS is the negative power supply; in the normal operating state, the current-voltage relationship of the flip voltage follower current sensor is as Figure 5 shown.

[0047] In terms of the working principle:

[0048] As Figure 2 shown, in the folded cascode operational amplifier circuit proposed in the present invention, the metal-oxide-semiconductor field-effect transistors M4, M7, and M8 form a differential structure of a flip voltage follower (DFVF), the metal-oxide-semiconductor field-effect transistors M3, M4, and M8 form a flip voltage follower current sensor (FVFCS), the metal-oxide-semiconductor field-effect transistor M14 and the cascode current source I4 form a source follower. The differential structure of the flip voltage follower (DFVF) plays a role in increasing the slew rate in the negative conversion stage, and the flip voltage follower current sensor (FVFCS) and the source follower play a role in increasing the slew rate in the positive conversion stage;

[0049] During the negative conversion stage, i.e., when VIN+ is much smaller than VIN-; at this time, almost all the current of the input current source I0 flows through the metal-oxide-semiconductor field-effect transistor M1 and into the metal-oxide-semiconductor field-effect transistor M3, thus causing the drain potential of the metal-oxide-semiconductor field-effect transistor M3 to rise rapidly; since the current of the metal-oxide-semiconductor field-effect transistor M6 is constant, therefore, the gate voltage of the metal-oxide-semiconductor field-effect transistor M6 increases as the drain voltage of the metal-oxide-semiconductor field-effect transistor M3 increases; for the metal-oxide-semiconductor field-effect transistor M4, the metal-oxide-semiconductor field-effect transistor M7, and the metal-oxide-semiconductor field-effect transistor M8 that form a flip voltage follower differential structure (DFVF), as the gate voltage of the metal-oxide-semiconductor field-effect transistor M7 increases, the current of the metal-oxide-semiconductor field-effect transistor M7 increases rapidly. Finally, when the current flowing through the metal-oxide-semiconductor field-effect transistor M4 reaches I0, the metal-oxide-semiconductor field-effect transistor M3 can maintain a current of I0, and the drain voltage of the metal-oxide-semiconductor field-effect transistor M3 reaches the maximum value. At this time, the current in the metal-oxide-semiconductor field-effect transistor M7 also reaches the maximum value, approximately I0. The current in the metal-oxide-semiconductor field-effect transistor M7 all comes from the discharge of the load capacitor. Thus, when the intermediate-stage static current is much smaller than the input-stage tail current, the discharge current of the load capacitor in the negative conversion stage is greatly increased, thereby improving the slew rate in the negative conversion stage;

[0050] During the positive conversion stage, that is, when VIN+ is much greater than VIN-; at this time, almost all the current of the input current source I0 flows through the metal-oxide-semiconductor field-effect transistor M2 and into the metal-oxide-semiconductor field-effect transistor M4; for the metal-oxide-semiconductor field-effect transistor M3, the metal-oxide-semiconductor field-effect transistor M4, and the metal-oxide-semiconductor field-effect transistor M8, they form a flip voltage follower current sensor (FVFCS). As the input current increases rapidly, the current of the metal-oxide-semiconductor field-effect transistor M3 also increases, and thus the current of the metal-oxide-semiconductor field-effect transistor M10 also increases; at this time, the gate voltage of the metal-oxide-semiconductor field-effect transistor M10 drops. Through the action of the source follower formed by the metal-oxide-semiconductor field-effect transistor M14 and the cascode current source I4, the gate voltages of the metal-oxide-semiconductor field-effect transistor M12 and the metal-oxide-semiconductor field-effect transistor M13 drop accordingly, so that the metal-oxide-semiconductor field-effect transistor M12 and the metal-oxide-semiconductor field-effect transistor M13 do not limit the currents of the metal-oxide-semiconductor field-effect transistor M10 and the metal-oxide-semiconductor field-effect transistor M11. Therefore, through the current source formed by the metal-oxide-semiconductor field-effect transistor M10 and the metal-oxide-semiconductor field-effect transistor M11, the current of the metal-oxide-semiconductor field-effect transistor M11 also increases. Finally, the current flowing through the metal-oxide-semiconductor field-effect transistor M3 is equal to the current I0 flowing through the metal-oxide-semiconductor field-effect transistor M4, and the current flowing through the metal-oxide-semiconductor field-effect transistor M11 is equal to the current flowing through the metal-oxide-semiconductor field-effect transistor M10. The current in the metal-oxide-semiconductor field-effect transistor M11 charges all the load capacitors. Thus, when the static current in the intermediate stage is much smaller than the tail current in the input stage, the charging current of the load capacitor in the positive conversion stage is greatly increased, thereby improving the slew rate in the positive conversion stage.

[0051] In summary, taking the traditional folded cascode structure operational amplifier circuit as shown in Figure 1 as the comparative example, the comparison results of the slew rate of the folded cascode structure operational amplifier circuit in this embodiment and the comparative example are as shown in Figure 6 shown. When consuming the same static current (taking the tail current in the input stage as 100 μA, the current in the intermediate stage as 3 μA, and the total current as 106 μA as an example), when the load is 10 pf, the slew rate in the negative conversion stage of the traditional folded cascode structure is 0.724 V / μs, and the slew rate in the positive conversion stage is 0.693 V / μs; the slew rate in the negative conversion stage of the circuit structure proposed by the present invention is 9.745 V / μs, and the slew rate in the positive conversion stage is 9.597 V / μs; thus, it can be seen that the slew rate in the negative conversion stage is increased by 13.460 times, and the slew rate in the positive conversion stage is increased by 13.848 times.

[0052] In addition, compared with the traditional folded cascode structure under normal conditions (the input-stage tail current of the traditional folded cascode structure is 100 μA, the intermediate-stage current is 65 μA, and the total current is 230 μA), when the load is 10 pF, the slew rate of the traditional folded cascode structure in the negative conversion stage is 9.855 V / μs, and the slew rate in the positive conversion stage is 9.548 V / μs. The circuit structure proposed by the present invention reduces the power consumption by 52.609% while achieving almost the same slew rate.

[0053] Therefore, the present invention provides a folded cascode operational amplifier circuit with low power consumption and large slew rate, which can achieve a relatively high slew rate with a relatively large input differential tail current and an extremely small intermediate-stage static current.

[0054] The above are only the specific embodiments of the present invention. Any feature disclosed in this specification, unless specifically described, can be replaced by other equivalent or similar-purpose alternative features; all the features disclosed, or all the steps in any method or process, can be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A folded cascode operational amplifier circuit with low power consumption and large slew rate, comprising: Current sources I0 to I4, transistors M1 to M14, resistor R1, load capacitor CL; characterized in that: The gate of transistor M1 is connected to the non-inverting input terminal VIN+, and the gate of transistor M2 is connected to the inverting input terminal VIN-; the sources of transistor M1 and transistor M2 are connected, and current source I0 is connected between the source of transistor M1 and the positive power supply rail; the drains of transistor M1, the drain of transistor M3, the sources of transistor M5, and the sources of transistor M6 are connected; The drains of transistor M2, the drain of transistor M4, the sources of transistor M7, and the sources of transistor M8 are connected. The sources of transistor M3 and transistor M4 are both connected to the negative power supply rail. The gates of transistor M3, the gate of transistor M4, and the drain of transistor M8 are connected, and current source I3 is connected between the drain of transistor M8 and the positive power supply rail; The gates of transistor M5, the gate of transistor M8, and the gate of transistor M9 are connected. The drain and gate of transistor M9 are connected. Current source I1 is connected between the drain of transistor M9 and the positive power supply rail. Resistor R1 is connected between the gate of transistor M9 and the negative power supply rail; the drain of transistor M5, the gate of transistor M10, the gate of transistor M11, the drain of transistor M12, and the gate of transistor M14 are connected; The gate of transistor M12, the gate of transistor M13, and the source of transistor M14 are connected. Current source I4 is connected between the source of transistor M14 and the negative power supply rail; the sources of transistor M10, the source of transistor M11, and the drain of transistor M14 are all connected to the positive power supply rail. The drain of transistor M10 and the source of transistor M12 are connected. The drain of transistor M11 and the source of transistor M13 are connected; The gates of transistor M6 and the gate of transistor M7. The drain and gate of transistor M6 are connected. Current source I1 is connected between the gate of transistor M6 and the positive power supply rail; the drain of transistor M7 and the drain of transistor M13 are connected and connected to the output voltage terminal Vout. Load capacitor CL is connected between the output voltage terminal Vout and the negative power supply rail.

2. The folded cascode operational amplifier circuit with low power consumption and large slew rate according to claim 1, characterized in that Transistors M4, M7, and M8 form a differential flip voltage follower structure (DFVF).

3. The folded cascode operational amplifier circuit with low power consumption and large slew rate according to claim 1, characterized in that Transistors M3, M4, and M8 form a flip voltage follower current sensor (FVFCS).

4. The folded cascode operational amplifier circuit with low power consumption and large slew rate according to claim 1, characterized in that, Transistor M14 and current source I4 form a source follower.

5. The folded cascode operational amplifier circuit with low power consumption and large slew rate according to claim 1, characterized in that Current sources I0 to I4 all adopt cascode current sources.

6. The folded cascode operational amplifier circuit with low power consumption and large slew rate according to claim 1, characterized in that, Transistors M1 to M14 all adopt metal oxide semiconductor field effect transistors.

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