Driving signal supply device and driving signal calibration method thereof

Abstract

The invention discloses a driving signal supply device and a driving signal calibration method thereof. The driving signal supply device includes an oscillation circuit, a driving signal generation circuit, and a control circuit. The oscillation circuit includes a plurality of oscillators each including an inverter and outputs a plurality of oscillation signals. A switching characteristic of each inverter included in one of the plurality of oscillators is different from a switching characteristic of each inverter included in another of the plurality of oscillators. The control circuit detects a process corner of the semiconductor device based on the plurality of oscillation signals to generate a control signal. The drive signal generation circuit generates a drive signal of the semiconductor device based on the control signal.

Description

[0001] This patent application claims the priority benefit of Korean Patent Application No. 10-2023-0102163 filed in the Korean Intellectual Property Office on August 4, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the present disclosure described herein are directed to a semiconductor device, and more particularly, to a driving signal supplying device and a driving signal calibration method thereof. Background Art

[0003] Semiconductor devices are electronic components that rely on the unique electrical properties of semiconductor materials to achieve their functions. Examples of semiconductor devices include memory devices, power management devices, and sensor devices.

[0004] The semiconductor device may include a driving signal supply device and may operate based on a driving signal generated by the driving signal supply device. The driving signal may be an internal voltage or an internal clock signal supplied to one or more components included in the semiconductor device.

[0005] Semiconductor devices may be manufactured in accordance with defined hardware specifications. However, due to process, voltage, and temperature (PVT) variations, the semiconductor device may not be properly manufactured as expected or may not operate as expected in accordance with the hardware specifications. As a result, the performance of the semiconductor device may deteriorate. For example, the voltage level of an internal voltage may not reach the voltage level defined by the hardware specifications, or may exceed the voltage level defined by the hardware specifications, or an internal clock signal may not maintain its desired duty cycle. Summary of the invention

[0006] An embodiment of the present disclosure provides a driving signal supplying device that supplies a driving signal satisfying a performance condition of a hardware specification of the electronic device to an electronic device.

[0007] An embodiment of the present disclosure provides a method for calibrating a driving signal of a driving signal supply device.

[0008] According to an embodiment, a drive signal supply device includes an oscillation circuit, a drive signal generating circuit and a control circuit. The oscillation circuit outputs a plurality of oscillation signals. The oscillation circuit includes a plurality of oscillators, and each of the plurality of oscillators includes an inverter. The switching characteristics of each inverter included in one of the plurality of oscillators are different from the switching characteristics of each inverter included in another of the plurality of oscillators. The control circuit detects a process angle of a semiconductor device based on the plurality of oscillation signals to generate a control signal. The drive signal generating circuit generates a drive signal of the semiconductor device based on the control signal.

[0009] According to an embodiment, in a method for calibrating a drive signal, a plurality of oscillation signals are output by an oscillation circuit. The oscillation circuit includes a plurality of oscillators, and each of the plurality of oscillators includes an inverter. The switching characteristics of each inverter included in one of the plurality of oscillators are different from the switching characteristics of each inverter included in another of the plurality of oscillators. A process angle of a semiconductor device is detected based on the plurality of oscillation signals. The drive signal of the semiconductor device is calibrated based on the process angle.

[0010] According to an embodiment, a drive signal supply device includes an oscillation circuit, a drive signal generating circuit and a control circuit. The oscillation circuit outputs a plurality of oscillation signals. The oscillation circuit includes a plurality of oscillators, and each of the plurality of oscillators includes an inverter. The switching characteristics of each inverter included in one oscillator among the plurality of oscillators are different from the switching characteristics of each inverter included in another oscillator among the plurality of oscillators. The control circuit performs a comparison operation based on the plurality of oscillation signals to generate a control signal. The drive signal generating circuit generates a drive signal of a semiconductor device based on the control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings.

[0012] Figure 1 is a block diagram illustrating a driving signal supplying device according to an embodiment of the present disclosure.

[0013] Figure 2 is used to describe manufacturing including Figure 1 Graph showing process changes in a process of a semiconductor device of a driving signal supply device.

[0014] Figure 3 Is used to describe instructions Figure 2 Process distribution and process variation Figure 2 Illustration of the process angle.

[0015] Figure 4A It is shown Figure 1 A block diagram of an embodiment of an oscillator circuit.

[0016] Figure 4B Is used to describe Figure 4A A diagram of the switching characteristics of an oscillator.

[0017] Figure 5 It is shown Figure 1 A block diagram of an embodiment of a control circuit.

[0018] Figure 6 It is shown Figure 5 A block diagram of an embodiment of a process angle determiner.

[0019] Figure 7 It shows that it includes Figure 6 Process angle determiner Figure 5 Flowchart of an embodiment of the control circuit operation.

[0020] Figure 8 It is used to describe the embodiments according to the present disclosure. Figure 7 Schematic diagram of a process angle determination process.

[0021] Fig. 9 Is used to describe Figure 7 A diagram of two or more reference values ​​of .

[0022] Fig.10 It is shown Figure 1 A block diagram of an embodiment of a drive signal generating circuit.

[0023] Fig.11 It is shown Figure 5 A block diagram of an embodiment of a process angle determiner.

[0024] Fig.12 It shows that it includes Fig.11 Process angle determiner Figure 5 Flowchart of an embodiment of the control circuit operation.

[0025] Fig.13 Is used to describe Fig.12 Schematic diagram of a process angle determination process.

[0026] Fig.14 It is shown Figure 1 A block diagram of an embodiment of a drive signal generating circuit.

[0027] Fig.15 is a flow chart illustrating a driving signal calibration method according to an embodiment of the present disclosure.

[0028] Fig.16 It shows reference Fig.15 A block diagram of an embodiment of a process for detecting process corners is described.

[0029] Fig.17 It shows reference Fig.16 A block diagram of an embodiment of a process for determining a process corner is described.

[0030] Fig.18 It shows reference Fig.16 A block diagram of an embodiment of a process for determining a process corner is described.

[0031] Fig.19 is a flow chart illustrating a driving signal calibration method according to an embodiment of the present disclosure.

[0032] Fig. 20 is a block diagram illustrating an electronic system including a driving signal supplying device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] The embodiments of the present disclosure will be described below in detail and clearly to the extent that those skilled in the art can perform the present disclosure.

[0034] Figure 1 is a block diagram illustrating a driving signal supplying device according to an embodiment of the present disclosure.

[0035] Reference Figure 1 , a driving signal supply device (DSSD) 100 may be included in the semiconductor device 300. The driving signal supply device 100 may generate one or more driving signals DSs to be supplied to one or more components included in the semiconductor device 300. For example, the one or more driving signals DSs may be an internal voltage or an internal clock signal, but the present disclosure is not limited thereto.

[0036] The driving signal supply device 100 may include an oscillation circuit (OSC) 110 , a control circuit 130 , and a driving signal generating circuit 150 .

[0037] The oscillation circuit 110 may output a plurality of oscillation signals OSs having different oscillation periods or different oscillation frequencies. For example, the oscillation circuit 110 may include a plurality of oscillators 111-1 to 111-n (n is 2 or more), and the oscillation circuit 110 may output a plurality of oscillation signals OSs by using the plurality of oscillators 111-1 to 111-n.

[0038] In one embodiment, each of the plurality of oscillators 111-1 to 111-n includes an inverter, and the switching characteristics of each inverter (e.g., 113-1) included in one of the plurality of oscillators 111-1 to 111-n may be different from the switching characteristics of each inverter (e.g., 113-n) included in another (or additional) oscillator of the plurality of oscillators 111-1 to 111-n. For example, each of the plurality of oscillators may be implemented with a ring oscillator. The inverter included in each ring oscillator may have the same switching characteristics, but the inverter included in one ring oscillator and the inverter included in another (or additional) ring oscillator of the plurality of ring oscillators may have different switching characteristics. For example, the first ring oscillator included in the plurality of oscillators 111-1 to 111-n may include only an inverter having a first switching characteristic, and the second ring oscillator included in the plurality of oscillators 111-1 to 111-n may include only an inverter having a second switching characteristic different from the first switching characteristic.

[0039] In one embodiment, each inverter included in each of the multiple oscillators 111-1 to 111-n includes a p-type metal oxide semiconductor (PMOS) transistor and an n-type metal oxide semiconductor (NMOS) transistor, and according to the hardware specifications of each of the PMOS transistor and the NMOS transistor included in each inverter, the inverter may have the above switching characteristics.

[0040] In one embodiment, for the plurality of oscillators 111-1 to 111-n for outputting a plurality of oscillation signals OSs having different oscillation periods or different oscillation frequencies, the hardware specifications of the PMOS transistor and the NMOS transistor included in each inverter may be independently defined regardless of the plurality of PMOS transistors and the plurality of NMOS transistors included in the semiconductor device 300 but not included in the drive signal supply device 100. The hardware specifications of each of the PMOS transistor and the NMOS transistor included in each inverter may be used to calibrate the one or more drive signals DSs in the process of generating the one or more drive signals DSs by the drive signal supply device 100. Reference will be made to Figure 4A and Figure 4B The oscillation circuit 110 is described.

[0041] The control circuit 130 may receive a plurality of oscillation signals OSs from the oscillation circuit 110. In one embodiment, the control circuit 130 is configured to detect process characteristics of the semiconductor device 300 based on the plurality of oscillation signals OSs and may generate the control signal CTLD based on the detected process characteristics, which may depend on a manufacturing process used to manufacture the semiconductor device 300.

[0042] In one embodiment, the control circuit 130 may detect a process corner of the semiconductor device 300 from the plurality of oscillation signals OSs, and may generate the control signal CTLD based on the process corner. The process corner may be an index for identifying a process characteristic by classifying a process distribution based on a given standard, the process distribution indicating a process variation of the semiconductor device 300 according to a manufacturing process. The detection of the process corner may mean detecting a type of process corner or estimating a type of process corner, and may include determining or identifying the process corner. Figure 5 , Figure 6 and Fig.11 The control circuit 130 is described.

[0043] The driving signal generating circuit 150 may generate one or more driving signals DSs of the semiconductor device 300 based on the control signal CTLD.

[0044] In one embodiment, the control circuit 130 controls the operation of the driving signal generating circuit 150 by using the control signal CTLD. For example, the control circuit 130 may calibrate the one or more driving signals DSs by using the control signal CTLD. For example, the driving signal generating circuit 150 may adjust the voltage level or duty cycle of the one or more driving signals DSs of the semiconductor device 300 based on the control signal CTLD, and may generate and output the one or more driving signals DSs whose voltage level or duty cycle is adjusted.

[0045] In one embodiment, the driving signal generating circuit 150 provides one or more driving signals DSs as the feedback signal FDS to the oscillating circuit 110, and the oscillating circuit 110 may output a plurality of oscillating signals OSs again. For example, the oscillating circuit 110 may modify one of the oscillating signals OSs based on the feedback signal FDS. Fig.10 and Fig.14 The drive signal generating circuit 150 is described.

[0046] Through the above configuration, the driving signal supply device according to the embodiment of the present disclosure can detect the process angle as a process characteristic of the semiconductor device by using multiple oscillators that output multiple oscillation signals with different oscillation periods or different oscillation frequencies, and can generate and calibrate one or more driving signals to be supplied to each component included in the semiconductor device based on the process angle.

[0047] One or more driving signals satisfying the performance conditions of the hardware specification can be supplied to the semiconductor device through the driving signal supply device regardless of PVT variation. Therefore, the performance degradation of the semiconductor device can be prevented.

[0048] Figure 2 is used to describe manufacturing including Figure 1 Graph showing process changes in a process of a semiconductor device of a driving signal supply device.

[0049] Reference Figure 2 In the process of manufacturing semiconductor devices, a plurality of chips (or bare dies) including a plurality of semiconductor devices may be formed in one wafer 10 . Figure 2 2 shows an example in which a semiconductor device 300a is formed in one chip (eg, 30), and the semiconductor device 300a may include a driving signal supply device 100a. The semiconductor device 300a and the driving signal supply device 100a may correspond to Figure 1 The semiconductor device 300 and the driving signal supply device 100 are provided.

[0050] The PMOS transistor 51 and the NMOS transistor 53 included in the driving signal supply device (DSSD) 100a may correspond to the transistors included in a plurality of oscillators (eg, Figure 1 The PMOS transistor 55 and the NMOS transistor 57 included in the semiconductor device 300a and formed outside the drive signal supply device 100a may correspond to a plurality of PMOS transistors and a plurality of NMOS transistors included in the semiconductor device 300a but not included in the drive signal supply device 100a.

[0051] In one embodiment, there may be process variations in the transistors 51, 53, 55, and 57 of the semiconductor device 300a manufactured during the manufacturing process. The transistors 51 and 53 may be manufactured so that the inverter included in each of the plurality of oscillators 111-1 to 111-n has a specific switching characteristic as described above, regardless of the process variations. However, when the transistors are manufactured by the same manufacturing process, the plurality of oscillators 111-1 to 111-n may output a plurality of oscillation signals affected by the process variations.

[0052] In one embodiment, referring to Figure 1 The described process angle may relate to the transistors 55 and 57 included in the semiconductor device 300a. For example, detection or estimation of the process angle may be performed for the transistors 55 and 57, and the voltage level or duty cycle of one or more driving signals to be supplied to the semiconductor device 300a may be calibrated (or adjusted) based on the process angle.

[0053] Reference Figure 2 The semiconductor device 300a formed in one chip and the driving signal supply device 100a included in the semiconductor device 300a are described, but the remaining chips formed in the wafer 10 may be implemented in the same manner or in a similar manner. Therefore, the driving signal supply device for the semiconductor device included in each of the plurality of chips formed in the wafer 10 may be implemented for each chip.

[0054] Figure 3 Is used to describe instructions Figure 2 Process distribution and process variation of Figure 2 Illustration of the process angle.

[0055] exist Figure 3 , reference numeral 71 indicates a graph of the process profile 31. Figure 3 , the horizontal axis represents the speed of the NMOS transistor (or the magnitude of the leakage current in the saturation mode of the NMOS transistor), and the vertical axis represents the speed of the PMOS transistor (or the magnitude of the leakage current in the saturation mode of the PMOS transistor).

[0056] In association with the performance conditions of the hardware specifications of the semiconductor device, the process corner may be represented by: 1) "Fast (F)" when the NMOS transistor is manufactured so that the speed of the NMOS transistor is fast compared to a defined speed range, 2) "Slow (S)" when the NMOS transistor is manufactured so that the speed of the NMOS transistor is slow compared to a defined speed range, and 3) "Typical (T)" when the NMOS transistor is manufactured so that the speed of the NMOS transistor satisfies the defined speed range. The speed of the PMOS transistor may be represented in the same manner as the NMOS transistor.

[0057] In association with the performance conditions of the hardware specifications of the semiconductor device, when the NMOS transistor is manufactured so that the speed of the NMOS transistor is slow compared to the defined speed range and when the PMOS transistor is manufactured so that the speed of the PMOS transistor is fast compared to the defined speed range, the process angle may be represented by "slow-fast (SF)". In association with the performance conditions, when the NMOS transistor is manufactured so that the speed of the NMOS transistor is fast compared to the defined speed range and when the PMOS transistor is manufactured so that the speed of the PMOS transistor is slow compared to the defined speed range, the process angle may be represented by "fast-slow (FS)". As in the above description, process angles "FF", "TT" and "SS" may be defined. For example, the process angle may be represented by a combination of two letters sequentially indicating the characteristics of the NMOS transistor and the characteristics of the PMOS transistor, the two letters being determined according to the manufacturing process.

[0058] exist Figure 3 , reference numeral 75 indicates a table of process corners “SF” (e.g., “slow-fast”), “TF” (e.g., “typical-fast”), “FF” (e.g., fast-fast), “ST” (e.g., “slow-typical”), “TT” (e.g., “typical-typical”), “FT” (e.g., “fast-typical”), “SS” (e.g., “slow-slow”), “TS” (e.g., “typical-slow”), and “FS” (e.g., “fast-slow”). Each process corner may be represented by a unique index number.

[0059] Figure 4A It is shown Figure 1 A block diagram of an embodiment of an oscillator circuit, and Figure 4B Is used to describe Figure 4A A diagram of the switching characteristics of an oscillator.

[0060] Reference Figure 4AThe oscillation circuit (OSC) 500 may output a plurality of oscillation signals having different oscillation periods or different oscillation frequencies. For example, the oscillation circuit 500 may include a plurality of ring oscillators (RO1 (510) to ROn (530)) (n is 2 or more), and the plurality of ring oscillators RO1 to ROn may output a plurality of oscillation signals OS1 to OSn having different oscillation frequencies (e.g., f1 to fn).

[0061] In one embodiment, each of the plurality of ring oscillators 510 and 530 includes an inverter, and the switching characteristics of each inverter included in one of the plurality of ring oscillators 510 and 530 may be different from the switching characteristics of each inverter included in another (or additional) ring oscillator included in the plurality of ring oscillators 510 and 530.

[0062] In one embodiment, each inverter included in each of the plurality of ring oscillators 510 and 530 includes a PMOS transistor and an NMOS transistor connected in series between a power supply voltage VDD and a ground voltage. According to the hardware specification of each of the PMOS transistor and the NMOS transistor included in each inverter, the inverter may have a switching characteristic. For example, the PMOS transistor and the NMOS transistor included in the ring oscillator 510 may be defined as having channel widths Wp1 and Wn1, respectively. For example, the PMOS transistor and the NMOS transistor included in the ring oscillator 530 may be defined as having channel widths Wpn and Wnn, respectively.

[0063] Reference Figure 4A and Figure 4B , the switching characteristics of an inverter may represent the relationship between changes in an input signal and changes in an output signal over time, and may be distinguished from direct current (DC) characteristics, which represent the relationship between changes in an input signal and changes in an output signal without considering the passage of time.

[0064] The oscillation frequency of the ring oscillator may be determined based on logical effort, electrical effort, parasitic delay, or the number of inverters included in the ring oscillator. Logical effort may be defined by the ratio of the input capacitance of a given gate to the input capacitance of an inverter capable of transmitting the same output current. For example, the channel widths Wn1 and Wnn of the NMOS transistors included in the ring oscillators 510 and 530 may be determined to have the same value. The channel width Wpn of the PMOS transistor included in the ring oscillator 530 may be determined to be greater than the channel width Wp1 of the PMOS transistor included in the ring oscillator 510. According to the above scheme, the ring oscillators 510 and 530 may be implemented to have different logical efficiencies, and the ring oscillators 510 and 530 may output a plurality of oscillation signals having different oscillation periods or different oscillation frequencies.

[0065] In one embodiment, a ratio of channel widths may be defined for each inverter included in each ring oscillator. In each inverter included in each ring oscillator, the ratio of channel widths may be defined as a ratio of a channel width of a PMOS transistor to a channel width of an NMOS transistor. For example, each inverter included in the ring oscillator (RO1) 510 may have a ratio of channel widths: Wp1 / Wn1. Each inverter included in the ring oscillator (ROn) 530 may have a ratio of channel widths: Wpn / Wnn. For example, the ratio of the channel widths of each inverter included in the ring oscillator (ROn) 530 may be greater than the ratio of the channel widths of each inverter included in the ring oscillator (RO1) 510.

[0066] In one embodiment, the number of ring oscillators included in the oscillation circuit 500 may be determined according to the type of the driving signal. For example, when the driving signal is an internal voltage, the number of ring oscillators included in the oscillation circuit 500 may be 2 or more. For example, when the driving signal is an internal clock signal, the number of ring oscillators included in the oscillation circuit 500 may be 3 or more. However, the present disclosure is not limited thereto.

[0067] Figure 5 It is shown Figure 1 A block diagram of an embodiment of a control circuit.

[0068] Reference Figure 1 and Figure 5 , the control circuit 700 may correspond to the control circuit 130. In one embodiment, the control circuit 700 receives a plurality of oscillation signals OSs (OS1, . . . , OSn), detects a process corner of the semiconductor device based on the plurality of oscillation signals OSs, and generates a control signal CTLD based on the process corner.

[0069] The control circuit 700 may include a counter 710 (eg, a counter circuit), a process angle determiner 730 (eg, a logic circuit), and a control signal generator 750 .

[0070] The counter 710 may count the plurality of oscillation signals OSs to generate a plurality of count values ​​CNTVs (CNTV1, ..., CNTVn). For example, the counter 710 may count the rising edge or the falling edge of each of the plurality of oscillation signals OSs. For example, the counter 710 may count the oscillation signal OS1 to generate the count value CNTV1, and may count the oscillation signal OSn to generate the count value CNTVn.

[0071] In one embodiment, the process angle determiner 730 determines the process angle based on the plurality of count values ​​CNTVs. In one embodiment, the process angle determiner 730 generates and outputs process angle information PRCI including information on the process angle.

[0072] The control signal generator 750 receives the process corner information PRCI and generates a control signal CTLD based on the process corner information PRCI.

[0073] In one embodiment, the process angle determiner 730 stores reference value information (REFI) 731, which includes two or more reference voltages or two or more reference values ​​for classifying (or distinguishing) the types of process angles. The reference value information 731 may be stored in the process angle determiner 730 in advance before the driving signal supply device according to an embodiment of the present disclosure operates.

[0074] In one embodiment, depending on the driving signal supply device (eg, Figure 1 When the drive signal supply device generates or calibrates an internal voltage, two or more reference values ​​may be used. When the drive signal supply device generates or calibrates an internal clock signal, two or more reference values ​​do not need to be used.

[0075] In one embodiment, the process angle determiner 730 may be implemented differently according to the case where the driving signal supply device generates or calibrates the internal voltage and the case where the driving signal supply device generates or calibrates the internal clock signal, and may classify (or distinguish) the types of process angles in different ways. Figures 6 to 10 Describes the situation where an internal voltage is generated or calibrated and will refer to Figures 11 to 14 Describes the situation where an internal clock signal is generated or calibrated.

[0076] Figure 6 It is shown Figure 5 A block diagram of an embodiment of a process angle determiner.

[0077] Reference Figure 5 and Figure 6 , the process angle determiner 730a may correspond to the process angle determiner 730. The process angle determiner 730a may be used to generate or calibrate an internal voltage as a driving signal to be supplied to the semiconductor device.

[0078] The process angle determiner 730a may determine the process angle based on two or more reference values ​​REF1 and REF2 for classifying (or distinguishing) the types of process angles and a plurality of count values ​​CNTV1 and CNTV2. In this case, the oscillation circuit (eg, Figure 4A 500) may include two oscillators (or two ring oscillators), and may generate oscillation signals OS1 and OS2 (ie, when Figure 4A or Figure 5 Where n is 2). A plurality of count values ​​CNTV1 and CNTV2 may be generated by counting the oscillation signals OS1 and OS2, respectively. Although the number of oscillators included in the oscillation circuit is two in this example, the disclosed embodiments are not limited thereto. Figure 4A and Figure 4B As described above, a ratio of a channel width of each inverter included in the ring oscillator outputting the oscillation signal OS2 may be greater than a ratio of a channel width of each inverter included in the ring oscillator outputting the oscillation signal OS1.

[0079] The process angle determiner 730 a may include an average value calculator 731 a (eg, a logic circuit) and comparators 733 a and 735 a (eg, a comparator circuit).

[0080] The average value calculator 731 a may receive the plurality of count values ​​CNTV1 and CNTV2 , and may calculate an average count value AVG_CNTV by averaging the plurality of count values ​​CNTV1 and CNTV2 .

[0081] In one embodiment, the comparators 733a and 735a compare the average count value AVG_CNTV with two or more reference values ​​REF1 and REF2 to determine the process angle. In one embodiment, the comparator 733a compares the average count value AVG_CNTV with the reference value REF1 to generate a comparison result CR1, and the comparator 735a compares the average count value AVG_CNTV with the reference value REF2 to generate a comparison result CR2.

[0082] The process angle determiner 730a may determine the type of process angle based on the comparison results CR1 and CR2. Figure 7The process of determining the type of process angle is described. The process angle determiner 730a may generate and output process angle information PRCI including information about the process angle. For example, the process angle determiner 730a may generate the process angle information PRCI based on the comparison results CR1 and CR2 (or may output the comparison results CR1 and CR2 as the process angle information PRCI).

[0083] Figure 7 It shows that it includes Figure 6 Process angle determiner Figure 5 Flowchart of an embodiment of the control circuit operation.

[0084] Reference Figures 5 to 7 , the control circuit 700 receives a plurality of oscillation signals OS1 and OS2 ( S100 ).

[0085] The counter 710 counts the plurality of oscillation signals OS1 and OS2 to generate a plurality of count values ​​CNTV1 and CNTV2 ( S200 ).

[0086] The process angle determiner 730 a averages the plurality of count values ​​CNTV1 and CNTV2 to generate an average count value AVG_CNTV ( S300 ).

[0087] The process angle determiner 730a determines whether the average count value AVG_CNTV is less than the reference value REF1 (S510). If the average count value AVG_CNTV is not less than the reference value REF1, the process angle determiner 730a determines whether the average count value AVG_CNTV is less than the reference value REF2 (S530). The process angle determiner 730a may classify the type of process angle according to the determination results in operations S510 and S530. Fig.12 As described above, the process angle determiner 730a may classify the types of process angles in a manner different from that of the process angle determiner 730b. For example, the first to third types of process angles classified by the process angle determiner 730a may be different from the fourth to sixth types of process angles classified by the process angle determiner 730b.

[0088] When the average count value AVG_CNTV is less than the reference value REF1 (Yes in operation S510), the process corner determiner 730a determines that the process corner has the first type (S710). When it is determined that the process corner has the first type, the control signal generator 750 increases the voltage level IVL of the internal voltage (S910). In one embodiment, in association with the performance conditions of the hardware specification of the semiconductor device, the first type corresponds to the following situation: the transistor of the semiconductor device is manufactured so that the speed of the transistor is slow compared to the defined speed range.

[0089] When the average count value AVG_CNTV is greater than or equal to the reference value REF1 ("No" in operation S510), and when the average count value AVG_CNTV is less than the reference value REF2 ("Yes" in operation S530), the process angle determiner 730a determines that the process angle has the second type (S730). When determining that the process angle has the second type, the control signal generator 750 maintains or maintains the voltage level IVL of the internal voltage (S930). In association with the performance conditions of the hardware specification of the semiconductor device, the second type may correspond to the following case: the transistor of the semiconductor device is manufactured so that the speed of the transistor satisfies the defined speed range.

[0090] When the average count value AVG_CNTV is greater than or equal to the reference value REF1 (No in operation S510), and when the average count value AVG_CNTV is greater than or equal to the reference value REF2 (No in operation S530), the process angle determiner 730a determines that the process angle has the third type (S750). When it is determined that the process angle has the third type, the control signal generator 750 reduces the voltage level IVL of the internal voltage (S950). In one embodiment, in association with the performance condition of the hardware specification of the semiconductor device, the third type corresponds to the following situation: the transistor of the semiconductor device is manufactured so that the speed of the transistor is faster than the defined speed range. The reference Figure 8 The first type, the second type and the third type are described. Fig. 9 Describes reference values ​​REF1 and REF2. Figure 7 S510 is shown to occur before S530, but in an alternative embodiment, S530 is performed first.

[0091] Figure 8 It is used to describe the Figure 7 Schematic diagram of a process angle determination process.

[0092] exist Figure 8 , reference numeral 91 denotes an average count value AVG_CNTV associated with process corners “SF”, “TF”, “FF”, “ST”, “TT”, “FT”, “SS”, “TS”, and “FS”, and reference numeral 93 denotes a first type, a second type, and a third type. Figure 8The average count value AVG_CNTV indicated by reference numeral 91 may be data collected by a test operation performed in advance before the drive signal supply device according to an embodiment of the present disclosure operates. For example, a plurality of average count values ​​AVG_CNTV may be collected from a plurality of test semiconductor devices, the plurality of test semiconductor devices being manufactured to indicate various process corners “SF”, “TF”, “FF”, “ST”, “TT”, “FT”, “SS”, “TS”, and “FS”, and each of the test semiconductor devices including a drive signal supply device (e.g., Figure 1 of 100).

[0093] In one embodiment, "AVG3" may represent an average count value AVG_CNTV collected from test semiconductor devices indicating process corners "SS", "TS", and "ST". "AVG2" may represent an average count value AVG_CNTV collected from test semiconductor devices indicating process corners "TT", "SF", and "FS". "AVG1" may represent an average count value AVG_CNTV collected from test semiconductor devices indicating process corners "FF", "TF", and "FT". In one embodiment, AVG1 is greater than AVG2, and AVG2 is greater than AVG3.

[0094] In one embodiment, process corners corresponding to (or associated with) the same average count value AVG_CNTV or similar average count values ​​AVG_CNTV may be classified as one type of process corner. Figure 8 93, the process corners "SS", "TS", and "ST" corresponding to the average count value AVG_CNTV having AVG3 may be classified as the process corners of the first type 93-1. The process corners "TT", "SF", and "FS" corresponding to the average count value AVG_CNTV having AVG2 may be classified as the process corners of the second type 93-2. The process corners "FF", "TF", and "FT" corresponding to the average count value AVG_CNTV having AVG1 may be classified as the process corners of the third type 93-3.

[0095] Fig. 9 Is used to describe Figure 7 A diagram of two or more reference values ​​of .

[0096] Reference Figures 7 to 9 , reference values ​​REF1 and REF2 may be set to classify the first type 93 - 1 , the second type 93 - 2 , and the third type 93 - 3 of the process corners.

[0097] In one embodiment, the reference value REF1 is used to classify the first type 93-1 and the second type 93-2 and is set to be less than AVG2 and greater than AVG3. The reference value REF2 is used to classify the third type 93-3 and the second type 93-2 and is set to be less than AVG1 and greater than AVG2.

[0098] As reference Figure 7 As described above, the process angle determiner 730 may determine whether the average count value AVG_CNTV is less than the reference value REF1 ( S510 ), and may determine whether the average count value AVG_CNTV is less than the reference value REF2 ( S530 ).

[0099] The process corner determiner 730 may determine the type of the process corner based on the determination results of operations S510 and S530 , and the control signal generator 750 may increase, maintain, or decrease the voltage level IVL of the internal voltage in operation S910 , operation S930 , or operation S950 .

[0100] Fig.10 It is shown Figure 1 A block diagram of an embodiment of a drive signal generating circuit.

[0101] Reference Figure 1 and Fig.10 , the driving signal generating circuit 900a may correspond to the driving signal generating circuit 150. The driving signal generating circuit 900a may be configured from a circuit including a process angle determiner (eg, Figure 6 730a) of the control circuit (for example, Figure 5 700) receives a control signal CTLD and may generate or calibrate one or more driving signals DSs including an internal voltage IV based on the control signal CTLD.

[0102] The driving signal generating circuit 900a may include a controller 910a (e.g., a control circuit) and an internal voltage generator 930a. The controller 910a may control the internal voltage generator 930a based on a control signal CTLD. The internal voltage generator 930a may generate or calibrate one or more driving signals DSs including an internal voltage IV under the control of the controller 910a.

[0103] In one embodiment, under the control of the controller 910a, the internal voltage generator 930a may calibrate the voltage level of the internal voltage IV by increasing, maintaining, or decreasing the voltage level of the internal voltage IV in operation S910, operation S930, or operation S950.

[0104] Fig.11 It is shown Figure 5 A block diagram of an embodiment of a process angle determiner.

[0105] Reference Figure 5 and Fig.11 , the process angle determiner 730b may correspond to the process angle determiner 730. The process angle determiner 730b may be used to generate or calibrate an internal clock signal as a driving signal to be provided to the semiconductor device.

[0106] In one embodiment, the process angle determiner 730 determines the process angle based on the plurality of count values ​​CNTV1, CNTV2, and CNTV3. Figure 4A 500) may include three oscillators (or three ring oscillators), and may generate oscillation signals OS1, OS2, and OS3 (ie, when Figure 4A or Figure 5 3). A plurality of count values ​​CNTV1, CNTV2, and CNTV3 may be generated by counting the oscillation signals OS1, OS2, and OS3, respectively. Although the number of oscillators included in the oscillation circuit is three in this example, the disclosed embodiments are not limited thereto. Figure 4A and Figure 4B As described above, the ratio of the channel width of each inverter included in the ring oscillator that outputs the oscillation signal OS3 may be greater than the ratio of the channel width of each inverter included in the ring oscillator that outputs the oscillation signal OS2. The ratio of the channel width of each inverter included in the ring oscillator that outputs the oscillation signal OS2 may be greater than the ratio of the channel width of each inverter included in the ring oscillator that outputs the oscillation signal OS1.

[0107] The process angle determiner 730 b may include comparators 731 b and 733 b .

[0108] Comparators 731b and 733b may compare multiple count values ​​CNTV1, CNTV2, and CNTV3 to determine the process angle. In one embodiment, comparator 731b compares count values ​​CNTV1 and CNTV2 to generate comparison result CR3, and comparator 733b compares count values ​​CNTV2 and CNTV3 to generate comparison result CR4.

[0109] The process angle determiner 730b may determine the type of the process angle based on the comparison results CR3 and CR4. Fig.12 The process of determining the type of process angle is described. The process angle determiner 730b may generate and output process angle information PRCI including information about the process angle. For example, the process angle determiner 730b may generate process angle information PRCI based on the comparison results CR3 and CR4 (or may output the comparison results CR3 and CR4 as process angle information PRCI).

[0110] Fig.12It shows that it includes Fig.11 Process angle determiner Figure 5 Flowchart of an embodiment of the control circuit operation.

[0111] Reference Figure 5 , Fig.11 and Fig.12 , the control circuit 700 receives a plurality of oscillation signals OS1, OS2 and OS3 (S100-1).

[0112] The counter 710 counts the plurality of oscillation signals OS1 , OS2 , and OS3 to generate a plurality of count values ​​CNTV1 , CNTV2 , and CNTV3 ( S200 - 1 ).

[0113] The process angle determiner 730b determines whether the count value CNTV1 is greater than the count value CNTV2 (S510-1). If the count value CNTV1 is not greater than the count value CNTV2, the process angle determiner 730b determines whether the count value CNTV3 is greater than the count value CNTV2 (S530-1). The process angle determiner 730b may classify the type of process angle according to the determination results of operations S510-1 and S530-1. Figure 7 As described above, the process angle determiner 730b may classify the types of process angles in a different manner from the process angle determiner 730a. For example, the fourth to sixth types of process angles classified by the process angle determiner 730b may be different from the first to third types of process angles classified by the process angle determiner 730a.

[0114] When the count value CNTV1 is greater than the count value CNTV2 (yes in operation S510-1), the process angle determiner 730b determines that the process angle has a fourth type (S710-1). When it is determined that the process angle has the fourth type, the control signal generator 750 reduces the duty cycle DTR of the internal clock signal (S910-1). In one embodiment, in association with the performance conditions of the hardware specification of the semiconductor device, the fourth type corresponds to a case where the PMOS transistor and the NMOS transistor of the semiconductor device are manufactured to be unbalanced. For example, the fourth type may correspond to a case where the PMOS transistor and the NMOS transistor are manufactured so that the speed of the PMOS transistor is relatively faster than the speed of the NMOS transistor.

[0115] When the count value CNTV1 is less than or equal to the count value CNTV2 (No in operation S510-1), and when the count value CNTV3 is greater than the count value CNTV2 (Yes in operation S530-1), the process angle determiner 730b determines that the process angle has the fifth type (S730-1). When it is determined that the process angle has the fifth type, the control signal generator 750 increases the duty cycle DTR of the internal clock signal (S930-1). In association with the performance conditions of the hardware specification of the semiconductor device, the fifth type may correspond to a case where the PMOS transistor and the NMOS transistor of the semiconductor device are manufactured to be unbalanced. For example, the fifth type may correspond to a case where the PMOS transistor and the NMOS transistor are manufactured so that the speed of the PMOS transistor is relatively slower than the speed of the NMOS transistor.

[0116] In one embodiment, the process angle determiner 730b performs operation S530-1 immediately after operation S200-1 without performing operation S510-1 to determine that the process angle has the fifth type. For example, when the count value CNTV3 is greater than the count value CNTV2 (yes in operation S530-1), the process angle determiner 730b may determine that the process angle has the fifth type (S730-1).

[0117] When the count value CNTV1 is less than or equal to the count value CNTV2 (No in operation S510-1), and when the count value CNTV3 is less than or equal to the count value CNTV2 (No in operation S530-1), the process angle determiner 730b determines that the process angle has the sixth type (S750-1). When determining that the process angle has the sixth type, the control signal generator 750 maintains or maintains the duty cycle DTR of the internal clock signal (S950-1). In association with the performance conditions of the hardware specification of the semiconductor device, the sixth type may correspond to a case where the PMOS transistor and the NMOS transistor of the semiconductor device are manufactured to be balanced. For example, the sixth type may correspond to a case where the PMOS transistor and the NMOS transistor are manufactured so that the speed of the PMOS transistor is substantially equal to the speed of the NMOS transistor. Reference will be made to Fig.13 Describe the fourth, fifth, and sixth types.

[0118] Fig.13 It is used to describe the Fig.12 Schematic diagram of a process angle determination process.

[0119] exist Fig.13 , reference numeral 95 indicates count values ​​CNTV1, CNTV2, and CNTV3 associated with process corners "TT", "SS", "FF", "SF", and "FS", and reference numeral 97 indicates a fourth type, a fifth type, and a sixth type. Fig.13The count values ​​CNTV1, CNTV2, and CNTV3 indicated by reference numeral 95 may be data collected by a test operation performed in advance before the drive signal supply device according to an embodiment of the present disclosure operates. For example, a plurality of count values ​​CNTV1, CNTV2, and CNTV3 may be collected from a plurality of test semiconductor devices, the plurality of test semiconductor devices being manufactured to indicate various process corners "TT", "SS", "FF", "SF", and "FS", and each of the test semiconductor devices including a drive signal supply device (e.g., Figure 1 of 100).

[0120] In one embodiment, count values ​​CNTV1, CNTV2, and CNTV3 collected from a test semiconductor device indicating a process corner "TT" may be close to CV5. Count values ​​CNTV1, CNTV2, and CNTV3 collected from a test semiconductor device indicating process corners "SS", "SF", and "FS" may be close to CV4. Count values ​​CNTV1, CNTV2, and CNTV3 collected from a test semiconductor device indicating a process corner "FF" may be between CV6 and CV7. CV7 may be greater than CV6, CV6 may be greater than CV5, and CV5 may be greater than CV4.

[0121] In one embodiment, process corners corresponding to count values ​​CNTV1 , CNTV2 , and CNTV3 having the same pattern or similar patterns may be classified as one type of process corner.

[0122] For example, referring to Fig.13 97 , a process corner “SF” corresponding to a case where the count value CNTV1 is greater than the count value CNTV2 may be classified as a process corner of a fourth type 97 - 4 .

[0123] For example, a process corner “FS” corresponding to a case where the count value CNTV1 is less than or equal to the count value CNTV2 and the count value CNTV3 is greater than the count value CNTV2 may be classified as a process corner of the fifth type 97 - 5 .

[0124] For example, process corners “FF”, “TT”, and “SS” corresponding to a case where the count value CNTV1 is less than or equal to the count value CNTV2 and the count value CNTV3 is less than or equal to the count value CNTV2 may be classified as process corners of the sixth type 97 - 6 .

[0125] Fig.14 It is shown Figure 1 A block diagram of an embodiment of a drive signal generating circuit.

[0126] Reference Figure 1 and Fig.14, the driving signal generating circuit 900b may correspond to the driving signal generating circuit 150. The driving signal generating circuit 900b may be configured from a circuit including a process angle determiner (eg, Fig.11 The process angle determiner 730b) of the control circuit (eg, Figure 5 700) receives the control signal CTLD and can generate or calibrate one or more driving signals DSs including the internal clock signal IC.

[0127] The driving signal generating circuit 900b may include a controller 910b and an internal clock generator 930b. The controller 910b may control the internal clock generator 930b based on a control signal CTLD. The internal clock generator 930b may generate or calibrate one or more driving signals DSs including an internal clock signal IC under the control of the controller 910b.

[0128] In one embodiment, under the control of the controller 910b, the internal clock generator 930b may calibrate the internal clock signal IC by reducing, maintaining, or increasing the duty ratio of the internal clock signal IC in operation S910-1, operation S930-1, or operation S950-1.

[0129] As reference Fig.12 As described above, the process angle determiner 730b may determine the process angle by comparing a plurality of count values ​​with each other. Figure 4A 500) may include a plurality of oscillators, and the plurality of oscillators may include a first oscillator outputting a first oscillation signal, a second oscillator outputting a second oscillation signal, and a third oscillator outputting a third oscillation signal.

[0130] In one embodiment, each inverter included in the first oscillator may have a first ratio of channel widths, each inverter included in the second oscillator may have a second ratio of channel widths, and each inverter included in the third oscillator may have a third ratio of channel widths. The second ratio of channel widths may be greater than the first ratio of channel widths, and the third ratio of channel widths may be greater than the second ratio of channel widths.

[0131] The process angle determiner 730b may determine the process angle by comparing the frequency of the first oscillation signal, the frequency of the second oscillation signal, and the frequency of the third oscillation signal. Figure 5 710) can count the rising edge or falling edge of each of the first oscillation signal, the second oscillation signal and the third oscillation signal to generate a corresponding count value. As the frequency of the oscillation signal increases, the count value obtained by counting the oscillation signal can increase.

[0132] In one embodiment, the counter counts the first oscillation signal to generate a first count value, counts the second oscillation signal to generate a second count value, and counts the third oscillation signal to generate a third count value. The process angle determiner 730b can compare the frequencies of the first oscillation signal, the second oscillation signal, and the third oscillation signal by comparing the first count value, the second count value, and the third count value.

[0133] In one embodiment, when the frequency of the first oscillation signal is higher than the frequency of the second oscillation signal (for example, when the count value CNTV1 is greater than the count value CNTV2), the process angle determiner 730b may determine that the process angle has the fourth type, and when determining that the process angle has the fourth type, the control signal generator (for example, Figure 5 750) can reduce the duty cycle of the internal clock signal.

[0134] In one embodiment, when the frequency of the first oscillation signal is lower than or equal to the frequency of the second oscillation signal and when the frequency of the third oscillation signal is higher than the frequency of the second oscillation signal (for example, the count value CNTV1 is less than or equal to the count value CNTV2 and when the count value CNTV3 is greater than the count value CNTV2), the process angle determiner 730b may determine that the process angle has the fifth type, and when determining that the process angle has the fifth type, the control signal generator may increase the duty cycle of the internal clock signal.

[0135] In one embodiment, when the frequency of the first oscillation signal is lower than or equal to the frequency of the second oscillation signal and when the frequency of the third oscillation signal is lower than or equal to the frequency of the second oscillation signal (for example, the count value CNTV1 is less than or equal to the count value CNTV2 and when the count value CNTV3 is less than or equal to the count value CNTV2), the process angle determiner 730b may determine that the process angle has the sixth type, and when determining that the process angle has the sixth type, the control signal generator may maintain the duty cycle of the internal clock signal.

[0136] Fig.15 is a flow chart illustrating a driving signal calibration method according to an embodiment of the present disclosure.

[0137] Reference Fig.15 , in the driving signal calibration method, a plurality of oscillation signals are output (S1000).

[0138] In one embodiment, operation S1000 is performed by an oscillating circuit (eg, Figure 1 110 or Figure 4A500). For example, the oscillation circuit may include a plurality of oscillators, and each of the plurality of oscillators may include an inverter. The switching characteristics of each inverter included in one of the plurality of oscillators may be different from the switching characteristics of each inverter included in another (or additional) oscillator of the plurality of oscillators. For example, each of the plurality of oscillators may be implemented with a ring oscillator. In this case, the inverter included in each ring oscillator may have the same switching characteristics, but the inverter included in one ring oscillator and the inverter included in another (or additional) ring oscillator may have different switching characteristics.

[0139] A process corner of a semiconductor device is detected based on a plurality of oscillation signals ( S1300 ).

[0140] In one embodiment, operation S1300 is performed by a control circuit (eg, Figure 5 700) or a process angle determiner (e.g., Figure 5 730 Figure 6 730a or Fig.11 The process corner may be an index for identifying a process characteristic by classifying a process distribution based on a given standard, the process distribution indicating a process variation of a semiconductor device according to a semiconductor device manufacturing process.

[0141] In one embodiment, the process corner is detected by performing one or more operations including a comparison operation based on a plurality of oscillation signals. For example, the comparison operation may include Figure 7 Operation S510 and operation S530 may include Fig.12 Operation S510 - 1 and operation S530 - 1.

[0142] One or more driving signals of a semiconductor device are calibrated based on a process corner ( S1500 ).

[0143] In one embodiment, the number of ring oscillators included in the oscillation circuit may be determined according to the type of the driving signal. For example, when the driving signal is an internal voltage, the number of ring oscillators may be 2 or more; when the driving signal is an internal clock signal, the number of ring oscillators may be 3 or more.

[0144] In one embodiment, in the process of detecting the process corner, two or more reference values ​​may or may not be used depending on the type of the driving signal. When the driving signal is an internal voltage, two or more reference values ​​may be used; when the driving signal is an internal clock signal, two or more reference values ​​may not be used.

[0145] Fig.16 It shows reference Fig.15 A block diagram of an embodiment of a process for detecting process corners is described. For example, Fig.15 The S1300 can be Fig.16 accomplish.

[0146] Reference Fig.15 and Fig.16 In the process of detecting the process corner, a plurality of count values ​​are generated by counting a plurality of oscillation signals (S1310).

[0147] A process angle is determined based on the plurality of count values ​​(S1330).

[0148] Fig.17 It shows reference Fig.15 A block diagram of an embodiment of a process for determining a process corner is described. For example, Fig.15 The S1300 can be Fig.17 accomplish.

[0149] Reference Fig.15 and Fig.17 In the process of determining the process angle, an average count value is calculated by averaging a plurality of count values ​​(S1331-1).

[0150] The process corner is identified (or determined) based on the average count value and two or more reference values ​​for classifying the type of the process corner (S1333-1).

[0151] In one embodiment, operations S1331-1 and S1333-1 may correspond to reference Figures 5 to 10 Described embodiments.

[0152] Fig.18 It shows reference Fig.16 A block diagram of an embodiment of a process for determining a process corner is described. For example, Fig.15 Operations S1000 and S1300 can be performed by Fig.18 accomplish.

[0153] Reference Fig.15 and Fig.18 In the step of outputting a plurality of oscillation signals, a first oscillation signal, a second oscillation signal and a third oscillation signal are output (S1001-3).

[0154] In the process of determining the process angle, the first oscillation signal, the second oscillation signal, and the third oscillation signal are compared (S1331-3).

[0155] In one embodiment, the frequency of the first oscillation signal, the frequency of the second oscillation signal, and the frequency of the third oscillation signal may be compared during operation S1331 - 3 .

[0156] In the process of determining the process angle, the process angle is identified (or determined) according to the result calculated by comparing the first oscillation signal, the second oscillation signal, and the third oscillation signal (S1333-3). The result can be generated by comparing the frequency of the first oscillation signal, the frequency of the second oscillation signal, and the frequency of the third oscillation signal.

[0157] In one embodiment, operations S1001-3, S1331-3, and S1333-3 may correspond to reference Figures 5 to 14 Described embodiments.

[0158] Fig.19 is a flow chart illustrating a driving signal calibration method according to an embodiment of the present disclosure.

[0159] Reference Figure 7 and Fig.19 , the control circuit receives a plurality of oscillation signals OS1 and OS2 ( S100 ).

[0160] The counter counts the plurality of oscillation signals OS1 and OS2 and generates a plurality of count values ​​CNTV1 and CNTV2 ( S200 ).

[0161] The process angle determiner averages the plurality of count values ​​CNTV1 and CNTV2 to generate an average count value AVG_CNTV ( S300 ).

[0162] The process corner determiner compares the average count value AVG_CNTV with reference values ​​REF1 and REF2 (S500) to determine the type of the process corner PRC (S700).

[0163] In one embodiment, the type of process corner PRC is referenced Figure 7 The first type, the second type, or the third type described. In association with the performance conditions according to the hardware specifications of the semiconductor device, the first type or the third type may correspond to a case where the transistor of the semiconductor device is manufactured so that the speed of the transistor is slow or fast compared to the defined speed range. In association with the performance conditions of the hardware specifications of the semiconductor device, the second type may correspond to a case where the transistor of the semiconductor device is manufactured so that the speed of the transistor satisfies the defined speed range.

[0164] The control signal generator may calibrate (or adjust) a voltage level IVL of the internal voltage IV based on the process corner PRC ( S900 ).

[0165] In one embodiment, when the process corner PRC corresponds to the first type or the third type, the control signal generator may increase or decrease the voltage level IVL of the internal voltage IV. When the process corner PRC corresponds to the second type, the control signal generator may maintain the voltage level IVL of the internal voltage IV.

[0166] The process corner determiner determines whether the process corner PRC corresponds to the second type ( S910 ).

[0167] When the process corner PRC does not correspond to the second type (No in operation S910), the driving signal generating circuit uses the internal voltage IV of the increased or decreased voltage level as a feedback signal (eg, Figure 1 For example, the internal voltage IV of the increased or decreased voltage level may be used as the power supply voltage (eg, Figure 4A VDD) is provided to the oscillation circuit OSC.

[0168] In one embodiment, the oscillation circuit may output the plurality of oscillation signals OS1 and OS2 again, and the control circuit may generate a control signal (eg, Figure 1 and Figure 5 CTLD) and thus output it again.

[0169] In one embodiment, operations S100 , S200 , S300 , S500 , S700 , S900 , S910 , and S930 are repeatedly performed until the process corner PRC corresponds to the second type.

[0170] When the process corner PRC corresponds to the second type (Yes in operation S910 ), the driving signal generating circuit may output the internal voltage IV to the semiconductor device.

[0171] Fig. 20 is a block diagram illustrating an electronic system including a driving signal supplying device according to an embodiment of the present disclosure.

[0172] Reference Fig. 20 , the electronic system 1500 may include a processor 1510, a memory device 1520, a storage device 1530, an image sensor 1540, an input / output device 1550, and a driving signal supply device 1560. The electronic system 1500 may communicate with a video card, a sound card, a memory card, a universal serial bus (USB) device, etc., or may also include a port capable of communicating with any other electronic device.

[0173] Processor 1510 may perform specific calculations or tasks. In one embodiment, processor 1510 may be a microprocessor or a central processing unit (CPU).

[0174] The processor 1510 may communicate with the memory device 1520 , the storage device 1530 , the image sensor 1540 , and the input / output device 1550 through at least one of an address bus, a control bus, and a data bus.

[0175] In one embodiment, processor 1510 may also be connected to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

[0176] The memory device 1520 may store data required for the operation of the electronic system 1500. For example, the memory device 1520 may be implemented with dynamic RAM (DRAM), mobile DRAM, static RAM (SRAM), phase change RAM (PRAM), ferroelectric RAM (FRAM), resistive RAM (RRAM), and / or magnetoresistive RAM (MRAM).

[0177] The storage device 1530 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, or the like.

[0178] The input / output device 1550 may include input devices such as a keyboard, a keypad, and a mouse, and output devices such as a printer and a display.

[0179] The driving signal supply device 1560 may provide driving signals applied to the operation of the electronic system 1500. For example, the driving signal supply device 1560 may generate one or more driving signals to be supplied to the components 1510, 1520, 1530, 1540, and 1550 of the electronic system 1500. For example, the one or more driving signals may include an internal voltage or an internal clock signal, and the driving signal supply device 1560 may correspond to the driving signal supply device according to an embodiment of the present disclosure.

[0180] The image sensor 1540 may be connected to the processor 1510 through a bus or any other communication link and may perform communication.

[0181] Through the above configuration, the driving signal supply device according to the embodiment of the present disclosure can detect the process angle as a process characteristic of the semiconductor device by using multiple oscillators that output multiple oscillation signals with different oscillation periods or different oscillation frequencies, and can generate and calibrate one or more driving signals to be supplied to each component included in the semiconductor device based on the process angle.

[0182] One or more driving signals satisfying the performance conditions of the hardware specification can be supplied to the semiconductor device through the driving signal supply device regardless of PVT variation. Therefore, the performance degradation of the semiconductor device can be prevented.

[0183] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A driving signal supply device, comprising: an oscillation circuit including a plurality of oscillators each including an inverter and configured to output a plurality of oscillation signals, wherein a switching characteristic of each inverter included in one of the plurality of oscillators is different from a switching characteristic of each inverter included in another of the plurality of oscillators; a control circuit configured to detect a process corner of the semiconductor device based on the plurality of oscillation signals to generate a control signal; and The drive signal generating circuit is configured to generate a drive signal for the semiconductor device based on the control signal.

2. The driving signal supply device according to claim 1, wherein: The control circuit includes: a counter configured to count the plurality of oscillation signals to generate a plurality of count values; a logic circuit configured to determine a process corner based on the plurality of count values; and The control signal generator is configured to generate a control signal based on the process corner.

3. The driving signal supply device according to claim 2, wherein: The driving signal of the semiconductor device is an internal voltage to be supplied to the semiconductor device, and The logic circuit is configured as follows: The process corner is determined based on two or more reference values ​​for classifying the type of the process corner and the plurality of count values.

4. The driving signal supply device according to claim 3, wherein: The logic circuit is configured as: calculating an average count value by averaging the plurality of count values; and The process angle is determined based on a result of comparing the average count value with the two or more reference values.

5. The driving signal supply device according to claim 4, wherein: The two or more reference values ​​include a first reference value and a second reference value, The logic circuit is configured to determine that the process corner is of the first type when the average count value is less than a first reference value, and The control signal generator is configured to increase a voltage level of the internal voltage when it is determined that the process corner is of the first type.

6. The driving signal supply device according to claim 5, wherein: After increasing the voltage level of the internal voltage, the drive signal generating circuit supplies the internal voltage having the increased voltage level to the oscillation circuit, The oscillator circuit outputs a plurality of second oscillation signals, and The control circuit determines the process angle of the semiconductor device again based on the plurality of second oscillation signals to generate a control signal.

7. The driving signal supply device according to claim 5, in, The logic circuit is configured to determine that the process corner is a second type when the average count value is greater than or equal to a first reference value and when the average count value is less than a second reference value, and The control signal generator is configured to maintain a voltage level of the internal voltage when the process corner is determined to be of the second type.

8. The driving signal supply device according to claim 2, wherein: The driving signal of the semiconductor device is an internal clock signal to be provided to the semiconductor device, and The logic circuit is configured to determine the process angle based on a result of comparing the plurality of count values ​​with each other.

9. The driving signal supply device according to claim 8, wherein: The plurality of oscillators include: A first oscillator configured to output a first oscillation signal; A second oscillator configured to output a second oscillation signal; and A third oscillator is configured to output a third oscillation signal. wherein each inverter included in the first oscillator has a first ratio of channel widths, each inverter included in the second oscillator has a second ratio of channel widths, and each inverter included in the third oscillator has a third ratio of channel widths, wherein the second ratio of the channel widths is greater than the first ratio of the channel widths, and the third ratio of the channel widths is greater than the second ratio of the channel widths, and The logic circuit is configured to determine the process angle based on a result of comparing the frequency of the first oscillation signal, the frequency of the second oscillation signal, and the frequency of the third oscillation signal.

10. The driving signal supply device according to claim 9, wherein: The counters are configured as: counting the first oscillation signal to generate a first count value; counting the second oscillation signal to generate a second count value; and counting the third oscillation signal to generate a third count value, and The logic circuit compares the frequency of the first oscillation signal with the frequency of the second oscillation signal by comparing the first count value with the second count value.

11. The driving signal supply device according to claim 10, wherein: When the frequency of the first oscillation signal is higher than the frequency of the second oscillation signal, the logic circuit determines that the process corner is of the first type, and The control signal generator is configured to reduce a duty cycle of the internal clock signal when it is determined that the process corner is of the first type.

12. The driving signal supply device according to claim 11, wherein: When the first count value is greater than the second count value, the logic circuit determines that the process corner is of the first type.

13. The driving signal supply device according to claim 9, wherein: When the frequency of the third oscillation signal is higher than the frequency of the second oscillation signal, the logic circuit determines that the process corner is of the second type, and The control signal generator is configured to increase the duty cycle of the internal clock signal when it is determined that the process corner is of the second type.

14. The driving signal supply device according to claim 9, wherein: When the frequency of the first oscillation signal is lower than or equal to the frequency of the second oscillation signal and when the frequency of the third oscillation signal is lower than or equal to the frequency of the second oscillation signal, the logic circuit determines that the process corner is a third type, and The control signal generator is configured to maintain the duty cycle of the internal clock signal when the process corner is determined to be of the third type.

15. The driving signal supply device according to any one of claims 1 to 14, wherein: Each inverter included in each of the plurality of oscillators includes a p-type metal oxide semiconductor (PMOS) transistor and an n-type metal oxide semiconductor (NMOS) transistor, wherein each inverter included in each of the plurality of oscillators has a channel width ratio, the channel width ratio being a ratio of a channel width of the PMOS transistor to a channel width of the NMOS transistor, and wherein a ratio of channel widths of each inverter included in one of the plurality of oscillators is different from a ratio of channel widths of each inverter included in another of the plurality of oscillators.

16. A method for calibrating a drive signal, the method comprising: outputting a plurality of oscillation signals through an oscillation circuit, the oscillation circuit comprising a plurality of oscillators, each oscillator comprising an inverter, wherein a switching characteristic of each inverter included in one of the plurality of oscillators is different from a switching characteristic of each inverter included in another of the plurality of oscillators; detecting a process corner of a semiconductor device based on the plurality of oscillation signals; and A driving signal of a semiconductor device is calibrated based on a process corner.

17. The method according to claim 16, wherein: The steps for detecting process corners include: counting the plurality of oscillation signals to generate a plurality of count values; and A process angle is determined based on the plurality of count values.

18. The method according to claim 17, wherein: The steps to determine the process angle include: calculating an average count value by averaging the plurality of count values; and The process corner is identified based on the average count value and two or more reference values ​​for classifying the type of the process corner.

19. The method according to claim 17, wherein: The step of outputting the plurality of oscillation signals comprises: outputting a first oscillation signal, a second oscillation signal and a third oscillation signal, and The step of determining the process angle includes: identifying the process angle based on a result of comparing the frequency of the first oscillation signal, the frequency of the second oscillation signal, and the frequency of the third oscillation signal.

20. A driving signal supply device, comprising: an oscillation circuit including a plurality of oscillators each including an inverter and configured to output a plurality of oscillation signals, wherein a switching characteristic of each inverter included in one of the plurality of oscillators is different from a switching characteristic of each inverter included in another of the plurality of oscillators; a control circuit configured to perform a comparison operation based on the plurality of oscillation signals to generate a control signal; and The drive signal generating circuit is configured to generate a drive signal for the semiconductor device based on the control signal.

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