Clock frequency divider, clock frequency dividing method and system on chip
By designing a clock divider with dynamic gated and glitch-free switching functions, the increase in power consumption and frequency-dividing ratio switching caused by the clock divider circuit in the prior art is solved. Signal abnormality problem, achieving lower power consumption and more stable clock signal output.
Patent Information
- Application Number
- CN202310966607.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-02
- Publication Date
- 2025-02-14
AI Technical Summary
The clock frequency division circuit of existing chip systems still operates when no clock signal is needed, resulting in increased power consumption and easy to generate glitches during frequency division ratio switching, affecting the stability of the chip.
A clock divider is designed, including a driving clock input, a frequency-dividing ratio input, a gated input and a clock output. The enablement and disabling of the clock divider is controlled through a gated signal, and switching in the frequency-dividing ratio. The output target clock signal is switched to the target clock signal corresponding to the new frequency division ratio after the current signal period is over.
It is realized that the driving clock of the clock divider circuit is turned off when no clock signal is needed, which reduces power consumption, and avoids signal abnormalities during frequency division switching through glitch-free processing, and improves the stability of the chip.
Smart Images
Figure CN119449017A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a clock divider, and more particularly to a circuit, method and related on-chip system for performing frequency division processing on a clock signal. Background Art
[0002] The operation of existing chip systems usually requires multiple clock specifications, and therefore includes complex clock circuit structures to achieve multiple clock specifications to ensure the smooth operation of the chip system. For example, the system clock frequency required by the chip may be different when performing different tasks, and the working clock frequencies of different module resources of the chip may also be different at the same time. Generally, the main clock is divided into different frequencies by a frequency division circuit inside the chip to generate clock signals of different frequencies, which are provided to different tasks and modules. The quality of the clock signal generated by the frequency division circuit has a great impact on the working function and performance of the chip.
[0003] There is therefore a need for improved techniques for clock division. Summary of the invention
[0004] One of the objects of the present disclosure is to provide a clock divider.
[0005] According to one aspect of the present application, a clock divider is provided, comprising: a driving clock input terminal for receiving a driving clock signal; a division ratio input terminal for receiving a division ratio signal; a gating input terminal for receiving a gating signal; a clock output terminal for outputting a target clock signal; a first processing module, configured to process the driving clock signal according to the division ratio signal when the gating signal indicates that the clock divider is enabled, so as to generate a target clock signal corresponding to the division ratio signal; and a second processing module, configured to stop the operation of the first processing module when the gating signal indicates that the clock divider is disabled.
[0006] In one embodiment of the present application, the second processing module is configured to process a gating signal and a driving clock signal, so that when the gating signal indicates to disable the clock divider, the input of the first processing module is switched to an invalid level signal at an invalid level of the output target clock signal.
[0007] In one embodiment of the present application, the clock divider also includes a third processing module. When the division ratio signal indicates a change from the first division ratio to the second division ratio, the third processing module is configured to switch the output target clock signal to the target clock signal corresponding to the second division ratio generated by the first processing module after the current signal cycle ends.
[0008] In one embodiment of the present application, when the frequency division ratio signal indicates that the frequency division ratio is changed to 1, the third processing module is configured to switch the output target clock signal to the driving clock signal after the current signal cycle ends.
[0009] In one embodiment of the present application, the clock divider further includes a fourth processing module for asynchronously processing the driving clock signal and the division ratio signal.
[0010] In one embodiment of the present application, the clock divider further includes a fifth processing module for asynchronously processing the driving clock signal and the gating signal.
[0011] In one embodiment of the present application, the maximum division ratio of the clock divider depends on the bit width of the first processing module and the division ratio signal is between one and the maximum division ratio.
[0012] According to one aspect of the present application, a clock division method is provided, comprising: receiving a driving clock signal; receiving a division ratio signal; receiving a gating signal; when the gating signal indicates enable, processing the driving clock signal according to the division ratio signal to output a target clock signal corresponding to the division ratio signal; and when the gating signal indicates disable, stopping processing the driving clock signal.
[0013] In one embodiment of the present application, the method further includes: processing a gating signal and a driving clock signal so that when the gating signal indicates disabling, the received driving clock signal is switched to an invalid level signal at an invalid level of the output target clock signal.
[0014] In one embodiment of the present application, the method further includes: when the division ratio signal indicates a change from a first division ratio to a second division ratio, processing the division ratio signal and the driving clock signal so that the output target clock signal switches to the target clock signal corresponding to the second division ratio after the current signal cycle ends.
[0015] In one embodiment of the present application, the method further includes: when the frequency division ratio signal indicates that the frequency division ratio is changed to one, causing the output target clock signal to switch to the driving clock signal after the current signal cycle ends.
[0016] In one embodiment of the present application, the method further includes: asynchronously processing the driving clock signal and the frequency division ratio signal.
[0017] In one embodiment of the present application, the method further includes: asynchronously processing the driving clock signal and the gating signal.
[0018] According to another aspect of the present application, a system on chip is provided, comprising the clock divider as described above.
[0019] Other characteristic features and advantages of the present application will become apparent from the following description with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The included drawings are for illustrative purposes and are only used to provide examples of possible structures and arrangements of the inventive apparatus disclosed herein and methods of applying the same to computing devices. These drawings in no way limit any changes in form and detail that may be made to the embodiments by those skilled in the art without departing from the spirit and scope of the embodiments. The embodiments will be more easily understood through the following detailed description in conjunction with the accompanying drawings, in which like reference numerals represent similar structural elements.
[0021] Figure 1 A schematic diagram of a clock divider according to an embodiment of the present application is shown.
[0022] Figure 2 A schematic diagram of an implementation of a clock divider according to an embodiment of the present application is shown.
[0023] Figure 3 A timing diagram of signals processed by a clock divider according to an embodiment of the present application is shown.
[0024] Figure 4 A schematic diagram of an implementation of a clock divider according to an embodiment of the present application is shown.
[0025] Figure 5 A schematic diagram showing an implementation of a processing module of a clock divider according to an embodiment of the present application is shown.
[0026] Figure 6 A schematic diagram showing an implementation of a circuit for performing asynchronous processing of a clock divider according to an embodiment of the present application is shown.
[0027] Figure 7 A schematic diagram showing another implementation of a circuit for performing asynchronous processing of a clock divider according to an embodiment of the present application is shown.
[0028] Figure 8 A flow chart of a clock frequency division method according to an embodiment of the present application is shown.
[0029] Note that in the embodiments described below, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same functions, and their repeated descriptions are omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.
[0030] For ease of understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like sometimes do not represent actual positions, sizes, and ranges, etc. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges, etc. disclosed in the drawings and the like. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show details of specific components. DETAILED DESCRIPTION
[0031] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.
[0032] The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the present disclosure and its application or use. That is, the circuit structures herein are shown in an exemplary manner to illustrate different embodiments of the present disclosure, and are not intended to be limiting. Those skilled in the art will understand that they are merely exemplary ways that can be used to implement the present application, rather than exhaustive ways.
[0033] Technologies, methods, and apparatus known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, such technologies, methods, and apparatus should be considered part of the authorization specification.
[0034] As mentioned above, the clock circuit is very important for the operation of the chip system. Generally, multiple clock signals are provided to the chip system by clock division. Clock division is to convert the same clock signal into clock signals of different frequencies through a certain circuit structure. For example, the four-frequency division can be achieved in the following way. Through the circuit structure with frequency division function, when the clock triggers four cycles, the circuit outputs a periodic signal. For example, a pulse clock can be used to trigger a counter. The counter is reset once and outputs a pulse every time it counts four numbers. In this way, the four-frequency division function can be achieved.
[0035] The circuit used for clock frequency division is closely related to the structure, scale, performance and power consumption of the internal circuit of the chip. Generally speaking, when the circuit performance requirements are met, low-frequency clocks are used as much as possible to save power consumption. Power consumption is very important for circuit performance. In the prior art, when the clock signal is not needed in a certain period of time, the output clock signal provided is usually turned off by a gating signal on the output side of the clock circuit. In this case, the input side of the clock frequency division circuit is still receiving the driving clock signal, and the driving clock signal is still processed inside the clock frequency division circuit, but the target clock signal output on the output side is turned off. Therefore, the clock frequency division circuit is still running at this time, which is disadvantageous from the perspective of saving power consumption. Moreover, as a common situation, when the signal processed by the clock circuit is a high-frequency signal, the power consumption of the clock circuit will greatly increase the standby power consumption of the chip, so it is very worthy of discussion.
[0036] On the other hand, as the application requirements change, dynamically adjusting the clock output frequency through software control or adaptive control is a common requirement for clock circuits. When switching the frequency division ratio, the clock circuit of the prior art usually generates glitches in the output signal of the clock circuit. As a clock signal, the glitches will introduce noise into the subsequent signal, causing abnormal chip operation. This is very detrimental to the stable operation of the chip.
[0037] The present application proposes a clock divider, a clock division method and a system on chip including the clock divider. The clock divider according to an embodiment of the present application can be implemented with an extremely low-cost circuit structure and can output a desired divided clock signal very flexibly.
[0038] According to an embodiment of the present application, the clock divider can support dynamic gating. When the output clock signal is not needed, the driving clock of the entire divider is also turned off. This not only ensures that the circuit driven by the generated divided clock will not flip, but also ensures that the clock divider circuit itself will not flip, thereby reducing power consumption to the optimum. When processing high-frequency clock signals in general, the power consumption of the clock circuit saved by the technical solution of an embodiment of the present application is very considerable.
[0039] According to an embodiment of the present application, a clock divider can support dynamic configuration of the frequency division ratio. When the frequency division ratio is switched dynamically, the output target clock signal will not be interrupted, and the desired clock signals of different frequencies can be switched without glitch processing. Through glitch-free processing, the clock divider according to an embodiment of the present application will not cause abnormalities in the effective pulse width of the output divided clock when the frequency division ratio is switched or the gating signal is switched. In addition, according to an embodiment of the present application, a clock divider can not only support two or more frequency divisions, but also support one frequency division, which enriches the function of the circuit and can meet the needs of one frequency division.
[0040] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
[0041] Figure 1 A schematic diagram of a clock divider according to an embodiment of the present application is shown. A clock divider 100 according to an embodiment of the present application may include a drive clock input terminal 101 for receiving a drive clock signal. The drive clock signal may be a master clock signal of a chip system. The drive clock signal may have any suitable frequency. The clock divider 100 may also include a frequency division ratio input terminal 102 for receiving a frequency division ratio signal. Even frequency division and odd frequency division may be requested through the frequency division ratio signal. According to an embodiment of the present application, one or more of a plurality of frequency division modes may be implemented through different implementations.
[0042] The clock divider 100 may further include a gating input terminal 103 for receiving a gating signal, and a clock output terminal 104 for outputting a target clock signal.
[0043] As mentioned above, when the clock signal is not needed in a certain period of time, in order to save power consumption, the clock divider can be shut down by a gating signal. When the clock signal is needed, the clock divider can be enabled by a gating signal to provide a clock signal of the desired frequency through clock division processing.
[0044] The clock divider 100 may further include a first processing module 105, which is configured to process the driving clock signal according to the frequency division ratio signal when the gating signal indicates that the clock frequency division circuit is enabled, so as to generate a target clock signal corresponding to the frequency division ratio signal for output at the clock output terminal 104. The clock divider 100 may further include a second processing module 106, which is configured to stop the operation of the first processing module 105 when the gating signal indicates that the clock frequency division circuit is disabled.
[0045] The first processing module 105 can be implemented in any suitable manner, and one or more implementations of the first processing module 105 will be described in detail with reference to the accompanying drawings. Those skilled in the art will understand that the first processing module 105 can be implemented in any suitable manner known in the art or that may appear in the future as needed. The subsequent specific implementations of the first processing module 105 are only exemplary and are not intended to limit the scope of the present disclosure.
[0046] In one embodiment of the present disclosure, when the output clock signal is not needed, the operation of the first processing module 105 is stopped by the second processing module 106, instead of just shutting off the generated target clock signal at the output terminal. This at least saves the power consumption required for the operation of the first processing module 105. When the processed driving clock signal is a high-frequency signal, the power consumption saved will be considerable.
[0047] In one embodiment according to the present disclosure, the second processing module 106 may be a module that implements the following functions: processing the gating signal and the driving clock signal, so that when the gating signal indicates that the clock divider is disabled, the input of the first processing module 105 is switched to an invalid level signal at the invalid level of the output target clock signal. For example, when the high level signal or the rising edge is a valid signal, the input of the first processing module 105 may be switched to a low level signal at the low level of the output target clock signal. The following description will be made with the high level signal or the rising edge as the valid signal. In this embodiment, since the input of the first processing module 105 is switched to a low level signal, the first processing module 105 will no longer process the driving clock signal according to the frequency division ratio signal, for example, by flipping the driving clock signal to generate the desired target clock signal, which saves power consumption. Moreover, the input of the first processing module 105 is switched to a low level at the low level of the output target clock signal, which avoids the target clock signal from being abnormally output as a high level, and ensures that the pulse width of the high level meets the operation of the frequency division ratio switching.
[0048] Those skilled in the art will appreciate that the function of stopping the operation of the first processing module may be achieved by any suitable means known in the art or that may appear in the future. The above is merely exemplary and is not intended to limit the scope of the present disclosure.
[0049] return Figure 1In one embodiment of the present disclosure, the clock divider may further include a third processing module 107. When the frequency division ratio signal indicates a change from the first frequency division ratio to the second frequency division ratio, the first processing module 105 processes the driving clock signal according to the second frequency division ratio signal to generate a target clock signal corresponding to the second frequency division ratio. The third processing module 107 may process the frequency division ratio signal and the driving clock signal so that the output target clock signal switches to the target clock signal corresponding to the second frequency division ratio after the current signal cycle ends. This can effectively avoid abnormal effective pulse widths in the output target signal. In the following reference Figure 3 The signal timing diagram is further explained.
[0050] In one embodiment of the present disclosure, when the division ratio signal indicates that the division ratio changes to one, the target clock signal to be output is the driving clock signal, and the first processing module 105 is configured to send the driving clock signal to the third processing module 107, and the third processing module 107 is configured to make the output target clock signal switch to the driving clock signal after the current signal cycle ends.
[0051] Supporting a frequency division of one can enrich the functions of the clock frequency divider. Moreover, the third processing module realizes a glitch-free switching between a driving clock signal corresponding to a frequency division ratio of one and a target clock signal corresponding to other frequency division ratios.
[0052] In one embodiment of the present disclosure, the maximum division ratio of the clock divider depends on the bit width of the first processing module, and the division ratio signal input through the division ratio input terminal is between 1 and the maximum division ratio.
[0053] In addition, the present application takes into account that the clock domain of the input signals of the clock divider, such as the division ratio signal and the gating signal, may be asynchronous with the clock domain of the driving clock signal of the clock divider, or the clock domain of the division ratio signal and the gating signal may be synchronous with the clock domain of the driving clock signal of the clock divider but at different frequencies. When asynchronous, the division ratio signal and the gating signal need to be processed asynchronously with the driving clock signal. For the case of synchronization but different frequencies, in order to facilitate subsequent processing, such as convergence timing during layout and routing in subsequent processes, especially when the driving clock signal is at high frequency, such as when the driving clock signal exceeds 1GHz, asynchronous processing is also performed.
[0054] In one embodiment of the present disclosure, the clock divider may further include a fourth processing module 108 for asynchronously processing the drive clock signal and the frequency division ratio signal. In one embodiment of the present disclosure, the clock divider may further include a fifth processing module 109 for asynchronously processing the drive clock signal and the gating signal. Figure 6 and Figure 7 Details modules for asynchronous processing.
[0055] Those skilled in the art will understand that the third processing module 107, the fourth processing module 108, and the fifth processing module 109 described above may be optional. According to one or more embodiments of the present disclosure, one or more of the third processing module 107, the fourth processing module 108, and the fifth processing module 109 may be included, or one or more of the third processing module 107, the fourth processing module 108, and the fifth processing module 109 may not be included.
[0056] In one embodiment of the present disclosure, a processing module or one or more functions of a processing module can be selected through parameter configuration. For example, two configuration parameters can be set: a gating support parameter GATE_TYPE and a frequency division ratio support parameter SUPPORT_DIV1. The following four frequency dividers can be configured through these two parameters: support gating and support 1-N frequency division ratio, support gating and support 2-N frequency division ratio, do not support gating and support 1-N frequency division ratio, do not support gating and support 2-N frequency division ratio, where N is the maximum frequency division ratio. The desired configuration can be achieved through parameters. The clock divider selected through parameter configuration can achieve gating and frequency division ratio control through the input signal to output the target clock signal without burrs.
[0057] One or more embodiments of the present disclosure will be described below in conjunction with specific circuit structures and signal timing diagrams. Those skilled in the art will understand that the described circuit structures are merely exemplary, and one or more parts of the clock divider of the present disclosure may be implemented in any suitable manner known in the art or that may appear in the future.
[0058] Figure 2 A schematic diagram of an implementation of a clock divider according to an embodiment of the present application is shown. Figure 2 The circuit shown can be implemented by configuring the gating support parameter GATE_TYPE to 1 and the divide-by-one support parameter SUPPORT_DIV1 to 0. Figure 2 The circuit shown supports gating and supports a 2-N frequency division ratio. The circuit includes an input terminal div_num for receiving a frequency division ratio signal. As mentioned above, the frequency division input terminal div_num can have online software configurability, and the frequency division ratio can be dynamically changed at any time. For example, the frequency division ratio can be dynamically input through software. Figure 2 The circuit shown also includes an input terminal clk for receiving a driving clock signal. The driving clock signal may come from a main clock signal of the circuit. Figure 2 The circuit shown further includes an input terminal clk_en for receiving a gating signal. Figure 2 The circuit shown also includes an input terminal rstn for performing a reset operation on the circuit.
[0059] Figure 2 The embodiment may further include a module CK_Divn (n≥2). When the gating signal from the input terminal clk_en indicates that the clock frequency division circuit is enabled, the module CK_Divn (n≥2) processes the driving clock signal from the input terminal clk according to the frequency division ratio signal from the input terminal div_num to generate a target clock signal corresponding to the frequency division ratio signal for output at the clock output terminal clk_out. For example, when the gating signal is at a high level, it indicates that the clock frequency division circuit is enabled. In this example, according to the frequency division ratio signal from the frequency division ratio input terminal div_num, for example, the frequency division ratio signal can indicate that a frequency division of four is performed, and the driving clock signal is processed by a frequency division of four to obtain a target clock signal, which is output to the clock output terminal clk_out. Those skilled in the art will understand that the frequency division process can be performed in any suitable manner known in the art or that may appear in the future.
[0060] Figure 2 The embodiment may further include a module Gen_GateEn and a module CK_GT. The module Gen_GateEn receives a gating signal from an input terminal clk_en and a driving clock signal from an input terminal clk. The module CK_GT receives a driving clock signal from an input terminal clk and a signal Gate_en processed by the module Gen_GateEn, and sends the gated_clk signal to the module CK_Divn (n≥2) after processing. When the gating signal indicates that the clock frequency division circuit is enabled, the gated_clk signal may be an enabled driving clock signal, and the module CK_Divn (n≥2) may be used to process the gated_clk signal according to the division ratio signal to generate a target clock signal corresponding to the division ratio signal. When the gating signal indicates that the clock frequency division circuit is disabled, the gated_clk signal may be a turned-off driving clock signal, for example, the driving clock signal is adjusted to a low level signal, and the module CK_Divn (n≥2) will stop operating. That is, in Figure 2 In the circuit structure, the module Gen_GateEn and the module CK_GT realize the function of stopping processing the driving clock signal to generate the target clock signal when the gating signal indicates to disable the clock frequency division circuit. This realizes dynamic gating. When the output clock signal is not needed, the driving clock of the entire clock frequency division circuit is turned off. This not only ensures that the circuit driven by the generated frequency division clock will not flip, but also ensures that the clock frequency division circuit itself will not flip, thereby reducing the power consumption to the optimum. In the case of high frequency driving clock signal, for example, when the driving clock signal exceeds 1GHz, the power consumption saved will be considerable.
[0061] In order to avoid abnormality of the output target clock signal, when the gate signal indicates disable, the module Gen_GateEn and the module CK_GT are processed to switch the input of the module CK_Divn (n≥2), such as the gated_clk signal, to a low level signal at the low level of the output target clock signal clk_out. This will avoid turning off the gated_clk signal when the output target clock signal clk_out is at a high level, so that the output target clock signal clk_out is abnormally high.
[0062] exist Figure 1 The second processing module 106 according to one embodiment of the present application can be implemented as Figure 3 Module Gen_GateEn and module CK_GT in the embodiment shown. The following will be further described with reference to the timing diagram. In this article, a high level signal is used as an example for description as a valid signal. Those skilled in the art will understand that the technical solution to be protected by this application is also applicable to the case where a low level or falling edge signal is a valid signal.
[0063] In one embodiment of the present disclosure, when the frequency division ratio signal indicates a change from the first frequency division ratio to the second frequency division ratio, the module CK_Divn (n≥2) can process the frequency division ratio signal and the drive clock signal so that the output target clock signal is switched to the target clock signal corresponding to the second frequency division ratio after the current signal cycle ends. This can avoid glitches in the output target clock signal or abnormalities in the effective pulse width.
[0064] exist Figure 1 The first processing module 105 and the third processing module 107 according to one embodiment of the present application can be implemented as Figure 3 The module CK_Divn (n≥2) in the illustrated embodiment will be described in detail below in conjunction with the signal timing diagram.
[0065] Figure 3 A timing diagram of signals processed by a clock divider according to an embodiment of the present application is shown. The figure shows a division ratio signal, a gating signal, a drive clock signal, a processed drive clock signal, and a target clock signal. At time t1, the division ratio signal changes, for example, it can be changed from a two-division before time t1 to a six-division after time t1. At time t1, the drive clock signal is at a high level, and the output target clock signal is also at a high level. If the target clock signal is switched at time t1, a pulse width abnormality will occur. In order to avoid glitches in the output clock signal, it can be achieved by, for example Figure 1 The third processing module 107 shown in FIG. 1 or for example in FIG. Figure 2The part of the module CK_Divn (n≥2) shown in the figure processes the frequency division ratio signal and the driving clock signal so that the output target clock signal is switched to the target clock signal corresponding to the second frequency division ratio after the current signal cycle ends. That is, the output target clock signal is not switched at time t1, but after the current signal cycle of the target clock signal ends, that is, at t2, the output is switched to the target clock signal divided by 6.
[0066] At t3, the gate signal changes from the enabled state to the disabled state, and the output target clock signal is at a high level. If the drive clock signal is turned off at t3, the target clock signal will remain high, resulting in signal abnormality. To avoid abnormality, for example, Figure 1 The second processing module shown in or for example in Figure 2 The modules Gen_GateEn and CK_GT shown in FIG. 1 process the gate signal and drive the clock signal, so that when the gate signal indicates disable, at the low level of the output target clock signal, Figure 3 As shown in the figure, it is time t4. Figure 1 The input of the first processing module 105 shown in or Figure 2 The input of the module CK_Divn (n ≥ 2) shown in Figure 2 It is shown as gated_clk, which switches to a low level signal, and then Figure 1 The first processing module 105 shown in Figure 2 The module CK_Divn (n≥2) shown stops processing operation, which causes the output target clock signal to remain low.
[0067] Through such processing, the clock frequency division circuit can be dynamically gated, and when the output clock signal is not needed, the driving clock of the entire frequency division circuit is turned off. That is to say, it is not just to turn off the generated target clock signal at the output end so that the circuit driven by the frequency division clock will not flip, but to turn off the driving clock of the frequency division circuit to ensure that the clock frequency division circuit itself does not flip, thereby reducing power consumption to the optimum. At the same time, by selecting the shutdown time, the output target clock signal is avoided from being abnormal.
[0068] Figure 4 A schematic diagram of an implementation of a clock divider according to an embodiment of the present application is shown. For example, Figure 4 The circuit shown can be implemented by configuring the gating support parameter GATE_TYPE to 1 and the divide-by-one support parameter SUPPORT_DIV1 to 1. Figure 4 The circuit shown supports gating as well as 1-N division ratio, where N is the maximum division ratio. Figure 4 The circuit shown is Figure 2 The circuits shown are similar and to avoid duplication of description only the different parts are described here.
[0069] and Figure 2 The circuit shown is different. Figure 4 The circuit shown also includes a module CK_DIV1 and a module CK_SWITCH. Figure 1 A portion of the first processing module 105 shown in FIG. 1 can be implemented as a module CK_DIV1, Figure 1 A portion of the third processing module 107 shown in FIG. 1 may be implemented as a module CK_SWITCH.
[0070] When the frequency division ratio signal from the input terminal div_num indicates that the frequency division ratio is changed to one, the module CK_DIV1 sends the driving clock signal to the module CK_SWITCH, and the module CK_SWITCH can perform a clock selection operation to switch the currently outputted target clock signal to the driving clock signal without burrs. In one embodiment, when the frequency division ratio signal indicates that the frequency division ratio is changed to one, the module CK_DIV1 sends the driving clock signal to the module CK_SWITCH, and the module CK_SWITCH causes the outputted target clock signal to switch to the driving clock signal after the current signal cycle ends.
[0071] When the division ratio signal from the input terminal div_num indicates that the division ratio changes from 1 to other division ratios, the module CK_Divn (n≥2) sends the clock signal corresponding to the current division ratio to the module CK_SWITCH. The module CK_SWITCH can perform a clock selection operation to switch the target clock signal to the clock signal corresponding to the current division ratio without burrs.
[0072] That is, the module CK_SWITCH performs clock selection between the driving clock signal and the divided clock signal, so that the circuit outputs the target clock signal corresponding to the current frequency division ratio signal without glitches.
[0073] Figure 5 A schematic diagram of an implementation of a processing module of a clock divider according to an embodiment of the present application is shown. For example, Figure 4 The module CK_SWITCH in can be implemented as Figure 5 The circuit structure shown in FIG. Figure 5 The clk_in0 and clk_in1 in the circuit can receive Figure 4The output of module CK_Divn (n≥2) and the output of module CK_DIV1 are combined to perform clock selection between the output of module CK_Divn (n≥2) and the output of module CK_DIV1 when the division ratio signal from the input terminal div_num indicates that the division ratio is changed to one or from one to other division ratios, so that the target clock signal can be output without glitches.
[0074] Those skilled in the art will understand that the above are only examples, and the clock signal may be selected by any suitable method known in the art or that may appear in the future to output the desired target clock signal without glitches.
[0075] As mentioned above, in order to facilitate subsequent processing, when the division ratio signal and the gating signal of the clock divider are asynchronous or synchronous but different in frequency with the driving clock signal of the clock divider, the division ratio signal and the driving clock signal can be processed asynchronously, or the gating signal and the driving clock signal can be processed asynchronously.
[0076] Figure 6 A circuit for asynchronously processing a gating signal and a driving clock signal in a clock divider according to an embodiment of the present application is shown. The circuit may include an input terminal clk_en_in for receiving a gating signal to be asynchronously processed. The circuit may also include an input terminal clk for receiving a driving clock signal. The circuit may also include a reset signal input terminal rst_n. After two-level or three-level synchronization, the gating signal after asynchronous processing is output at the output terminal clk_en.
[0077] Figure 7 A circuit for asynchronously processing a frequency division ratio signal and a driving clock signal in a clock divider according to an embodiment of the present application is shown. The circuit may include an input terminal div_num_en_in and an input terminal div_num_in for receiving a frequency division ratio signal to be asynchronously processed. The circuit may also include an input terminal clk for receiving a driving clock signal. The circuit may also include a reset signal input terminal rst_n. The flip edge of the signal at the input terminal div_num_en_in indicates that the signal at the input terminal div_num_in is updated and stable, so the asynchronous processing circuit first synchronizes the input terminal div_num_en_in signal by two to three levels, and then performs an XOR judgment with the signal after the first-level synchronization to generate an enable pulse, and the enable pulse is used to latch the div_num_in signal, and the output after latching is div_num.
[0078] Those skilled in the art will understand that when the gate control signal and the frequency division ratio signal are in the same clock domain as the driving clock signal of the frequency division circuit, the asynchronous processing may not be performed. Those skilled in the art will understand that the above is only an example, and the above asynchronous processing may be performed in any suitable manner known in the art or that may appear in the future.
[0079] Figure 8 A flow chart of a clock frequency division method according to an embodiment of the present application is shown. One or more steps of the clock frequency division method can be implemented by the clock frequency divider or clock frequency division circuit as described above.
[0080] like Figure 8 As shown, in step 801, a driving clock signal is received. In step 802, a frequency division ratio signal is received. In step 803, a gating signal is received. In step 804, when the gating signal indicates enable, the driving clock signal is processed according to the frequency division ratio signal to output a target clock signal corresponding to the frequency division ratio signal; and when the gating signal indicates disable, the driving clock signal is stopped from being processed. By stopping the processing of the driving clock signal instead of shutting down the generated target clock signal, power consumption can be saved. When the processed driving clock signal is a high-frequency signal, the power consumption saved is considerable.
[0081] In one embodiment of the present application, stopping processing the driving clock signal includes: processing a gating signal and a driving clock signal, so that when the gating signal indicates disablement, the received driving clock signal is switched to an invalid level signal at an invalid level of the output target clock signal. This can prevent the target clock signal from abnormally maintaining a valid level and causing a malfunction.
[0082] In one embodiment of the present application, the method may further include the following steps: when the frequency division ratio signal indicates a change from the first frequency division ratio to the second frequency division ratio, the frequency division ratio signal and the drive clock signal are processed so that the output target clock signal is switched to the target clock signal corresponding to the second frequency division ratio after the current signal cycle ends. In one embodiment of the present application, the method may further include the following steps: when the frequency division ratio signal indicates a change from the first frequency division ratio to the second frequency division ratio, the output target clock signal is switched to the drive clock signal after the current signal cycle ends. This can avoid glitches or abnormal effective pulse widths in the target clock signal when the frequency division ratio is switched.
[0083] In one embodiment of the present application, the method may further include the following steps: asynchronously processing the drive clock signal and the frequency division ratio signal. In one embodiment of the present application, the method may further include the following steps: asynchronously processing the drive clock signal and the gating signal. By asynchronously processing the drive clock signal and the frequency division ratio signal or asynchronously processing the drive clock signal and the gating signal, it is beneficial to converge the timing during layout and routing in subsequent processes, so that the circuit performance is optimized.
[0084] According to another aspect of the present application, a system on chip is provided, comprising the clock divider as described above.
[0085] The clock divider, clock division method and system on chip disclosed in the present invention are described above in conjunction with specific embodiments. However, it should be understood that any feature of any embodiment may be combined and / or replaced with any other feature of any other embodiment.
[0086] Aspects of the present disclosure may be implemented in various electronic devices. Examples of electronic devices may include, but are not limited to, consumer electronic products, components of consumer electronic products, electronic test equipment, cellular communication infrastructure such as base stations, etc. Examples of electronic devices may include, but are not limited to, mobile phones such as smart phones, wearable computing devices such as smart watches or headphones, phones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), microwave ovens, refrigerators, in-vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, CD players, digital music players such as MP3 players, radios, portable cameras, cameras such as digital cameras, portable memory chips, washing machines, dryers, washing machines / dryers, peripheral devices, clocks, etc. In addition, electronic devices may include incomplete products.
[0087] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.
[0088] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.
[0089] Although some specific embodiments of the present application have been shown in detail by example, it will be appreciated by those skilled in the art that the above examples are intended to be illustrative only and do not limit the scope of the present application. It will be appreciated by those skilled in the art that the above embodiments can be modified without departing from the scope and essence of the present application. The scope of the present application is defined by the appended claims.
Claims
1. A clock divider, comprising: A driving clock input terminal, used for receiving a driving clock signal; A frequency division ratio input terminal, used for receiving a frequency division ratio signal; A gate input terminal, used for receiving a gate signal; A clock output terminal, used for outputting a target clock signal; A first processing module is configured to process the driving clock signal according to a frequency division ratio signal to generate a target clock signal corresponding to the frequency division ratio signal when a gating signal indicates to enable the clock divider; as well as The second processing module is configured to stop the operation of the first processing module when the gating signal indicates to disable the clock divider.
2. The clock divider of claim 1 , wherein the second processing module is configured to process a gating signal and a driving clock signal, so that when the gating signal indicates disabling the clock divider, the input of the first processing module is switched to an invalid level signal at an invalid level of the output target clock signal.
3. The clock divider as described in claim 1 further includes a third processing module. When the division ratio signal indicates a change from the first division ratio to the second division ratio, the third processing module is configured to switch the output target clock signal to the target clock signal corresponding to the second division ratio generated by the first processing module after the current signal cycle ends. 4 . The clock divider of claim 3 , wherein when the division ratio signal indicates that the division ratio is changed to 1, the third processing module is configured to switch the output target clock signal to the driving clock signal after a current signal cycle ends. 5 . The clock divider as claimed in claim 1 , further comprising a fourth processing module for asynchronously processing the driving clock signal and the frequency division ratio signal. 6 . The clock divider as claimed in claim 1 , further comprising a fifth processing module for asynchronously processing the driving clock signal and the gating signal. 7 . The clock divider of claim 1 , wherein a maximum division ratio of the clock divider depends on a bit width of the first processing module and a division ratio signal between 1 and a maximum division ratio.
8. A clock frequency division method, comprising: receiving a driving clock signal; receiving a frequency division ratio signal; receiving a gating signal; When the gating signal indicates enabling, processing the driving clock signal according to the frequency division ratio signal to output a target clock signal corresponding to the frequency division ratio signal; as well as When the gating signal indicates disabling, the driving clock signal is stopped from being processed.
9. The clock frequency division method according to claim 8, wherein stopping processing the driving clock signal comprises: The gating signal and the driving clock signal are processed so that when the gating signal indicates disabling, the received driving clock signal is switched to an inactive level signal at an inactive level of the output target clock signal.
10. The clock frequency division method according to claim 8, further comprising: When the frequency division ratio signal indicates a change from the first frequency division ratio to the second frequency division ratio, the frequency division ratio signal and the driving clock signal are processed so that the output target clock signal is switched to the target clock signal corresponding to the second frequency division ratio after the current signal cycle ends.
11. The clock frequency division method according to claim 8, further comprising: When the frequency division ratio signal indicates that the frequency division ratio is changed to 1, the output target clock signal is switched to the driving clock signal after the current signal cycle ends.
12. The clock frequency division method according to claim 8, further comprising: The driving clock signal and the frequency division ratio signal are processed asynchronously.
13. The clock frequency division method according to claim 8, further comprising: The driving clock signal and the gating signal are processed asynchronously.
14. A system on chip comprising the clock divider as claimed in any one of claims 1 to 7.