Circuit device and physical quantity detection device

Abstract

The invention provides a circuit device and a physical quantity detection device, which can share processing of physical quantity and processing of temperature correction operation or fault diagnosis. The circuit device (20) includes: a drive circuit (30) that drives the physical quantity transducer (10); a detection circuit (60) that detects a physical quantity on the basis of a detection signal from the physical quantity transducer (10) and outputs detection data of the physical quantity; a DSP (100) that performs digital signal processing including digital filtering processing on the detection data; a storage unit (160) that stores a program in which a plurality of commands are described; and a CPU (130) that operates on the basis of a program and performs at least one of a temperature correction operation and a failure diagnosis of the detection data.

Description

Technical Field

[0001] The present invention relates to a circuit device, a physical quantity detection device, and the like. Background Art

[0002] Patent document 1 discloses the following sensor failure prediction system: a processor generates prediction information related to a staged or continuous state until a physical quantity sensor fails based on signal information and reference information related to a measured value of a drive signal or a detection signal, thereby detecting in advance the state until a physical quantity sensor fails.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-153891

[0004] However, in the prior art of Patent Document 1, it is not clear how the prediction information of the failure and the detection signal of the physical quantity are generated, specifically by what structure of the processor. Summary of the invention

[0005] One embodiment of the present disclosure relates to a circuit device, comprising: a driving circuit that drives a physical quantity transducer; a detection circuit that detects a physical quantity based on a detection signal from the physical quantity transducer and outputs detection data of the physical quantity; a DSP that performs digital signal processing including digital filtering processing on the detection data; a storage unit that stores a program containing multiple commands; and a CPU that operates based on the program to perform at least one of temperature correction calculation and fault diagnosis on the detection data.

[0006] Furthermore, another aspect of the present disclosure relates to a physical quantity detection device including the circuit device described above and the physical quantity transducer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a configuration example of a circuit device and a physical quantity detection device according to the present embodiment.

[0008] Figure 2 This is a detailed configuration example of the circuit device and the physical quantity detection device according to the present embodiment.

[0009] Figure 3 This is a structural example of a fault detection circuit.

[0010] Figure 4 It is an example of a physical quantity transducer.

[0011] Figure 5 It is a signal waveform diagram for explaining the operation of this embodiment.

[0012] Figure 6 It is a signal waveform diagram for explaining the operation of this embodiment.

[0013] Figure 7 It is an explanatory diagram of the angular velocity dependency of the fault diagnosis result in the present embodiment.

[0014] Figure 8 This is a block diagram showing a detailed configuration example of a DSP and a CPU.

[0015] Fig. 9 This is an example of the hardware structure of a CPU.

[0016] Fig.10 It is a signal waveform diagram explaining the operation of the CPU.

[0017] Fig.11 This is a state transition diagram that explains the operation of the CPU.

[0018] Fig.12 This diagram illustrates the coordinated operation of the DSP and CPU.

[0019] Fig.13 This is a diagram illustrating the execution sequence of the DSP.

[0020] Fig.14 This is an explanatory diagram of low-pass filtering.

[0021] Fig.15 It is an explanatory diagram of notch filter processing.

[0022] Fig.16 This is a diagram for explaining user-defined filtering processing.

[0023] Fig.17 It is a diagram for explaining the operation of the CPU of the comparative example.

[0024] Fig.18 This is a diagram to explain the noise generated during the fault diagnosis cycle.

[0025] Fig.19 This is a diagram for explaining the operation of the DSP and CPU in this embodiment.

[0026] Fig. 20 This is a diagram for explaining the operating frequencies of the DSP and CPU.

[0027] Description of symbols

[0028] 5: physical quantity detection device; 10: physical quantity transducer; 11, 12: vibrating piece; 13, 14: driving electrode; 15, 16: detection electrode; 17: ground electrode; 18A, 18B, 18C, 18D: driving arm; 19A, 19B: detection arm; 20: circuit device; 21: base; 22A, 22B: connecting arm; 30: driving circuit; 32: amplifier circuit; 40: gain control circuit; 42: full-wave rectifier circuit; 44: integration circuit; 50: driving signal output circuit; 52: synchronization signal output circuit; 60: detection circuit, 61: amplifier circuit; 62, 63: Q / V conversion circuit 64: differential amplifier circuit; 65: adder circuit; 66, 67: AC amplifier circuit; 70: FLL circuit; 80: diagnostic synchronization signal generation circuit; 90, 91: synchronous detection circuit; 92, 93: filter unit; 94, 95: A / D conversion circuit; 96: synchronous detection circuit; 97: filter unit; 98: frequency division circuit; 99: A / D conversion circuit; 101: adder unit; 102: gain processing unit; 104: low-pass filter unit; 106: notch filter unit; 108: user-defined filter unit; 130: CPU; 131: low-pass filter unit; 132: temperature correction calculation unit; 133: temperature 134: zero point correction unit; 135: sensitivity correction unit; 136: addition unit; 137: gain processing unit, 138: self-diagnosis unit; 139: neural network operation unit; 140: angle calculation unit; 142: acquisition circuit; 144: command decoder; 146: operation circuit; 160: storage unit; 162: register unit; 164: non-volatile memory; 170: fault detection circuit; 180: interface circuit; 190: comb filter unit; 192: comb filter unit; 194: frequency division circuit; C1, C2: coupling capacitors; CK: clock signal; CKCP, CKDP: action clock Signal; CPQ, DPQ: data; DG: feedback signal; DQA: detection data; DQB, DQC, DQD: fault detection data; DS: drive signal; DV: signal; MCK: main clock signal; PQ: detection value; S, S1, S2: detection signal; SC, ZC: temperature correction value; SYC: synchronization signal; SYC2, SYC3: diagnostic synchronization signal; TDA: temperature data; TQ: temperature detection signal; VC: control voltage; VS1, VS2: signal; VT: threshold; f1: first frequency; f2: second frequency, fp1: first action frequency; fp2: second action frequency. DETAILED DESCRIPTION

[0029] Hereinafter, the present embodiment will be described. In addition, the present embodiment described below does not unduly limit the contents of the claims. In addition, not all of the structures described in the present embodiment are necessarily essential components.

[0030] 1. Circuit devices, physical quantity detection devices

[0031] Figure 1 The circuit device 20 and the physical quantity detection device 5 of this embodiment are shown as examples of structures. The physical quantity detection device 5 as a sensor device includes a physical quantity transducer 10 and the circuit device 20. The physical quantity detection device 5 can also be called a physical quantity measuring device. In addition, the circuit device 20 and the physical quantity detection device 5 are not limited to Figure 1 The structure can be modified in various ways, such as omitting some of its structural elements or adding other structural elements.

[0032] The physical quantity transducer 10 is an element for detecting a physical quantity, and is a vibrator as an example. When the physical quantity transducer 10 is a vibrator, the physical quantity transducer 10 has a vibrating plate, and the physical quantity is detected by the vibration of the vibrating plate. For example, when the physical quantity transducer 10 is a gyro sensor element, the angular velocity is detected as a physical quantity. As a gyro sensor element, for example, there is a sensor element having a piezoelectric vibrating plate formed by a thin plate of a piezoelectric material such as quartz. Specifically, the gyro sensor element is a sensor element having a vibrating plate of a double T-shaped, tuning fork-shaped or H-shaped shape formed by a quartz substrate such as a Z-cut. Alternatively, as a gyro sensor element, a MEMS (Micro Electro Mechanical Systems) type sensor element may also be used. In addition, the physical quantity detected by the physical quantity transducer 10 may also be a physical quantity other than angular velocity, such as angular acceleration, angle, acceleration, velocity, moving distance or pressure.

[0033] The circuit device 20 is, for example, a semiconductor circuit device, and as an example, is an integrated circuit device called an IC (Integrated Circuit). The circuit device 20 may also be called a physical quantity detection circuit. Figure 1 In the embodiment, the circuit device 20 includes a driving circuit 30 , a detection circuit 60 , a DSP (Digital Signal Processor) 100 , a CPU (Central Processing Unit) 130 , and a storage unit 160 .

[0034] The driving circuit 30 is a circuit that drives the physical quantity transducer 10. For example, the driving circuit 30 drives the physical quantity transducer 10 by outputting a driving signal DS to the physical quantity transducer 10. For example, when the physical quantity transducer 10 has a vibrating piece, the vibrating piece is driven to vibrate by the driving signal DS from the driving circuit 30. The driving signal DS is, for example, a rectangular wave signal, but may also be a sine wave signal. Taking a gyro sensor element as an example, the vibrating piece is vibrated by the driving of the driving circuit 30, and the Coriolis force is detected, thereby detecting the angular velocity.

[0035] The detection circuit 60 detects the physical quantity based on the detection signal S from the physical quantity transducer 10. For example, the detection circuit 60 detects the physical quantity based on the detection signal S and outputs the detection data DQA of the physical quantity. The detection signal S is, for example, a detection signal of the physical quantity using the drive frequency of the drive signal DS as a carrier frequency. The detection circuit 60 detects the physical quantity in the detection signal S by, for example, performing synchronous detection on a signal based on the detection signal S using a synchronization signal. The detection data DQA output by the detection circuit 60 is digital data, for example, data indicating the detection level of the detected physical quantity.

[0036] DSP 100 is a processor that performs digital signal processing. DSP 100 performs digital signal processing including digital filtering processing on the detection data DQA of the physical quantity from the detection circuit 60. Moreover, the detection data after the digital filtering processing performed by DSP 100 is output as, for example, the final detection value of the physical quantity of the physical quantity detection device 5. As digital filtering processing that DSP 100 can perform, there are various filtering processing such as low-pass filtering processing, notch filtering processing, high-pass filtering processing, band-pass filtering processing or user-defined filtering processing. In addition, the digital signal processing performed by DSP 100 is not limited to digital filtering processing, and various digital signal processing such as digital temperature compensation processing and various correction processing can be performed. DSP 100 is a digital signal processing circuit composed of hardware circuits for performing various digital signal processing.

[0037] The storage unit 160 stores a program in which a plurality of commands are recorded. The storage unit 160 is a storage circuit composed of a memory or a register circuit. In the program stored in the storage unit 160, a plurality of commands executable by the CPU 130 are recorded. The plurality of commands are a command set. Such commands include, for example, arithmetic operation commands such as addition, subtraction, immediate value addition, immediate value subtraction, comparison or immediate value comparison, shift operation commands such as right logical shift, right arithmetic shift or left logical shift, logical operation commands such as AND, OR, XOR or NOT, and transfer commands between registers and SRAMs, or various conditional branching commands. In addition, the storage unit 160 may also store information other than the program, for example, information such as filter coefficients required for digital filter processing of the DSP 100 may also be stored. In addition, the storage unit 160 may be implemented by a volatile memory such as a RAM, or by a non-volatile memory such as an EPROM, an EEPROM or a ROM, or by both a volatile memory and a non-volatile memory.

[0038] The CPU 130 operates based on the program stored in the storage unit 160. For example, the CPU 130 interprets each of the plurality of commands described in the program and performs various calculations based on the interpretation results. In addition, the CPU 130 operates based on the program in this way to perform at least one of the temperature correction calculation and fault diagnosis of the detection data of the detection circuit 60. For example, the commands described in the program are various commands for performing such temperature correction calculations and fault diagnosis. For example, the temperature correction calculation is a process of calculating the temperature correction value for the temperature compensation processing of the detection data. For example, the temperature correction calculation is a process of calculating the temperature correction value for zero point correction and the temperature correction value for sensitivity correction. The temperature compensation processing is a process of suppressing and compensating the variation of the detection value of the physical quantity caused by the temperature variation. The fault diagnosis is the diagnosis of the abnormal state of the circuit device 20 and the physical quantity detection device 5 including the circuit device 20. As the fault diagnosis, for example, there are the fault diagnosis using the electrostatic leakage component described later, the fault diagnosis using the mechanical leakage component, or the fault diagnosis of the computing unit such as the DSP 100 and the CPU 130. The CPU 130 may also include a peripheral circuit in addition to the core circuit of the CPU. As peripheral circuits, there are watchdog timer circuits, clock counters, threshold value determination circuits, and the like.

[0039] The DSP 100 and the CPU 130 are prepared as macro blocks, for example, and are laid out in the circuit device 20, which is a semiconductor IC. For example, the macro blocks of the DSP 100 and the CPU 130 are used in the circuit devices 20 and the physical quantity detection devices 5 of a plurality of products.

[0040] Thus, the circuit device 20 of the present embodiment includes: a driving circuit 30 that drives the physical quantity transducer 10; a detection circuit 60 that detects the physical quantity based on the detection signal S from the physical quantity transducer 10; a DSP that performs digital signal processing on the detection data DQA of the detection circuit 60; and a CPU 130 that operates based on the program stored in the storage unit 160 to perform temperature correction calculation and fault diagnosis of the detection data. In this way, the detection data DQA of the physical quantity in the detection circuit 60 can be subjected to digital signal processing including digital filtering processing by the DSP 100 to obtain the detection value of the physical quantity. For example, the DSP 100, which is faster than the CPU 130, can be used to output the detection value of the physical quantity with a higher throughput. On the other hand, the temperature correction calculation or fault diagnosis can be performed by the CPU 130 that operates by the program stored in the storage unit 160. For example, the temperature correction calculation or fault diagnosis with a high degree of freedom can be performed by the CPU 130 using a rewritable program. That is, it is possible to realize a circuit device 20 and a physical quantity detection device 5 that can share the processing of physical quantity and temperature correction calculation or fault diagnosis. In addition, for example, by exchanging data between the DSP 100 and the CPU 130, coordinated operation using two computing devices (DSP, CPU) can also be realized.

[0041] 2. Detailed structure example

[0042] Figure 2 Detailed configuration examples of the circuit device 20 and the physical quantity detection device 5 of this embodiment are shown. The circuit device 20 includes a drive circuit 30, a detection circuit 60, a DSP 100, a CPU 130, and a storage unit 160. In addition, the circuit device 20 may include a fault detection circuit 170 and an interface circuit 180. In addition, the circuit device 20 and the physical quantity detection device 5 are not limited to Figure 2 The structure can be modified in various ways, such as omitting some of its structural elements or adding other structural elements.

[0043] The physical quantity transducer 10 as a sensor element has vibration pieces 11, 12, drive electrodes 13, 14, detection electrodes 15, 16, and a ground electrode 17. The vibration pieces 11, 12 are, for example, piezoelectric vibration pieces formed of a thin plate of a piezoelectric material such as quartz. Specifically, the vibration pieces 11, 12 are vibration pieces formed of a Z-cut quartz substrate. In addition, the piezoelectric material of the vibration pieces 11, 12 may also be a material other than quartz, such as ceramics, silicon, etc.

[0044] The driving electrode 13 is provided with a driving signal DS from the driving circuit 30, whereby the driving vibration piece 11 vibrates. Furthermore, the feedback signal DG from the driving electrode 14 is input to the driving circuit 30. For example, the feedback signal DG based on the vibration of the vibration piece 11 is input to the driving circuit 30. Furthermore, the vibration piece 11 for driving vibrates, and the vibration piece 12 for detection vibrates, and the charge generated by the vibration is input to the detection circuit 60 from the detection electrodes 15 and 16 as the detection signals S1 and S2. Here, the ground electrode 17 is set to GND as the ground potential. Based on these detection signals S1 and S2, the circuit device 20 detects physical quantities such as angular velocity corresponding to the detection signals S1 and S2.

[0045] The driving circuit 30 includes an amplifier circuit 32 , a gain control circuit 40 , a driving signal output circuit 50 , and a synchronization signal output circuit 52 .

[0046] The amplifier circuit 32 amplifies the feedback signal DG from the physical quantity transducer 10. For example, the amplifier circuit 32 as an I / V conversion circuit converts the current feedback signal DG from the physical quantity transducer 10 into a voltage signal DV and outputs it. The amplifier circuit 32 can be implemented by an operational amplifier, a feedback resistor element, a feedback capacitor, etc.

[0047] The gain control circuit 40 outputs a control voltage VC to the drive signal output circuit 50 to control the amplitude of the drive signal DS. Specifically, the gain control circuit 40 as an AGC circuit monitors the signal DV and controls the gain of the oscillation loop. For example, in the drive circuit 30, in order to keep the sensitivity of the sensor constant, it is necessary to keep the amplitude of the drive voltage provided to the physical quantity transducer 10 constant. Therefore, a gain control circuit 40 for automatically adjusting the gain is provided in the oscillation loop of the drive vibration system. The gain control circuit 40 automatically adjusts the gain variably so that the amplitude of the feedback signal DG from the physical quantity transducer 10 is constant.

[0048] The gain control circuit 40 includes a full-wave rectifier circuit 42 and an integration circuit 44. The full-wave rectifier circuit 42 performs full-wave rectification of the AC signal DV output by the amplifier circuit 32. The integration circuit 44 performs integration processing of the signal from the full-wave rectifier circuit 42. Specifically, the integration circuit 44 performs integration processing of the signal after full-wave rectification by the full-wave rectifier circuit 42, and outputs the control voltage VC obtained by the integration processing to the drive signal output circuit 50. In this way, the control voltage VC corresponding to the DC voltage obtained by smoothing the full-wave rectified signal can be output to the drive signal output circuit 50.

[0049] The drive signal output circuit 50 outputs a drive signal DS based on the signal DV amplified by the amplifier circuit 32. The drive signal output circuit 50 outputs a rectangular wave drive signal DS such that the control voltage VC from the gain control circuit 40 becomes a voltage on the high potential side, that is, a high-level voltage. In the case where the drive signal output circuit 50 outputs a rectangular wave drive signal DS like this, the drive signal output circuit 50 can be implemented by a comparator or the like. In addition, a modification such as the drive signal output circuit 50 outputting a sinusoidal drive signal DS can also be performed.

[0050] The synchronization signal output circuit 52 outputs a synchronization signal SYC. The synchronization signal SYC is a signal based on the drive signal DS. For example, the synchronization signal SYC is a signal generated based on the drive signal Ds. Specifically, the synchronization signal SYC is a signal corresponding to the drive signal DS, for example, a clock signal of the first frequency that is the same frequency as the drive signal DS of the first frequency. For example, the synchronization signal SYC is a signal in phase (same phase) with the drive signal DS. Here, the same phase includes the situation of being approximately in phase. Specifically, in Figure 2 In the embodiment, the synchronization signal output circuit 52 generates the synchronization signal SYC based on the signal DV from the amplifier circuit 32. For example, Figure 2 As shown, when the drive circuit 30 receives the feedback signal DG generated by the drive signal DS from the physical quantity transducer 10 and performs feedback control, the synchronization signal SYC is a signal generated based on the feedback signal DG. Specifically, the synchronization signal SYC is a signal generated based on the signal DV after the feedback signal DG is amplified by the amplifier circuit 32. For example, the synchronization signal output circuit 52 outputs the synchronization signal SYC by shaping the waveform of the sine wave signal DV into a rectangular wave signal using a comparator or the like. Alternatively, the synchronization signal SYC may also be a signal generated by buffering the drive signal DS. The synchronization signal SYC may also be called a reference signal or a detection clock signal, for example.

[0051] The detection circuit 60 includes an amplifier circuit 61 , a synchronous detection circuit 90 , a filter unit 92 , and an A / D conversion circuit 94 .

[0052] The amplifier circuit 61 receives the detection signals S1 and S2 from the physical quantity transducer 10 and performs charge-voltage conversion, signal amplification, and gain adjustment. The detection signals S1 and S2 form a differential signal. The amplifier circuit 61 includes Q / V conversion circuits 62 and 63, a differential amplifier circuit 64, and an AC amplifier circuit 66.

[0053] The Q / V conversion circuits 62 and 63 convert the detection signals S1 and S2, which are charge signals from the physical quantity transducer 10, into voltage signals. The Q / V conversion circuits 62 and 63 are continuous charge-voltage conversion circuits having feedback resistors.

[0054] The differential amplifier circuit 64 performs differential amplification of the signals VS1 and VS2 from the Q / V conversion circuits 62 and 63. Thus, the physical quantity signals included in the signals VS1 and VS2 are amplified. That is, since the physical quantity signals included in the signals VS1 and VS2 are differential signals, the signals are amplified by performing differential amplification. The AC amplifier circuit 66 amplifies the output signal of the differential amplifier circuit 64 and outputs it as the output signal AQA of the amplifier circuit 61. In the AC amplifier circuit 66, for example, the gain adjustment of the signal is performed.

[0055] The synchronous detection circuit 90 performs synchronous detection on the output signal AQA of the amplifier circuit 61 based on the synchronization signal SYC. This makes it possible to extract a desired signal, that is, a physical quantity signal included in the output signal QA, and detect the physical quantity.

[0056] For example, the detection signals S1 and S2, which are charge signals from the physical quantity transducer 10, are phase-delayed by 90 degrees relative to the drive signal DS, which is a voltage signal. In addition, the phase is delayed by 90 degrees in the Q / V conversion circuits 62 and 63 of the amplifier circuit 61. Therefore, the output signal AQA of the amplifier circuit 61 is phase-delayed by 180 degrees relative to the drive signal DS. Therefore, by performing synchronous detection, for example, using the synchronous signal SYC in phase with the drive signal DS, it is possible to remove useless signals, etc., which are phase-delayed by 90 degrees relative to the drive signal DS, and detect the physical quantity.

[0057] The filter unit 92 performs filtering processing such as low-pass filtering processing on the output signal SQA of the synchronous detection circuit 90. The filter unit 92 functions as a pre-filter of the subsequent A / D conversion circuit 94. In addition, the filter unit 92 also functions as a circuit for attenuating useless signals that are not completely removed by synchronous detection. The A / D conversion circuit 94 performs A / D conversion on the analog output signal FQA from the filter unit 92 and outputs digital detection data DQA.

[0058] The DSP 100 performs various digital signal processing on the detection data DQA of the physical quantity from the detection circuit 60. The CPU 130 performs temperature correction calculation based on the detection data DQA and the temperature detection data. The DSP 100 performs temperature compensation processing on the detection data DQA based on the temperature correction value obtained by the temperature correction calculation of the CPU 130. Then, the DSP 100 performs digital filtering processing such as low-pass filtering processing and notch filtering processing on the detection data after the temperature compensation processing. In addition, the CPU 130 performs fault diagnosis processing based on the fault detection data DQB and DQC from the fault detection circuit 170. The details of the fault detection circuit 170 will be described later.

[0059] The storage unit 160 includes a register unit 162 and a nonvolatile memory 164. The nonvolatile memory 164 stores various information required for the operation of the circuit device 20. For example, a program for operating the CPU 130 is stored in the nonvolatile memory 164. As the nonvolatile memory 164, for example, an EPROM, an EEPROM, or a flash memory can be used. The information stored in the nonvolatile memory 164 is transferred to the register unit 162. Each circuit such as the DSP 100 and the CPU 130 of the circuit device 20 operates based on the information from the register unit 162, or writes various status information to the register unit 162. In addition, the register unit 162 can be accessed from the outside via the interface circuit 180. The register unit 162 can be implemented by, for example, a RAM, a flip-flop circuit, etc.

[0060] The interface circuit 180 is a circuit for communicating with an external processing device, etc. For example, the interface circuit 180 communicates with the external processing device based on a given communication standard. For example, the interface circuit 180 performs serial communication such as I2C (Inter-Integrated Circuit) or SPI (Serial Peripheral Interface).

[0061] Figure 3 FIG. 1 shows a configuration example of the fault detection circuit 170. In addition, the fault detection circuit 170 is not limited to Figure 3 The structure can be modified in various ways, such as omitting some of the structural elements or adding other structural elements. The fault detection circuit 170 includes an adding circuit 65, an AC amplifier circuit 67, an FLL circuit 70, a diagnostic synchronization signal generating circuit 80, synchronous detection circuits 91, 96, filter units 93, 97, A / D conversion circuits 95, 99, and a frequency dividing circuit 98.

[0062] The adding circuit 65 performs the calculation from Figure 2 The Q / V conversion circuits 62 and 63 of the Q / V conversion circuits 62 and 63 perform addition amplification on the signals VS1 and VS2. Thus, the electrostatic leakage signal and the like contained in the signals VS1 and VS2 are amplified. That is, the electrostatic leakage signal contained in the signals VS1 and VS2 is a signal of the same phase, so the signal is amplified by performing addition amplification. The AC amplifier circuit 67 amplifies the output signal of the adder circuit 65 and outputs it as the output signal AQB of the amplifier circuit 61.

[0063] The FLL circuit 70 is a circuit having an oscillation circuit and generating a clock signal CK of a target frequency through the oscillation circuit. FLL is the abbreviation of Frequency Locked Loop. For example, the FLL circuit 70 compares the frequency of the clock signal CK with the target frequency, and generates a clock signal CK of a frequency consistent with the target frequency through the oscillation circuit. Moreover, the FLL circuit 70 uses the synchronization signal SYC based on the drive signal DS as a reference clock signal to generate the clock signal CK of the target frequency. For example, the FLL circuit 70 generates a clock signal CK whose frequency ratio relative to the synchronization signal SYC as the reference clock signal is kept constant. The frequency ratio is a multiplication rate, and constant includes approximately constant. In the FLL circuit 70, the frequency ratio of the clock signal CK relative to the synchronization signal SYC is locked. The synchronization signal SYC is, for example, a clock signal of the first frequency having the same frequency as the drive signal DS of the first frequency. The synchronization signal SYC can also be called a reference signal or a detection clock signal, for example.

[0064] The diagnostic synchronization signal generating circuit 80 generates a diagnostic synchronization signal SYC2 of a fault of the second frequency based on the clock signal CK. For example, the synchronization signal SYC based on the drive signal DS of the first frequency is a signal of the first frequency, and in contrast, the diagnostic synchronization signal SYC2 is a signal of the second frequency. As an example, the diagnostic synchronization signal SYC2 is a signal of a frequency twice that of the synchronization signal SYC. Moreover, in the present embodiment, for example, a synchronization process is performed by the FLL circuit 70 and the diagnostic synchronization signal generating circuit 80 so that the edge of the diagnostic synchronization signal SYC2 is close to the edge of the synchronization signal SYC. For example, a synchronization process is performed so that the edge of the diagnostic synchronization signal SYC2 is within a given range relative to the edge of the synchronization signal SYC. The range is, for example, a range of less than one clock period of the clock signal CK. In addition, the edge of the signal is a rising edge or a falling edge of the signal.

[0065] The synchronous detection circuit 91 performs synchronous detection on the output signal AQB of the AC amplifier circuit 67 based on the diagnostic synchronization signal SYC2. The output signal AQB is a signal obtained by adding and amplifying the signals VS1 and VS2, and therefore includes an electrostatic leakage signal, which is, for example, a signal of the second frequency. Therefore, by performing synchronous detection on the output signal AQB using the diagnostic synchronization signal SYC2 of the second frequency, the electrostatic leakage signal included in the output signal AQB can be extracted. In addition, the filter unit 93 performs filtering processing such as low-pass filtering processing on the output signal SQB of the synchronous detection circuit 91. The A / D conversion circuit 95 performs A / D conversion on the analog output signal FQB from the filter unit 93 and outputs the fault detection data DQB. Thus, the CPU 130 can perform fault diagnosis by detecting whether there is a static leakage signal.

[0066] On the other hand, the synchronous detection circuit 96 performs synchronous detection on the output signal AQB of the AC amplifier circuit 67 based on the diagnostic synchronization signal SYC3. The diagnostic synchronization signal SYC3 is, for example, a square wave voltage signal that is 90 degrees ahead of the phase of the synchronization signal SYC for detecting the physical quantity signal. Therefore, the synchronous detection circuit 96 can extract the vibration leakage signal contained in the output signal AQB by performing synchronous detection on the output signal AQB based on the diagnostic synchronization signal SYC3. In addition, the filter unit 97 performs filtering processing such as low-pass filtering processing on the output signal SQC of the synchronous detection circuit 96. The A / D conversion circuit 99 performs A / D conversion on the analog output signal FQC from the filter unit 97 and outputs the fault detection data DQC. Thus, the CPU 130 can perform fault diagnosis by detecting the presence or absence of the vibration leakage signal.

[0067] The frequency division circuit 98 divides the clock signal CK from the FLL circuit 70, and outputs the clock signal ADCK for A / D conversion and the main clock signal MCK of the circuit device 20 used in the DSP 100 and the like. The A / D conversion circuits 94, 95, and 99 perform A / D conversion based on the clock signal ADCK. As an example, the clock signal CK is, for example, 8 MHz, the main clock signal MCK is, for example, 4 MHz, and the clock signal ADCK is, for example, about 47 to 48 kHz. For example, by shifting the clock signal ADCK for A / D conversion from 50 kHz as the driving frequency, it is possible to prevent the noise of the A / D conversion from having an adverse effect on the detection accuracy of the angular velocity and the like.

[0068] For example, in the present embodiment, fault diagnosis is performed using the electrostatic leakage component generated by the coupling capacitance of the driving electrode 13 and the detection electrodes 15 and 16. The coupling capacitance is an electrostatic coupling capacitance. For example, a coupling capacitance is formed between the driving electrode 13 to which the driving signal DS is provided and the detection electrode 15 that outputs the detection signal S1, and a coupling capacitance is also formed between the driving electrode 13 and the detection electrode 16 that outputs the detection signal S2. In this way, the coupling capacitance is formed due to the physical structure of the electrode of the physical quantity transducer 10, and the electrostatic leakage component caused by the coupling capacitance appears in the detection signals S1 and S2. By detecting the signal of the electrostatic leakage component, i.e., the electrostatic leakage signal, by synchronous detection of the synchronous detection circuit 91 based on the diagnostic synchronization signal SYC2, fault diagnosis using the detection of the electrostatic leakage signal can be achieved.

[0069] Figure 4 A double-T-shaped gyro sensor element is shown as an example of the physical quantity transducer 10 .

[0070] Figure 4The physical quantity transducer 10 has driving arms 18A, 18B, 18C, 18D, detection arms 19A, 19B, a base 21, and connecting arms 22A, 22B. The detection arms 19A, 19B extend in the +Y axis direction and the -Y axis direction relative to the rectangular base 21. In addition, the connecting arms 22A, 22B extend in the +X axis direction and the -X axis direction relative to the base 21. Furthermore, the driving arms 18A, 18B extend from their distal ends in the +Y axis direction and the -Y axis direction relative to the connecting arm 22A. In addition, the driving arms 18C, 18D extend from their distal ends in the +Y axis direction and the -Y axis direction relative to the connecting arm 22B. The hammer head provided at the distal end side of the driving arms 18A, 18B, 18C, 18D and the detection arms 19A, 19B is used as a hammer for frequency adjustment, for example. When the Z axis is set as the thickness direction of the physical quantity transducer 10, the physical quantity transducer 10 as a gyro sensor element detects the angular velocity around the Z axis. The X axis and the Y axis are coordinate axes orthogonal to the Z axis, and the X axis and the Y axis are orthogonal to each other. The vibrating plate of the physical quantity transducer 10 can be formed of piezoelectric materials such as quartz, lithium tantalate or lithium niobate. Among them, quartz is preferably used as the constituent material of the vibrating plate. The X axis, the Y axis, and the Z axis are also referred to as the electric axis, the mechanical axis, and the optical axis of the quartz substrate, respectively. The quartz substrate is composed of a plate-shaped Z-cut quartz plate having a thickness in the Z-axis direction.

[0071] The driving electrodes 13 are formed on the upper and lower surfaces of the driving arms 18A and 18B, and the driving electrodes 14 are formed on the right and left sides of the driving arms 18A and 18B. The driving electrodes 14 are formed on the upper and lower surfaces of the driving arms 18C and 18D, and the driving electrodes 13 are formed on the right and left sides of the driving arms 18C and 18D. Furthermore, the driving signal DS from the driving circuit 30 is provided to the driving electrode 13, and the feedback signal DG from the driving electrode 14 is input to the driving circuit 30.

[0072] Detection electrodes 15 are formed on the upper and lower surfaces of the detection arm 19A, and ground electrodes 17 are formed on the right and left sides of the detection arm 19A. Detection electrodes 16 are formed on the upper and lower surfaces of the detection arm 19B, and ground electrodes 17 are formed on the right and left sides of the detection arm 19B. Detection signals S1 and S2 from the detection electrodes 15 and 16 are input to the detection circuit 60.

[0073] In addition, grooves (not shown) are provided on the upper and lower surfaces of the driving arms 18A, 18B, 18C, 18D and the detection arms 19A and 19B for improving the electric field effect between the electrodes. By providing the grooves, a larger amount of charge can be generated with a smaller amount of deformation. In addition, the upper surface is the surface on the +Z axis direction side, and the lower surface is the surface on the -Z axis direction side. The right side surface is the side surface on the +X axis direction side, and the left side surface is the side surface on the -X axis direction side.

[0074] Next, Figure 4 When the driving signal DS is applied to the driving electrode 13 by the driving circuit 30, the driving arms 18A, 18B, 18C, and 18D perform the following operations by the inverse piezoelectric effect. Figure 4 Bending vibration as shown by arrow A1. Bending vibration is also called excitation vibration. For example, the vibration posture shown by the solid line of arrow A1 and the vibration posture shown by the dotted line are repeated at a specified frequency. That is, bending vibration is performed in which the ends of the driving arms 18A and 18C repeatedly approach and separate from each other, and the ends of the driving arms 18B and 18D also repeatedly approach and separate from each other. At this time, the driving arms 18A and 18B and the driving arms 18C and 18D vibrate line-symmetrically with respect to the X-axis passing through the center of gravity of the base 21, so the base 21, the connecting arms 22A and 22B, and the detection arms 19A and 19B hardly vibrate.

[0075] In this state, when the angular velocity with the Z axis as the rotation axis acts on the physical quantity transducer 10 and the physical quantity transducer 10 rotates around the Z axis, the driving arms 18A, 18B, 18C, and 18D vibrate as shown by arrow A2 due to the Coriolis force. That is, the Coriolis force in the direction of arrow A2, which is orthogonal to the direction of arrow A1 and the direction of the Z axis, acts on the driving arms 18A, 18B, 18C, and 18D, thereby generating a vibration component in the direction of arrow A2. The vibration of arrow A2 is transmitted to the base 21 via the connecting arms 22A and 22B, thereby the detection arms 19A and 19B perform bending vibration in the direction of arrow A3. The charge signals generated by the piezoelectric effect of the bending vibration of the detection arms 19A and 19B are input to the detection circuit 60 as detection signals S1 and S2, and the angular velocity around the Z axis is detected.

[0076] For example, if the angular velocity of the physical quantity transducer 10 around the Z axis is ω, the mass is m, and the vibration velocity is v, the Coriolis force is expressed as Fc=2m·v·ω. Therefore, the detection circuit 60 can obtain the angular velocity ω around the Z axis by detecting the expected signal, which is the physical quantity signal corresponding to the Coriolis force.

[0077] Moreover, in Figure 4In the embodiment, there is a coupling capacitance C1 between the driving electrode 13 and the detection electrode 15, and there is a coupling capacitance C2 between the driving electrode 13 and the detection electrode 16. Therefore, when the driving electrode 13 is driven by the driving signal DS, the frequency component of the alternating current contained in the driving signal DS is propagated to the detection electrode 16, and the charge signal of the alternating current based on the frequency component appears in the detection signals S1 and S2. Therefore, when the driving signal DS has a second frequency component, the charge signal of the alternating current based on the second frequency component will appear in the detection signals S1 and S2. Then, the signal of the second frequency component appearing in the detection signals S1 and S2 is added and amplified by the adding circuit 65, and the diagnostic synchronization signal SYC2 based on the second frequency is detected in the synchronous detection circuit 91. Then, the CPU 130 determines whether a fault has occurred based on the detection result.

[0078] Next, use Figure 5 , Figure 6 The operation of this embodiment is described with reference to the signal waveform diagram. Figure 5 It is a signal waveform diagram for explaining detection of physical quantity components included in the detection signals S1 and S2 of the physical quantity transducer 10 .

[0079] The signal DV is an output signal of the amplifier circuit 32 of the drive circuit 30, and is an AC signal of the first frequency f1. The first frequency f1 is, for example, the drive frequency of the drive circuit 30, and is 50 kHz as an example. The drive signal DS is a signal generated by the drive signal output circuit 50 based on the signal DV from the amplifier circuit 32. The drive signal DS is a signal in phase with the signal DV, and is a square wave voltage signal of a voltage set to a high level based on the control voltage VC from the gain control circuit 40. The drive signal DS has a component of the first frequency f1 as the drive frequency, and has a component of the second frequency f2=2×f1. The signal of the first frequency can also be called a signal of ω, and the signal of the second frequency can also be called a signal of 2ω. For example, the drive signal DS has a component of the second frequency f2 superimposed on the high-level voltage. The component of the second frequency f2 is a component generated by the full-wave rectifier circuit 42 of the gain control circuit 40. For example, the signal DV is full-wave rectified by the full-wave rectifier circuit 42, and has a component of a second frequency f2 that is twice the first frequency f1, in addition to the component of the first frequency f1. The component of the second frequency f2 overlaps with the control voltage VC from the integration circuit 44 that integrates the full-wave rectified signal from the full-wave rectifier circuit 42, so the component of the second frequency f2 appears in the high-level voltage of the drive signal DS.

[0080] The synchronization signal SYC is generated by, for example, waveform-shaping a sinusoidal (AC) signal DV into a square wave signal by the synchronization signal output circuit 52. The synchronization signal SYC is a signal in phase with the drive signal DS and is a square wave voltage signal of the first frequency f1.

[0081] Figure 5 The signals VS1 and VS2 represent the signals of the physical quantity components contained in the output signals of the Q / V conversion circuits 62 and 63. In addition, in the present embodiment, the signals of the physical quantity components are also appropriately recorded as physical quantity signals. The signals VS1 and VS2 constitute differential signals of opposite phases to each other. Then, the amplifier circuit 61 outputs the output signal AQA generated by differentially amplifying the signals VS1 and VS2 by the differential amplifier circuit 64. The synchronous detection circuit 90 performs synchronous detection on the output signal AQA of the amplifier circuit 61 based on the synchronization signal SYC, and outputs the output signal SQA. The output signal SQA becomes a full-wave rectified signal. In addition, the filter unit 92 outputs the DC voltage signal after smoothing the output signal SQA as a full-wave rectified signal as an output signal FQA. The DC voltage output signal FQA is A / D converted by the A / D conversion circuit 94 and input to the DSP 100 as digital detection data DQA. The DSP 100 detects the angular velocity as a physical quantity based on the detection data DQA.

[0082] Figure 6 1 is a signal waveform diagram for explaining detection of electrostatic leakage components included in the detection signals S1 and S2 of the physical quantity transducer 10 .

[0083] Regarding the signal DV, the drive signal DS, and the synchronization signal SYC, due to Figure 5 The same, so the detailed description is omitted. Figure 6 As shown, in the present embodiment, a diagnostic synchronization signal SYC2 of a second frequency f2 is digitally generated by an FLL circuit 70 and a diagnostic synchronization signal generating circuit 80. That is, the FLL circuit 70 uses the synchronization signal SYC based on the drive signal DS as a reference clock signal to generate a clock signal CK of a target frequency. The clock signal CK is, for example, a high-speed clock signal of 8 MHz. Moreover, the diagnostic synchronization signal generating circuit 80 generates a diagnostic synchronization signal SYC2 of a second frequency f2 based on the high-speed clock signal CK. The diagnostic synchronization signal SYC2 becomes a signal of a second frequency f2 that is twice the synchronization signal SYC, which is a signal of the first frequency f1. Moreover, for example, the diagnostic synchronization signal SYC2 becomes a signal whose rising edge is within the range of, for example, one clock period of the clock signal CK relative to the rising edge of the synchronization signal SYC.

[0084] Figure 6The signals VS1 and VS2 represent the signals of the electrostatic leakage components contained in the output signals of the Q / V conversion circuits 62 and 63. The signals of the electrostatic leakage components in the signals VS1 and VS2 are the second frequency components of the drive signal DS transmitted through the Figure 4 The signals transmitted through the coupling capacitors C1 and C2 described in the figure become signals in phase with each other. Furthermore, the amplifier circuit 61 outputs an output signal AQB generated by adding and amplifying the signals VS1 and VS2 through the adding circuit 65. The synchronous detection circuit 91 performs synchronous detection on the output signal AQB of the amplifier circuit 61 based on the diagnostic synchronization signal SYC2, and outputs an output signal SQB which is a full-wave rectified signal. Since the signal of the second frequency component of the drive signal DS is transmitted through the coupling capacitors C1 and C2, the signal of the electrostatic leakage component in the signals VS1 and VS2 becomes a signal of the second frequency f2. Therefore, by performing synchronous detection using the diagnostic synchronization signal SYC2 of the second frequency f2, the electrostatic leakage component can be detected. Furthermore, Figure 3 The filter unit 93 outputs a DC voltage signal after smoothing the output signal SQB as a full-wave rectified signal as an output signal FQB. The DC voltage output signal FQB is A / D converted by the A / D conversion circuit 95 and input to the CPU 130 as digital fault detection data DQB. The CPU 130 performs fault diagnosis based on the fault detection data DQB. For example, when the CPU 130 detects a signal of an electrostatic leakage component through the detection of the synchronous detection circuit 91, it determines that no fault has occurred. On the other hand, when the CPU 130 does not detect a signal of an electrostatic leakage component through the detection of the synchronous detection circuit 91, it determines that a fault such as a broken line has occurred.

[0085] In addition, the CPU 130 also performs fault diagnosis using mechanical leakage based on the fault detection data DQC due to mechanical leakage from the fault detection circuit 170 .

[0086] In addition, Figure 5 In the differential amplifier circuit 64, the differential amplification of the signals VS1 and VS2 is performed, so that Figure 6 The electrostatic leakage component signal of the same phase that appears in the signals VS1 and VS2 hardly appears in the output signal AQA and is not detected by the synchronous detection circuit 90. Figure 6 In the example, the signal VS1 and VS2 are added and amplified by the adding circuit 65, so Figure 5 The signal of the physical quantity component of the differential signal appearing in the signals VS1 and VS2 hardly appears in the output signal AQB and is not detected by the synchronous detection circuit 91.

[0087] Figure 7It is an explanatory diagram of the angular velocity dependence of the fault diagnosis result in the present embodiment. The horizontal axis is the angular velocity as a physical quantity, and the vertical axis represents the output variation of the normal time reference. The output variation of the normal time reference represents the variation after correction in a manner that becomes 0 when no disconnection occurs. VT is a threshold value used for fault diagnosis. Under normal circumstances, the output variation is lower than the threshold value VT, so the CPU 130 can determine that no abnormality has occurred. On the other hand, in the case of a double-sided disconnection where a disconnection occurs on both sides of the detection signal S1 side and the detection signal S2 side, the output variation exceeds the threshold value VT, so the CPU 130 can determine that an abnormality has occurred. In addition, in the case of a single-sided disconnection where a disconnection occurs only on the detection signal S1 side or only on the detection signal S2 side, the output variation also exceeds the threshold value VT, so the CPU 130 can determine that an abnormality has occurred.

[0088] For example, if a single-side disconnection occurs, Figure 2 The adding circuit 65 performs addition amplification on the signals VS1 and VS2, and the signal of the physical quantity component is not cancelled, but remains in the output signal AQB of the amplifier circuit 61. Figure 6 The signal of the physical quantity component corresponding to the signal DV remains in the output signal AQB. In this case, if the duty ratio of the diagnostic synchronization signal SYC2 is 50%, then Figure 6 The signal of the physical quantity component after synchronous detection in period TA of the diagnostic synchronization signal SYC2 and the signal of the physical quantity component after synchronous detection in period TB cancel each other out, and thus do not appear in the output signal FQB of the filter unit 93. This is because, when the duty cycle of the diagnostic synchronization signal SYC2 is 50%, period TA and period TB become the same length. Similarly, the signal of the physical quantity component after synchronous detection in period TC and the signal of the physical quantity component after synchronous detection in period TD cancel each other out, and thus do not appear in the output signal FQB of the filter unit 93. Therefore, the signal of the physical quantity component does not appear in the output signal FQB of the filter unit 93, and only the signal of the electrostatic leakage component can be detected.

[0089] On the other hand, when the duty ratio of the diagnostic synchronization signal SYC2 cannot be maintained, the lengths of the period TA and the period TB are different, or the lengths of the period TC and the period TD are different. Figure 6The signal of the physical quantity component after synchronous detection in the period TA and the signal of the physical quantity component after synchronous detection in the period TB do not cancel each other out and remain. In addition, the signal of the physical quantity component after synchronous detection in the period TC and the signal of the physical quantity component after synchronous detection in the period TD do not cancel each other out and remain. As a result, the signal of the physical quantity component remains in the output signal FQB of the filter unit 93, and the fault diagnosis result has angular velocity dependence in, for example, a single-side wire break. Therefore, if it is determined whether an abnormality has occurred by comparison with the threshold value VT, a problem of erroneous abnormality diagnosis will occur.

[0090] In this regard, in the present embodiment, the diagnostic synchronization signal SYC2 is generated by digital processing performed by the FLL circuit 70 and the diagnostic synchronization signal generating circuit 80. Therefore, it is possible to prevent the generation of the diagnostic synchronization signal SYC2 with mixed duty ratios, and to maintain the duty ratio of the diagnostic synchronization signal SYC2. Figure 6 By setting the period TA and the period TB or the period TC and the period TD to the same length, it is possible to digitally generate a diagnostic synchronization signal SYC2 with a duty cycle of, for example, 50%. As a result, even in the case of a single-sided wire break, the output variation does not have angular velocity dependency. Therefore, when the output variation is lower than the threshold value VT, it can be determined as a normal state where no abnormality has occurred, and when the output variation exceeds the threshold value VT, it can be appropriately determined that an abnormality such as a single-sided wire break or a double-sided wire break has occurred.

[0091] As described above, the circuit device 20 of the present embodiment includes: a driving circuit 30 that drives the physical quantity transducer 10; a detection circuit 60 that detects the physical quantity based on the detection signals S1 and S2 from the physical quantity transducer 10 and outputs the detection data DQA of the physical quantity; and a DSP 100 that performs digital signal processing on the detection data DQA. In addition, the circuit device 20 includes: a storage unit 160 that stores a program that describes a plurality of commands; and a CPU 130 that operates based on the stored program and performs at least one of temperature correction calculation and fault diagnosis of the detection data DQA. For example, the CPU 130 performs a temperature correction calculation to obtain a temperature correction value for temperature compensation processing based on the detection data DQA of the detection circuit 60. Alternatively, the CPU 130 performs fault diagnosis of the circuit device 20 and the physical quantity detection device 5 based on the fault detection data DQB, DQB, etc. from the fault detection circuit 170.

[0092] In this way, the high-speed DSP 100 can be used to perform calculations of the detection data DQA of physical quantities such as angular velocity, and the CPU 130 with a high degree of freedom can be used to perform calculations such as temperature correction and fault diagnosis. For example, since the DSP 100 is a circuit dedicated to the calculation of the detection data DQA, digital signal processing such as digital filtering processing for the detection data DQA can be performed at high speed. In addition, the CPU 130 operates based on the program stored in the storage unit 160, so it can perform calculation processing with a high degree of freedom. For example, by performing the detection processing of the physical quantity by the DSP 100 capable of high-speed processing, the detection value of the physical quantity can be output without delay. In addition, the CPU 130 that operates based on the program can perform fault diagnosis and temperature calculation with a high degree of freedom. For example, by preparing two computing units of the circuit device 20 to perform coordinated operations, high-speed operations and high-reliability operations can be performed. One of the two computing units is the CPU 130, which can be programmably operated by the program stored in the storage unit 160. For example, the CPU 130 can perform calculations of temperature correction values ​​such as temperature characteristic coefficients transmitted to the DSP 100, calculations for fault diagnosis, comparison of detection results between the DSP 100 and the CPU 130, kernel calculations of neural networks, or angle calculations based on angular velocity. One of the two operators is the DSP 100 that performs calculations of physical quantities such as angular velocity calculations, and the DSP 100 performs various digital filtering processes such as temperature compensation processing, low-pass filtering, notch filtering, or user-defined filtering using the temperature correction value received from the CPU 130. For example, the CPU 130 and the DSP 100 exchange data with each other and perform coordinated actions. For example, complex calculations are performed by the CPU 130, and the results are reflected to the DSP 100 after the results are determined. Therefore, even if complex and high-precision calculations are performed, the output interval of physical quantities such as angular velocity can be unaffected. For example, the calculation of fault diagnosis can be performed without affecting the calculation of physical quantities such as angular velocity. In addition, the action speed of the fault diagnosis itself is also improved, and the probability of misjudgment of faults can also be reduced.

[0093] 3. DSP, CPU

[0094] Next, a specific example of the DSP 100 and the CPU 130 will be described. In the present embodiment, a CPU 130 for controlling the physical quantity transducer 10 is provided. The program for causing the CPU 130 to operate is transferred from the non-volatile memory 164 to a volatile memory such as an SRAM when the power is turned on, for example. The volatile memory is provided in the storage unit 160. Then, the CPU 130 reads the program from the volatile memory and operates. By using the volatile memory as a data memory, an initial value can be transferred to the data memory during the CPU startup (boot) action. In addition, it is also possible to transfer the initial value to the data memory by setting it to be transferred to the data memory when the power is turned on. The CPU 130 operates, for example, with a 16-bit command length set through a program with an operation code of 5 bits. For example, 512 commands can be stored in the volatile memory. The CPU 130 can, for example, perform 16-bit fixed-point operations, 32-bit floating-point operations, and can also perform conversion operations between fixed-point and floating-point. The operation cycle of CPU 130 is fixed at 3 cycles, for example, but after the branch instruction, it becomes a process of inputting a NOP command. In addition, a stack frame and a stack pointer are built in to handle the call of a subroutine (function). In addition, CPU 130 supports the operation of a neural network, and has a built-in watchdog timer for monitoring the operation of CPU 130. In addition, CPU 130 has a built-in quartz clock counter, a threshold determination circuit, an output circuit of a PWM waveform, a control circuit of GPIO, or a comparison circuit for fault diagnosis as peripheral circuits. For example, the operation frequency of DSP 100 is about 12 kHz, and CPU 130 operates at an operation frequency of 1, 4, 6, or 12 divided by the operation frequency of DSP 100.

[0095] DSP 100 is equipped with, for example, 2nd to 4th order IIR low-pass filters, a digital operation unit, a limiting process, a 4th order notch filter, and a user-defined filter. The low-pass filter can be set to be turned on, off, the number of times, and the cut-off frequency. The cut-off frequency of the low-pass filter changes according to the driving frequency of the physical quantity transducer 10 such as the gyro sensor, so it has the function of automatically adjusting the filter coefficient. The notch filter can be set to be turned on and off. The output scale and output polarity can be changed through registers. For example, a limiting process unit with a limit of ±500dps is installed in the front stage of the user-defined filter, and a watchdog timer is also installed, so that even if the gain is reduced in the user-defined filter, it will not conflict with the judgment of compliance.

[0096] Figure 81 is a block diagram showing a detailed configuration example of the DSP 100 and the CPU 130. Detection data DQA of physical quantities such as angular velocity is input to the DSP 100 and the CPU 130 via a comb filter unit 190. A temperature detection signal TQ is input to the CPU 130 via a comb filter unit 192. The comb filter units 190 and 192 perform filtering processing such as moving average. The temperature detection signal TQ is input from a temperature sensor (not shown).

[0097] DSP 100 includes an adding unit 101, a gain processing unit 102, a low-pass filter unit 104, a notch filter unit 106, and a user-defined filter unit 108. CPU 130 includes a low-pass filter unit 131, a temperature correction operation unit 132, an adding unit 136, a gain processing unit 137, a self-diagnosis unit 138, a neural network operation unit 139, and an angle calculation unit 140. The temperature correction operation unit 132 includes a temperature calculation unit 133, a zero point correction unit 134, and a sensitivity correction unit 135. The program stored in the storage unit 160 is a program for causing CPU 130 to operate as each unit of CPU 130. In addition, DSP 100 and CPU 130 are not limited to Figure 8 The structure can be modified in various ways, such as omitting some of the structural elements or adding other structural elements.

[0098] The low-pass filter unit 131 of the CPU 130 performs low-pass filtering processing based on, for example, IIR (Infinite Impulse Response) on the temperature detection signal TQ input via the comb filter unit 192. The temperature calculation unit 133 of the temperature correction operation unit 132 calculates the temperature data TDA based on the temperature detection signal TQ after the low-pass filtering processing.

[0099] The zero-point correction unit 134 of the temperature correction calculation unit 132 obtains a temperature correction value ZC for zero-point correction based on the temperature data TDA. Zero-point correction is also called offset correction, and is a correction for making the detected value of the angular velocity zero when the angular velocity is zero. For example, the zero-point correction unit 134 approximates the output variation characteristic of the angular velocity with respect to the temperature by, for example, a 4th-order function, and obtains the temperature correction value ZC by inverting the sign of the approximate value. Then, the addition unit 101 of the DSP 101 performs an addition process of the temperature correction value ZC as an offset correction value, thereby realizing the zero-point correction of the detection data DQA.

[0100] The sensitivity correction unit 135 of the temperature correction calculation unit 132 obtains a temperature correction value SC for sensitivity correction based on the temperature data TDA. Sensitivity correction is also called gain correction. For example, the sensitivity correction unit 135 approximates the output sensitivity variation characteristic of the angular velocity with respect to the temperature by, for example, a 4th-order function, and obtains the temperature correction value SC by inverting the sign of the approximate value. Then, the gain processing unit 102 of the DSP 101 performs a gain adjustment process based on the temperature correction value SC as the gain correction value, thereby realizing sensitivity correction of the detection data DQA.

[0101] By performing such zero point correction and sensitivity correction, temperature compensation processing is realized for the detection data DQA of the detection circuit 60. For example, temperature compensation processing is realized to suppress the variation of the detection value PQ of the angular velocity with respect to temperature variation.

[0102] Then, the low-pass filter unit 104 of the DSP 100 performs digital low-pass filtering on the data DPQ after the zero point correction and sensitivity correction. The filter coefficients of the low-pass filtering are stored in the register unit 162 of the storage unit 160, for example.

[0103] The notch filter unit 106 performs notch filtering on the data after the low-pass filtering. The notch filtering is, for example, filtering for attenuating (removing) detuned frequency components. The filter coefficients of the notch filtering are stored in the register unit 162 of the storage unit 160, for example.

[0104] In addition, the user-defined filter unit 108 performs a user-defined filter process on the data after the low-pass filter process and the notch filter process. Then, for example, the user-defined filter unit 108 outputs the detection value PQ of the angular velocity as a physical quantity. The user-defined filter process is a filter process in which the characteristics such as the filter coefficient can be set by the user. For example, the user-defined filter process is a filter process that can be set by the user. Figure 2 The interface circuit 180 of the user defines the filter processing characteristics. The filter processing characteristics are set, for example, the order of the filter, the frequency characteristics, etc. The information of the user-defined filter processing characteristics is written and stored in the register unit 162 of the storage unit 160 via the interface circuit 180.

[0105] Furthermore, the adding section 136 of the CPU 130 performs zero point correction of the detection data DQA by performing addition processing of the temperature correction value ZC as an offset correction value. Furthermore, the gain processing section 137 of the CPU 130 performs sensitivity correction of the detection data DQA by performing gain processing based on the temperature correction value SC as a gain correction value.

[0106] Furthermore, the self-diagnosis unit 138 compares the data DPQ generated by the zero point calibration and sensitivity calibration of the DSP 100 with the data CPQ generated by the zero point calibration and sensitivity calibration of the CPU 130. Then, based on the result of the comparison processing of the data DPQ generated by the DSP and the data CPQ generated by the CPU, the fault diagnosis of the DSP 100 and the CPU 130 is performed. For example, when the data DPQ generated by the DSP and the data CPQ generated by the CPU are consistent within a given determination range (reference range), the self-diagnosis unit 138 determines that no fault has occurred, and when they are inconsistent, it determines that a fault has occurred. Then, the self-diagnosis unit 138 outputs the fault detection data DQD indicating the diagnosis result.

[0107] The neural network operation unit 139 performs various operations based on the neural network. For example, Figure 2 The storage unit 160 stores a learned model based on a neural network. Then, the neural network operation unit 139 inputs the processing object data into the learned model, and outputs the output data of the learned model as the operation result data of the neural network. For example, a learned model obtained by learning the temperature compensation processing that cannot be approximated by a fourth-order function, the temperature compensation processing of DIP in the temperature characteristic, etc. is prepared. For example, a learned model obtained by learning in a manner of outputting the temperature correction value of these temperature compensation processing for the input of temperature data TDA is prepared and stored in the storage unit 160. Then, the neural network operation unit 139 realizes these temperature compensation processing by performing neural network operations using the learned model.

[0108] The angle calculation unit 140 performs calculation processing to obtain an angle based on the detection value of the angular velocity output by the DSP 100. For example, the angle calculation unit 140 obtains the angle by performing integration processing on the detection value of the angular velocity.

[0109] As described above, in the present embodiment, the CPU 130 obtains the temperature correction values ​​ZC and SC by performing temperature correction calculation based on the temperature data TDA. For example, the zero point correction unit 134 of the CPU 130 performs a calculation process of zero point correction based on the temperature data TDA, thereby obtaining the temperature correction value ZC for zero point correction. In addition, the sensitivity correction unit 135 of the CPU 130 performs a calculation process of sensitivity correction based on the temperature data TDA, thereby obtaining the temperature correction value SC for sensitivity correction. Then, the DSP 130 performs temperature compensation processing of the detection data DQA based on the temperature correction values ​​ZC and SC. For example, the addition unit 101 of the DSP 100 performs an addition process based on the temperature correction value ZC from the CPU 130, thereby realizing the zero point correction in the temperature compensation process. In addition, the gain processing unit 102 of the DSP 100 performs a gain process based on the temperature correction value SC from the CPU 130, thereby realizing the sensitivity correction in the temperature compensation process. In this way, the temperature correction calculation, which is a complex calculation process, is executed by the CPU 130, so that an appropriate temperature correction value can be obtained. In addition, the CPU 130 can be operated programmably based on the program stored in the storage unit 160, so there is an advantage that, for example, various temperature correction calculations can be realized. On the other hand, the temperature compensation processing based on the temperature correction value is executed by the DSP 100 that can operate at a higher speed than the CPU 130. Thus, high-speed temperature compensation processing for the detection data DQA of the physical quantity can be realized.

[0110] In addition, in the present embodiment, the CPU 130 performs a comparison process between the DSP-generated data DPQ generated by the DSP 100 through the temperature compensation process based on the temperature correction values ​​ZC and SC and the CPU-generated data CPQ generated by the CPU 130 through the temperature compensation process based on the temperature correction values ​​ZC and SC. Then, the CPU 130 performs a fault diagnosis of the DSP 100 and the CPU 130 based on the result of the comparison process. Figure 8In the above, the comparison process and the fault diagnosis process are performed by the self-diagnosis unit 138. For example, when the CPU 130 determines that the data DPQ generated by the DSP is consistent with the data CPQ generated by the CPU, it is determined that the DSP 100 and the CPU 130 are not faulty. On the other hand, when the CPU 130 determines that the data DPQ generated by the DSP is inconsistent with the data CPQ generated by the CPU, it is determined that the DSP 100 and the CPU 130 are faulty. For example, when the data DPQ generated by the DSP is inconsistent with the data CPQ generated by the CPU, it is considered that a malfunction has occurred in the temperature correction calculation of the temperature correction calculation unit 132, or a malfunction has occurred in the temperature compensation process of the zero point correction and the sensitivity correction of the DSP 100. Therefore, in this case, it is determined that a malfunction has occurred in the DSP 100 and the CPU 130. In this way, by comparing the result of the temperature compensation process of the DSP 100 based on the temperature correction value calculated by the CPU 130 and the result of the temperature compensation process of the CPU 130 based on the temperature correction value calculated by the CPU 130, it is possible to perform self-fault diagnosis of the DSP 100 and the CPU 130. By performing such self-fault diagnosis, the reliability of the circuit device 20 and the physical quantity detection device 5 can be improved.

[0111] Fig. 9 1 shows an example of the hardware structure of the CPU 130. Fig. 9 As shown, the CPU 130 includes a fetch circuit 142, a command decoder 144, and an operation circuit 146. These circuits are provided in the core circuit of the CPU 130. The fetch circuit 142 fetches the command of the program. For example, the program stored in the storage unit 160 includes a plurality of commands IS1, IS2, and IS3. The fetch circuit 142 fetches each of these multiple commands. Then, the command decoder 144 interprets the command fetched by the fetch circuit 142. For example, the command decoder 144 interprets the command by performing a decoding process of the command code. The operation circuit 146 performs an operation process based on the interpretation result of the command decoder 144. For example, the operation circuit 146 performs an arithmetic operation such as addition or subtraction, a shift operation such as a logical shift or arithmetic shift, and a logical operation such as AND, OR, or XOR. In this way, the command of the program stored in the storage unit 160 can be fetched by the fetch circuit 142, the command decoder 144 interprets the fetched command, and the operation circuit 146 performs an operation process based on the interpretation result. Thus, using the CPU 130 capable of performing various operations based on the program, various processes for detecting physical quantities and the like can be executed by the CPU 130 .

[0112] Fig.10 1 is a signal waveform diagram for explaining an example of the operation of the CPU 130 . Fig.10CKCP is the operation clock signal of CPU 130. When the trigger start signal TSC becomes valid, CPU 130 starts processing. DATME represents the data of the memory of storage unit 160, and CKME is the clock signal for the memory. Since the bus width of the memory of storage unit 160 is 8 bits, Fig.10 As shown in B1, the reading of inst[15:0] as a 16-bit command requires a period of 2 cycles. After reading the command, the 8-bit EDC for detecting / correcting bit errors is read, and when it is determined that there is no bit error, the command is acquired by the CPU 130. Thereafter, as shown in B2 and B3, the CPU 130 performs a three-cycle process for each command, namely, decoding processing (Decode), execution processing (Exe) of the ALU (Arithmetic Logic Unit), and write-back processing (WB).

[0113] Fig.11 1 is a state transition diagram for explaining the operation of the CPU 130. The CPU 130 transitions to the idle state after a power-on reset (POR). Then, the CPU 130 waits until a Fig.10 until the trigger start signal TSC is issued. When the trigger start signal TSC and the trigger boost signal TBC are issued at the same time, the action mode of CPU 130 changes to the mode of startup action. When only the trigger start signal TSC is issued, the action mode of CPU 130 changes to the normal action mode. The difference between the startup action and the normal action is that the starting position of the program counter is different. In the case of the startup action, the program counter starts from ADR:1. In the case of normal action, the program counter starts from 0. In the case of any action, after the END command is issued, the CPU 130 enters the idle state and stands by until the trigger start signal TSC is issued again. It is assumed that the startup action is performed only once, for example, after the power is turned on. In addition, in the normal action mode, when a branch command to the neural network is executed, it is transferred to the neural network operation mode, and when the processing is completed, it returns to the normal action mode.

[0114] Fig.12 This is a diagram for explaining the cooperative operation of the CPU 130 and the DSP 100. Fig.12CP1 to CP4 represent the processes executed by the CPU 130, and DP11 to DP32 represent the processes executed by the DSP 100. For example, the DSP 100 executes processes DP11 to DP14 using the temperature correction value TCV1 obtained by the CPU 130 in the process CP1. For example, the temperature correction value TCV1 obtained by the CPU 130 in the process CP1 is latched by the register unit 162, and the DSP 100 executes processes DP11 to DP14 using the latched temperature correction value TCV1. In addition, the DSP 100 executes processes DP21 to DP24 using the temperature correction value TCV2 obtained by the CPU 130 in the process CP2. For example, the temperature correction value TCV2 obtained by the CPU 130 in the process CP2 is latched by the register unit 162, and the DSP 100 executes processes DP21 to DP24 using the latched temperature correction value TCV2. Similarly, the DSP 100 executes the processes DP31 to DP32 using the temperature correction value TCV3 obtained by the CPU 130 in the process CP3. Thus, in the present embodiment, the CPU 130 can execute a relatively complex process such as temperature correction calculation, and the DSP 100 capable of high-speed operation can execute a coordinated action such as a plurality of processes at high speed using the temperature correction value obtained by the CPU 130 in the process.

[0115] Fig.13 1 is a diagram showing an example of the execution sequence of DSP 100. Idle indicates idle, Culc indicates digital processing such as temperature compensation processing. In addition, NF1 and NF2 indicate notch filter processing, IIR1 to IIR4 indicate low-pass filter processing based on IIR, Clip indicates limit processing, and UF1 and UF2 indicate user-defined filter processing. DSP 100 executes sequentially Fig.13 In addition, in this embodiment, DSP 100 performs each process of the execution sequence. Fig.13 All sequences in the DSP 100 are checked to prevent problems such as zero point variation caused by current consumption variation due to the difference in the number of execution sequences of the DSP 100. For example, in the case of jumping to a non-existent state, an error flag is set.

[0116] Next, the details of the digital filter processing performed by the DSP 100 will be described. Fig.14 yes Figure 8 104 is a diagram for explaining the low-pass filtering process performed by the low-pass filtering unit 104. In the low-pass filtering process, the number of times and the cut-off frequency can be set as the filter setting. For example, Fig.14As shown, the number of times, for example, 2, 3, or 4, can be set by LPOD[1:0]. In addition, the cutoff frequency, for example, 1, 10, 25, 50, 100, 200, 400, 500, 1000, 2000, or 3000 Hz can be set by LPFC[3:0]. The cutoff frequency is set to a frequency corresponding to the drive frequency of the drive circuit 30, for example. In addition, in the default setting, a normal filter setting (for example, 2 times and a cutoff frequency of 100 Hz) is used.

[0117] In addition, the notch filter unit 106 performs a notch filter process for attenuating the components of a given frequency band. For example, the notch filter unit 106 performs a notch filter process for attenuating the detuned frequency component. For example, in a physical quantity transducer 10 such as a gyro sensor, the generation of useless signals of detuned frequencies caused by mechanical vibrations such as interference becomes a problem. Therefore, the notch filter unit 106, which is a band-stop filter, performs a notch filter process for attenuating the detuned frequency component. For example, when the resonant frequency on the driving side is fd and the resonant frequency on the detection side is fs, the notch filter unit 106 performs a notch filter process for attenuating the component of the detuned frequency Δf=|fd-fs|. Thus, it is possible to prevent the degradation of detection accuracy and the like caused by useless signals of the detuned frequency. For example, in the notch filter unit 106, 2 or 4 times can be selected as the number of times. Fig.15 The left side of shows an example of the transfer function of the notch filter processing when the order is 2. Fig.15 The right side of shows an example of a transfer function of a notch filter process when the order is 4. Each coefficient of these transfer functions can be set by register setting of the register unit 162.

[0118] Fig.16 1 is an explanatory diagram of the user-defined filtering process performed by the user-defined filtering unit 108. In the user-defined filtering process, the filter unit (FU) that can perform the process up to 2 times can be used by cascading up to 4 units. Thus, it is possible to handle up to 2 times × 4 units = 8 times. The number of filter units used by cascading can be set by UFU[1:0], which is the setting value of the filter unit usage number setting register. For example, Fig.16 As shown, when UFU[1:0]=00, only one filter unit FU1 is connected. When UFU[1:0]=01, two filter units FU1 and FU2 are connected in cascade. When UFU[1:0]=10, three filter units FU1, FU2, and FU3 are connected in cascade. When UFU[1:0]=11, four filter units FU1, FU2, FU3, and FU4 are connected in cascade.

[0119] Thus, in this embodiment, as digital filter processing, the DSP 100 performs low-pass filter processing in which the cutoff frequency is set according to the drive frequency of the drive circuit 30. For example, Fig.14 The cut-off frequency of the low-pass filter processing shown is set according to the driving frequency of the driving circuit 30. Specifically, the cut-off frequency of the low-pass filter processing shown in FIG. Fig.14 LPFC[3:0]. For example, when the drive frequency is low, the cutoff frequency is set to a low value, and when the drive frequency is high, the cutoff frequency is set to a high value. Figure 2 In the embodiment, the most suitable driving frequency for the vibration of the vibration pieces 11 and 12 is different according to the characteristics, materials or types of the vibration pieces 11 and 12 of the physical quantity transducer 10. Therefore, when the optimal driving frequency is high, the cutoff frequency is set high, and when the optimal driving frequency is low, the cutoff frequency is set low. In this way, the cutoff frequency of the low-pass filtering process can be set to an appropriate cutoff frequency corresponding to the optimal driving frequency of the physical quantity transducer 10. Thus, the frequency components of the useless signals that deteriorate the detection accuracy are appropriately attenuated by the low-pass filtering process, thereby achieving an improvement in the detection accuracy.

[0120] In addition, the DSP 100 performs notch filtering as digital filtering. Fig.15 As described in the DSP 100, the DSP 100 performs notch filtering processing to attenuate the components of a given frequency band. For example, in a physical quantity transducer 10 such as a gyro sensor, when an unnecessary signal of a detuned frequency is generated, the DSP 100 performs notch filtering processing to attenuate the components of the detuned frequency. In this way, the notch filtering processing attenuates the components of the frequency that degrades the detection accuracy, thereby achieving an improvement in the detection accuracy.

[0121] In addition, the DSP 100 performs filter processing whose characteristics can be set as digital filter processing. Fig.16 For example, by setting the number of cascade-connected filter units, the characteristics of the user-defined filter processing can be set. Figure 2 The interface circuit 180 is used to perform the filtering process. For example, the characteristics of the filtering process can be set by having the external processing device write the setting information of the characteristics of the filtering process to the register unit 162 via the interface circuit 180. In this way, the DSP 100 can perform the filtering process desired by the user, and the circuit device 20 can output the detection value of the physical quantity after the desired filtering process. Therefore, it is possible to provide the circuit device 20 and the physical quantity detection device 5 that can meet various expectations of the user.

[0122] Next, the operation cycle and operation frequency of the DSP 100 and the CPU 130 will be described. For example, Fig.171 is a diagram for explaining the operation of the CPU 130 in a comparative example of the present embodiment. In this comparative example, the DSP 100 is not provided in the circuit device 20, and various processes are performed only by the CPU 130. Fig.17 In the embodiment, the operation cycle of the CPU 130 becomes a cycle corresponding to the operation frequency of 3 kHz, and in each operation cycle, processing related to the angular velocity and processing for the fault diagnosis are performed. Fig.17 EQ1 to EQ8 represent the processing of fault diagnosis. As an example, EQ1 is Figure 3 , Figure 7 EQ2 is a fault diagnosis process using the mechanical leakage component. Figure 8 EQ4 to EQ8 are the processes of self-fault diagnosis of the data DPQ generated by the DSP and the data CPQ generated by the CPU as described in the previous section. In addition, EQ4 to EQ8 are the processes of other fault diagnosis. Then, in the last operation cycle of the CPU 130, the final fault diagnosis determination process using the results of EQ1 to EQ8 is performed. As a result, the cycle of fault diagnosis becomes a cycle equivalent to 9 cycles of the CPU 130, which becomes a cycle corresponding to the operation frequency of 330 Hz.

[0123] However, in the method of this comparative example, the processing of angular velocity is performed in an action cycle corresponding to a frequency as slow as 3kHz, and there is a problem that high-speed processing cannot be achieved. In addition, noise of a frequency corresponding to the cycle of fault diagnosis is generated, and the noise cannot be sufficiently attenuated by low-pass filtering, thereby causing problems such as reduced detection accuracy. For example, if a rest period occurs during which no fault diagnosis processing is performed, the current consumption during the rest period is less than the current consumption during the action period other than the rest period, thereby generating noise of a frequency corresponding to the cycle of fault diagnosis. For example Fig.18 An example of noise characteristics in a comparative example is shown. The horizontal axis represents frequency, and the vertical axis represents noise level. Fig.18 F1 is the noise at the detuned frequency. Fig.18 In addition to the noise of the detuned frequency shown by F1, noises shown by F2, F3, and F4 are also generated. These noises are noises of frequencies corresponding to the cycle of fault diagnosis. The noise of the frequency of 330 Hz corresponding to the cycle of fault diagnosis cannot be fully attenuated in the low-pass filter processing with a cutoff frequency of about 500 Hz, for example, and thus becomes a component of useless signals, reducing the detection accuracy of physical quantities.

[0124] Fig.19 FIG. 1 is a diagram for explaining the operation of the DSP 100 and the CPU 130 in this embodiment. Fig.19, the DSP 100 operates at an operation cycle corresponding to an operation frequency of 12 kHz, and the CPU 130 operates at an operation cycle corresponding to an operation frequency of 1 kHz. 12 kHz, which is the operation frequency of the DSP 100, is the first operation frequency, and 1 kHz, which is the operation frequency of the CPU 130, is the second operation frequency. The second operation frequency is an operation frequency lower than the first operation frequency. The operation cycle corresponds to, for example, the inverse of the operation frequency.

[0125] Furthermore, the DSP 100 performs processing related to the angular velocity in each operation cycle corresponding to 12 kHz. Fig.19 Executed in each action cycle Figure 8 Digital signal processing such as temperature compensation processing and digital filtering processing described in .

[0126] On the other hand, the CPU 130 executes the process of the fault diagnosis in the operation cycle corresponding to 1 kHz. For example, the CPU 130 executes the process of the fault diagnosis of EQ1 to EQ8 in the operation cycle of 1 kHz.

[0127] In this way, the DSP 100 can be used to perform processing related to the angular velocity at a high-speed operating frequency of 12 kHz. Fig.17 Compared with the comparative example, it is possible to perform processing on the angular velocity at a high speed and output the detected value of the angular velocity.

[0128] In addition, Fig.17 In the comparative example of , the fault diagnosis cycle becomes a cycle corresponding to 330 Hz, so the fault diagnosis cycle is Fig.18 The problem of reduced detection accuracy due to the noise shown in F2, F3, and F3. Fig.19 In the present embodiment, the cycle of the fault diagnosis is a cycle corresponding to 1 kHz, so even if noise corresponding to the cycle of the fault diagnosis is generated, it can be attenuated by low-pass filtering with a cutoff frequency of about 500 Hz, for example. Therefore, it is possible to prevent the reduction of detection accuracy due to the cycle of the fault diagnosis.

[0129] Fig. 20 1 is an explanatory diagram of the operating frequency of the DSP 100 and the CPU 130. Fig. 20As shown, DSP 100 operates at a first operating frequency fp1. On the other hand, CPU 130 operates at a second operating frequency fp2. The first operating frequency fp1 of DSP 100 is, for example, 12kHz. The second operating frequency fp2 of CPU 130 is, for example, 1kHz, 2kHz, 3kHz, 12kHz, which is a frequency below the first operating frequency fp1. In addition, the second operating frequency fp2 of CPU 130 is a variable frequency such as 1kHz, 2kHz, 3kHz, 12kHz. For example, DSP 100 operates based on the operating clock signal CKDP, and CPU 130 operates based on the operating clock signal CKCP. Moreover, the frequency dividing circuit 194 divides the operating clock signal CKDP for DSP and outputs the operating clock signal CKCP for CPU. The frequency dividing ratio of the frequency dividing circuit 194 is set by a frequency dividing ratio setting value. The frequency dividing ratio setting value is stored, for example, in Figure 2 The second operating frequency fp2 of the CPU 130 is set to a non-volatile memory 164 and a register unit 162. In this way, by changing the frequency division ratio of the frequency division circuit 194 according to the frequency division ratio setting value, the second operating frequency fp2 of the CPU 130 can be variably set to 1kHz, 2kHz, 3kHz or 12kHz. For example, when the CPU 130 performs a large number of processes or the load of the processes performed by the CPU 130 is heavy, the second operating frequency fp2 is set to a higher frequency. On the other hand, when the CPU 130 performs a small number of processes or the load of the processes performed by the CPU 130 is light, the second operating frequency fp2 is set to a low frequency. Thus, the second operating frequency fp2 of the CPU 130 can be set to an appropriate frequency corresponding to the number of processes, the content of the processes or the processing load of the CPU 130.

[0130] Thus, in the present embodiment, the DSP 100 operates at the first operating frequency fp1, and the CPU 130 operates at the second operating frequency fp2 which is lower than the first operating frequency fp1. That is, the DSP 100 operates at a frequency higher than the operating frequency of the CPU 130, and the CPU 130 operates at a frequency lower than the operating frequency of the DSP 100. Thus, processing of physical quantities such as angular velocity can be performed by the DSP 100 which operates at the higher first operating frequency fp1. Thus, for example, the detection value of the physical quantity can be output with a high throughput. On the other hand, with respect to the CPU 130, by operating at the second operating frequency fp2 which is lower than the first operating frequency fp1 of the DSP 100, it is possible to prevent situations such as excessive power consumption in the CPU 130.

[0131] In addition, the second operating frequency fp2 of the CPU 130 is variable. Fig. 20In the embodiment, the second operating frequency fp2 is a variable frequency such as 1kHz, 2kHz, 3kHz or 12kHz. Thus, for example, when the DSP 100 is operated at the high-speed first operating frequency fp1, the CPU 130 can be operated at the second operating frequency fp2 of an appropriate frequency corresponding to the processing quantity, processing content or processing load. For example, the CPU 130 can be operated programmably based on the program stored in the storage unit 160, and thus can be operated at the second operating frequency fp2 of an appropriate frequency corresponding to the processing of the program. Thus, the circuit device 20 and the physical quantity detection device 5 of various products corresponding to various processing can be provided.

[0132] In the present embodiment, when the first operating frequency is fp1, the second operating frequency is fp2, and m is an integer greater than 1, the relationship fp2=fp1 / m holds. Fig. 20 For example, when fp1=12kHz, by setting m=12, 6, 4, 1, fp2=1kHz, 2kHz, 3kHz, 12kHz is set. In any case, fp2≤fp1, and fp2 is a variable frequency. In this way, for example, the CPU 130 can be operated at the second operating frequency fp2 obtained by dividing the first operating frequency fp1, so that the CPU 130 can perform various processing quantities, processing contents or processing loads. For example, by causing the CPU 130 to operate at the operating clock signal CKCP obtained by dividing the operating clock signal CKDP of the DSP 100 by the frequency dividing circuit 194, the CPU 130 can perform various processing.

[0133] As described above, the circuit device of this embodiment includes: a driving circuit that drives the physical quantity transducer; a detection circuit that detects the physical quantity based on the detection signal from the physical quantity transducer and outputs the detection data of the physical quantity. In addition, the circuit device includes: a DSP that performs digital signal processing including digital filtering processing on the detection data; a storage unit that stores a program in which a plurality of commands are recorded; and a CPU that operates based on the program and performs at least one of temperature correction calculation and fault diagnosis of the detection data.

[0134] In this way, the detection data of the physical quantity in the detection circuit can be processed by the DSP through digital signal processing including digital filtering processing, and the processing of the physical quantity can be executed. On the other hand, the temperature correction calculation or fault diagnosis can be executed by the CPU that operates according to the program stored in the storage unit. Therefore, it is possible to realize a circuit device in which the DSP and the CPU can share the processing of the physical quantity and the processing of the temperature correction calculation or fault diagnosis.

[0135] In the present embodiment, the CPU may obtain a temperature correction value by performing a temperature correction calculation based on the temperature data, and the DSP may perform temperature compensation processing on the detection data based on the temperature correction value.

[0136] Thus, the temperature correction operation, which is a complex operation, is performed by the CPU, thereby obtaining an appropriate temperature correction value. On the other hand, the temperature compensation processing based on the temperature correction value is performed by the DSP that can operate at high speed, thereby realizing high-speed temperature compensation processing for the detection data of the physical quantity.

[0137] In addition, in the present embodiment, the CPU may compare data generated by the DSP through temperature compensation processing based on the temperature correction value with data generated by the CPU through temperature compensation processing based on the temperature correction value, and perform fault diagnosis of the DSP and the CPU based on the result of the comparison processing.

[0138] Thus, by comparing the result of the temperature compensation process of the DSP based on the temperature correction value calculated by the CPU and the result of the temperature compensation process of the CPU based on the temperature correction value calculated by the CPU, it is possible to perform self-fault diagnosis of the DSP and the CPU.

[0139] In the present embodiment, the CPU may include an acquisition circuit that acquires a command, a command decoder that interprets the acquired command, and an operation circuit that performs an operation based on the interpretation result of the command decoder.

[0140] In this way, the command of the program stored in the storage unit can be acquired by the acquisition circuit, the acquired command can be interpreted by the command decoder, and the operation circuit can execute operation processing based on the interpretation result.

[0141] In the present embodiment, the DSP may perform low-pass filter processing in which a cutoff frequency is set according to a drive frequency of the drive circuit as the digital filter processing.

[0142] In this way, the cutoff frequency of the low-pass filter process can be set to an appropriate cutoff frequency corresponding to the optimal drive frequency of the physical quantity transducer.

[0143] In the present embodiment, the DSP may perform notch filter processing for attenuating a predetermined frequency component as the digital filter processing.

[0144] In this way, the frequency component that deteriorates the detection accuracy is attenuated by the notch filter process, thereby improving the detection accuracy.

[0145] Furthermore, in the present embodiment, the DSP may perform a filter process whose characteristics can be set via an interface circuit as a digital filter process.

[0146] In this way, the DSP can be made to perform filtering processing desired by the user and output the detection value of the physical quantity after the desired filtering processing.

[0147] In the present embodiment, the DSP may operate at a first operating frequency, and the CPU may operate at a second operating frequency that is lower than the first operating frequency.

[0148] In this way, the processing of physical quantities can be performed by the DSP operating at a relatively high first operating frequency. On the other hand, the CPU can be operated at a second operating frequency that is lower than the first operating frequency of the DSP.

[0149] Furthermore, in the present embodiment, the second operating frequency of the CPU may be variable.

[0150] In this way, while the DSP is operated at the high-speed first operating frequency, the CPU can be operated at the second operating frequency of an appropriate frequency according to the number of processes, the content of processes, or the processing load.

[0151] In the present embodiment, when the first operating frequency is fp1, the second operating frequency is fp2, and m is an integer greater than or equal to 1, fp2=fp1 / m may be satisfied.

[0152] In this way, for example, the CPU can be operated at the second operating frequency obtained by dividing the first operating frequency, and the CPU can be caused to execute various processes having different processing quantities, processing contents, or processing loads.

[0153] Furthermore, the physical quantity detection device of the present embodiment may include the circuit device and the physical quantity transducer described above.

[0154] In addition, the present embodiment is described in detail as described above, but those skilled in the art can easily understand that various modifications can be made without substantially departing from the new matters and effects of the present invention. Therefore, such modifications are all included in the scope of the present invention. For example, in the specification or the accompanying drawings, a term recorded at least once with a different term in a broader sense or synonymous can be replaced with the different term in any part of the specification or the accompanying drawings. In addition, the structure of the circuit device, the physical quantity detection device, the physical quantity transducer, etc. is not limited to the structure described in the present embodiment, and various modifications can be made.

Claims

1. A circuit device, characterized in that: The circuit arrangement comprises: A driving circuit that drives the physical quantity transducer; a detection circuit that detects a physical quantity based on a detection signal from the physical quantity transducer and outputs detection data of the physical quantity; DSP, which performs digital signal processing including digital filtering processing on the detection data; a storage unit storing a program in which a plurality of commands are recorded; as well as The CPU operates based on the program to perform at least one of temperature correction calculation and fault diagnosis of the detection data.

2. The circuit arrangement according to claim 1, characterized in that The CPU obtains a temperature correction value by performing the temperature correction calculation based on the temperature data. The DSP performs temperature compensation processing on the detection data based on the temperature correction value.

3. The circuit arrangement according to claim 2, characterized in that The CPU performs comparison processing and performs fault diagnosis of the DSP and the CPU based on the result of the comparison processing. The comparison processing is a comparison processing of data generated by the DSP through temperature compensation processing based on the temperature correction value and data generated by the CPU through temperature compensation processing based on the temperature correction value.

4. The circuit arrangement according to claim 1, characterized in that The CPU comprises: an acquisition circuit, which acquires the command; a command decoder that interprets the acquired command; and The operation circuit performs operation processing based on the interpretation result of the command decoder.

5. The circuit arrangement according to claim 1, characterized in that The DSP performs a low-pass filter process in which a cutoff frequency is set according to a drive frequency of the drive circuit as the digital filter process.

6. The circuit arrangement according to claim 1, characterized in that The DSP performs notch filter processing for attenuating a predetermined frequency component as the digital filter processing.

7. The circuit arrangement according to claim 1, characterized in that The DSP performs a filter process whose characteristics can be set via an interface circuit as the digital filter process.

8. The circuit arrangement according to claim 1, characterized in that The DSP operates at a first operating frequency. The CPU operates at a second operating frequency that is lower than the first operating frequency.

9. The circuit arrangement according to claim 8, characterized in that The second operating frequency of the CPU is variable.

10. The circuit arrangement according to claim 8, characterized in that When the first operating frequency is fp1, the second operating frequency is fp2, and m is an integer greater than or equal to 1, fp2=fp1 / m.

11. A physical quantity detection device, characterized in that: The physical quantity detection device comprises: The circuit arrangement of any one of claims 1 to 10; and The physical quantity transducer.

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