A LDPC code parallel GPU decoding method and system

Abstract

The invention provides a decoding method and system of an LDPC code parallel GPU, which relates to the field of communication technology. The method comprises: reading an LDPC code through a CPU; allocating a check matrix parameter to a constant memory space of a GPU, and initializing the constant memory space; allocating a global memory space for channel information, a decoding hard decision result, and C2V through the GPU; quantizing the channel information into signed character data; setting a GPU thread block based on a sub-block dimension of a check matrix; utilizing intra-frame parallelism to perform hierarchical updating of the LDPC code through floating-point operations; storing the hierarchical information in a shared memory space of a GPU, and initializing the hierarchical information through the channel information; iteratively updating the initialized hierarchical information to generate a decoding result of data to be transmitted; transmitting the decoding result to a host memory space of a CPU; and releasing resources after completing the decoding of a codeword.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an LDPC code parallel GPU decoding method and system. Background Art

[0002] Low-Density Parity-Check Codes (LDPC) are linear block codes with sparse check matrices. LDPC codes are widely used in communications and storage due to their excellent error correction capabilities. Graphics Processing Units (GPUs) are processors designed specifically for processing graphics and parallel computing tasks. The GPU parallel decoding method for LDPC codes is an efficient decoding method designed by utilizing the characteristics of LDPC codes and the high parallel computing capabilities of GPUs to decode the received coded data and restore the original data.

[0003] Based on LDPC code and GPU parallel decoding, by making full use of the high parallel computing power of GPU, it is of great significance to improve the decoding efficiency of LDPC code in high data rate scenarios, significantly accelerate the complex iterative calculation process, and meet the real-time requirements. At the same time, this method can also reduce the delay in the decoding process, improve the reliability and anti-interference ability of the communication system, and is suitable for 5G communication, satellite remote sensing and data storage.

[0004] The traditional LDPC code decoding method has high computational complexity when processing long code lengths, and it is difficult to meet the real-time and high-throughput requirements of the satellite-to-ground high-speed data transmission system. In addition, the storage is frequently accessed during the LDPC code decoding process, but the memory access efficiency is insufficient, which becomes a bottleneck affecting the overall performance. As a result, the characteristics of the sparse check matrix of the LDPC code cannot be fully utilized, the parallelism design is not high enough, and the computing resources are not fully utilized, making it difficult to flexibly adjust the technology under different channel conditions. At the same time, it is difficult to meet the requirements of low power consumption and high efficiency, which in turn leads to reduced reliability of the communication system, poor anti-interference ability, and low memory access efficiency. Summary of the invention

[0005] In order to solve the technical problems that the traditional LDPC code decoding method in the prior art has high computational complexity when processing long code lengths, and is difficult to meet the requirements of the satellite-to-ground high-speed data transmission system for real-time and high throughput, resulting in the inability to fully utilize the characteristics of the LDPC code sparse check matrix, the parallelism design is not high enough, and the computing resources are not fully utilized, making it difficult to flexibly adjust the technology under different channel conditions, and it is difficult to meet the requirements of low power consumption and high efficiency, which in turn leads to reduced reliability of the communication system, poor anti-interference ability, and low memory access efficiency, the present invention provides a LDPC code parallel GPU decoding method and system.

[0006] The technical solution provided by the embodiment of the present invention is as follows:

[0007] First aspect

[0008] An embodiment of the present invention provides a LDPC code parallel GPU decoding method, comprising:

[0009] S1: Read the LDPC code and the check matrix parameters of the LDPC code through the CPU;

[0010] S2: Allocate the check matrix parameters to the constant memory space of the GPU and initialize the constant memory space;

[0011] S3: Allocate global memory space for channel information, decoding hard decision results and C2V through the CPU;

[0012] S4: quantize the channel information into signed character data;

[0013] S5: Setting GPU thread blocks based on the sub-block dimensions of the check matrix information portion;

[0014] S6: using the intra-frame parallelism consistent with the GPU thread block size, partially update the parity of the LDPC code according to the row index in the check matrix sub-block through floating-point operations to obtain the hierarchical information;

[0015] S7: storing the layer information in the shared memory space of the GPU as an unsigned short integer data type, and initializing the layer information by using the quantized channel information to obtain the initialized layer information;

[0016] S8: Iteratively update the initialization hierarchical information until the maximum number of iterations is reached, and generate a decoding result of the data to be transmitted;

[0017] S9: transmitting the decoding result to the host memory space of the CPU through asynchronous transmission to update the decoding hard judgment result in the host memory space;

[0018] S10: After decoding of all codewords is completed, the resources of the CPU and GPU are released.

[0019] Second aspect

[0020] An embodiment of the present invention provides an LDPC code parallel GPU decoding system, comprising:

[0021] processor;

[0022] A memory stores computer-readable instructions, and when the computer-readable instructions are executed by the processor, the LDPC code parallel GPU decoding method of the first aspect is implemented.

[0023] The third aspect

[0024] An embodiment of the present invention provides a computer-readable storage medium, on which a computer program is stored. When the program is executed by a processor, the LDPC code parallel GPU decoding method according to the first aspect is implemented.

[0025] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0026] In the present invention, the check matrix parameters of the LDPC code and the LDCP code are read by the CPU, and then the check matrix parameters are allocated to the constant memory space of the GPU, and the constant memory space is initialized, memory space is allocated for channel information, decoding hard judgment results and C2V, and the channel information is quantized into signed character data. The GPU thread block is set based on the sub-block dimension of the check matrix information part, the intra-frame parallelism is set, and the check matrix sub-blocks of the LDPC code are hierarchically updated according to the parity state of the check matrix sub-block label through floating-point operations to obtain hierarchical information, and the hierarchical information is stored in the shared memory space of the GPU as an unsigned short integer data type, and the hierarchical information is initialized by the quantized channel information to obtain the initialized hierarchical information. The initialized hierarchical information is iteratively updated to generate the decoding result of the data to be transmitted, and finally the decoding result is transmitted to the host memory space of the CPU through an asynchronous transmission method to update the decoding hard judgment result in the host memory space. After the decoding of all code words is completed, the resources of the CPU and GPU are released. Combining LDPC codes with GPU parallel decoding can not only achieve high decoding rates, but also has high flexibility and scalability, further improving the reliability and anti-interference capability of the communication system, making full use of computing resources, meeting the real-time and high throughput requirements of satellite-to-ground high-speed data transmission systems, and achieving low power consumption and high efficiency requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0028] Figure 1 A schematic diagram of a flow chart of a LDPC code parallel GPU decoding method provided by an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of the architecture of a LDPC code parallel GPU decoding method provided by an embodiment of the present invention;

[0030] Figure 3A schematic diagram of the parity partitioning of a check matrix sub-block and thread mapping relationship according to the present invention;

[0031] Figure 4 A schematic diagram of a method for calculating the scaling storage of row-to-column information provided by an embodiment of the present invention;

[0032] Figure 5 A schematic diagram of the structure of an LDPC code parallel GPU decoding system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The technical solution of the present invention is described below in conjunction with the accompanying drawings.

[0034] In the embodiments of the present invention, words such as "exemplarily" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "example" is intended to present the concept in a specific way. In addition, in the embodiments of the present invention, the meaning expressed by "and / or" can be both, or it can be either of the two.

[0035] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0036] Reference Manual Attached Figure 1 , shows a flow chart of a LDPC code parallel GPU decoding method provided by an embodiment of the present invention.

[0037] The embodiment of the present invention provides a LDPC code parallel GPU decoding method, which can be implemented by a LDPC code parallel GPU decoding device, and the LDPC code parallel GPU decoding device can be a terminal or a server. The processing flow of the LDPC code parallel GPU decoding method can include the following steps:

[0038] S1: Read the LDPC code and the check matrix parameters of the LDPC code through the CPU.

[0039] Among them, the central processing unit (CPU) is responsible for the core calculation and task allocation of the system. It is used here to initialize and manage the parameter reading of LDPC code and check matrix. Low-density parity-check code (LDPC) is a linear block code with a sparse check matrix, which is used to correct errors when transmitting data. The check matrix parameters are important information in the LDPC code check matrix, which defines the relationship between data bits and check bits in the codeword, including the position of non-zero elements.

[0040] It should be noted that the CPU reads the check matrix parameters of the LDPC code and pre-processes the data before loading it into the GPU, laying the foundation for subsequent parallel decoding operations. Its advantage is that it effectively utilizes the efficient management capabilities of the CPU, separates the data reading, formatting and allocation tasks from the GPU's computing tasks, and reduces the burden on the GPU. In addition, by managing the check matrix parameters on the CPU side, the data structure can be optimized before GPU memory allocation, improving the efficiency of data loading and reducing memory access latency.

[0041] In a possible implementation manner, the check matrix parameters specifically include: an absolute column position, an offset offset, and a compensation value delta.

[0042] Among them, the absolute column position represents the absolute index position of the column where the non-zero element in the check matrix is ​​located, the offset offset is used to describe the relative distance or offset value of some non-zero elements in the check matrix relative to a certain reference position, and the compensation value delta is the correction value introduced by position calculation or matrix operation in some special cases.

[0043] It should be noted that these parameters (absolute column position, offset, and compensation value delta) are used together to describe the position of non-zero elements in the LDPC check matrix, which facilitates efficient search and calculation in sparse matrix operations. By combining absolute position and relative offset value, storage overhead can be reduced while improving matrix operation efficiency. The compensation value delta further provides flexibility for handling special cases or optimizing algorithm flow.

[0044] Reference Manual Attached Figure 2 , shows a schematic diagram of the architecture of an LDPC code parallel GPU decoding method provided by an embodiment of the present invention.

[0045] Figure 2In the figure, h_channel in the host memory space (CPU side) represents the storage of the original data received from the channel, h_decision represents the storage of the hard decision result after decoding is completed, and the CPU is responsible for the control of the overall process, including data transmission, initialization and task allocation. The shared memory space (sh_L) in the GPU chip (GPU side) is used to store hierarchical information, with fast access speed, which is convenient for threads in the GPU to share data. The constant memory is responsible for storing the absolute column position, offset offset and compensation value delta of the check matrix. Registers are allocated to each thread in the register space for temporary storage of calculation data, where the column index represents the column position of the non-zero element, the row-to-column variable represents the storage of row-to-column information, and the intermediate calculation results are stored in other variables. The global memory space stores d_channel, that is, the channel information stored on the GPU side, which is transmitted from h_channel. d_C2V represents the storage of messages from the check node to the variable node (row-to-column information), and d_decision represents the storage of the hard decision result after the GPU decoding is completed and transmitted back to the CPU's h_decision. The PCIE bus connects the CPU and GPU and is responsible for data transmission.

[0046] The CPU receives data from the channel and stores the channel information in h_channel. It then calculates the absolute column position, offset and compensation value delta of the check matrix, and stores these parameters in the constant memory of the GPU. Using the PCIE bus, the h_channel data is transferred to the d_channel of the GPU global memory. The GPU allocates shared memory (sh_L) and register resources to store layer information and intermediate variables, loads the channel information of d_channel into the shared memory sh_L, and initializes it. Each thread block of the GPU (the number of threads is 0.5Z) is responsible for updating some check nodes and variable nodes. According to the column index and row-to-column variables, the new layer information is calculated in the register. The row-to-column message update is calculated by each thread. The minimum value and the second minimum value are stored in the global memory d_C2V. Within the maximum number of iterations, the GPU repeats the update operation of the check nodes and variable nodes until the maximum number of iterations is reached. After decoding is completed, the GPU stores the hard decision result in d_decision and transmits the decoding result in d_decision back to the CPU through the PCIE bus. The CPU receives the h_decision result and completes the decoding process. The entire system greatly improves the decoding speed and efficiency of LDPC codes through GPU parallel computing and efficient memory management, meeting the needs of satellite-to-ground high-speed data transmission systems.

[0047] S2: Allocate the check matrix parameters to the constant memory space of the GPU and initialize the constant memory space.

[0048] Among them, the Graphics Processing Unit (GPU) is good at parallel computing and is responsible for high-intensity computing tasks in LDPC decoding. Constant memory space is a special memory in the GPU that is optimized for storing fixed data. Since constant memory has a high-speed cache, fast access speed and is shared by multiple threads, it is very suitable for storing unchanging data such as check matrix parameters.

[0049] It should be noted that by loading the check matrix parameters into the constant memory space of the GPU and initializing them, the cache characteristics of the constant memory are effectively utilized, greatly improving the data access efficiency. The check matrix parameters are fixed during the decoding process, so storing them in the constant memory can reduce storage competition during multi-threaded access and improve the parallel computing performance of the GPU. At the same time, the initialization process ensures the integrity and consistency of the data, providing accurate input for subsequent calculations.

[0050] In a possible implementation manner, after S1 and before S3, the process further includes: preprocessing the check matrix, where the preprocessing process specifically includes:

[0051] Read the parameters of the check matrix from a file or constants.

[0052] Calculate the absolute column position of the first row of non-zero sub-blocks in the parity check matrix.

[0053] Set the offset and compensation value delta of the non-zero sub-block to the preset size.

[0054] It should be noted that this process ensures the integrity and consistency of the data and provides accurate input for subsequent calculations. Through this design, not only the global memory access of the GPU is reduced, but also the memory access latency is reduced, thereby improving the overall performance and decoding efficiency of the system.

[0055] S3: Allocate global memory space for channel information, decoding hard decision results and C2V through the CPU.

[0056] Among them, channel information is the probability or confidence value of data received from the communication channel, which usually reflects the possibility of whether the data bit is "0" or "1". The decoding hard decision result refers to the direct mapping of the confidence of the channel information or intermediate result to "0" or "1" in LDPC decoding to generate the decoded data output. The information from the check node to the variable node or the row-to-column information (C2V, Check-to-Variable) is the intermediate information transferred from the check node to the variable node during the LDPC decoding process, which represents the possibility of the variable node satisfying the check equation. The global memory space refers to the storage space in the GPU specifically allocated for channel information, decoding hard decision results and C2V, which is used to store the values ​​of these data and support fast access and operation during parallel computing.

[0057] It should be noted that by allocating global memory space in the GPU for channel information, decoding hard judgment results and C2V, key data is directly loaded into the GPU computing environment, thereby reducing frequent data transmission between the CPU and GPU, reducing communication delays, and improving data processing efficiency. This localized storage design makes full use of the GPU's high-bandwidth and low-latency video memory, supports fast access and efficient updates during parallel computing, and by independently allocating global memory space for each type of data, it can maximize storage management and improve data reading and writing efficiency.

[0058] S4: Quantize the channel information into signed character data.

[0059] Among them, signed character data is a data storage format used to represent integer data, and can represent both positive and negative values ​​(such as 8-bit data ranging from -128 to 127). By quantizing the channel information from floating-point data to signed character data, the storage space required for data storage is greatly reduced, while reducing the bandwidth requirements and latency of GPU memory access. Quantization processing can also reduce the data complexity in the calculation process, allowing the GPU to process more data with higher efficiency. In addition, signed character data supports the representation of positive and negative values, retains the sign characteristics of the channel information, and does not affect the accuracy of decoding.

[0060] S5: Setting the GPU thread block based on the sub-block dimension of the check matrix information portion.

[0061] Among them, the check matrix information part is the part related to the check node in the LDPC check matrix, which indicates the relationship between the data bit and the check bit. The sub-block dimension refers to dividing the check matrix into smaller sub-blocks (usually small matrices of fixed size). The dimension of each sub-block indicates its row and column size. The GPU thread block is the basic execution unit of threads in the GPU. Multiple thread blocks work in parallel to complete large computing tasks together.

[0062] Specifically, the present invention sets the size of the thread block to 0.5Z (Z is the sub-block dimension) according to the characteristics of the sub-block of the check matrix information part, and updates the even-numbered rows of the sub-block first and then the odd-numbered rows during the decoding process, so that it can be ensured that the row weights of all rows updated simultaneously when layered decoding is adopted are not greater than 1. Similarly, if the sub-block dimension Z is large, the dimension of the thread block can be set to 0.25Z to avoid the thread block being too large.

[0063] It should be noted that by reasonably setting the GPU thread block size based on the sub-block dimension of the check matrix, the GPU computing resource allocation and thread parallelism are optimized. This design makes full use of the sparse characteristics of the LDPC check matrix, so that each thread block focuses on processing the computing tasks of one or more sub-blocks, reducing resource competition and communication overhead between threads. The dynamic adaptation of the thread block size improves the utilization of the GPU, ensures the balanced distribution of computing tasks, and avoids thread idleness or overload.

[0064] Reference Manual Attached Figure 3 , shows a schematic diagram of the relationship between parity partitioning of a check matrix sub-block and thread mapping provided by an embodiment of the present invention.

[0065] Figure 3 In the figure, the thread block is the basic execution unit in GPU computing. It contains multiple threads. Thread 1-thread 6 is responsible for processing part of the data matrix. The rows of the matrix in the figure are processed in parallel by different thread blocks. Each thread block contains multiple threads. The thread is the smallest unit responsible for computing in the GPU. The "1" marked in the matrix represents the non-zero elements in the sparse matrix. These elements may be constraints or data values ​​in the check matrix. The threads will focus on processing these non-zero elements and skip zero elements.

[0066] Figure 3 A schematic diagram of dividing the parity position of the row in the check matrix sub-block and the corresponding thread mapping is given. The advantage of this division and mapping is that it can improve the adaptability of the LDPC decoding method described in the present invention, emphasizing the mapping relationship between the thread and the row data and the efficient processing of non-zero elements. Its role is to improve the computational efficiency of sparse matrix operations (such as LDPC check or update), make full use of the parallel capability of GPU, and optimize memory access. It is a key design concept in sparse matrix calculations or large-scale parallel tasks.

[0067] S6: Using the intra-frame parallelism that is consistent with the GPU thread block size, the LDPC code is partially updated in parallel according to the parity of the row index in the check matrix sub-block through floating-point operations to obtain hierarchical information.

[0068] Among them, intra-frame parallelism refers to the thread block set in the GPU, whose size matches the parallelism of data frame processing, ensuring that all thread blocks can synchronously and efficiently process different parts of the same data frame. Floating-point operations are used to process calculations involving decimals. In the LDPC decoding process, floating-point operations are often used to accurately calculate the probability value of belief propagation and improve the accuracy of decoding. Hierarchical update refers to updating the confidence values ​​of check nodes and variable nodes layer by layer after the hierarchical operation of the check matrix.

[0069] Specifically, the present invention adopts inter-frame and intra-frame parallelism, and the intra-frame parallelism is 0.5Z or 0.25Z, corresponding to the thread block dimension, that is, the check nodes belonging to the same sub-block are partially updated in parallel. The main reason for using partial parallel update for sub-blocks is that the row weights of most rows of non-zero sub-blocks of the adopted codeword sub-matrix are likely to be greater than 1. For the layered decoding algorithm, the row weights of all rows updated in parallel at the same time cannot be greater than 1. If it is greater than 1, it will cause confusion in the layered information update.

[0070] It should be noted that by setting the intra-frame parallelism consistent with the GPU thread block size, efficient parallel processing of computing tasks within the data frame is ensured, and the parallel computing capability of the GPU is utilized to the maximum extent. In addition, by using floating-point operations to update the check matrix sub-blocks in layers, the calculation accuracy can be improved, while avoiding global data dependence and reducing synchronization overhead between threads. This layered processing method is divided according to the parity position of the rows in the check matrix sub-blocks.

[0071] S7: Store the layered information in the shared memory space of the GPU as an unsigned short integer data type, and initialize the layered information using the quantized channel information to obtain initialized layered information.

[0072] Among them, hierarchical information refers to the intermediate information (such as C2V and V2C information) stored between check nodes and variable nodes during the LDPC decoding process, which is used to support layer-by-layer iterative updates and decoding calculations. The shared memory space of the GPU is an efficient memory area in the GPU, allowing all threads in the same thread block to quickly access shared data. The quantized channel information refers to the quantization of the received floating-point channel information (probability or confidence) into a smaller data type (such as a short integer) to reduce storage requirements and improve memory access efficiency. Initializing hierarchical information refers to the process of setting the hierarchical information to an initial state.

[0073] It should be noted that by storing the hierarchical information in the shared memory space of the GPU and initializing it with the quantized channel information, the data access efficiency is significantly improved. The high-speed characteristics of the shared memory make the access to the hierarchical information much faster than the global memory, reducing the memory access latency and computing bottlenecks. At the same time, using the quantized channel information as the initialization value not only reduces the memory usage, but also ensures the efficient loading of the initial state, providing a reliable foundation for subsequent iterative updates.

[0074] In a possible implementation manner, initializing the hierarchical information using the quantized channel information in S7 specifically includes:

[0075] Multiply the quantized channel information and the floating-point scaling factor.

[0076] The shared memory space is initialized with the multiplied channel information.

[0077] It should be noted that the combination of hierarchical information initialization and shared storage not only optimizes the parallel computing performance, but also effectively reduces the consumption of computing resources, making the decoding process faster and more accurate, giving full play to the parallel computing capabilities of the GPU, and ensuring the stability of data calculation.

[0078] S8: Iteratively update the initialized hierarchical information until a maximum number of iterations is reached, and generate a decoding result of the data to be transmitted.

[0079] Among them, the iterative update is to continuously update the information between the check nodes and the variable nodes through the belief propagation algorithm or the minimum sum algorithm, gradually approaching the correct decoding result until the decoding conditions are met or the maximum number of iterations is reached. The decoding result is the final output of the LDPC decoding process, which represents the decoded data (generally the hard judgment result after verification, which is used to restore the original transmitted information).

[0080] It should be noted that by iteratively updating the initialized hierarchical information and utilizing the strong error correction capability of LDPC codes, the process of gradually approaching the correct decoding result is achieved. This step is controlled by the maximum number of iterations, which not only ensures the reliability of the decoding process but also avoids falling into invalid calculations. The parallel computing advantages of the GPU are fully utilized in this process, and multiple threads complete the hierarchical update at the same time, improving the computing efficiency.

[0081] In a possible implementation, S8 specifically includes:

[0082] S801: Calculate the column index according to the absolute column position, the offset offset and the compensation value delta.

[0083] The column index is a data mark used to identify the position of a column where a non-zero element in the check matrix is ​​located during the LDPC code decoding process.

[0084] S802: Read the hierarchical information according to the column index, convert it into a floating point number and store it in a hierarchical information temporary variable register.

[0085] The hierarchical information temporary variable register is a storage resource in the GPU, which is used to store temporary data during the calculation process. The register is used to store the intermediate calculation results after reading from the hierarchical information and converting them into floating-point numbers. These data are quickly accessed by the thread in the next calculation.

[0086] S803: Update the information of the column-to-row information variable register by using the difference between the layer information temporary variable register and the row-to-column temporary variable register.

[0087] Among them, the row-to-column temporary variable register is temporary data stored in the GPU register, which is used to save the information (V2C information) passed from the variable node to the check node, and the column-to-row information variable register is a register used to store the updated check node to variable node transfer information (C2V information). Its value is obtained through calculation and is the key data after the check node is updated during the LDPC decoding process.

[0088] S804: The number of iterations is increased by 1, and the process returns to step S801 until the maximum number of update iterations is reached, and a decoding result of the data to be transmitted is generated.

[0089] It should be noted that the combination of quantization and storage optimization in the iterative update process further reduces memory usage and memory access latency. Ultimately, while ensuring high-precision decoding, it achieves rapid convergence, meets the requirements of high efficiency and real-time performance of the satellite-to-ground high-speed data transmission system, and is the core link of the entire GPU parallel decoding architecture.

[0090] Reference Manual Attached Figure 4 , showing a schematic diagram of a row-to-column information scaling storage calculation method provided by an embodiment of the present invention.

[0091] Figure 4 In the figure, (a) represents the row-to-column information magnification storage method, and (b) represents the row-to-column information reduction reading calculation method. The row-to-column information magnification storage method is to multiply the minimum value and the second minimum value of the absolute value of the floating-point row-to-column information by an amplification factor, and then limit the amplitude range to between 0 and 255 and convert it into unsigned character data. The row-to-column information reduction reading calculation method, that is, when using the minimum value and the second minimum value of the absolute value of the row-to-column information to restore the row-to-column information, it is necessary to multiply the unsigned character minimum value or the second minimum value by the inverse of the amplification factor, that is, the reduction factor, and then convert it into a floating point number for the subsequent calculation.

[0092] In a possible implementation, the calculation process of the value of the row-to-column temporary variable register is specifically as follows:

[0093] According to the minimum sum algorithm of LDPC, the absolute value of row-to-column information of the same row is the minimum value and the second minimum value of the absolute value of the corresponding column-to-row information.

[0094] The minimum value and the second minimum value of the absolute value of the row-to-column information are unsigned quantized with a preset bit.

[0095] Among them, those skilled in the art can set the size of the preset bit according to actual conditions, and the present invention does not limit it.

[0096] The minimum value, the second minimum value, the minimum value position, and the sign are all stored in the row-to-column temporary variable register using the unsigned char data type to replace the complete row-to-column information.

[0097] It should be noted that the value of the row-to-column temporary variable register is restored by checking the node to the variable node information. For the LDPC minimum sum algorithm, the absolute value of the row-to-column information of the same row is the minimum and second minimum of the absolute value of the corresponding column-to-row information. Therefore, it is only necessary to store the minimum and second minimum of the row-to-column information of the same row, the minimum position and the sign to restore the row-to-column information of the same row. Although the use of this method to restore the row-to-column information of the same row will undoubtedly increase the amount of additional calculations, the row weight of LDPC is generally large, which can greatly reduce the storage of row-to-column information, thereby reducing the number of accesses to the global memory, and ultimately effectively improving the decoding rate. Considering that the absolute value of the row-to-column information is small, the present invention performs 8-bit unsigned quantization (quantization range is 0 to 255) on the minimum and second minimum of the absolute value of the row-to-column information of the same row.

[0098] In a possible implementation, the minimum and second minimum absolute values ​​of the row-to-column information are unsignedly quantized with preset bits, specifically: the minimum and second minimum absolute values ​​of the row-to-column information and the amplification factor are multiplied and converted into unsigned character data.

[0099] It should be noted that the quantization method is to multiply the minimum value and the second minimum value of the absolute value of the row-to-column information by an amplification factor, and then limit the amplitude range to between 0 and 255 and convert it into unsigned character data. Correspondingly, when the minimum value and the second minimum value of the absolute value of the row-to-column information are used to restore the row-to-column information, it is necessary to multiply the unsigned character type minimum value or the second minimum value by the inverse of the amplification factor, and then convert it into a floating point number for the subsequent calculation. For the position of the minimum value, considering that the row weight of the LDPC code will not exceed 256 in practical applications, the present invention uses unsigned character data to complete the storage of the minimum value position. Since the row weights of different LDPC codes are different, in order to achieve efficient storage of row-to-column information symbols of different row weight code words, the present invention also uses unsigned character data to store row-to-column information symbols, so that it is convenient to determine how many unsigned integer data are needed to store symbols according to the row weight. The present invention uses a unified unsigned character data type to store the minimum value, the second minimum value, the minimum value position and the symbol of the row-to-column information.

[0100] S9: Transmit the decoding result to the host memory space of the CPU through asynchronous transmission to update the decoding hard judgment result in the host memory space.

[0101] Among them, the asynchronous transmission mode refers to a method of data transmission between the CPU and the GPU, which allows the transmission operation and the computing task to be performed simultaneously instead of sequentially, thereby reducing waiting time and improving resource utilization. The CPU host memory space refers to the CPU memory, which is used to store the decoding results transmitted back from the GPU and further participate in subsequent data processing or analysis. The decoding hard decision result is the final data after the decoding result is hard-determined (directly mapped to binary "0" or "1"), which represents the decoded information.

[0102] It should be noted that the decoding results calculated by the GPU are transmitted back to the CPU host memory through asynchronous transmission, which significantly reduces the data transmission delay between the CPU and the GPU. The design of asynchronous transmission allows calculation and data transmission to be carried out in parallel, thereby making full use of system resources and improving overall efficiency. In addition, this design avoids the time wasted by the CPU waiting for the GPU to complete the task, speeds up the data processing process, and the updated decoding hard judgment results are directly stored in the host memory, providing immediate and efficient support for subsequent data analysis or transmission. This mechanism achieves efficient collaboration between the GPU and the CPU while ensuring the decoding speed, meeting the requirements of high-speed communication systems for real-time performance and high throughput.

[0103] S10: After decoding of all codewords is completed, the resources of the CPU and GPU are released.

[0104] Resource release refers to releasing the memory space allocated in the CPU and GPU and destroying the asynchronous stream after the computing task is completed, ensuring that system resources are recovered in a timely manner and avoiding resource leakage.

[0105] It should be noted that by releasing the CPU and GPU memory space and destroying the asynchronous stream in time after the decoding task is completed, resource waste and potential memory leaks are effectively avoided. The resource release operation ensures that the system's memory and computing resources can be quickly reallocated for new computing tasks, improving the system's availability and stability.

[0106] In a possible implementation, releasing the resources of the CPU and GPU in S10 specifically includes: releasing the memory space of the CPU, releasing the video memory space of the GPU, and destroying the asynchronous stream.

[0107] Among them, the CPU memory space refers to the memory area used by the CPU to store channel information (h-channel) and decoding hard decision results (h-decision). These data are used on the CPU side to initialize or process decoding results. The GPU video memory space is the video memory allocated on the GPU, which is used to store channel information (d-channel) and decoding intermediate results or decoding hard decision results (d-decision), supporting GPU to perform parallel computing. Asynchronous streams are asynchronous task execution tools used in GPU computing, allowing multiple computing tasks or data transmission operations to be performed in parallel, thereby improving computing efficiency.

[0108] It should be noted that by efficiently releasing CPU and GPU resources, the scalability and flexibility of the overall system are improved, ensuring that the decoder can run stably for a long time and adapt to the requirements of high reliability and efficiency of the satellite-to-ground high-speed data transmission system.

[0109] In the present invention, the belief propagation algorithm (BP) and the minimum sum algorithm (Min-Sum) are two commonly used algorithms in LDPC code decoding. They are both based on the factor graph representation and iterative processing in graph theory. The calculation process of the BP algorithm is relatively complex. In contrast, the minimum sum algorithm is a simplification of the BP algorithm, which reduces the calculation complexity by replacing the multiplication operation with the addition and minimum value operation. This simplification makes the Min-Sum algorithm more efficient in implementation, especially in applications that require fast decoding. The present invention adopts the Min-Sum algorithm to complete the decoding of LDPC. In the decoding process of LDPC code, the Flooding message transmission strategy and the layered message transmission strategy are two main message transmission strategies. The layered message transmission strategy has significant advantages over the traditional Flooding strategy in the LDPC decoding process. It improves the calculation efficiency and decoding accuracy by reducing redundant calculations and error propagation. In addition, the layered strategy can adapt to different communication environments, while reducing storage requirements and improving decoding speed. This layered strategy facilitates the optimized use of resources and is easy to improve the overall decoding performance.

[0110] In a specific embodiment, LDPC code and GPU parallel decoding mainly includes three processes: decoding initialization process, layered decoding process and resource release process:

[0111] During the decoding initialization process, the parameters of the check matrix H=[Hs|Hp] of the LDPC code are preprocessed and initialized, and memory and video memory space are allocated for the information to be stored. The preprocessing and initialization of the check matrix parameters first reads the sub-block dimension Z of the sub-matrix Hs of the check matrix from a file or constant, the column position nx of the non-zero sub-block, the offset offset and the compensation value delta. For the Hp sub-block, the present invention sets the offset offset to 0 and the compensation value delta to 1 for the position where the diagonal of each sub-block is 1; and sets the offset offset to Z-1 and the compensation value delta to 1 for the position where the non-diagonal of each sub-block is 1. For the LDPC decoder described in the present invention, the size of the thread block is set to 0.5Z or 0.25Z.

[0112] In the layered decoding process, in the decoding stage, the present invention adopts inter-frame and intra-frame parallelism, and the intra-frame parallelism is 0.5Z or 0.25Z, corresponding to the thread block dimension, that is, the check nodes belonging to the same sub-block are partially updated in parallel. The main reason why the present invention adopts partial update for sub-blocks is that the row weights of most rows of the non-zero sub-blocks of the adopted codeword sub-matrix Hp are greater than 1. For the layered decoding algorithm, the row weights of all rows updated in parallel at the same time cannot be greater than 1. If they are greater than 1, it will cause confusion in the update of layered information. Therefore, according to the characteristics of the Hp sub-block, the present invention sets the size of the thread block to 0.5Z. During the decoding process, the even rows of the sub-block are updated first, and then the odd rows are updated. In this way, it can be ensured that the row weights of all rows updated simultaneously when layered decoding are adopted are not greater than 1. Similarly, if the sub-block dimension Z is large, the dimension of the thread block can be set to 0.25Z to avoid the thread block being too large.

[0113] The hierarchical decoding process mainly includes initializing the hierarchical information sh_L; allocating on-chip shared memory and register resources before decoding, and then completing the iterative update of the hierarchical information and row-to-column information C2V; making hard decisions on the updated hierarchical information; and outputting the hard decision results to the hard decision global memory space d_output.

[0114] Resource release process: After the decoder completes decoding of all codewords, it needs to release or destroy the memory and video memory allocated during the initialization process and the asynchronous stream created. Release the memory space h_channel and h_decision, release the video memory space d_channel and d_decision, and destroy the asynchronous stream.

[0115] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0116] In the present invention, the LDPC code and the check matrix parameters of the LDPC code are read by the CPU, and then the check matrix parameters are allocated to the constant memory space of the GPU, and the constant memory space is initialized, and the video memory space is allocated for the channel information, the decoding hard judgment result and the C2V, and the channel information is quantized into signed character data. The GPU thread block is set based on the sub-block dimension of the check matrix information part, the intra-frame parallelism is set, and the check matrix sub-block of the LDPC code is partially updated in parallel according to the parity of the row index in the check matrix sub-block through floating-point operations to obtain layered information, and the layered information is stored in the shared memory space of the GPU as an unsigned short integer data type, and the layered information is initialized by the quantized channel information to obtain the initialized layered information. The initialized layered information is iteratively updated to generate the decoding result of the data to be transmitted, and finally the decoding result is transmitted to the host memory space of the CPU through an asynchronous transmission mode to update the decoding hard judgment result in the host memory space, and after the decoding of all code words is completed, the resources of the CPU and GPU are released. Combining LDPC codes with GPU parallel decoding can not only achieve high decoding rates, but also has high flexibility and scalability, further improving the reliability and anti-interference capability of the communication system, making full use of computing resources, meeting the real-time and high throughput requirements of satellite-to-ground high-speed data transmission systems, and achieving low power consumption and high efficiency requirements.

[0117] Reference Manual Attached Figure 5 , shows a structural schematic diagram of an LDPC code parallel GPU decoding system provided by the present invention.

[0118] The present invention further provides a LDPC code parallel GPU decoding system 20, which is applied to the above-mentioned LDPC code parallel GPU decoding method, comprising:

[0119] Processor 201.

[0120] The memory 202 stores computer-readable instructions. When the computer-readable instructions are executed by the processor 201, the LDPC code parallel GPU decoding method of the method embodiment is implemented.

[0121] The LDPC code parallel GPU decoding system 20 provided by the present invention can execute the above-mentioned LDPC code parallel GPU decoding method and achieve the same or similar technical effects. To avoid repetition, the present invention will not go into details.

[0122] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0123] In the present invention, the LDPC code and the check matrix parameters of the LDPC code are read by the CPU, and then the check matrix parameters are allocated to the constant memory space of the GPU, and the constant memory space is initialized, and the global memory space is allocated for the channel information, the decoding hard judgment result and the C2V, and the channel information is quantized into signed character data. The GPU thread block is set based on the sub-block dimension of the check matrix information part, the intra-frame parallelism is set, and the check matrix sub-block of the LDPC code is partially updated in parallel according to the parity of the row index in the check matrix sub-block through floating-point operations to obtain layered information, and the layered information is stored in the shared memory space of the GPU as an unsigned short integer data type, and the layered information is initialized by the quantized channel information to obtain the initialized layered information. The initialized layered information is iteratively updated to generate the decoding result of the data to be transmitted, and finally the decoding result is transmitted to the host memory space of the CPU through an asynchronous transmission mode to update the decoding hard judgment result in the host memory space, and after the decoding of all code words is completed, the resources of the CPU and GPU are released. Combining LDPC codes with GPU parallel decoding can not only achieve high decoding rates, but also has high flexibility and scalability, further improving the reliability and anti-interference capability of the communication system, making full use of computing resources, meeting the real-time and high throughput requirements of satellite-to-ground high-speed data transmission systems, and achieving low power consumption and high efficiency requirements.

[0124] It should be understood that the processor in the embodiment of the present invention may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0125] It should also be understood that the memory in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0126] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented by software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When a computer instruction or computer program is loaded or executed on a computer, a process or function according to an embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by wired (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state hard disk.

[0127] It should be understood that the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship, but it may also indicate an "and / or" relationship. Please refer to the context for specific understanding.

[0128] In the present invention, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0129] It should be understood that in various embodiments of the present invention, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0130] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0131] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described equipment, devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0132] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0133] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0134] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0135] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0136] An embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the decoding method of LDPC code parallel GPU based on LDPC code and GPU parallelism as described in the method embodiment is implemented.

[0137] A computer-readable storage medium provided by the present invention can implement the steps and effects of the LDPC code parallel GPU decoding method based on LDPC code and GPU parallelism of the above method embodiment. To avoid repetition, the present invention will not go into details.

[0138] The beneficial effects brought about by the technical solution provided by the embodiment of the present invention include at least:

[0139] In the present invention, the check matrix parameters of the LDPC code and the LDCP code are read by the CPU, and then the check matrix parameters are allocated to the constant memory space of the GPU, and the constant memory space is initialized, memory space is allocated for channel information, decoding hard judgment results and C2V, and the channel information is quantized into signed character data. The GPU thread block is set based on the sub-block dimension of the check matrix information part, the intra-frame parallelism is set, and the check matrix sub-blocks of the LDPC code are hierarchically updated according to the parity state of the check matrix sub-block label through floating-point operations to obtain hierarchical information, and the hierarchical information is stored in the shared memory space of the GPU as an unsigned short integer data type, and the hierarchical information is initialized by the quantized channel information to obtain the initialized hierarchical information. The initialized hierarchical information is iteratively updated to generate the decoding result of the data to be transmitted, and finally the decoding result is transmitted to the host memory space of the CPU through an asynchronous transmission method to update the decoding hard judgment result in the host memory space. After the decoding of all code words is completed, the resources of the CPU and GPU are released. Combining LDPC codes with GPU parallel decoding can not only achieve high decoding rates, but also has high flexibility and scalability, further improving the reliability and anti-interference capability of the communication system, making full use of computing resources, meeting the real-time and high throughput requirements of satellite-to-ground high-speed data transmission systems, and achieving low power consumption and high efficiency requirements.

[0140] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

[0141] There are a few points to note:

[0142] (1) The drawings of the embodiments of the present invention only involve structures related to the embodiments of the present invention. Other structures may refer to conventional designs.

[0143] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present invention, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0144] (3) In the absence of conflict, the embodiments of the present invention and the features therein may be combined with each other to obtain new embodiments.

[0145] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. The protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A LDPC code parallel GPU decoding method, characterized in that: include: S1: Reading an LDPC code and a check matrix parameter of the LDPC code through a CPU; S2: Allocate the check matrix parameters to the constant memory space of the GPU and initialize the constant memory space; S3: Allocate global memory space for channel information, decoding hard decision results and C2V through the CPU; S4: quantizing the channel information into signed character data; S5: Setting GPU thread blocks based on the sub-block dimensions of the check matrix information portion; The size of the GPU thread block is 0.5Z, where Z is the sub-block dimension; S6: using the intra-frame parallelism consistent with the GPU thread block size, partially updating the LDPC code in parallel according to the parity of the row index in the check matrix sub-block through floating-point operations to obtain hierarchical information; The partially parallel updating of the LDPC code according to the parity of the row index in the check matrix sub-block by floating-point operation is specifically as follows: first updating the even rows of the sub-block, and then updating the odd rows; S7: storing the layer information in the shared memory space of the GPU as an unsigned short integer data type, and initializing the layer information by using the quantized channel information to obtain initialized layer information; The initializing the hierarchical information by using the quantized channel information in S7 specifically includes: multiplying the quantized channel information and a floating-point scaling factor; Initializing the shared memory space through the multiplied channel information; S8: iteratively updating the initialization hierarchical information until a maximum number of iterations is reached, and generating a decoding result of the data to be transmitted; S9: transmitting the decoding result to the host memory space of the CPU by asynchronous transmission to update the decoding hard judgment result in the host memory space; S10: After decoding of all codewords is completed, the resources of the CPU and the GPU are released.

2. The LDPC code parallel GPU decoding method according to claim 1, characterized in that: The check matrix parameters specifically include: absolute column position, offset and compensation value delta.

3. The LDPC code parallel GPU decoding method according to claim 2, characterized in that: After S1 and before S3, the process further includes: preprocessing the check matrix, wherein the preprocessing process specifically includes: Read the check matrix parameters from a file or a constant; Calculating the absolute column positions of the first row elements of the non-zero sub-blocks in the check matrix; The offset of the non-zero sub-block and the compensation value delta are set to preset sizes.

4. The LDPC code parallel GPU decoding method according to claim 2, characterized in that: The S8 specifically includes: S801: Calculate a column index according to the absolute column position, the offset offset and the compensation value delta; S802: Read the hierarchical information according to the column index, convert it into a floating point number and store it in a hierarchical information temporary variable register; S803: Update the information of the column-to-row information variable register by using the difference between the layer information temporary variable register and the row-to-column temporary variable register; S804: The number of iterations is increased by 1, and the process returns to step S801 until the maximum number of update iterations is reached, and a decoding result of the data to be transmitted is generated.

5. The LDPC code parallel GPU decoding method according to claim 4, characterized in that: The calculation process of the value of the row-to-column temporary variable register is specifically as follows: According to the minimum sum algorithm of the LDPC, the absolute value of the row-to-column information of the same row is the minimum value and the second minimum value of the absolute value of the corresponding column-to-row information; Performing unsigned quantization of preset bits on the minimum value and the second minimum value of the absolute value of the row-to-column information; The minimum value, the second minimum value, the minimum value position and the sign are all stored in the row-to-column temporary variable register using an unsigned character data type to replace the complete row-to-column information.

6. The LDPC code parallel GPU decoding method according to claim 5, characterized in that: The unsigned quantization of the minimum value and the second minimum value of the absolute value of the row-to-column information with preset bits is specifically: multiplying the minimum value and the second minimum value of the absolute value of the row-to-column information and the amplification factor, and converting them into unsigned character data.

7. The LDPC code parallel GPU decoding method according to claim 1, characterized in that: The releasing of the resources of the CPU and the GPU in S10 specifically includes: releasing the memory space of the CPU, releasing the video memory space of the GPU, and destroying the asynchronous stream.

8. A LDPC code parallel GPU decoding system, characterized in that: include: processor; A memory having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by the processor, the LDPC code parallel GPU decoding method according to any one of claims 1 to 7 is implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the LDPC code parallel GPU decoding method according to any one of claims 1 to 7 is implemented.

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