DFE receiving link, sending link, method and system

Abstract

The invention discloses a DFE receiving link, a DFE sending link, a method and a system, and relates to the technical field of communication. The DFE receiving link comprises a multi-carrier digital receiving channel and a single-carrier digital receiving channel which are respectively connected with a receiving channel selection module, and the receiving channel selection module is configured to select the multi-carrier digital receiving channel or the single-carrier digital receiving channel according to a digital signal receiving requirement corresponding to data to be received; therefore, the receiving channel selection module is connected with the multi-carrier digital receiving channel and the single-carrier digital receiving channel, so that a (multi-carrier / single-carrier) digital receiving channel meeting a digital signal receiving request can be selected from the multi-carrier digital receiving channel and the single-carrier digital receiving channel according to the digital signal receiving request corresponding to the data to be received; and carrying out data transmission processing on the to-be-received data so as to meet communication requirements in various scenes.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a DFE receiving link, a transmitting link, a method and a system. Background Art

[0002] The Digital Front End (DFE) is a bridge between the analog domain and baseband processing. Its main task is to be responsible for sampling rate conversion, digital up and down conversion, digital filtering and other functions after analog / digital (A / D) conversion. For example, see Figure 1 As shown in the figure, DFE is a system with complete digital functions after the A / D module in the entire digital receiver.

[0003] At present, the DFE system is mainly set up for specific scenarios, that is, usually the required carrier set is determined according to the communication requirements in the specific scenario (such as digital signal transmission requirements), and then a digital signal transmission channel is constructed based on at least one carrier included in the carrier set, thereby obtaining the corresponding DFE system.

[0004] However, when the above-mentioned DFE system is used for digital signal transmission, the digital signal transmission channel is set for specific communication needs, which causes the above-mentioned DFE system to be unable to meet the communication needs in various scenarios; therefore, there is an urgent need for a DFE link that can meet various communication needs. Summary of the invention

[0005] The embodiments of the present application provide a DFE receiving link, a transmitting link, a method and a system to meet communication requirements in various scenarios.

[0006] In a first aspect, an embodiment of the present application provides a DFE receiving link, wherein the DFE receiving link includes:

[0007] A multi-carrier digital receiving channel and a single-carrier digital receiving channel respectively connected to a receiving channel selection module; wherein the receiving channel selection module is configured to: select the multi-carrier digital receiving channel or the single-carrier digital receiving channel according to the digital signal reception requirement corresponding to the data to be received.

[0008] In the above embodiment, the multi-carrier digital receiving channel and the single-carrier digital receiving channel are connected through the receiving channel selection module, and according to the digital signal receiving request corresponding to the data to be received, the (multi-carrier / single-carrier) digital receiving channel that meets the digital signal receiving request can be selected from the multi-carrier digital receiving channel and the single-carrier digital receiving channel to perform data transmission processing of the data to be received. Obviously, the use of the above-mentioned DFE receiving link for digital signal reception is a DFE receiving link that can meet various communication requirements.

[0009] In an optional embodiment, the multi-carrier digital receiving channel includes: a first first-in-first-out buffer module, a DC correction module and multiple carrier digital receiving sub-channels arranged in sequence; wherein each carrier digital receiving sub-channel includes: a first digital gain control module, a first mixing module, a first integral comb line filter, a first digital filter, a second digital filter, a first imbalance correction module, a third digital filter and a second first-in-first-out buffer module arranged in sequence.

[0010] In an optional embodiment, the single-carrier digital receiving channel includes: a first first-in-first-out buffer module, a DC correction module, a first digital gain control module, a first mixing module, a first integral comb line filter, a first digital filter, a second digital filter, a first imbalance correction module, a third digital filter and a second first-in-first-out buffer module arranged in sequence.

[0011] In the above embodiment, the receiving operation of digital signals in various scenarios can be completed through the multi-carrier digital receiving channel and the single-carrier digital receiving channel included in the DFE receiving link.

[0012] In an optional embodiment, any one of the first digital filter, the second digital filter and the third digital filter is used to: perform a single multiplication operation and a single addition operation on each data element contained in the first serial data stream received by any one of the filters through a high-speed clock, so as to obtain a filtering result of the first serial data stream; wherein the first serial data stream represents the data to be received.

[0013] In an optional embodiment, the first mixing module is used to perform mixing processing on the IQ complex signal output by the first digital gain control module according to a coordinate rotation digital calculation method, the first integral comb line filter has an extended bit width that satisfies the extraction multiple range, and the first imbalance correction module is used to perform correction processing on the IQ complex signal output by the first digital filter according to a set first correction factor.

[0014] In the above embodiment, by improving the first digital filter, the second digital filter, the third digital filter, the first mixing module, the first integral comb line filter and the first imbalance correction module in the DFE receiving link (i.e., algorithm optimization or structure optimization processing), the computing resources are greatly compressed and reused, thereby greatly reducing the logic resource consumption of the processing module.

[0015] In an optional embodiment, the DFE receiving link also includes: a first power supply area and a second power supply area; wherein the first power supply area is used to provide power for the multi-carrier digital receiving channel, and the second power supply area is used to provide power for the single-carrier digital receiving channel.

[0016] In the above embodiment, power partitioning and cross-clock domain processing are used to further reduce the power consumption of the chip circuit in different scenarios. That is, multi-channel and single-channel partitions are designed for circuit power consumption, and dynamic power consumption management is performed to further reduce the overall power consumption of the circuit.

[0017] In an optional embodiment, the multiple ports included in the DFE receiving link are designed according to a preset port design method.

[0018] In the above embodiment, the multiple modules included in the DFE receiving link are all configured in a unified port mirroring manner, with unified module ports and layout, which is more conducive to integration.

[0019] In a second aspect, an embodiment of the present application further provides a DFE transmission link, wherein the DFE transmission link includes:

[0020] A multi-carrier digital transmission channel and a single-carrier digital transmission channel respectively connected to a transmission channel selection module; wherein the transmission channel selection module is configured to: select the multi-carrier digital transmission channel or the single-carrier digital transmission channel according to the digital signal transmission requirement corresponding to the data to be transmitted.

[0021] In the above embodiment, the multi-carrier digital transmission channel and the single-carrier digital transmission channel are connected through the transmission channel selection module, and according to the digital signal transmission request corresponding to the data to be transmitted, the (multi-carrier / single-carrier) digital transmission channel that meets the digital signal transmission request can be selected from the multi-carrier digital transmission channel and the single-carrier digital transmission channel to perform data transmission processing of the data to be transmitted; obviously, the use of the above-mentioned DFE transmission link for digital signal transmission can meet the DFE transmission link of various communication requirements.

[0022] In an optional embodiment, the multi-carrier digital transmission channel includes: a plurality of carrier digital transmission sub-channels arranged in sequence, a carrier aggregation module, a second imbalance correction module and a third first-in-first-out buffer module; wherein each carrier digital receiving and transmitting sub-channel includes: a fourth first-in-first-out buffer module, a fourth digital filter, a fifth digital filter, a sixth digital filter, a second integral comb line filter, a second mixing module and a second digital gain control module arranged in sequence.

[0023] In an optional embodiment, the single-carrier digital transmission channel includes: a fourth first-in-first-out buffer module, a fourth digital filter, a fifth digital filter, a sixth digital filter, a second integral comb line filter, a second mixing module, a second digital gain control module, a second imbalance correction module and a third first-in-first-out buffer module arranged in sequence.

[0024] In the above embodiment, the sending operation of digital signals in various scenarios can be completed through the multi-carrier digital sending channel and the single-carrier digital sending channel included in the DFE sending link.

[0025] In an optional embodiment, any one of the fourth digital filter, the fifth digital filter and the sixth digital filter is used to: perform a single multiplication operation and a single addition operation on each data element contained in the second serial data stream received by any one of the filters through a high-rate clock, so as to obtain a filtering result of the second serial data stream; wherein the second serial data stream represents the data to be sent.

[0026] In an optional embodiment, the second mixing module is used to perform mixing processing on the IQ complex signal output by the fifth digital filter according to a coordinate rotation digital calculation method, or to perform mixing processing on the IQ complex signal output by the second integral comb line filter, the second integral comb line filter having an extended bit width that satisfies the interpolation multiple range, and the second imbalance correction module is used to perform correction processing on the IQ complex signal output by the carrier aggregation module according to a set second correction factor.

[0027] In the above embodiment, by improving the fourth digital filter, the fifth digital filter and the sixth digital filter, the second mixing module, the second integral comb line filter and the second imbalance correction module in the DFE transmission link (i.e., algorithm optimization or structure optimization processing), the computing resources are greatly compressed and reused, thereby greatly reducing the logic resource consumption of the processing module.

[0028] In an optional embodiment, the DFE transmission link also includes: a first power supply area and a second power supply area; wherein the first power supply area is used to provide power for the multi-carrier digital transmission channel, and the second power supply area is used to provide power for the single-carrier digital transmission channel.

[0029] In the above embodiment, power partitioning and cross-clock domain processing are used to further reduce the power consumption of the chip circuit in different scenarios. That is, multi-channel and single-channel partitions are designed for circuit power consumption, and dynamic power consumption management is performed to further reduce the overall power consumption of the circuit.

[0030] In an optional embodiment, the multiple ports included in the DFE sending link are designed according to a preset port design method.

[0031] In the above embodiment, multiple modules included in the link sent through DFE are all configured according to a unified port mirroring setting, and the module ports and layout are unified, which is more conducive to integration.

[0032] In a third aspect, an embodiment of the present application further provides a method for receiving data in a DFE receiving link, the method comprising:

[0033] determining digital signal reception requirements associated with a data reception scenario for data to be received;

[0034] Based on the digital signal reception requirement, determining the digital signal receiving channel of the data to be received; wherein the digital signal receiving channel is a multi-carrier digital receiving channel or a single-carrier digital receiving channel;

[0035] The data to be received is received through the digital signal receiving channel.

[0036] In an optional embodiment, receiving the to-be-received data through the digital signal receiving channel includes:

[0037] If the digital signal receiving channel is the multi-carrier digital receiving channel, acquiring a first carrier set corresponding to the digital signal receiving requirement;

[0038] The data to be received is received through the carrier digital receiving sub-channels corresponding to each of the multiple carriers included in the first carrier set in the multi-carrier digital receiving channel.

[0039] Based on the data receiving method of the DFE receiving link, after determining the digital signal receiving requirement associated with the data receiving scenario of the data to be received, the digital signal receiving channel corresponding to the digital signal receiving requirement can be determined according to the correspondence between the digital signal receiving requirement and the digital signal receiving channel, so that the data to be received is received through the determined digital signal receiving channel. In this way, the digital signal receiving requirements in various scenarios are met, that is, the communication needs in various scenarios are met.

[0040] In a fourth aspect, an embodiment of the present application further provides a method for sending data in a DFE sending link, the method comprising:

[0041] determining digital signal transmission requirements associated with a data transmission scenario for data to be transmitted;

[0042] Based on the digital signal transmission requirement, determining the digital signal transmission channel of the data to be transmitted; wherein the digital signal transmission channel is a multi-carrier digital transmission channel or a single-carrier digital transmission channel;

[0043] The data to be sent is sent through the digital signal sending channel.

[0044] In an optional embodiment, sending the data to be sent through the digital signal sending channel includes:

[0045] If the digital signal sending channel is the multi-carrier digital sending channel, acquiring a second carrier set corresponding to the digital signal sending requirement;

[0046] The data to be sent is sent through the carrier digital sending sub-channels corresponding to each of the multiple carriers included in the second carrier set in the multi-carrier digital sending channel.

[0047] Based on the data sending method of the DFE sending link, after determining the digital signal sending requirements associated with the data sending scenario of the data to be sent, the digital signal sending channel corresponding to the digital signal sending requirements can be determined according to the correspondence between the digital signal sending requirements and the digital signal sending channels, so that the data to be sent is sent through the determined digital signal sending channel. In this way, the digital signal sending requirements in various scenarios are met, that is, the communication needs in various scenarios are met.

[0048] In a fifth aspect, an embodiment of the present application further provides a DFE system, the DFE system comprising: a DFE receiving link and a DFE transmitting link;

[0049] The DFE receiving link comprises: a multi-carrier digital receiving channel and a single-carrier digital receiving channel respectively connected to a receiving channel selection module; wherein the receiving channel selection module is configured to: select the multi-carrier digital receiving channel or the single-carrier digital receiving channel according to a digital signal receiving requirement corresponding to the data to be received;

[0050] The DFE transmission link includes: a multi-carrier digital transmission channel and a single-carrier digital transmission channel respectively connected to a transmission channel selection module; wherein the transmission channel selection module is configured to: select the multi-carrier digital transmission channel or the single-carrier digital transmission channel according to a digital signal transmission requirement corresponding to data to be transmitted.

[0051] In the above embodiment, by connecting the multi-carrier digital receiving channel and the single-carrier digital receiving channel through the receiving channel selection module, the (multi-carrier / single-carrier) digital receiving channel that meets the digital signal receiving request corresponding to the data to be received can be selected from the multi-carrier digital receiving channel and the single-carrier digital receiving channel to perform data transmission processing of the data to be received; and by connecting the multi-carrier digital transmitting channel and the single-carrier digital transmitting channel through the transmitting channel selection module, the (multi-carrier / single-carrier) digital transmitting channel that meets the digital signal transmitting request corresponding to the data to be transmitted can be selected from the multi-carrier digital transmitting channel and the single-carrier digital transmitting channel to perform data transmission processing of the data to be transmitted; obviously, the above-mentioned DFE system is used for digital signal transmission, and a DFE system that can meet various communication requirements.

[0052] In addition, other features and advantages of the present application will be described in the subsequent description, and partly become apparent from the description, or be understood by practicing the present application. The purpose and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor. In the drawings:

[0054] Figure 1 A schematic diagram of the structure of a digital receiver front end provided in an embodiment of the present application;

[0055] Figure 2 A schematic diagram of the location of a DFE in a baseband chip provided in an embodiment of the present application;

[0056] Figure 3 A schematic diagram of the structure of a DFE receiving link provided in an embodiment of the present application;

[0057] Figure 4 A schematic diagram of the structure of a DFE receiving link and a DFE transmitting link provided in an embodiment of the present application;

[0058] Figure 5 A schematic diagram of the distribution of a (sub)carrier provided in an embodiment of the present application;

[0059] Figure 6 A simplified calculation model diagram of a FIR filter provided in an embodiment of the present application;

[0060] Figure 7 A schematic diagram of the structure of a CIC decimation filter provided in an embodiment of the present application;

[0061] Figure 8 A schematic diagram of the structure of a DFE system transmission link provided in an embodiment of the present application;

[0062] Fig. 9 A schematic diagram of the structure of a CIC interpolation filter provided in an embodiment of the present application;

[0063] Fig.10 A schematic diagram of power partition control provided in an embodiment of the present application;

[0064] Fig.11 A schematic diagram of the structure of a module unified interface provided in an embodiment of the present application;

[0065] Fig.12 A schematic diagram of an implementation flow of a data receiving method of a DFE receiving link provided in an embodiment of the present application;

[0066] Fig.13 A schematic diagram of an implementation flow of a method for sending data in a DFE sending link provided in an embodiment of the present application;

[0067] Fig.14 A schematic diagram of the structure of a DFE system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the technical solution of the present application, rather than all of the embodiments. Based on the embodiments recorded in the application documents, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the technical solution of the present application.

[0069] It should be noted that in the description of this application, "multiple" is understood as "at least two". "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. A and B are connected, which can represent two situations: A and B are directly connected and A and B are connected through C. In addition, in the description of this application, words such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order.

[0070] In addition, the collection, dissemination, and use of data in the technical solution of this application comply with the requirements of relevant national laws and regulations.

[0071] The following is a brief introduction to the design concept of the embodiment of the present application:

[0072] In the baseband chip, DFE digital signal processing is the first step to complete air interface signal processing, which will directly affect the performance and indicators of the entire wireless communication system. However, due to the variety of communication signal systems and styles (or modes), it is necessary to design a DFE processing that is compatible with multiple systems and styles.

[0073] It should be noted that the signal system is a general term for the physical layer waveform of the wireless communication signal during the wireless transmission process, which usually consists of a set of signal processing processes composed of different technologies. For example, the signal system can be: multi-carrier, single carrier or spread spectrum, etc.

[0074] For example, see Figure 2 As shown in the figure, the DFE in the baseband chip is located between the Radio Frequency Interface (RFIF) and the Direct Memory Access (DMA), and is mainly used for the transmission of digital signals between the two; and in the process of digital signal transmission, it also involves related processing of digital signals (such as DC correction, gain control, mixing, interpolation and extraction, filtering and in-phase quadrature (IQ) correction, etc.).

[0075] It should also be noted that if Figure 2 As shown, the baseband chip also includes: a central processing unit (CPU), on-chip storage, a peripheral interface, a direct memory access module DMAG, other modules, an asynchronous conversion module ASC, a bus conversion module X2H, a high-performance expansion interface (Advanced eXtensible Interface, AXI) bus, and an advanced high-performance bus (Advanced High Performance Bus, AHB); wherein X2H is a bus conversion module for converting from the AXI bus to the AHB bus, m1~m5 represent bus master interfaces respectively, and s1~s5 represent bus slave interfaces respectively.

[0076] In addition, in order to better process the digital signals, the parameters and structured designs corresponding to the above-mentioned multiple functions are usually adaptively adjusted according to the signal processing of different signal systems. That is, the current DFE system is mainly set up for specific scenarios and only meets the communication needs in specific scenarios.

[0077] In view of this, the embodiments of the present application provide a DFE receiving link, a transmitting link, a method and a system to meet the communication needs in various scenarios, that is, data transmission of digital signals compatible with multiple systems (standards).

[0078] See also Figure 3 As shown, the DFE receiving link includes: a multi-carrier digital receiving channel and a single-carrier digital receiving channel respectively connected to a receiving channel selection module; wherein the receiving channel selection module is configured to: select the multi-carrier digital receiving channel or the single-carrier digital receiving channel according to the digital signal receiving requirement corresponding to the data to be received;

[0079] The receiving channel selection module connects the multi-carrier digital receiving channel and the single-carrier digital receiving channel. In this way, according to the digital signal receiving request corresponding to the data to be received, the (multi-carrier / single-carrier) digital receiving channel that meets the digital signal receiving request can be selected from the multi-carrier digital receiving channel and the single-carrier digital receiving channel to perform data transmission processing on the data to be received.

[0080] Optionally, the receiving channel selection module can select a multi-carrier digital receiving channel or a single-carrier digital receiving channel through register configuration parameters; in this way, one of the multi-carrier digital receiving channel and the single-carrier digital receiving channel can be selected through register configuration parameters to achieve switching between single / multi-channel parts.

[0081] It should be noted that if Figure 3 As shown, in the embodiment of the present application, the data transmission direction corresponding to the above-mentioned DFE receiving link is: RFIF→DMA, that is, processing the data from the RFIF and moving its output to the memory through DMA.

[0082] In an alternative implementation, see Figure 4 As shown, the multi-carrier digital receiving channel includes: a first first-in first-out buffer module ( Figure 4 The first FIFO in the DC correction module ( Figure 4 DC in) and multiple carrier digital receiving sub-channels; wherein each carrier digital receiving sub-channel includes: a first digital gain control module ( Figure 4 DGC in), the first mixing module ( Figure 4 MIX in), the first integral comb line filter ( Figure 4 CIC in), the first digital filter ( Figure 4 FIR0 in), the second digital filter ( Figure 4 FIR1 in), the first imbalance correction module ( Figure 4 IQ in), the third digital filter ( Figure 4 FIR2 in the Figure 4 The second FIFO in the multi-carrier digital receiving channel); it should be noted that xN indicates that the multi-carrier digital receiving channel is an N-carrier digital receiving channel, where N is an integer greater than 1.

[0083] Still Figure 4 As shown, the single-carrier digital receiving channel includes: a first first-in first-out buffer module ( Figure 4 The first FIFO in the DC correction module ( Figure 4 DC in), the first digital gain control module ( Figure 4 DGC in), the first mixing module ( Figure 4 MIX in), the first integral comb line filter ( Figure 4 CIC in), the first digital filter ( Figure 4 FIR0 in), the second digital filter ( Figure 4 FIR1 in), the first imbalance correction module ( Figure 4 IQ in), the third digital filter ( Figure 4 FIR2 in the Figure 4 The second FIFO in the .

[0084] For example, see Figure 5 As shown, the multi-carrier digital receiving channel can be a 16 (sub) carrier channel. Therefore, the multi-carrier digital receiving channel can complete carrier separation processing of various combinations such as 16 (sub) carriers, 8 (sub) carriers, 4 (sub) carriers, and 2 (sub) carriers, and can process multiple different frequency points (sub) carriers at the same time; wherein, the parameters of each (sub) carrier channel (i.e., carrier digital receiving sub-channel) can be configured separately or turned off, and the combination method between each (sub) carrier channel is flexible and changeable, and the processing results and processes are highly consistent.

[0085] In addition, the above-mentioned single-carrier digital receiving channel (i.e., the single-channel part) only contains resource modules for processing a single (sub)carrier (i.e., multiple modules included in the single-carrier digital receiving channel), and compatibility is taken into account for communication signals of two types of systems, namely, low-speed single-carrier and high-speed spread spectrum modes, thereby expanding the parameter configuration and processing capability range of the DFE system.

[0086] In addition, all modules in the carrier digital receiving sub-channels and single-carrier digital receiving channels have a bypass function, that is, by setting the corresponding bypass register, the data can be directly passed to the next-level module without being processed by the current module.

[0087] Furthermore, in order to compress logic resources, some modules in the DFE receiving link are improved as follows:

[0088] Optionally, any one of the above-mentioned first digital filter FIR0, second digital filter FIR1 and third digital filter FIR2 is used to: through a high-speed clock, perform a single multiplication operation and a single addition operation on each data element contained in the first serial data stream received by any filter, so as to obtain a filtering result of the first serial data stream; wherein the first serial data stream represents the data to be received.

[0089] Among them, the high-speed clock can make the sub-functional modules reused, so that the circuit operating frequency is higher, more data can be processed per unit time, and the processing is faster, so that more data can be processed and the circuit area can be reduced. For example, while two multipliers are needed, a multiplier in the embodiment of the present application can calculate twice.

[0090] Through the above-mentioned embodiments, the technical disadvantage of the traditional direct structure of the digital filter, in which the number of multipliers and adders involved in the calculation is related to the filter order and the higher the order, the more multiplications and additions are consumed, is avoided. By utilizing a high-speed clock and exchanging time for space, combined with a gate, the complete operation of the digital filter can be realized with a single multiplication and addition.

[0091] For example, see Figure 6 As shown, {d1,...,d n} is the first serial data stream, {p1,...,p n / 2+1} is the filter coefficient, sum is the summation result, the above digital filters (FIR0, FIR1 and FIR2) respectively select the filter coefficients (i.e. p1, ..., p n / 2+1 ) and the data elements (i.e., d1, ..., d n ), adding and multiplying in sequence, and then accumulating and summing the multiple multiplication results, and finally outputting a filtering result. The resource consumption of the digital filter with such a structure can be reduced a lot, that is, the digital filter (FIR0, FIR1 and FIR2) designed by the embodiment of the present application compresses the logic resources.

[0092] Specifically, for the first serial data stream {d1,...,d n}, in the first calculation, select d1 and d n Enter a1 and a2 respectively, add them, multiply them with p1 and enter the sum accumulator. In the second calculation, select d2 and d n-1 Enter a1 and a2 respectively, add them, multiply them with p2 and enter the sum accumulator, and so on until all the data elements contained in the first serial data stream are calculated.

[0093] Optionally, the first mixing module MIX is used to mix the IQ complex signal output by the first digital gain control module DGC according to the coordinate rotation digital computer (CORDIC) method; in this way, the mixing function is realized by the CORDIC algorithm, which only requires registers and adder logic, avoiding the technical disadvantages of the traditional general multiplier multiplying the local carrier, which consumes multiplier resources, occupies a large area, and consumes local memory resources.

[0094] Exemplarily, with the idea of ​​CORDIC vector rotation, the incoming IQ complex signal (i.e., the IQ complex signal output by the first digital gain control module DGC) is rotated by a certain angle in sequence, and the rotation step calculates the phase control word according to the mixing frequency. Each signal sampling point accumulates different phases according to the rotation angle, and the phase increases arithmetic difference according to the sampling point in sequence, and automatically overflows after exceeding one cycle, which is equivalent to starting from zero after a cycle phase reaches 2π (i.e., phase quadrant judgment and automatic compensation), thereby realizing the equivalent function of signal mixing. It should be noted that the formula corresponding to the CORDIC method can be expressed as follows:

[0095]

[0096] Among them, x i-1 and i-1 represents the real and imaginary parts of the IQ complex signal after the previous rotation, K i Represents the gain factor, which can be corrected when the IQ complex signal is initially input; σ i The value is ±1, and its specific value is determined according to the convergence value, representing the rotation direction, v i represents the rotated IQ complex signal.

[0097] Obviously, from the above, it can be seen that after the IQ complex signal is input into the first mixing module MIX, the phase control word can be accumulated. If the phase does not overflow, the phase quadrant judgment is performed; on the contrary, if the phase overflows, the phase quadrant judgment is performed after automatic compensation, so as to rotate and iterate the IQ complex signal angle multiple times until the iteration reaches the set iteration threshold (e.g., 15 times), and then the corresponding result is output.

[0098] It should be noted that in the embodiment of the present application, a better (mixing) accuracy can be achieved by iterating the angle rotation of each IQ complex signal more than 15 times.

[0099] Optionally, the first integral comb line filter CIC has an extended bit width that satisfies the decimation multiple range. In the embodiment of the present application, the intermediate process of CIC is to adapt to the full dynamic range. Therefore, the decimation multiple range of the extended bit width needs to satisfy the calculation of maintaining the maximum extended bit width precision. For example, see Figure 7 As shown, it is a CIC decimation filter, which first has a five-stage integrator or is configured as a four-stage, then passes through the decimator, the decimation multiple is 1 to 255, and then passes through a five-stage differentiator or is configured as a four-stage, and the delay is 1; it can be seen that the CIC here is a decimation filter, which is used in the DFE digital receiving link, and the decimation multiple can be flexibly set.

[0100] In addition, the result can be truncated according to the extraction when outputting. For example, the expanded bit width [B:0] is truncated to n bits, and the output [B:n]+[n-1] is used as the final output result. This cutoff method is equivalent to the rounding nearest() function, which can increase the fixed-point calculation bit width and retain the accuracy.

[0101] In addition, during the CIC calculation process, bit width expansion will occur, so that the input signal has gain. Optionally, the bit width expansion calculation can be expressed as follows:

[0102]

[0103] Among them, B in is the input data bit width; B out is the output data bit width; bracket operation To round up, Nlog2(DM) is the data bit width of the input data gain.

[0104] Optionally, the first imbalance correction module IQ is used to perform correction processing on the IQ complex signal output by the first digital filter FIR0 according to a set first correction factor.

[0105] Specifically, the consistency of analog devices such as filters and mixers on the in-phase branch and the orthogonal branch cannot be guaranteed, which leads to certain differences in the I-path and Q-path signals, which are mainly manifested in the appearance of mirror spectrum components, constellation point imbalance and severe signal distortion, thereby reducing the dynamic range and sensitivity of the entire communication system. In order to solve the above problems, in the embodiment of the present application, an IQ correction module is specially designed to correct the IQ imbalance problem by configuring a correction factor (i.e., the first correction factor).

[0106] Exemplarily, first, the amplitude and phase imbalance parameters are estimated in advance:

[0107]

[0108]

[0109] Among them, y I (n) and y Q (n) is the sampling signal of the in-phase (I) and quadrature (Q) branches; α is the amplitude correction factor in the first correction factor; is the phase correction factor in the first correction factor.

[0110] Furthermore, after the first correction factor is estimated in advance, the configuration parameters can be written into the register, and in order to reduce the operation of trigonometric functions in hardware, the multiplication term can be configured as a whole after the first correction factor is calculated; in addition, the sampled signals of the corrected in-phase (I) and quadrature (Q) branches can be expressed as follows:

[0111]

[0112] Among them, y I ′(n) and y′ Q (n) is the sampled signal of the in-phase (I) and quadrature (Q) branches after correction.

[0113] It is not difficult to find that based on the above improvements to each module in the DFE receiving link (i.e., algorithm optimization or structure optimization processing), the computing resources are greatly compressed and reused, thereby greatly reducing the logic resource consumption of the processing module.

[0114] See also Figure 8 As shown, the DFE transmission link includes: a multi-carrier digital transmission channel and a single-carrier digital transmission channel respectively connected to the transmission channel selection module; wherein the transmission channel selection module is configured to: select the multi-carrier digital transmission channel or the single-carrier digital transmission channel according to the digital signal transmission requirements corresponding to the data to be transmitted.

[0115] The transmission channel selection module connects the multi-carrier digital transmission channel and the single-carrier digital transmission channel. In this way, according to the digital signal transmission request corresponding to the data to be sent, the (multi-carrier / single-carrier) digital transmission channel that meets the digital signal transmission request can be selected from the multi-carrier digital transmission channel and the single-carrier digital transmission channel to perform data transmission processing for the data to be sent.

[0116] Optionally, the transmission channel selection module can also select the multi-carrier digital transmission channel or the single-carrier digital transmission channel through register configuration parameters; in this way, one of the multi-carrier digital transmission channel or the single-carrier digital transmission channel can be selected through register configuration parameters to realize switching between single / multi-channel parts.

[0117] It should be noted that if Figure 8As shown, in the embodiment of the present application, the data transmission direction corresponding to the above-mentioned DFE sending link is: DMA→RFIF, that is, data is moved in reverse through DMA and finally output from RFIF.

[0118] In an optional implementation, Figure 4 As shown, the multi-carrier digital transmission channel includes: a plurality of carrier digital transmission sub-channels arranged in sequence, a carrier aggregation module ( Figure 4 COM in), the second unbalance correction module ( Figure 4 IQ) and the third FIFO buffer module ( Figure 4 wherein each carrier digital receiving and sending sub-channel comprises: a fourth first-in first-out buffer module ( Figure 4 The fourth FIFO in the fourth digital filter ( Figure 4 FIR0 in), the fifth digital filter ( Figure 4 FIR1 in), the sixth digital filter ( Figure 4 FIR2 in), the second integral comb line filter ( Figure 4 CIC in the second mixer module ( Figure 4 MIX in) and the second digital gain control module ( Figure 4 DGC in); It should be noted that xN indicates that the multi-carrier digital transmission channel is an N-carrier digital transmission channel, where N is an integer greater than 1.

[0119] Still Figure 4 As shown, the single-carrier digital transmission channel includes: a fourth first-in first-out buffer module ( Figure 4 The fourth FIFO in the fourth digital filter ( Figure 4 FIR0 in), the fifth digital filter ( Figure 4 FIR1 in), the sixth digital filter ( Figure 4 FIR2 in), the second integral comb line filter ( Figure 4 CIC in the second mixer module ( Figure 4 MIX in), the second digital gain control module ( Figure 4 DGC in the second imbalance correction module ( Figure 4 IQ) and the third FIFO buffer module ( Figure 4 The third FIFO in (FIFO).

[0120] For example, Figure 5As shown, the above-mentioned multi-carrier digital transmission channel can be a 16 (sub) carrier channel. Therefore, the multi-carrier digital transmission channel can complete carrier separation processing of various combinations such as 16 (sub) carriers, 8 (sub) carriers, 4 (sub) carriers, 2 (sub) carriers, etc., and can simultaneously process multiple different frequency points (sub) carriers at the same time.

[0121] It should be noted that the 16-channel output of the multi-carrier digital transmission channel is finally sent to RFIF after the data is merged through the carrier aggregation module COM, and each (sub) carrier channel also has independent parameter configuration and works independently; and the above-mentioned single-carrier digital transmission channel (i.e., the single-channel part) is further simplified, eliminating one level of filtering (i.e., only the fourth digital filter FIR0 and the fifth digital filter FIR1), optimizing link resource consumption, and the parameters can also be flexibly configured.

[0122] In addition, all the modules in the carrier digital transmission sub-channels and the single-carrier digital transmission channel also have a bypass function, that is, by setting the corresponding bypass register, the data can be directly passed to the next-level module without being processed by the current module.

[0123] Obviously, based on the design of the above-mentioned DFE receiving link and DFE transmitting link, the use of a 16+1 channel combination can meet the needs of multi-carrier aggregation separation communication, and can also be suitable for the needs of narrowband low-speed single-carrier communication. It can also meet the reception and processing of spread spectrum broadband signals. Therefore, a design method of multiple system compatibility and multiple mode integration is realized in engineering, that is, the link module in the embodiment of the present application is flexible in design, and the configuration parameters have a wide range of adaptability, which is more in line with the actual engineering application needs.

[0124] In addition, it adopts a 16+1 flexible link structure, with each channel and module being independent, flexibly configurable and having bypass functions, and is compatible with different systems and working parameters to the greatest extent. It has multi-carrier and multi-channel real-time processing capabilities, and can schedule multiple subcarriers at the same time to reduce processing delays.

[0125] Exemplarily, the DFE transmission link and DFE reception link proposed in the embodiments of the present application meet the requirements of loading different physical layer waveform processing on the satellite terminal and meet the requirements of multi-carrier aggregation scenarios.

[0126] Furthermore, in order to compress logical resources, some modules in the DFE transmission link are improved as follows:

[0127] Optionally, any one of the fourth digital filter FIR0, the fifth digital filter FIR1 and the sixth digital filter FIR2 is used to: through a high-speed clock, perform a single multiplication operation and a single addition operation on each data element contained in the second serial data stream received by any filter, so as to obtain a filtering result of the second serial data stream; wherein the second serial data stream represents the data to be sent.

[0128] Optionally, the second mixing module MIX is used to mix the IQ complex signal output by the fifth digital filter FIR1 according to the coordinate rotation digital calculation method, or to mix the IQ complex signal output by the second integral comb line filter CIC, the second integral comb line filter CIC has an extended bit width that satisfies the interpolation multiple range, and the second imbalance correction module IQ is used to correct the IQ complex signal output by the carrier aggregation module COM according to a set second correction factor.

[0129] For example, see Fig. 9 As shown, it is a CIC interpolation filter, which first passes through a five-stage differentiator or is configured as a four-stage, then passes through an interpolator with an interpolation multiple of 1 to 255, and finally passes through a five-stage integrator or is configured as a four-stage. It can be seen that the CIC here is an interpolation filter used in the DFE digital transmission link, and the interpolation multiple can also be flexibly set.

[0130] It is not difficult to find that based on the above improvements to each module in the DFE transmission link, the resource consumption of the processing module is reduced by greatly compressing and reusing the computing resources.

[0131] In an optional implementation, the DFE receiving link and the DFE transmitting link each further include: a first power supply area and a second power supply area; wherein the first power supply area is used to provide power for a multi-carrier digital receiving channel and / or a multi-carrier digital transmitting channel, and the second power supply area is used to provide power for a single-carrier digital receiving channel and / or a single-carrier digital transmitting channel; in this way, through power supply partitioning and cross-clock domain processing, the power consumption of the chip circuit in different scenarios is further reduced, that is, multi-channel and single-channel partitions are designed for circuit power consumption, dynamic power consumption management is performed, and the overall power consumption of the circuit is further reduced.

[0132] For example, see Fig.10 As shown, the power partition layout of the 16-channel part (i.e., the multi-carrier digital receiving channel and the multi-carrier digital transmitting channel) and the single-channel part (i.e., the single-carrier digital receiving channel and the single-carrier data transmitting channel) is designed, and the power consumption control switch (e.g., PWR switch control) is designed to dynamically select whether the working area is powered on according to the scenario, thereby reducing the overall power consumption requirements of the DFE system or baseband chip.

[0133] Therefore, it should be noted that Figure 4 For the entire DFE receiving link and DFE transmitting link of the DFE system, FIFO is used to reduce the depth as much as possible and occupy less logic resources; for DC reception, DC bias will affect the signal quality of the receiving system, so it is necessary to use a certain correction factor to remove DC processing; IQ is used to correct the balance imbalance of the complex signal; DGC is used to adjust the amplitude of the signal; MIX is used for subcarrier frequency shifting; CIC reception is extraction and transmission is interpolation; FIR0 / FIR1 / FIR2 are digital filters with different order configurations and extraction and interpolation functions; COM represents signal merging.

[0134] Optionally, the multiple ports included in the DFE receiving link and the multiple ports included in the DFE transmitting link are designed according to a preset port design method. In this way, the multiple modules (such as MIX) included in the DFE receiving link and the DFE transmitting link are all set according to a unified port mirroring setting, unified module ports and layout, which is more conducive to integration, that is, cascading between modules.

[0135] For example, see Fig.11 As shown, the input interface includes input IQ complex signal, input valid signal and input ready signal; the output interface includes output IQ complex signal, output valid signal and output ready signal; other discrete signals are parameter configuration signals, and the parameter configuration of different modules will be different. Among them, the port definition of the module is shown in Table 1 below:

[0136] Table 1: Port definition of the module

[0137]

[0138] In addition, in the embodiment of the present application, the configurable matrix parameters of the DFE receiving link and the DFE transmitting link of the DFE system are shown in Table 2. The parameters of the DFE system are very flexible, the supported system modes are varied, and the functions are complete. Among them, the system mode is only an example, and more systems can be supported.

[0139] Table 2

[0140]

[0141]

[0142] See also Fig.12 As shown, the embodiment of the present application also provides a method for receiving data in a DFE receiving link. The execution subject takes RFIF as an example. The specific process of the method is as follows:

[0143] S1201: Determine a digital signal reception requirement associated with a data reception scenario of data to be received.

[0144] S1202: Determine a digital signal receiving channel for receiving data based on a digital signal receiving requirement.

[0145] The digital signal receiving channel is a multi-carrier digital receiving channel or a single-carrier digital receiving channel.

[0146] S1203: Receive data to be received through the digital signal receiving channel.

[0147] In an optional implementation, when executing step S1203, if the digital signal receiving channel is a multi-carrier digital receiving channel, the RFIP obtains the first carrier set corresponding to the digital signal reception requirement, thereby receiving the data to be received through the carrier digital receiving sub-channels corresponding to the multiple carriers included in the first carrier set in the multi-carrier digital receiving channel.

[0148] Based on the data receiving method of the DFE receiving link, after determining the digital signal receiving requirement associated with the data receiving scenario of the data to be received, the digital signal receiving channel corresponding to the digital signal receiving requirement can be determined according to the correspondence between the digital signal receiving requirement and the digital signal receiving channel, so that the data to be received is received through the determined digital signal receiving channel. In this way, the digital signal receiving requirements in various scenarios are met, that is, the communication needs in various scenarios are met.

[0149] See also Fig.13 As shown, the embodiment of the present application also provides a method for sending data of a DFE sending link, and the execution subject takes DMA as an example. The specific process of the method is as follows:

[0150] S1301: Determine a digital signal transmission requirement associated with a data transmission scenario of data to be transmitted;

[0151] S1302: Based on the digital signal sending requirement, determine a digital signal sending channel for the data to be sent.

[0152] Wherein, the digital signal transmission channel is a multi-carrier digital transmission channel or a single-carrier digital transmission channel;

[0153] S1303: Send the data to be sent through the digital signal sending channel.

[0154] In an optional implementation, when executing step S1303, if the digital signal transmission channel is a multi-carrier digital transmission channel, the DFE system obtains a second carrier set corresponding to the digital signal transmission requirement, thereby sending the data to be sent through the carrier digital transmission sub-channels corresponding to each of the multiple carriers included in the second carrier set in the multi-carrier digital transmission channel.

[0155] Based on the data sending method of the DFE sending link, after determining the digital signal sending requirements associated with the data sending scenario of the data to be sent, the digital signal sending channel corresponding to the digital signal sending requirements can be determined according to the correspondence between the digital signal sending requirements and the digital signal sending channels, so that the data to be sent is sent through the determined digital signal sending channel. In this way, the digital signal sending requirements in various scenarios are met, that is, the communication needs in various scenarios are met.

[0156] Further, see Fig.14 As shown, the embodiment of the present application further provides a DFE system, the DFE system comprising: a DFE receiving link and a DFE sending link;

[0157] The DFE receiving link includes: a multi-carrier digital receiving channel and a single-carrier digital receiving channel respectively connected to the receiving channel selection module; wherein the receiving channel selection module is configured to: select the multi-carrier digital receiving channel or the single-carrier digital receiving channel according to the digital signal receiving requirement corresponding to the data to be received;

[0158] The DFE transmission link includes: a multi-carrier digital transmission channel and a single-carrier digital transmission channel respectively connected to the transmission channel selection module; wherein the transmission channel selection module is configured to: select the multi-carrier digital transmission channel or the single-carrier digital transmission channel according to the digital signal transmission requirement corresponding to the data to be transmitted.

[0159] In the above embodiment, by connecting the multi-carrier digital receiving channel and the single-carrier digital receiving channel through the receiving channel selection module, the (multi-carrier / single-carrier) digital receiving channel that meets the digital signal receiving request corresponding to the data to be received can be selected from the multi-carrier digital receiving channel and the single-carrier digital receiving channel to perform data transmission processing of the data to be received; and by connecting the multi-carrier digital transmitting channel and the single-carrier digital transmitting channel through the transmitting channel selection module, the (multi-carrier / single-carrier) digital transmitting channel that meets the digital signal transmitting request corresponding to the data to be transmitted can be selected from the multi-carrier digital transmitting channel and the single-carrier digital transmitting channel to perform data transmission processing of the data to be transmitted; obviously, the above-mentioned DFE system is used for digital signal transmission, and a DFE system that can meet various communication requirements.

[0160] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A DFE receiving link, characterized in that: The DFE receiving link includes: A multi-carrier digital receiving channel and a single-carrier digital receiving channel respectively connected to a receiving channel selection module; wherein the receiving channel selection module is configured to: select the multi-carrier digital receiving channel or the single-carrier digital receiving channel according to the digital signal reception requirement corresponding to the data to be received.

2. The DFE receiving link according to claim 1, wherein: The multi-carrier digital receiving channel includes: a first first-in-first-out buffer module, a DC correction module and a plurality of carrier digital receiving sub-channels arranged in sequence; wherein each carrier digital receiving sub-channel includes: a first digital gain control module, a first mixing module, a first integral comb line filter, a first digital filter, a second digital filter, a first imbalance correction module, a third digital filter and a second first-in-first-out buffer module arranged in sequence.

3. The DFE receiving chain of claim 1, wherein: The single-carrier digital receiving channel includes: a first first-in-first-out buffer module, a DC correction module, a first digital gain control module, a first mixing module, a first integral comb line filter, a first digital filter, a second digital filter, a first unbalance correction module, a third digital filter and a second first-in-first-out buffer module which are arranged in sequence.

4. The DFE receiving link according to claim 2 or 3, characterized in that: Any one of the first digital filter, the second digital filter and the third digital filter is used to: perform a single multiplication operation and a single addition operation on each data element contained in the first serial data stream received by any one of the filters through a high-speed clock, so as to obtain a filtering result of the first serial data stream; wherein the first serial data stream represents the data to be received.

5. The DFE receiving link according to claim 2 or 3, wherein: The first mixing module is used to mix the IQ complex signal output by the first digital gain control module according to the coordinate rotation digital calculation method, the first integral comb line filter has an extended bit width that satisfies the extraction multiple range, and the first imbalance correction module is used to correct the IQ complex signal output by the first digital filter according to the set first correction factor.

6. The DFE receiving chain of claim 1, wherein: The DFE receiving link further includes: a first power supply area and a second power supply area; wherein the first power supply area is used to provide power for the multi-carrier digital receiving channel, and the second power supply area is used to provide power for the single-carrier digital receiving channel.

7. The DFE receiving chain of claim 1, wherein: The multiple ports included in the DFE receiving link are designed according to a preset port design method.

8. A DFE transmission link, characterized in that: The DFE transmission link includes: A multi-carrier digital transmission channel and a single-carrier digital transmission channel respectively connected to a transmission channel selection module; wherein the transmission channel selection module is configured to: select the multi-carrier digital transmission channel or the single-carrier digital transmission channel according to the digital signal transmission requirement corresponding to the data to be transmitted.

9. The DFE transmission link according to claim 8, wherein: The multi-carrier digital transmission channel includes: a plurality of carrier digital transmission sub-channels arranged in sequence, a carrier aggregation module, a second imbalance correction module and a third first-in-first-out buffer module; wherein each carrier digital receiving and transmitting sub-channel includes: a fourth first-in-first-out buffer module, a fourth digital filter, a fifth digital filter, a sixth digital filter, a second integral comb line filter, a second mixing module and a second digital gain control module arranged in sequence.

10. The DFE transmission link according to claim 8, wherein: The single-carrier digital transmission channel includes: a fourth first-in-first-out buffer module, a fourth digital filter, a fifth digital filter, a sixth digital filter, a second integral comb line filter, a second mixing module, a second digital gain control module, a second imbalance correction module and a third first-in-first-out buffer module, which are arranged in sequence.

11. The DFE transmission link according to claim 10, wherein: Any one of the fourth digital filter, the fifth digital filter and the sixth digital filter is used to: perform a single multiplication operation and a single addition operation on each data element contained in the second serial data stream received by any one of the filters through a high-speed clock, so as to obtain a filtering result of the second serial data stream; wherein the second serial data stream represents the data to be sent.

12. The DFE transmission link according to claim 10, wherein: The second mixing module is used to mix the IQ complex signal output by the fifth digital filter according to the coordinate rotation digital calculation method, or to mix the IQ complex signal output by the second integral comb line filter, the second integral comb line filter has an extended bit width that satisfies the interpolation multiple range, and the second imbalance correction module is used to correct the IQ complex signal output by the carrier aggregation module according to the set second correction factor.

13. The DFE transmission link according to claim 8, wherein: The DFE transmission link further includes: a first power supply area and a second power supply area; wherein the first power supply area is used to provide power for the multi-carrier digital transmission channel, and the second power supply area is used to provide power for the single-carrier digital transmission channel.

14. The DFE transmission link according to claim 8, wherein: The multiple ports included in the DFE transmission link are designed according to a preset port design method.

15. A data receiving method for a DFE receiving link, characterized in that: include: determining digital signal reception requirements associated with a data reception scenario for data to be received; Based on the digital signal reception requirement, determining the digital signal receiving channel of the data to be received; wherein the digital signal receiving channel is a multi-carrier digital receiving channel or a single-carrier digital receiving channel; The data to be received is received through the digital signal receiving channel.

16. The method according to claim 15, characterized in that The receiving the to-be-received data through the digital signal receiving channel includes: If the digital signal receiving channel is the multi-carrier digital receiving channel, acquiring a first carrier set corresponding to the digital signal receiving requirement; The data to be received is received through the carrier digital receiving sub-channels corresponding to each of the multiple carriers included in the first carrier set in the multi-carrier digital receiving channel.

17. A method for sending data in a DFE sending link, characterized in that: include: determining digital signal transmission requirements associated with a data transmission scenario for data to be transmitted; Based on the digital signal transmission requirement, determining the digital signal transmission channel of the data to be transmitted; wherein the digital signal transmission channel is a multi-carrier digital transmission channel or a single-carrier digital transmission channel; The data to be sent is sent through the digital signal sending channel.

18. The method according to claim 17, characterized in that The sending of the data to be sent through the digital signal sending channel includes: If the digital signal sending channel is the multi-carrier digital sending channel, acquiring a second carrier set corresponding to the digital signal sending requirement; The data to be sent is sent through the carrier digital sending sub-channels corresponding to each of the multiple carriers included in the second carrier set in the multi-carrier digital sending channel.

19. A DFE system, characterized in that: include: DFE receive link and DFE transmit link; The DFE receiving link comprises: a multi-carrier digital receiving channel and a single-carrier digital receiving channel respectively connected to a receiving channel selection module; wherein the receiving channel selection module is configured to: select the multi-carrier digital receiving channel or the single-carrier digital receiving channel according to a digital signal receiving requirement corresponding to the data to be received; The DFE transmission link includes: a multi-carrier digital transmission channel and a single-carrier digital transmission channel respectively connected to a transmission channel selection module; wherein the transmission channel selection module is configured to: select the multi-carrier digital transmission channel or the single-carrier digital transmission channel according to a digital signal transmission requirement corresponding to data to be transmitted.

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