Satellite terminal automatic test system and application method

Abstract

The embodiment of the application provides a satellite terminal automatic test system and an application method, wherein the satellite terminal automatic test system comprises a system main body, a first synchronous transmission board card and a second synchronous transmission board card; wherein the system main body is used for sending a test data sending instruction carrying original data to the first synchronous transmission board card; the first synchronous transmission board card is used for extracting the original data from the test data sending instruction and sending the original data to a test satellite terminal; the second synchronous transmission board card is used for receiving loopback data from a satellite terminal to be tested and sending the loopback data to the system main body; and the system main body is further used for comparing the loopback data with the original data, calculating a synchronous data transmission automatic test result, and realizing automatic test of a satellite terminal synchronous data service, thereby avoiding the problem of low test efficiency caused by a manual test scheme in the prior art.

Description

TECHNICAL FIELD

[0001] The embodiment of the present application relates to the technical field of satellite communication test, in particular to an automatic test system for synchronous data service of a satellite terminal and an application method. BACKGROUND

[0002] At present, some automatic test schemes for the performance indexes of satellite terminal radio frequency and protocols have appeared in the market, and the performance indexes of synchronous data service are still tested by manual mode. The manual test scheme compares error codes by receiving and transmitting random bit streams by an error code instrument, and then a tester records test results, so that the manual test scheme has high labor cost and low test efficiency. SUMMARY

[0003] The main purpose of the embodiment of the present application is to provide an automatic test system for a satellite terminal and an application method, which aims to test the performance indexes of synchronous data service by an automatic mode.

[0004] In a first aspect, an automatic test system for a satellite terminal is provided, which comprises a system main body, a first synchronous transmission board card and a second synchronous transmission board card, wherein,

[0005] The system main body is used for sending a test data sending instruction carrying original data to the first synchronous transmission board card.

[0006] The first synchronous transmission board card is used for extracting the original data from the test data sending instruction and sending the original data to a test satellite terminal.

[0007] The second synchronous transmission board card is used for receiving loopback data from a satellite terminal to be tested and sending the loopback data to the system main body, wherein the loopback data is data obtained by loopback transmission of the original data through the test satellite terminal, a satellite communication system radio frequency and the satellite terminal to be tested.

[0008] The system main body is further used for comparing the loopback data with the original data and calculating an automatic test result of synchronous data transmission.

[0009] By the system provided in the first aspect, the automatic test of the synchronous data service of the satellite terminal can be realized, and the problem of low test efficiency caused by the manual test scheme for testing the performance indexes of the synchronous data service in the prior art is avoided.

[0010] In a possible implementation manner, the system main body comprises a data management module, a test execution module and a front-end display module, wherein,

[0011] The data management module is used for processing system data, providing a unified encapsulated data management interface to other modules, and can integrate data of different sources and formats, realize centralized storage and management of data, facilitate sharing and access of data, improve data utilization and processing efficiency, reduce manual intervention, reduce error rate, and improve data processing speed and accuracy.

[0012] The test execution module is used for completing synchronous data transmission automation testing, can configure the synchronous transmission rate of the first synchronous transmission board and the second synchronous transmission board according to test parameters, reads the system data sample, sends the system data sample to the first synchronous transmission board, receives test data from the second synchronous transmission board through an external satellite communication system loopback, compares the test data with original data, and calculates a synchronous transmission automation test result. The test execution module can realize automation testing of satellite terminal synchronous data services, improve the efficiency and accuracy of the test process, reduce the dependence on manual operation and the risk of human error, and avoid the problem of low test efficiency caused by the manual test scheme for testing the performance indicators of synchronous data services in the prior art.

[0013] The front-end display module is used for providing a visual front-end display interface for users, managing the system data, monitoring and controlling the test process, and viewing the test process, test logs and test results. The front-end display module can display key information in the system to users in an intuitive manner, help users quickly obtain required information, and improve work efficiency.

[0014] In a possible implementation manner, the system data includes running data and test data.

[0015] The running data includes a local IP address and a port, a synchronous transmission board IP address and a port. The test data includes a synchronous transmission rate, a test data sample source, a test packet number, a sending bit number, a receiving bit number, a bit error number and a bit error rate.

[0016] In a possible implementation manner, the first synchronous transmission board and the second synchronous transmission board include the following components:

[0017] An instruction interaction module, a shared memory module and a synchronous transmission module. The instruction interaction module is used for test control instruction interaction and test data transceiving instruction interaction with the system main body, can complete efficient data processing and control through simplified instructions when processing complex computing tasks.

[0018] The instruction interaction module is used for test control instruction interaction and test data transceiving instruction interaction with the system main body, can complete efficient data processing and control through simplified instructions when processing complex computing tasks.

[0019] The shared memory module is used for data caching and cyclic read-write of other modules, the shared memory module can transmit data at the rising edge and the falling edge of each clock cycle, so as to realize double data transmission rate, improve the bandwidth of the memory, and enable the processor to access and process data faster;

[0020] The synchronous transmission module is used for transmitting test data in a synchronous mode, and also supports receiving data transmitted in a synchronous mode from a synchronous serial port;

[0021] The data block pointed to by the synchronous transmission module pointer is syncCnt, the data block pointed to by the instruction interaction module pointer is orderCnt, the length of a single data block is BlockLength, and the maximum count of data blocks is Max.

[0022] In a possible implementation manner, the system body communicates with the first synchronous transmission board card and the second synchronous transmission board card through a LAN connection line, and the first synchronous transmission board card and the second synchronous transmission board card both communicate with the satellite terminal to be tested and the satellite terminal for test through a synchronous serial port line.

[0023] In a second aspect, an application method of a satellite terminal automatic test system is provided, and is applied to a system body, a first synchronous transmission board card and a second synchronous transmission board card, and the method comprises the following steps:

[0024] The system body is connected with the first synchronous transmission board card and the second synchronous transmission board card;

[0025] The first synchronous transmission board card is connected with the satellite terminal for test, the second synchronous transmission board card is connected with the satellite terminal to be tested, and all the devices are powered on;

[0026] The system body configures test parameters and starts automatic test;

[0027] The system body sends a test data sending instruction carrying original data to the first synchronous transmission board card;

[0028] The first synchronous transmission board card extracts the original data from the test data sending instruction and sends the original data to the satellite terminal for test;

[0029] The second synchronous transmission board card receives loopback data from the satellite terminal to be tested;

[0030] The second synchronous transmission board card converts the loopback data into a test data receiving instruction form;

[0031] The second synchronous transmission board card sends the test data receiving instruction carrying the loopback data to the system main body, wherein the loopback data is data obtained by looping back the original data through the test satellite terminal, satellite communication system radio frequency and the satellite terminal to be tested;

[0032] The system main body is further configured to compare the loopback data with the original data and calculate a synchronous data transmission automation test result.

[0033] The method provided by the second aspect can realize automatic testing of synchronous data services of a satellite terminal, and avoids the problem of low testing efficiency caused by the fact that the performance indicators of synchronous data services are still tested by using a manual testing scheme in the prior art.

[0034] In a possible implementation manner, the first synchronous transmission board card extracts the original data from the test data sending instruction and applies the original data to an instruction interaction module, a shared memory module and a synchronous transmission module;

[0035] A data block count syncCnt pointed to by the synchronous transmission module pointer is set to zero;

[0036] A data block orderCnt pointed to by the instruction interaction module pointer is set to syncCnt+10;

[0037] The first synchronous transmission board card waits to receive a synchronous rate configuration instruction, and the instruction interaction module parses and sets a synchronous transmission rate, a test frame length and a synchronous sending interval;

[0038] The first synchronous transmission board card waits to receive a synchronous sending side configuration instruction, and a working mode is switched to a data sending mode;

[0039] The synchronous transmission module reads test data from a syncCnt position of the shared memory module and sends the test data to the outside through a synchronous serial port, and when a length of the test data reaches a length of a single data block BlockLength, the syncCnt of the shared memory module is circularly moved back by 1 bit, and the step is repeated;

[0040] The instruction interaction module listens to the test data sending instruction, parses the test data and writes the test data into a buffer, and if a length of data in the buffer exceeds 10*FrameLength and the first synchronous transmission board card satisfies the following conditions:

[0041] (orderCnt+10*FrameLength / BlockLength)mod Max<syncCnt, then read the test data of length 10*FrameLength from the buffer, write the test data from orderCnt position to the shared memory module in a circular manner, move the orderCnt backward by 10*FrameLength / BlockLength, wait for a time of SendInterval length, and repeat the step.

[0042] In a possible implementation, the second synchronous transmission board card converts the loopback data into a test data receiving instruction form and applies it to an instruction interaction module, a shared memory module and a synchronous transmission module.

[0043] Set the data block count syncCnt pointed to by the synchronous transmission module pointer to zero.

[0044] Set the data block orderCnt pointed to by the instruction interaction module pointer to zero.

[0045] The second synchronous transmission board card waits to receive a synchronization rate configuration instruction, and the instruction interaction module parses and sets a synchronous transmission rate, a test frame length and a synchronization sending interval.

[0046] The second synchronous transmission board card waits for a synchronization receiving side configuration instruction, and switches the working mode to a data receiving mode.

[0047] The synchronous transmission module obtains synchronization data from a synchronous serial port and writes the synchronization data from a syncCnt position to the shared memory module, and when the length of the synchronization data reaches a single data block length BlockLength, the syncCnt is moved backward by 1 bit in a circular manner, and the step is repeated.

[0048] If the second synchronous transmission board card satisfies the following condition:

[0049] (orderCnt+FrameLength / BlockLength)mod Max<syncCnt, then the instruction interaction module reads the synchronization data of length FrameLength from the orderCnt position of the shared memory module, encapsulates it into the test data receiving instruction, and sends it to the system main body, and the orderCnt of the shared memory module is moved backward by FrameLength / BlockLength in a circular manner, and the step is repeated.

[0050] In a third aspect, an electronic device is provided, including:

[0051] one or more processors;

[0052] a memory having stored thereon one or more programs, when executed by the one or more processors, cause the one or more processors to implement a method for applying a satellite terminal automated test system as described in any possible implementation of the second aspect.

[0053] In a fourth aspect, a computer-readable storage medium is provided, having stored thereon a computer program, which, when executed by a processor, implements a method for applying a satellite terminal automated test system as described in any possible implementation of the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0054] The accompanying drawings are included to provide a further understanding of the present application, and constitute a part of this specification that is made of the description of the application. The drawings illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application, but are not used to limit the present application.

[0055] Figure 1 A component architecture diagram of a satellite terminal automated test system provided by an embodiment of the present application is provided.

[0056] Figure 2 A component architecture diagram of a synchronous transmission board card of a satellite terminal automated test system provided by an embodiment of the present application is provided.

[0057] Figure 3 A flowchart of a method for applying a satellite terminal automated test system provided by an embodiment of the present application is provided.

[0058] Figure 4 A flowchart of a method for applying a satellite terminal automated test system provided by an embodiment of the present application is provided.

[0059] Figure 5 A flowchart of a method for applying a satellite terminal automated test system provided by an embodiment of the present application is provided.

[0060] Figure 6 A structural block diagram of an electronic device provided by an embodiment of the present application is provided. DETAILED DESCRIPTION

[0061] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0062] It should be noted that although the functional modules are divided in the device schematic diagram, and the logical sequence is shown in the flowchart, in some cases, the steps shown or described can be performed in a manner different from the module division in the device or the sequence in the flowchart. The terms "first", "second", and the like in the specification and claims and the above-described drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the specification is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the present application.

[0064] In addition, the technical features involved in each embodiment of the application described below can be combined with each other as long as there is no conflict. The embodiments of the application are further described below with reference to the accompanying drawings.

[0065] Please refer to Figure 1 , Figure 1 A satellite terminal automatic test system according to an embodiment of the application.

[0066] In a first aspect, as Figure 1 indicated, a satellite terminal automatic test system is provided, comprising: a system main body, a first synchronous transmission board card, and a second synchronous transmission board card.

[0067] The system main body is configured to send a test data sending instruction carrying original data to the first synchronous transmission board card.

[0068] It should be noted that the first synchronous transmission board card is configured to extract the original data from the test data sending instruction and send the original data to a test satellite terminal.

[0069] The second synchronous transmission board card is configured to receive loopback data from a satellite terminal under test and send the loopback data to the system main body, the loopback data being data obtained by transmitting the original data through the test satellite terminal, a satellite communication system radio frequency, and the satellite terminal under test.

[0070] The system main body is further configured to compare the loopback data with the original data and calculate a synchronous data transmission automatic test result.

[0071] The system provided in the first aspect enables automated testing of satellite terminal synchronous data services. It allows for customized test content and eliminates the need for a bit error rate tester, thus improving testing efficiency. This avoids the problems of high labor costs, low testing efficiency, and inability to customize test content that still require manual testing of synchronous data service performance indicators in existing technologies. This involves using a bit error rate tester to send and receive random bit streams for error comparison, followed by testers recording the test results.

[0072] like Figure 1 As shown, in one possible implementation, the main body of the system includes: a data management module, a test execution module, and a front-end display module;

[0073] The data management module is used to process system data and provide a unified, encapsulated data management interface to other modules. This module can integrate data from different sources and formats, enabling centralized storage and management, thus facilitating data sharing and access, improving data utilization and processing efficiency. Through this module, automated data processing, such as data cleaning, transformation, and loading, can be achieved, reducing manual intervention, lowering error rates, and improving the speed and accuracy of data processing.

[0074] The test execution module is used to complete automated testing of synchronous data transmission. It can configure the synchronous transmission rate of the first and second synchronous transmission boards according to test parameters, read the system data samples, send the system data samples to the first synchronous transmission board, and receive test data looped back through the external satellite communication system from the second synchronous transmission board. This data is then compared with the original data to calculate the automated synchronous transmission test result. The test execution module can automate the testing of satellite terminal synchronous data services, improving the efficiency and accuracy of the testing process, reducing reliance on manual operation and the risk of human error. It avoids the problem of low testing efficiency caused by the manual testing methods used in existing technologies to test the performance indicators of synchronous data services.

[0075] The front-end display module provides users with a visual interface for managing system data, monitoring and controlling the testing process, and viewing test progress, logs, and results. This module presents key system information intuitively, helping users quickly access necessary information, improving work efficiency, and providing robust support for user interaction with the computer system.

[0076] In one possible implementation, the system data includes operational data and test data.

[0077] In one embodiment, the running data includes, but is not limited to: local IP address and port, synchronous transmission board IP address and port, and the test data includes, but is not limited to: synchronous transmission rate, test data sample source, number of test packets, number of transmitted bits, number of received bits, number of erroneous bits, and bit error rate.

[0078] Those skilled in the art will understand that Figure 1 The structure shown is merely a partial structural diagram related to the embodiments of the present invention and does not constitute a limitation on the satellite terminal automated testing system applied thereto. A specific satellite terminal automated testing system may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0079] In one possible implementation, such as Figure 2 As shown, the structure of the first synchronous transmission board and the second synchronous transmission board includes:

[0080] The system includes an ARM-based instruction exchange module, a DDR-based shared memory module, and an FPGA-based synchronous transmission module.

[0081] The ARM-based instruction interaction module is used to exchange test control instructions and test data transmission and reception instructions with the main system. This ARM-based instruction interaction module can efficiently complete data processing and control through streamlined instructions when handling complex computational tasks.

[0082] The DDR-based shared memory module is used for data caching and cyclic read / write operations by other modules. The core advantage of this DDR-based shared memory module lies in its ability to transmit data on both the rising and falling edges of each clock cycle, thus achieving double the data transfer rate. This significantly increases memory bandwidth, enabling the processor to access and process data faster. Furthermore, the relatively low access latency of the DDR-based shared memory module allows the processor to respond to memory requests more quickly, improving the overall system response speed and performance.

[0083] The FPGA-based synchronous transmission module is used to send test data synchronously at the current synchronization rate, and also supports receiving data sent synchronously from external sources via the synchronous serial port. Due to the parallel processing capabilities of the FPGA, the FPGA-based synchronous transmission module can complete data synchronization and transmission with extremely low latency.

[0084] It should be noted that the data block pointed to by the synchronous transmission module pointer is syncCnt, the data block pointed to by the instruction interaction module pointer is orderCnt, the length of a single data block is BlockLength, and the maximum number of data blocks is Max.

[0085] As shown in Figure 1 and Figure 2 In one possible implementation, the system body communicates with the first synchronous transmission board card and the second synchronous transmission board card through a LAN connection line, and the first synchronous transmission board card and the second synchronous transmission board card both communicate with the satellite terminal to be tested and the satellite terminal for test through a synchronous serial port line.

[0086] The second aspect, as shown in Figure 3 provides an application method of a satellite terminal automatic test system, applied to a system body, a first synchronous transmission board card and a second synchronous transmission board card, and the method comprises the following steps:

[0087] S100, the system body is connected with the first synchronous transmission board card and the second synchronous transmission board card.

[0088] S200, the first synchronous transmission board card is connected with the satellite terminal for test, the second synchronous transmission board card is connected with the satellite terminal to be tested, and all the devices are powered on.

[0089] S300, the test parameter is configured in the front-end display interface in the system body.

[0090] It should be noted that the test parameter configured in the front-end display interface includes but is not limited to: test times, test packet number, synchronous transmission rate and synchronous transmission test sample source, and the synchronous data transmission test automation test is started.

[0091] S400, the test execution module in the system body starts to execute the automatic test based on the test parameter information sent by the front-end display interface.

[0092] S500, the test times are loaded, and the current test times are set to 0.

[0093] S600, the system body sends the synchronous transmission rate configuration instruction and the synchronous sending side configuration instruction to the first synchronous transmission board card, and sends the synchronous transmission rate configuration instruction and the synchronous receiving side configuration instruction to the second synchronous transmission board card.

[0094] It should be noted that the system body starts the test sending thread and the test receiving thread, binds the communication objects as the first synchronous transmission board card and the second synchronous transmission board card respectively, sends the synchronous transmission rate configuration instruction and the synchronous sending side configuration instruction to the first synchronous transmission board card, and sends the synchronous transmission rate configuration instruction and the synchronous receiving side configuration instruction to the second synchronous transmission board card.

[0095] S700, the system body sends a test data sending instruction carrying original data to the first synchronous transmission board card.

[0096] The test sending thread continuously sends the test data sending instruction to the first synchronous transmission board card, and records the number of sent bits and the number of sent packets.

[0097] S800, the first synchronous transmission board card extracts the original data from the test data sending instruction.

[0098] The first synchronous transmission board card analyzes the test data sending instruction, and sends the test data in a synchronous form through a synchronous serial port.

[0099] S900, the first synchronous transmission board card sends the original data to the test satellite terminal.

[0100] S1000, the second synchronous transmission board card receives the loopback data from the satellite terminal to be tested.

[0101] S1100, the second synchronous transmission board card converts the loopback data into a test data receiving instruction form.

[0102] S1200, the second synchronous transmission board card sends a test data receiving instruction carrying the loopback data to the system body, and the loopback data is data obtained by transmitting the original data through the test satellite terminal, the satellite communication system radio frequency and the satellite terminal to be tested.

[0103] The second synchronous transmission board card receives the test loopback data sent by the satellite terminal through a synchronous serial port, converts the test loopback data into a test data receiving instruction form, and sends the test data receiving instruction to the system body, which is parsed by the test receiving thread.

[0104] S1300, the system body compares the loopback data with the original data, and calculates the test results such as the number of received bits and the number of error bits in the synchronous data transmission automation.

[0105] S1400, if the test data packet is sent and the number of received bits does not change within a certain time, the test is ended, and the current test number is increased by 1.

[0106] S1500, it is judged whether the current test number has reached the preset test number, if yes, step S1600 is executed, and if not, step S600 is jumped to.

[0107] S1600, calculate a test bit error rate as a final test result, the bit error rate = the number of error bits / the number of transmitted bits.

[0108] The method provided by the second aspect can realize automatic testing of the satellite terminal synchronous data service, can define the test content, and does not need to rely on the error code instrument, improves the test efficiency, avoids the problem that the manual test scheme is still used to test the performance indicators of the synchronous data service in the prior art, the random bit stream is transmitted and received through the error code instrument to perform error code comparison, and then the tester records the test result, which leads to high labor cost and low test efficiency, and the test content cannot be defined.

[0109] In a possible implementation manner, as shown in FIG. 8, Figure 4 For step S800, the first synchronous transmission board card applies original data extracted from a test data sending instruction to an instruction interaction module, a shared memory module and a synchronous transmission module, which can specifically include the following steps.

[0110] S810, power on the first synchronous transmission board card and perform initialization.

[0111] S820, set the data block count syncCnt pointed to by the synchronous transmission module pointer to zero.

[0112] S830, set the data block orderCnt pointed to by the instruction interaction module pointer to syncCnt+10.

[0113] S840, the first synchronous transmission board card waits to receive a synchronous rate configuration instruction, the instruction interaction module parses and sets the synchronous transmission rate, the test frame length and the synchronous sending interval.

[0114] S850, the first synchronous transmission board card waits to receive a synchronous sending side configuration instruction, and the working mode is switched to a data sending mode.

[0115] S860, the synchronous transmission module performs step S861, and the instruction interaction module performs step S862.

[0116] S861, the synchronous transmission module reads the test data from the syncCnt position of the shared memory module, sends the test data to the outside through a synchronous serial port, when the length of the test data reaches the length of a single data block BlockLength, the syncCnt of the shared memory module is circularly moved back by 1 bit, and the step is repeated.

[0117] S862, the instruction interaction module listens to a test data sending instruction, parses the test data and writes the test data into a buffer, if the length of the data in the buffer exceeds 10*FrameLength, and the first synchronous transmission board card meets the following conditions:

[0118] (orderCnt+10*FrameLength / BlockLength)mod Max<syncCnt, then read test data from the buffer with length of 10*FrameLength, write the test data from orderCnt position to the shared memory module circularly, move orderCnt backward 10*FrameLength / BlockLength, wait for a time of SendInterval, repeat the step.

[0119] In one possible implementation, as shown in FIG. 11, for step S1100, the second synchronous transmission board card applies the loopback data to the instruction interaction module, the shared memory module and the synchronous transmission module in the form of test data receiving instruction, which can specifically include: Figure 5

[0120] S1110, power on the second synchronous transmission board card and perform initialization.

[0121] S1120, set the data block count syncCnt pointed by the synchronous transmission module pointer to zero.

[0122] S1130, set the data block orderCnt pointed by the instruction interaction module pointer to zero.

[0123] S1140, the second synchronous transmission board card waits for a synchronous receiving side configuration instruction, the instruction interaction module parses and sets the synchronous transmission rate, the test frame length and the synchronous sending interval.

[0124] S1150, the second synchronous transmission board card waits for a synchronous receiving side configuration instruction, and the working mode is switched to a data receiving mode.

[0125] S1160, the synchronous transmission module performs step S1161, and the instruction interaction module performs step S1162.

[0126] S1161, the synchronous transmission module obtains the synchronization data from the synchronous serial port, and writes the synchronization data from the syncCnt position to the shared memory module, when the length of the synchronization data reaches the length of a single data block BlockLength, the syncCnt is moved backward by 1 bit circularly, and the step is repeated.

[0127] S1162, if the second synchronous transmission board card meets the following conditions:

[0128] ​(orderCnt+FrameLength / BlockLength)mod Max<syncCnt, then the instruction interaction module reads the synchronization data of length FrameLength from the orderCnt position of the shared memory module, encapsulates as a test data receiving instruction, sends to the system main body, and the orderCnt of the shared memory module is circularly moved back by FrameLength / BlockLength bits. The step is repeated.

[0129] The embodiments of the present application also provide an electronic device, as shown in the figure, the electronic device 1400 includes: Figure 6

[0130] one or more processors 1410;

[0131] a memory 1420, on which one or more programs are stored, when the one or more programs are executed by the one or more processors 1410, the one or more processors 1410 implement the application method of the satellite terminal automatic test system provided by any one of the embodiments of the present application.

[0132] The memory 1420 is a kind of non-transient network system, and can be used to store non-transient software programs and non-transient computer executable programs.In addition, the memory 1420 can include high-speed random access memory, and can also include non-transient memory, such as at least one magnetic disk storage device, flash memory device, or other non-transient solid-state memory device.In some embodiments, the memory 1420 can optionally include a memory 1420 remotely arranged relative to the processor 1410, and these remote memories 1420 can be connected to the processor 1410 through a network.The above-mentioned network includes but is not limited to the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.

[0133] The memory 1420 can be realized in the form of read-only memory (ReadOnlyMemory, ROM), static storage device, dynamic storage device or random access memory (RandomAccessMemory, RAM).The memory 1420 can store operating system and other application programs, when the technology solution provided by the embodiments of the present application is realized by software or firmware, the related program codes are stored in the memory 1420, and the processor 1410 is called to execute the method of the embodiments of the present application.

[0134] ​The processor 1410 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an ASIC (Application Specific Integrated Circuit), or one or more integrated circuits, and is configured to execute related programs to implement the technical solutions provided by the embodiments of the present application.

[0135] In some embodiments, the electronic device further includes:

[0136] The input / output interface is configured to implement information input and output.

[0137] The communication interface is configured to implement communication interaction between the device and other devices, which can be achieved by wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0138] The bus is configured to transmit information between various components (such as the processor 1410, the memory 1420, the input / output interface, and the communication interface) of the device.

[0139] The processor 1410, the memory 1420, the input / output interface, and the communication interface can be connected to each other through the bus for internal communication within the device.

[0140] An embodiment of the present application also provides a computer readable storage medium storing computer executable instructions, which are used to execute the application method of the satellite terminal automatic test system provided by any one of the embodiments of the present application.

[0141] An embodiment of the present application also provides a computer program product including a computer program or computer instructions stored in a computer readable storage medium, and a processor of a computer device reads the computer program or computer instructions from the computer readable storage medium. The processor executes the computer program or computer instructions to make the computer device execute the application method of the satellite terminal automatic test system provided by any one of the embodiments of the present application.

[0142] The system architecture and application scenarios described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those skilled in the art can know that, with the evolution of system architecture and the appearance of new application scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0143] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing relevant hardware, and the computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, storage, databases, or other media in this application is intended to include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0144] Those skilled in the art can understand that all or some steps of the above-mentioned methods and systems can be implemented as software, firmware, hardware and appropriate combinations thereof. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, those skilled in the art know that communication media generally includes computer readable instructions, data structures, program modules or other data in modulated data signals such as carrier waves or other transmission mechanisms, and can include any information delivery medium.

[0145] The above describes some embodiments of the present application with reference to the accompanying drawings, and does not limit the scope of the present application. Any modification, equivalent replacement and improvement made by those skilled in the art without departing from the scope and essence of the present application shall be within the scope of the present application.

[0146] Those skilled in the art can understand that all or some steps in the above disclosed method, functional modules / units in the system and the device can be implemented as software, firmware, hardware and appropriate combinations thereof.

[0147] The terms "first", "second", "third", "fourth" and the like used in the description of the present application and the above drawings, if any, are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0148] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present separately, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0149] The above describes preferred embodiments of the embodiments of the present application with reference to the accompanying drawings, and does not limit the scope of the embodiments of the present application. Any modification, equivalent replacement and improvement made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall be within the scope of the embodiments of the present application.

Claims

1. A satellite terminal automated test system, characterized by, The system comprises a system body, a first synchronous transmission board card and a second synchronous transmission board card, wherein the system body is configured to send a test data sending instruction carrying original data to the first synchronous transmission board card; the first synchronous transmission board card is configured to extract the original data from the test data sending instruction and send the original data to a test satellite terminal; the second synchronous transmission board card is configured to receive loopback data from a to-be-tested satellite terminal and send the loopback data to the system body, the loopback data being data obtained by looping back the original data through the test satellite terminal, a satellite communication system radio frequency and the to-be-tested satellite terminal; the system body is further configured to compare the loopback data with the original data and calculate a synchronous data transmission automatic test result; the system body comprises a data management module, a test execution module and a front-end display module, wherein the data management module is configured to process system data and provide a unified encapsulated data management interface to other modules; the test execution module is configured to complete synchronous data transmission automatic testing; the front-end display module is configured to provide a visual front-end display interface, manage the system data, monitor and control a test process and view a test process, a test log and a test result; wherein the system data comprises running data and test data, the running data comprises a local IP address and a port, a synchronous transmission board card IP address and a port, and the test data comprises a synchronous transmission rate, a test data sample source, a test packet number, a sending bit number, a receiving bit number, a bit error number and a bit error rate. The first synchronous transmission board card and the second synchronous transmission board card comprise an instruction interaction module, a shared memory module and a synchronous transmission module, wherein 2. The satellite terminal automated testing system of claim 1, wherein, the instruction interaction module is configured to interact with the system body in test control instruction interaction and test data sending / receiving instruction interaction; the shared memory module is configured to provide data buffering and cyclic read / write for other modules; the synchronous transmission module is configured to send test data to the outside in a synchronous manner and also supports receiving data sent from the outside in a synchronous form from a synchronous serial port. The system body communicates with the first synchronous transmission board card and the second synchronous transmission board card through a LAN connection line, and the first synchronous transmission board card and the second synchronous transmission board card both communicate with the to-be-tested satellite terminal and the test satellite terminal through a synchronous serial port line. The method is applied to the system body, the first synchronous transmission board card and the second synchronous transmission board card, and comprises the following steps:

3. The satellite terminal automated testing system of claim 1, wherein, the system body is connected to the first synchronous transmission board card and the second synchronous transmission board card; 4. A method of applying a satellite terminal automated test system, characterized by, the first synchronous transmission board card is connected to a test satellite terminal, and the second synchronous transmission board card is connected to a to-be-tested satellite terminal; the system body configures test parameters and starts automatic testing; the system body sends a test data sending instruction carrying original data to the first synchronous transmission board card; the first synchronous transmission board card extracts the original data from the test data sending instruction and sends the original data to the test satellite terminal; the second synchronous transmission board card receives loopback data from the to-be-tested satellite terminal and sends the loopback data to the system body, the loopback data being data obtained by looping back the original data through the test satellite terminal, a satellite communication system radio frequency and the to-be-tested satellite terminal; ​ The second synchronous transmission board card receives loopback data from the satellite terminal to be tested; The second synchronous transmission board card converts the loopback data into a test data receiving instruction form; The second synchronous transmission board card sends the test data receiving instruction carrying the loopback data to the system main body, wherein the loopback data is data obtained by looping back the original data through the satellite terminal to be tested, a satellite communication system radio frequency and the satellite terminal to be tested; The system main body is further configured to compare the loopback data with the original data and calculate a synchronous data transmission automation test result.

5. The method of claim 4, wherein: The first synchronous transmission board card extracts the original data from the test data sending instruction and applies the original data to an instruction interaction module, a shared memory module and a synchronous transmission module, and the method comprises the following steps: Set the data block count syncCnt pointed to by the synchronous transmission module pointer to zero; Set the data block orderCnt pointed to by the instruction interaction module pointer to syncCnt+10; The first synchronous transmission board card waits to receive a synchronous transmission rate configuration instruction, and the instruction interaction module analyzes and sets a synchronous transmission rate, a test frame length and a synchronous sending interval; The first synchronous transmission board card waits to receive a synchronous sending side configuration instruction, and the working mode is switched to a data sending mode; The synchronization transmission module reads test data from the syncCnt position of the shared memory module, sends the test data to outside through a synchronization serial port, and when the length of the test data reaches the length of a single data block , the syncCnt of the shared memory module is circularly moved back by 1 bit, and the step is repeated. The instruction interaction module listens to the test data sending instruction, analyzes the test data and writes the test data into a buffer area, and if the data length of the buffer area exceeds 10*FrameLength and the first synchronous transmission board card meets the following conditions: If (orderCnt mod BlockLength) = 0, then read the test data of length 10*FrameLength from the buffer, write the test data from orderCnt position to the shared memory module, orderCnt is moved back 10*FrameLength / BlockLength bits, wait for a time of SendInterval length, repeat this step.

6. The method of claim 4, wherein: The second synchronous transmission board card converts the loopback data into a test data receiving instruction form and applies the loopback data to an instruction interaction module, a shared memory module and a synchronous transmission module, and the method comprises the following steps: Set the data block count syncCnt pointed to by the synchronous transmission module pointer to zero; Set the data block orderCnt pointed to by the instruction interaction module pointer to zero; The second synchronous transmission board card waits to receive a synchronous transmission rate configuration instruction, and the instruction interaction module analyzes and sets a synchronous transmission rate, a test frame length and a synchronous sending interval; The second synchronous transmission board card waits to receive a synchronous receiving side configuration instruction, and the working mode is switched to a data receiving mode; The synchronization transmission module acquires synchronization data from the synchronization serial port and writes the synchronization data from the syncCnt location into the shared memory module. When the length of the synchronization data reaches the length of a single data block... When this happens, the syncCnt loop shifts one position to the right and repeats this step. If the second synchronous transmission board card meets the following conditions: If the orderCnt is equal to the FrameLength, the instruction interaction module reads the synchronization data of the length of FrameLength from the orderCnt location of the shared memory module, encapsulates it as the test data receiving instruction, and sends it to the system body. The orderCnt of the shared memory module is moved back by FrameLength / BlockLength bits in a cycle, and this step is repeated. 7.An electronic device comprising: one or more processors; a memory having stored thereon one or more programs, which, when executed by the one or more processors, cause the one or more processors to implement an application method of the satellite terminal automation test system according to any one of claims 4-6. 8.A computer-readable storage medium having stored thereon a computer program, which, when executed by a processor, implements an application method of the satellite terminal automation test system according to any one of claims 4-6.

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