Adaptive 8K display system and method supporting AVS3 decoding

Abstract

The invention discloses a self-adaptive 8K display system and a self-adaptive 8K display method supporting AVS3 decoding. The display system comprises an internet access input module used for analyzing internet access data; the AVS3 data analysis module is used for analyzing the video data received by the network port input module based on the ARM processor; the AVS3 process control and scheduling module is used for acquiring a scheduling instruction by the ARM processor, dividing the analyzed video data into a plurality of parts according to a scheduling condition based on the scheduling instruction and then respectively writing the parts into different second DDR4 (Double Data Rate 4); the AVS3 decoding module is used for receiving the scheduling instruction based on an FPGA (Field Programmable Gate Array) device, and extracting corresponding analyzed video data from the second DDR4 based on the scheduling instruction for decoding; and the DDR4 cache module is used for caching data. The invention provides a self-adaptive 8K display system supporting AVS3 decoding, and the self-adaptive 8K display system supporting AVS3 decoding can support self-adaptive 8K display of AVS3 decoding.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an adaptive 8K display system and method supporting AVS3 decoding. Background Art

[0002] In the field of high-end display technology, 8K resolution combined with a high refresh rate of 60HZ or even 120HZ brings users an unprecedented visual experience, and this feature has quickly become the focus of market attention. However, the data volume of 8K60HZ / 120HZ video is extremely large without compression, which places extremely high demands on the bandwidth and transmission medium required for real-time transmission, greatly limiting its wide application in a large range.

[0003] With the increasing popularity of front-end 8K program sources and the continuous maturity of network transmission technology and set-top box receiving technology, how to achieve efficient 8K video transmission and display between the set-top box and the display end has become an urgent problem to be solved. In this context, it is particularly important to find a technology that can effectively compress the amount of 8K video data to reduce transmission requirements.

[0004] The AVS3 codec standard was created to solve this problem. This standard is mainly aimed at cutting-edge application fields such as ultra-high-definition broadcasting and film, panoramic video, augmented reality / virtual reality, and is also applicable to emerging fields such as autonomous driving, smart cities, smart medical care, and intelligent monitoring. It supports intelligent compression of ultra-high-resolution (8K and above) videos, as well as the application of various complex scenes such as panoramic video, three-dimensional video, screen mixed content video, high dynamic range video, and also covers the encoding requirements of immersive audio scenes. By using the AVS3 standard to compress ultra-high-resolution video, the amount of data that needs to be transmitted can be significantly reduced, thereby reducing the requirements for transmission bandwidth and media.

[0005] However, the current 8K display systems that support AVS3 decoding are all in sequential execution mode, the decoding method is very complex, and the processor running speed requirements are also very high, resulting in low decoding efficiency.

[0006] Therefore, the prior art still needs to be improved and enhanced. Summary of the invention

[0007] The main purpose of the present invention is to provide an adaptive 8K display system and method supporting AVS3 decoding, aiming to solve the problem that the decoding method of the 8K display system of AVS3 decoding in the prior art is very complicated, which makes the transmission of 8K video from the signal source such as the set-top box to the display end not fast enough and the decoding efficiency is low.

[0008] In order to achieve the above object, a first aspect of the present invention provides an adaptive 8K display system supporting AVS3 decoding, wherein the adaptive 8K display system supporting AVS3 decoding comprises:

[0009] The network port input module is used to parse network port data, identify and output 8K video data compressed by AVS3;

[0010] AVS3 data analysis module, used for analyzing the video data received by the network port input module based on the ARM processor to obtain scheduling data and analyzed video data;

[0011] AVS3 process control and scheduling module, used for extracting scheduling instructions from the scheduling data based on the ARM processor, and dividing the parsed video data into multiple copies according to the scheduling situation based on the scheduling instructions and writing them into different second DDR4s respectively;

[0012] An AVS3 decoding module, including a plurality of decoding modules, the number of which is the same as the number of the second DDR4, for receiving the scheduling instruction based on the FPGA device, and taking out the corresponding parsed video data from the second DDR4 for decoding based on the scheduling instruction, and writing the decoded video data into the corresponding second DDR4 after obtaining the decoded video data;

[0013] The DDR4 cache module includes a plurality of second DDR4s, and the plurality of second DDR4s are used to store the parsed video data and the decoded video data in partitions based on the scheduling instruction.

[0014] In one implementation, the adaptive 8K display system supporting AVS3 decoding further includes:

[0015] A video data reading module, configured to read the decoded video data from the plurality of second DDR4s in an image display order according to the scheduling instruction;

[0016] A resolution scaling module, used for scaling the decoded video data according to the resolution information of the back-end display device;

[0017] The video interface output module is used to output the scaled video data.

[0018] In one implementation, the AVS3 decoding module includes a plurality of slice decoding modules, and the plurality of slice decoding modules are used to decode the parsed video data simultaneously.

[0019] In a second aspect, the present invention further provides an adaptive 8K display method supporting AVS3 decoding, wherein the adaptive 8K display method supporting AVS3 decoding comprises:

[0020] Receive target video data, parse the target video data, and obtain target parameters and target parsed video data, wherein the target video data is 8K video data compressed by AVS3;

[0021] Obtaining target scheduling data and target decoding parameters based on the target parameters, and acquiring target scheduling instructions based on the target scheduling data;

[0022] Dividing the target parsed video data into a plurality of groups of data to be decoded based on the target scheduling instruction;

[0023] Based on the target decoding parameters, the plurality of groups of data to be decoded are decoded respectively to obtain target decoded video data.

[0024] In one implementation, parsing the target video data to obtain target parameters and target parsed video data includes:

[0025] The AVS3 encoded code stream data in the target video data is entropy decoded to obtain the target parameters and the target parsed video data, wherein the target parameters are parameter information of non-video encoded data obtained by entropy decoding the target video data, and the target parsed video data are encoding mode information, inter-frame motion information and encoded video data obtained by entropy decoding the target video data.

[0026] In one implementation, decoding the plurality of groups of data to be decoded based on the target decoding parameter to obtain target decoded video data includes:

[0027] When the target AVS3 decoding module performs decoding, the target data to be decoded is extracted from the target second DDR4 based on the target scheduling instruction, and the target data to be decoded is decoded based on the target decoding parameters to obtain the target decoded video data corresponding to the target AVS3 decoding module.

[0028] In one implementation, extracting target data to be decoded from the target second DDR4 based on the target scheduling instruction, and decoding the target data to be decoded based on the target decoding parameter, includes:

[0029] Dividing the target data to be decoded into a plurality of groups of picture groups to be decoded, each group of the picture groups to be decoded includes a target number of frame data;

[0030] Based on the target scheduling instruction and the target decoding parameters, each group of the target to-be-decoded picture groups is extracted and decoded in the video order of the target video, and then returned to the target second DDR4.

[0031] In one implementation, after obtaining the target decoded video data, the method further includes:

[0032] Get the target resolution of the backend display device;

[0033] Scaling the target decoded video data based on the target resolution to obtain target output video data, wherein the resolution of the target output video data is the same as the target resolution;

[0034] The target output video is output.

[0035] In one implementation, the outputting the target output video includes:

[0036] Based on the target scheduling instruction, pictures are extracted from the plurality of second DDR4s for output in a picture display order.

[0037] According to the third aspect of the present invention, an embodiment of the present invention further provides a terminal device, wherein the terminal device includes a memory, a processor, and an adaptive 8K display program supporting AVS3 decoding that is stored in the memory and can be run on the processor, and when the processor executes the adaptive 8K display program supporting AVS3 decoding, the steps of the adaptive 8K display method supporting AVS3 decoding described in the above scheme are implemented.

[0038] A fourth aspect of the present invention provides a storage medium, wherein the storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of any of the above-mentioned adaptive 8K display methods supporting AVS3 decoding.

[0039] Beneficial effect: Compared with the prior art, the present invention provides an adaptive 8K display system and method supporting AVS3 decoding. The adaptive 8K display system supporting AVS3 decoding provided by the present invention includes: a network port input module, which is used to perform network port data parsing, identify and output 8K video data compressed by AVS3; an AVS3 data parsing module, which is used to parse the video data received by the network port input module based on the ARM processor to obtain scheduling data and parsed video data; an AVS3 process control and scheduling module, which is used to extract scheduling instructions from the scheduling data based on the ARM processor, and divide the parsed video data into multiple parts according to the scheduling situation based on the scheduling instructions and write them into different second DDR4s respectively; an AVS3 decoding module, including multiple groups of decoding modules, the number of which is the same as the number of second DDR4s, for receiving the scheduling instructions based on an FPGA device, and taking out the corresponding parsed video data from the second DDR4 based on the scheduling instructions for decoding, and writing the decoded video data into the corresponding second DDR4 after obtaining the decoded video data; a DDR4 cache module, including multiple second DDR4s, which are used to partition and store the parsed video data and the decoded video data based on the scheduling instructions. The present invention provides users with an adaptive 8K display system that supports AVS3 decoding, which solves the problem that the decoding method of the 8K display system with AVS3 decoding in the prior art is very complicated, making the transmission of 8K video from the source such as the set-top box to the display terminal not fast enough and the decoding efficiency low. The adaptive 8K display that can support AVS3 high-efficiency decoding brings users a higher-definition viewing experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 A system structure principle diagram of an embodiment of an adaptive 8K display system supporting AVS3 decoding provided by the present invention;

[0041] Figure 2 A hardware architecture diagram of an embodiment of an adaptive 8K display system supporting AVS3 decoding provided by the present invention;

[0042] Figure 3 A display flow chart of an embodiment of an adaptive 8K display system supporting AVS3 decoding provided by the present invention;

[0043] Figure 4 A schematic diagram of a decoding module in an embodiment of an adaptive 8K display system supporting AVS3 decoding provided by the present invention;

[0044] Figure 5 An implementation flow chart of an embodiment of an adaptive 8K display method supporting AVS3 decoding provided by the present invention;

[0045] Figure 6A detailed flow chart of an embodiment of an adaptive 8K display method supporting AVS3 decoding provided by the present invention;

[0046] Figure 7 A decoding data flow diagram of an embodiment of an adaptive 8K display method supporting AVS3 decoding provided by the present invention;

[0047] Figure 8 A functional block diagram of a terminal device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0049] Embodiment 1

[0050] In the field of high-end display technology, 8K resolution combined with a high refresh rate of 60HZ or even 120HZ brings users an unprecedented visual experience, and this feature has quickly become the focus of market attention. However, the data volume of 8K60HZ / 120HZ video is extremely large without compression, which places extremely high demands on the bandwidth and transmission medium required for real-time transmission, greatly limiting its wide application in a large range.

[0051] With the increasing popularity of front-end 8K program sources and the continuous maturity of network transmission technology and set-top box receiving technology, how to achieve efficient 8K video transmission and display between the set-top box and the display end has become an urgent problem to be solved. In this context, it is particularly important to find a technology that can effectively compress the amount of 8K video data to reduce transmission requirements.

[0052] The AVS3 codec standard was created to solve this problem. This standard is mainly aimed at cutting-edge application fields such as ultra-high-definition broadcasting and film, panoramic video, augmented reality / virtual reality, and is also applicable to emerging fields such as autonomous driving, smart cities, smart medical care, and intelligent monitoring. It supports intelligent compression of ultra-high-resolution (8K and above) videos, as well as the application of various complex scenes such as panoramic video, three-dimensional video, screen mixed content video, high dynamic range video, and also covers the encoding requirements of immersive audio scenes. By using the AVS3 standard to compress ultra-high-resolution video, the amount of data that needs to be transmitted can be significantly reduced, thereby reducing the requirements for transmission bandwidth and media.

[0053] It is particularly worth mentioning that AVS3 is a source coding standard independently developed by my country with independent intellectual property rights. In view of this, in this embodiment, an innovative adaptive 8K display system supporting AVS3 decoding is proposed. The adaptive 8K display system supporting AVS3 decoding can receive the AVS3-encoded compressed 8K video source transmitted by the front-end set-top box and other sources through the Gigabit network port, then perform decoding processing, and finally achieve real-time output, providing a more convenient and fast solution for the efficient transmission and display of 8K video.

[0054] Specifically, Figure 1 As shown, the adaptive 8K display system supporting AVS3 decoding provided by this embodiment includes:

[0055] The network port input module is used to parse network port data, identify and output 8K video data compressed by AVS3;

[0056] AVS3 data analysis module, used for analyzing the video data received by the network port input module based on the ARM processor to obtain scheduling data and analyzed video data;

[0057] AVS3 process control and scheduling module, used for extracting scheduling instructions from the scheduling data based on the ARM processor, and dividing the parsed video data into multiple copies according to the scheduling situation based on the scheduling instructions and writing them into different second DDR4s respectively;

[0058] An AVS3 decoding module includes multiple groups of decoding modules, the number of the decoding modules is the same as the number of the second DDR4, and is used to receive the scheduling instruction based on the FPGA device, and take out the corresponding parsed video data from the second DDR4 based on the scheduling instruction for decoding, and write the decoded video data into the corresponding second DDR4 after obtaining the decoded video data; a DDR4 cache module includes multiple second DDR4s, and the multiple second DDR4s are used to partition and store the parsed video data and the decoded video data based on the scheduling instruction.

[0059] The adaptive 8K display system supporting AVS3 decoding also includes:

[0060] A video data reading module, configured to read the decoded video data from the plurality of second DDR4s in an image display order according to the scheduling instruction;

[0061] A resolution scaling module, used for scaling the decoded video data according to the resolution information of the back-end display device;

[0062] The video interface output module is used to output the scaled video data.

[0063] Specifically, refer to Figure 1The adaptive 8K display system supporting AVS3 decoding provided in this embodiment is mainly composed of the following parts: the network port input module, the AVS3 data parsing module, the AVS3 decoding module, the AVS3 process control and scheduling module, the video data reading module, the DDR4 cache module, including one of the first DDR4 and multiple of the second DDR4, the resolution scaling module, and the video interface output module. In this embodiment, the HDMI interface module is taken as an example. In more embodiments, the adaptive 8K display system supporting AVS3 decoding can also support other video output interface modules such as HDMI / DP / VBYONE.

[0064] Specifically, when the adaptive 8K display system supporting AVS3 decoding receives the data from the network port input module, it will first parse the network port data, identify and output AVS3 encoded video data.

[0065] Then, the video data enters the AVS3 data parsing module for AVS3 data parsing to obtain scheduling data and parsed video data. In this embodiment, the AVS3 data parsing is to perform entropy decoding on the video data. The parsed parsed video data is written into the corresponding DDR4 according to the scheduling situation in the scheduling data.

[0066] Reference Figure 1 It can be seen that, in this embodiment, the DDR4 cache module is mainly used to store the parsed video data and the decoded video data based on the scheduling instruction partitions.

[0067] Specifically, the DDR4 cache module includes a first DDR4 and multiple second DDR4s, wherein the first DDR4 is connected to the AVS3 data parsing module and is mainly used to store data required by the AVS3 data parsing module, and the multiple second DDR4s are simultaneously connected to the AVS3 data parsing module and the AVS4 decoding module and are used to store the parsed video data and the decoded video data based on the scheduling instruction partitions.

[0068] Specifically, the analyzed video data analyzed by the AVS3 data analysis module will be written into the corresponding second DDR4 according to the scheduling situation in the scheduling data. Figure 1 In this embodiment, two second DDR4s are taken as an example, the first one is the second DDR4_1, and the second one is the second DDR4_2. The parsed video data parsed by the AVS3 data parsing module will be divided into two parts according to the scheduling data and stored in the two second DDR4s respectively.

[0069] Then, in the decoding stage, different AVS3 decoding modules take out data from the corresponding second DDR4, perform AVS3 decoding, and obtain decoded video data. That is to say, in this embodiment, each of the AVS3 decoding modules corresponds to a second DDR4 module, and each of the AVS3 only reads the corresponding parsed video data from the corresponding second DDR4 for decoding, and returns the decoded video data to the corresponding second DDR4. In this way, two groups of DDR4 are used for data storage and transfer. Using two groups of DDR4 can double the read and write bandwidth and storage space, and the data exchange in the AVS3 decoding link can be cached using DDR4. At the same time, through reasonable cache scheduling, the two groups of decoding modules and their corresponding DDR4 modules are independent of each other and can perform synchronous frame decoding, which increases the time for decoding one frame and further realizes 8K60Hz real-time decoding.

[0070] Specifically, after the decoded video data is continuously written into the corresponding DDR4 after decoding, the video data reading module can read the decoded video data from the second DDR4 corresponding to the image frame according to the scheduling instruction and the image display order.

[0071] Then, the resolution scaling module obtains the resolution information of the back-end display device, scales the decoded video data accordingly according to the resolution information of the back-end display device, and finally outputs the scaled video data from the video interface output module, such as HDMI or other video interfaces.

[0072] Reference Figure 2 , the adaptive 8K display system supporting AVS3 decoding receives an 8K video signal compressed by AVS3 from a gigabit network port, then performs AVS3 decoding and scaling on the video signal, and then outputs it through a video interface such as HDMI / DP / VBYONE at a resolution adapted to the display. Compared with a 4K video signal, the pixel count of an 8K video signal has increased by 4 times, and a higher compression ratio is required to transmit the 8K video signal on a gigabit network port, which undoubtedly greatly increases the complexity of encoding and decoding and the amount of encoding and decoding data. In order to achieve 8K decoding with higher data volume and higher complexity, the present invention proposes a hardware architecture of ARM+FPGA+multiple groups of DDR4 to achieve AVS3 decoding of multiple video signals such as 8K60Hz / 120Hz.

[0073] Specifically, refer to Figure 3The adaptive 8K display system supporting AVS3 decoding adopts the hardware architecture of ARM+FPGA+multiple groups of DDR4. The ARM part is a hard core embedded in the FPGA. The ARM processor is good at sequential processing and control work, the FPGA is good at parallel processing, and the DDR4 is characterized by high bandwidth and large storage. Therefore, the network port data parsing and AVS3 data parsing that need to be executed sequentially and the AVS3 process control module for control scheduling are placed on the ARM side, and the AVS3 decoding process that can be processed in parallel is placed on the FPGA side for execution, and then the data at both ends and between modules are stored and exchanged through DDR4.

[0074] During the entire video display process, the ARM part is responsible for network port data analysis, AVS3 data analysis, and the AVS3 process control module responsible for scheduling the entire decoding process. The data storage and transfer part is handled by two sets of DDR4 outside the chip, and the rest is handled by the FPGA part.

[0075] Further, refer to Figure 4 The AVS3 decoding module includes multiple slice decoding modules, and the multiple slice decoding modules are used to decode the parsed video data simultaneously to reduce the amount of data that needs to be decoded by a single decoding module.

[0076] Specifically, in this embodiment, there are multiple slice decoding modules inside the AVS3 decoding module. Since FPGA is good at parallel processing, the multiple slice decoding modules can perform video decoding at the same time, which reduces the amount of data that needs to be decoded by a single decoding module, that is, reduces the number of clock cycles required for a single decoding module to decode a frame of data, speeds up the decoding speed of the entire frame of data, and realizes real-time decoding of 8K60Hz video.

[0077] It can be seen that this embodiment uses the hardware architecture of ARM+FPGA+multiple groups of DDR4, taking advantage of the sequential execution and control scheduling of ARM, and the parallel processing capabilities of FPGA, to achieve AVS3 real-time decoding of 8K60Hz video. At the same time, multiple groups of DDR4 cache structures are used to double the bandwidth and data storage capacity. Through reasonable scheduling, parallel decoding of multiple GOPs is achieved, and the decoding time of a group of GOPs is increased, so that AVS3 real-time decoding of up to 8K / 120Hz video can be achieved. Furthermore, by using the DDR4 cache system and scaling module, multiple interfaces (HDMI / DP / VBONE and other video output interfaces) and adaptive display of arbitrary resolution and frame rate are realized, and direct drive of various modules of up to 8K LCD / OLED is realized.

[0078] Furthermore, the adaptive 8K display system supporting AVS3 decoding disclosed in this embodiment supports AVS3 decoding, so that video input can use a more flexible and inexpensive Gigabit network port, which can adapt to more video source devices and save development costs. At the same time, according to the devices with different resolutions or different video interfaces at the back end, the corresponding video interface can be used to output the decoded video data of the corresponding resolution, frame rate and interface, thereby increasing the use scenarios of the device and further saving development costs.

[0079] In summary, the present embodiment provides an adaptive 8K display system supporting AVS3 decoding, including a network port input module, the network port input module is used to perform network port data analysis, identify and output 8K video data compressed by AVS3; it also includes an AVS3 data analysis module, the AVS3 data analysis module is used to analyze the video data received by the network port input module, obtain scheduling data and analyzed video data, and further includes an AVS3 process control and scheduling module, the AVS3 process control and scheduling module is used to obtain scheduling instructions based on the scheduling data and divide the analyzed video data into Multiple copies are written into different second DDR4s respectively; AVS3 decoding module, including multiple sets of decoding modules, the number of the decoding modules is the same as the number of the second DDR4, and is used to take out the corresponding parsed video data from the corresponding second DDR4 based on the scheduling instruction and decode it to obtain decoded video data; further, it also includes a DDR4 cache module, the DDR4 cache module includes a first DDR4 and multiple second DDR4s, the first DDR4 is used to store the data required by the AVS3 data parsing module, and the multiple second DDR4s are used to partition and store the parsed video data and the decoded video data based on the scheduling instruction. This embodiment provides users with an adaptive 8K display system that supports AVS3 decoding, which solves the problem that the decoding method of the 8K display system with AVS3 decoding in the prior art is very complicated, which makes the transmission of 8K video from the source such as the set-top box to the display end not fast enough and the decoding efficiency is low. The adaptive 8K display that can support AVS3 decoding brings users a higher-definition viewing experience.

[0080] Embodiment 2

[0081] Based on the above embodiments, the present invention also provides an adaptive 8K display method supporting AVS3 decoding, such as Figure 5 As shown, the multi-core homogeneous display method provided in this embodiment includes the steps of:

[0082] S100, receiving target video data, parsing the target video data, obtaining target parameters and target parsed video data, wherein the target video data is 8K video data compressed by AVS3.

[0083] The step of parsing the target video data to obtain target parameters and target parsed video data includes:

[0084] The AVS3 encoded code stream data in the target video data is entropy decoded to obtain the target parameters and the target parsed video data, wherein the target parameters are parameter information of non-video encoded data obtained by entropy decoding the target video data, and the target parsed video data are encoding mode information, inter-frame motion information and encoded video data obtained by entropy decoding the target video data.

[0085] Specifically, refer to Figure 6 In one embodiment, after the video data enters the adaptive 8K display system supporting AVS3 decoding, it is first decoded through the network port to obtain the original bit stream data. The original bit stream data is the 8K video data compressed by AVS3.

[0086] The original code stream data, that is, the target video data, is passed to the AVS3 data parsing module to parse the target video data. In this embodiment, the parsing of the target video data is to entropy decode the AVS3 coded code stream data in the target video data.

[0087] Among them, the parameter information of the non-video coding data parsed from the target video data is the target parameter. Furthermore, the target scheduling data and target decoding parameters can be obtained based on the target parameters, and the target scheduling data will be input into the AVS3 process control and scheduling module, and the AVS3 process control and scheduling module will control the decoding process according to the parameter information in the target scheduling data. The target decoding parameters are used for subsequent decoding. The remaining parsed coding mode information, inter-frame motion information, coded video data and other coded video data are the target parsed video data, which are used to split into data to be decoded.

[0088] S200, obtaining target scheduling data and target decoding parameters based on the target parameters, and acquiring target scheduling instructions based on the target scheduling data;

[0089] S300: Divide the target parsed video data into multiple groups of data to be decoded based on the target scheduling instruction.

[0090] After parsing the target parsed video data, the AVS3 process control and scheduling module will analyze the target scheduling data and the target decoding parameters based on the target parameters, and analyze the target scheduling instructions based on the target scheduling data, so as to control the decoding process of the target parsed video data based on the target scheduling instructions, determine which decoding module the different data in the target parsed video data corresponds to, and then write them into the DDR4 cache module corresponding to the corresponding decoding module.

[0091] S400 , decoding the plurality of groups of data to be decoded respectively based on the target decoding parameters to obtain target decoded video data.

[0092] The step of respectively decoding the plurality of groups of data to be decoded based on the target decoding parameters to obtain target decoded video data comprises:

[0093] When the target AVS3 decoding module performs decoding, the target data to be decoded is extracted from the target second DDR4 based on the target scheduling instruction, and the target data to be decoded is decoded based on the target decoding parameters to obtain the target decoded video data corresponding to the target AVS3 decoding module.

[0094] The step of extracting target data to be decoded from the target second DDR4 based on the target scheduling instruction, and decoding the target data to be decoded based on the target decoding parameter includes:

[0095] Dividing the target data to be decoded into a plurality of groups of picture groups to be decoded, each group of the picture groups to be decoded includes a target number of frame data;

[0096] Based on the target scheduling instruction and the target decoding parameters, each group of the target to-be-decoded picture groups is extracted and decoded in the video order of the target video, and then returned to the target second DDR4.

[0097] Specifically, refer again to Figure 4 It can be seen that there are multiple slice decoding modules inside the AVS3 decoding module. Due to the parallel processing characteristics of FPGA, these multiple slice decoding modules can perform video decoding at the same time, which reduces the amount of data that needs to be decoded by a single decoding module, that is, reduces the number of clock cycles required for a single decoding module to decode a frame of data, speeds up the decoding speed of the entire frame of data, and realizes real-time decoding of 8K60Hz video.

[0098] Further, refer to Figure 7 In this embodiment, a DDR4 frame buffer subsystem is also included, which can realize arbitrary frame rate switching display, which is helpful to solve the problem of unstable frame rate of instantaneous streaming pictures output by AVS3 decoding.

[0099] Specifically, in the process of decoding by the AVS3 decoding module, each link is carried out independently, and data caching and exchange are performed only through a single second DDR4 corresponding to a single decoding module. That is to say, after the AVS3 code stream data, that is, the target video data is input, after being parsed by the AVS3 data parsing module, different data types have been stored in the corresponding second DDR4 based on the target scheduling instruction, and then after the target number of frame data is cached in the corresponding second DDR4, the AVS3 decoding module is controlled to extract the target number of frame data from the corresponding second DDR4 to start decoding. Finally, after the AVS3 decoding module decodes the frames of the target number of data, the frame data is controlled to be read out in the display order. In this embodiment, the target number is not limited. The larger the target number, the less likely it is to be stuck, but a higher storage capacity is required; if the target number is smaller, the cache speed is faster, and the user can see the display screen faster.

[0100] Through such cache isolation, the decoding speed of each decoding link is not affected by the speed of the upstream and downstream links in the decoding process and the instability of the AVS3 code stream input bit rate, and the decoded picture can be output at a stable frame rate. At the same time, because of the DDR4 cache isolation, the bit rate of the input code stream and the frame rate of the decoded video output can be switched arbitrarily, ensuring the smooth switching display between low-bit rate pictures with single details and high-bit rate pictures with complex details, and the decoded output frame rate is adaptively switched and displayed according to the frame rate supported by the back-end display device.

[0101] according to Figure 7 As shown, in this embodiment, two groups of DDR4 are used as an example for data storage and transfer. Using two groups of DDR4 can double the read and write bandwidth and storage space, so that the data exchange in the AVS3 decoding link can be cached using DDR4. At the same time, through reasonable cache scheduling, the two groups of decoding modules and their corresponding DDR4 modules are independent of each other and can perform synchronous frame decoding, which increases the time for one frame decoding and further realizes 8K60Hz real-time decoding.

[0102] Specifically, the frame decoding of AVS3 is performed in units of a group of GOP (frame sequence), that is, a group of picture groups to be decoded. Each group of picture groups to be decoded is decoded independently, without reference to each other or affecting each other. Therefore, different picture groups to be decoded can be decoded at the same time, taking advantage of this feature and benefiting from the large cache capacity of DDR4.

[0103] It can be seen that in this embodiment, the to-be-decoded picture group is used as a unit, and scheduling is performed between two groups of decoding modules plus a DDR4 cache module. After the AVS3 parsing module parses the data, it determines which group of decoding modules the data of the current GOP belongs to according to the instructions of the AVS3 process control module, writes it into the corresponding DDR4 cache module, and then controls the corresponding decoding module to decode. After the decoding is completed, the decoded data is written back to the corresponding DDR4 cache module, and then the video reading module is controlled to read out from the corresponding DDR4 cache module in the display order.

[0104] In this way, by introducing the DDR4 frame buffer subsystem, data exchange between modules is carried out through the DDR4 data cache, so that the decoding modules do not interfere with each other, and arbitrary frame rate switching display can be achieved, solving the problem of unstable frame rate of instantaneous streaming images output by AVS3 decoding, and ensuring smooth switching display between low-bitrate images with single details and high-bitrate images with complex details.

[0105] After obtaining the target decoded video data, the method further includes:

[0106] Get the target resolution of the backend display device;

[0107] Scaling the target decoded video data based on the target resolution to obtain target output video data, wherein the resolution of the target output video data is the same as the target resolution;

[0108] The target output video is output.

[0109] Specifically, after the AVS3 decoding module completes decoding, the decoded video data is read out according to the image display order.

[0110] After reading out the decoded video data, the target resolution of the back-end display device is obtained, and the target decoded video data is scaled based on the target resolution to obtain target output video data, the resolution of the target output video data is the same as the target resolution, and finally output from a video interface such as HDMI.

[0111] In summary, this embodiment provides an adaptive 8K display method supporting AVS3 decoding. When displaying an 8K video compressed by AVS3, the target video data is received, the target video data is parsed, and target scheduling data and target parsed video data are obtained. The target video data is 8K video data compressed by AVS3. Then, a target scheduling instruction is obtained based on the target scheduling data, and the target parsed video data is divided into multiple groups of data to be decoded based on the target scheduling instruction. Finally, the multiple groups of data to be decoded are decoded respectively to obtain target decoded video data. This embodiment provides users with an adaptive 8K display method supporting AVS3 decoding, which solves the problem that the amount of 8K video data is too large and the AVS3 compression ratio is too high during efficient 8K video transmission between the set-top box and the display terminal in the prior art, resulting in a doubling of the decoding complexity and data volume. It can support adaptive 8K display with AVS3 decoding, bringing users a higher-definition viewing experience.

[0112] It should be understood that, although the various steps in the flowcharts given in the accompanying drawings of the present invention are displayed in sequence according to the indications of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of the steps in the present invention is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps of the present invention may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0113] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by signaling related hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided by the present invention can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0114] Embodiment 3

[0115] Based on the above embodiments, the present invention further provides a terminal device, the principle block diagram of the terminal device can be as follows: Figure 8 The terminal device may include one or more processors 100 ( Figure 8 Only one is shown), a memory 101 and a computer program 102 stored in the memory 101 and executable on one or more processors 100, for example, an adaptive 8K display method program supporting AVS3 decoding. When one or more processors 100 execute the computer program 102, the various steps in the adaptive 8K display method embodiment supporting AVS3 decoding can be implemented. Alternatively, when one or more processors 100 execute the computer program 102, the functions of the various modules / units in the adaptive 8K display method embodiment supporting AVS3 decoding can be implemented, which is not limited here.

[0116] In one embodiment, the processor 100 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0117] In one embodiment, the memory 101 may be an internal storage unit of an electronic device, such as a hard disk or memory of the electronic device. The memory 101 may also be an external storage device of the electronic device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device. Further, the memory 101 may also include both an internal storage unit of the electronic device and an external storage device. The memory 101 is used to store computer programs and other programs and data required by the terminal device. The memory 101 may also be used to temporarily store data that has been output or is to be output.

[0118] Those skilled in the art will understand that Figure 8 The principle block diagram shown in the figure is only a block diagram of a partial structure related to the scheme of the present invention, and does not constitute a limitation on the terminal device to which the scheme of the present invention is applied. The specific terminal device may include more or less components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0119] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, operating database or other media used in the embodiments provided by the present invention may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double operational data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0120] Embodiment 4

[0121] The present invention also provides a storage medium storing one or more programs, which can be executed by one or more processors to implement the steps of the adaptive 8K display method supporting AVS3 decoding described in the above embodiment.

[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An adaptive 8K display system supporting AVS3 decoding, characterized in that: The adaptive 8K display system supporting AVS3 decoding includes: The network port input module is used to parse network port data, identify and output 8K video data compressed by AVS3; AVS3 data analysis module, used for analyzing the video data received by the network port input module based on the ARM processor to obtain scheduling data and analyzed video data; AVS3 process control and scheduling module, used for extracting scheduling instructions from the scheduling data based on the ARM processor, and dividing the parsed video data into multiple copies according to the scheduling situation based on the scheduling instructions and writing them into different second DDR4s respectively; An AVS3 decoding module, including a plurality of decoding modules, the number of which is the same as the number of the second DDR4, for receiving the scheduling instruction based on the FPGA device, and taking out the corresponding parsed video data from the second DDR4 for decoding based on the scheduling instruction, and writing the decoded video data into the corresponding second DDR4 after obtaining the decoded video data; The DDR4 cache module includes a plurality of second DDR4s, and the plurality of second DDR4s are used to store the parsed video data and the decoded video data based on the scheduling instruction partitions.

2. The adaptive 8K display system supporting AVS3 decoding according to claim 1, characterized in that: The adaptive 8K display system supporting AVS3 decoding also includes: A video data reading module, configured to read the decoded video data from the plurality of second DDR4s in an image display order according to the scheduling instruction; A resolution scaling module, used for scaling the decoded video data according to the resolution information of the back-end display device; The video interface output module is used to output the scaled video data.

3. The adaptive 8K display system supporting AVS3 decoding according to claim 1, characterized in that: The AVS3 decoding module includes a plurality of slice decoding modules, and the plurality of slice decoding modules are used to decode the parsed video data simultaneously.

4. An adaptive 8K display method supporting AVS3 decoding, characterized in that: The adaptive 8K display system supporting AVS3 decoding as described in any one of claims 1 to 3 is applied, and the adaptive 8K display method supporting AVS3 decoding comprises: Receive target video data, parse the target video data, and obtain target parameters and target parsed video data, wherein the target video data is 8K video data compressed by AVS3; Obtaining target scheduling data and target decoding parameters based on the target parameters, and acquiring target scheduling instructions based on the target scheduling data; Dividing the target parsed video data into a plurality of groups of data to be decoded based on the target scheduling instruction; Based on the target decoding parameters, the plurality of groups of data to be decoded are decoded respectively to obtain target decoded video data.

5. The adaptive 8K display method supporting AVS3 decoding according to claim 4, characterized in that: The step of parsing the target video data to obtain target parameters and target parsed video data includes: The AVS3 encoded code stream data in the target video data is entropy decoded to obtain the target parameters and the target parsed video data, wherein the target parameters are parameter information of non-video encoded data obtained by entropy decoding the target video data, and the target parsed video data are encoding mode information, inter-frame motion information and encoded video data obtained by entropy decoding the target video data.

6. The adaptive 8K display method supporting AVS3 decoding according to claim 4, characterized in that: The step of respectively decoding the plurality of groups of data to be decoded based on the target decoding parameters to obtain target decoded video data comprises: When the target AVS3 decoding module performs decoding, the target data to be decoded is extracted from the target second DDR4 based on the target scheduling instruction, and the target data to be decoded is decoded based on the target decoding parameters to obtain the target decoded video data corresponding to the target AVS3 decoding module.

7. The adaptive 8K display method supporting AVS3 decoding according to claim 6, characterized in that: The step of extracting target data to be decoded from the target second DDR4 based on the target scheduling instruction, and decoding the target data to be decoded based on the target decoding parameter includes: Dividing the target data to be decoded into a plurality of groups of picture groups to be decoded, each group of the picture groups to be decoded includes a target number of frame data; Based on the target scheduling instruction and the target decoding parameters, each group of the target to-be-decoded picture groups is extracted and decoded in the video order of the target video, and then returned to the target second DDR4.

8. The adaptive 8K display method supporting AVS3 decoding according to claim 7, characterized in that: After obtaining the target decoded video data, the method further includes: Get the target resolution of the backend display device; Scaling the target decoded video data based on the target resolution to obtain target output video data, wherein the resolution of the target output video data is the same as the target resolution; The target output video is output.

9. The adaptive 8K display method supporting AVS3 decoding according to claim 8, characterized in that: The outputting the target output video includes: Based on the target scheduling instruction, pictures are extracted from the plurality of second DDR4s for output in a picture display order.

10. A terminal device, characterized in that: The terminal device includes a memory, a processor, and an adaptive 8K display program supporting AVS3 decoding that is stored in the memory and can be run on the processor. When the processor executes the adaptive 8K display program supporting AVS3 decoding, the steps of the adaptive 8K display method supporting AVS3 decoding as described in any one of claims 4-9 are implemented.

11. A storage medium, characterized in that: The storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the steps of the adaptive 8K display method supporting AVS3 decoding as described in any one of claims 4-9.

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