Image sensor and method of operating image sensor

Abstract

An image sensor and a method of operating an image sensor are provided, the image sensor including: an analog signal processing circuit configured to process an analog signal and output a digital signal; a digital data processing circuit comprising one or more digital circuits configured to process the digital signal; and a control circuit configured to control operation of the one or more digital circuits based on operation schedule information, where the operation schedule information includes one or more control time intervals associated with one or more operation sequences of the image sensor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0100602 filed on August 1, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to an image sensor and an operating method of the image sensor. Background Art

[0004] The image sensor includes an analog signal processing circuit and a digital data processing circuit, and converts light incident through a camera lens into digital data by using the analog signal processing circuit and the digital data processing circuit. The analog signal processing circuit can output a digital signal by receiving light, generating an analog signal based on the received light, and processing the analog signal. The digital data processing circuit can process the digital signal to output digital data.

[0005] Generally, the analog signal processing circuit and the digital data processing circuit can be implemented in one semiconductor chip. In this case, since the analog signal processing circuit and the digital data processing circuit share a ground voltage, the operation of the digital data processing circuit may affect the noise characteristics of the analog signal processing circuit. Summary of the invention

[0006] The present disclosure provides an image sensor capable of improving noise characteristics and reducing power consumption.

[0007] The present disclosure also provides an operating method of an image sensor.

[0008] According to one aspect of the present disclosure, an image sensor includes: an analog signal processing circuit configured to process an analog signal and output a digital signal; a digital data processing circuit including one or more digital circuits configured to process the digital signal; and a control circuit configured to control the operation of the one or more digital circuits based on operation scheduling information.

[0009] The operation scheduling information includes one or more control time intervals associated with one or more operation sequences of the image sensor.

[0010] According to one aspect of the present disclosure, a method of operating an image sensor includes: identifying an operation mode of the image sensor; determining an operation sequence based on the operation mode; and controlling operation of one or more digital circuits of the image sensor based on operation scheduling information including a control time interval associated with the operation sequence.

[0011] According to one aspect of the present disclosure, an image sensor includes: an analog signal processing circuit configured to process an analog signal and output a digital signal; a digital data processing circuit including one or more digital circuits configured to process the digital signal; and a control circuit configured to provide a first control signal to the analog signal processing circuit in each of one or more operation sequences of the image sensor, wherein the control circuit is further configured to control the operation of the one or more digital circuits based on operation sequence information, wherein the operation sequence information includes one or more control time intervals associated with the one or more operation sequences, and wherein the one or more control time intervals are set based on the first control signal.

[0012] According to one aspect of the present disclosure, an image sensor includes: an analog signal processing circuit, which includes: a pixel array; an analog-to-digital converter circuit; and a ramp generator; a digital data processing circuit, which includes one or more digital circuits; and a control circuit, wherein the analog signal processing circuit is configured to process the analog signal generated by the pixel array and output a digital signal, wherein the one or more digital circuits are configured to store the digital signal and perform image signal processing to enhance the characteristics of the digital signal, wherein based on a statistical analysis associated with the noise characteristics of the analog signal processing circuit, the one or more digital circuits are classified into a first digital circuit block and a second digital circuit block, and wherein the control circuit is configured to: control the operation of the one or more digital circuits based on operation scheduling information, wherein the operation scheduling information includes one or more control time intervals associated with one or more operation sequences of the image sensor, provide one or more clock signals to the one or more digital circuits, and block the clock signal to be provided to the first digital circuit block. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects, objects and features of the present disclosure will become clear by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0014] Figure 1 is a block diagram illustrating an image sensor according to an embodiment of the present disclosure;

[0015] Figure 2 It is shown Figure 1 An illustration of an embodiment of operation scheduling information;

[0016] Figure 3 It is shown Figure 1 A block diagram of an embodiment of an image sensor;

[0017] Figure 4A It is shown that the Figure 3 A circuit diagram of an embodiment of a pixel in a pixel array;

[0018] Figure 4B It is shown that the Figure 3 A block diagram of an embodiment of a comparison circuit and a counter circuit in an analog-to-digital converter circuit corresponding to one pixel;

[0019] Figure 4C It is shown Figure 3 A circuit diagram of an embodiment of a ramp generator;

[0020] Figure 5 Is used to describe Figure 3 A timing diagram of the operation of the image sensor;

[0021] Fig. 6A , Figure 6B and Figure 6C Is used to describe Figure 3 A timing diagram of one or more operation sequences of an image sensor;

[0022] Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7E Is used to describe Figure 3 a diagram of one or more control time intervals associated with one or more operation sequences of an image sensor;

[0023] Figure 8 , Fig. 9 and Fig.10 It is used to describe how to define 7A to 7E a diagram of one or more control time intervals;

[0024] Fig.11A It is used to describe the Figure 1 a diagram of the operation of one or more digital circuits in a digital data processing circuit;

[0025] Fig. 11B is a diagram for describing power consumption of a digital data processing circuit;

[0026] Fig. 12A and Fig. 12B It is shown Figure 1 An illustration of an embodiment of operation scheduling information;

[0027] Fig.13 and Fig.14 is a flowchart illustrating an operating method of an image sensor according to an embodiment of the present disclosure;

[0028] Fig.15 is a block diagram illustrating a computing system including an image sensor according to an embodiment of the present disclosure; and

[0029] Fig.16 is a block diagram illustrating an electronic system including an image sensor according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] Hereinafter, embodiments of the present disclosure will be described in detail and clearly to the extent that those skilled in the art can easily implement the present disclosure.

[0031] Terms such as "unit", "module", "component" and "block" may be implemented as hardware or software. Depending on the specific embodiment, multiple "units", "modules", "components" and "blocks" may be implemented as a single component, or a single "unit", "module", "component" and "block" may include multiple components.

[0032] It will be understood that when an element is referred to as being “connected” or “connected to” another element, it may be directly or indirectly connected to the other element, wherein the indirect connection includes “connection via a wireless communication network”.

[0033] Furthermore, when a component “includes” or “comprises” an element, unless there is a specific description contrary thereto, the component may further include other elements, rather than excluding other elements.

[0034] Throughout the specification, when a member is "on" another member, this includes not only that the member is in contact with the other member but also that another member exists between the two members.

[0035] Herein, the expression “at least one of a, b, and c” means “only a”, “only b”, “only c”, “both a and b”, “both a and c”, “both b and c”, or “all of a, b, and c”.

[0036] It will be understood that although the terms first, second, third, etc. may be used herein to describe various elements, the present disclosure should not be limited by these terms. These terms are only used to distinguish one element from another element.

[0037] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0038] The identification codes are used for convenience of description and are not intended to indicate the order of each step. Unless the context clearly indicates otherwise, each step may be implemented in an order different from the order shown.

[0039] Figure 1 is a block diagram illustrating an image sensor according to an embodiment of the present disclosure.

[0040] Reference Figure 1, the image sensor 100 may include an analog signal processing circuit 110 , a digital data processing circuit 130 , a control circuit 150 , and a memory 170 .

[0041] The analog signal processing circuit 110 can sense the light IL incident from the outside through the lens, and can generate a digital signal DS through photoelectric conversion. For example, the analog signal processing circuit 110 can generate a photocharge proportional to the intensity of the light IL, and can generate an analog signal based on the photocharge generated thereby. The analog signal processing circuit 110 can perform analog-to-digital conversion with respect to the analog signal, and can output the result of performing the analog-to-digital conversion as a digital signal DS. For example, the analog signal processing circuit 110 can output the digital signal DS to the digital data processing circuit 130.

[0042] The digital data processing circuit 130 may generate digital data DD by processing the digital signal DS received from the analog signal processing circuit 110. For example, the digital data processing circuit 130 may temporarily store the digital signal DS, may perform image signal processing for enhancing the quality of an image with respect to the digital signal DS, and may output a result of performing the image signal processing as digital data DD. For example, the digital data processing circuit 130 may output the digital data DD to the application processor 300 provided outside the image sensor 100.

[0043] The control circuit 150 may generate control signals CTL1 and CTL2 for controlling operations of the analog signal processing circuit 110 and the digital data processing circuit 130 , may provide the control signal CTL1 to the analog signal processing circuit 110 , and may provide the control signal CTL2 to the digital data processing circuit 130 .

[0044] The memory 170 may store information necessary for the control circuit 150 to control the operation of the analog signal processing circuit 110 and the digital data processing circuit 130. For example, the memory 170 may store operation scheduling information (OPSI) 171, and the control circuit 150 may control the operation of the analog signal processing circuit 110 and the digital data processing circuit 130 based on the operation scheduling information 171. For example, the operation scheduling information 171 may include one or more control time intervals associated with one or more operation sequences. For example, the digital data processing circuit 130 may include one or more digital circuits, and the control circuit 150 may control the operation of the one or more digital circuits based on the operation scheduling information 171. Figure 2 , Fig. 12A and Fig. 12B Operation scheduling information 171 is described.

[0045] In an embodiment, the control time interval may be a time interval in which the operation of the digital data processing circuit 130 having an influence on the operation of the analog signal processing circuit 110 has a negative impact on the noise characteristics of the analog signal processing circuit 110 .

[0046] For example, the operation of the analog signal processing circuit 110 (e.g., the operation of generating photocharges, analog signals, or digital signals DS) and the operation of the digital data processing circuit 130 (e.g., the operation of storing the digital signal DS or performing image signal processing) may be performed in parallel in time, and the operation of the digital data processing circuit 130 may affect the quality of the digital signal DS output from the analog signal processing circuit 110. In this case, the control time interval may indicate a time interval in which the quality of the digital signal DS is reduced to a given level or lower, and the control circuit 150 may block one or more clock signals or one or more power signals provided to the digital data processing circuit 130 during the control time interval. Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7E Describes the control time interval.

[0047] In an embodiment, the operation scheduling information 171 may include one or more operation modes of the image sensor 100, one or more operation sequences corresponding to the one or more operation modes, and one or more control time intervals corresponding to the one or more operation sequences. Fig. 6A , Figure 6B and Figure 6C Describes one or more sequences of operations.

[0048] In an embodiment, the digital data processing circuit 130 may include one or more digital circuits for temporarily storing the digital signal DS or performing image signal processing with respect to the digital signal DS, and the operation scheduling information 171 may also include information about a target digital circuit in which the supply of one or more clock signals or one or more power signals is blocked during the control time interval among the one or more digital circuits. Fig.11A Describe the target digital circuit.

[0049] In an embodiment, operation scheduling information 171 may be pre-stored in memory 170 before image sensor 100 performs a main operation for capturing an image (e.g., an operation based on an operation sequence according to an operation mode). For example, control circuit 150 may receive operation mode information OPMDI indicating a specific operation mode from application processor 300, and may block one or more clock signals or one or more power signals to be provided to a target digital circuit during a control time interval based on operation mode information OPMDI and operation scheduling information 171.

[0050] Through the above configuration, the image sensor according to an embodiment of the present disclosure can improve the noise characteristics of the analog signal processing circuit by blocking one or more clock signals or one or more power signals to be provided to the digital data processing circuit of the image sensor during the control time interval.

[0051] Before the operation mode or operation sequence is changed, the image sensor may perform a pre-scheduled operation at every given time interval (e.g., a "unit time interval"); the control time interval may be pre-defined as a portion of the unit time interval. Therefore, according to the pre-defined schedule, the image sensor according to the embodiment of the present disclosure can improve the noise characteristics of the analog signal processing circuit and can reduce power consumption without checking the detailed states of various circuits included in the analog signal processing circuit or the digital data processing circuit in real time.

[0052] Figure 2 It is shown Figure 1 A diagram of an embodiment of operation scheduling information.

[0053] Reference Figure 1 and Figure 2 , the operation scheduling information OPSI may include an operation mode, an operation sequence and a control time interval.

[0054] In an embodiment, the operation mode may include operation modes OPM1, OPM2, and OPM3, the operation sequence may include operation sequences OPSEQ1, OPSEQ2, and OPSEQ3, and the control time interval may include control time intervals CTINV1, CTINV2, and CTINV3. Figure 2An example is shown in which the operation sequences OPSEQ1, OPSEQ2 and OPSEQ3 correspond to the operation modes OPM1, OPM2 and OPM3, respectively, and the control time intervals CTINV1, CTINV2 and CTINV3 correspond to the operation sequences OPSEQ1, OPSEQ2 and OPSEQ3, respectively, but the correspondence between the operation modes OPM1, OPM2 and OPM3, the operation sequences OPSEQ1, OPSEQ2 and OPSEQ3, and the control time intervals CTINV1, CTINV2 and CTINV3 is provided as an example.

[0055] In an embodiment, each of the operation modes OPM1, OPM2, and OPM3 may indicate various ways in which the image sensor 100 performs a main operation to capture an image. For example, each of the operation modes OPM1, OPM2, and OPM3 may include one of a global exposure mode, a partial exposure mode, and a multiple exposure mode, and may include one of a fast shutter mode and a slow shutter mode. For example, each of the operation modes OPM1, OPM2, and OPM3 may include one of a global synchronization mode, a rolling shutter mode, and a hybrid shutter mode, and may include one of a video mode and a still image mode.

[0056] In an embodiment, the image sensor 100 may perform a predefined operation per unit time interval. For example, the image sensor 100 may operate in one or more reset time intervals and one or more signal time intervals included in the unit time interval.

[0057] In an embodiment, each of the operation sequences OPSEQ1, OPSEQ2, and OPSEQ3 may indicate a time sequence of one or more reset time intervals and one or more signal time intervals. For example, at each unit time interval of the image sensor 100 operation (or during a unit time interval of the image sensor 100 operation), according to each of the operation sequences OPSEQ1, OPSEQ2, and OPSEQ3, one or more reset time intervals and one or more signal time intervals may come (or start) in a preset order.

[0058] In an embodiment, each of the control time intervals CTINV1, CTINV2, and CTINV3 may include a portion of a reset time interval included in the corresponding operation sequence or a portion of a signal time interval included in the corresponding operation sequence. For example, the control time interval CTINV1 may include a portion of a reset time interval included in the operation sequence OPSEQ1 and a portion of a signal time interval included in the operation sequence OPSEQ1; similar to the control time interval CTINV1, the control time interval CTINV2 may include a portion of a reset time interval included in the operation sequence OPSEQ2 and a portion of a signal time interval included in the operation sequence OPSEQ2, and the control time interval CTINV3 may include a portion of a reset time interval included in the operation sequence OPSEQ3 and a portion of a signal time interval included in the operation sequence OPSEQ3.

[0059] In an embodiment, a first operation sequence (e.g., OPSEQ1) among one or more operation sequences (e.g., OPSEQ1 to OPSEQ3) may indicate a time sequence of a first reset time interval and a first signal time interval, the operation scheduling information OPSI may include a first control time interval (e.g., CTINV1) associated with the first operation sequence, and the first control time interval may include a portion of the first reset time interval or a portion of the first signal time interval.

[0060] Figure 3 It is shown Figure 1 A block diagram of an embodiment of an image sensor.

[0061] Reference Figure 3 , the image sensor 500 may include a pixel array 511, an analog-to-digital converter (ADC) circuit 513, a readout circuit 531, an image signal processor 533, a timing controller 551, a row driver 553, a ramp generator 555, and a column driver 557. The image sensor 500 may correspond to Figure 1 The image sensor 100 is provided.

[0062] The pixel array 511 may include a plurality of pixels arranged to be spaced apart from each other in the row direction and spaced apart from each other in the column direction. Each of the plurality of pixels may be connected to one of the plurality of rows and one of the plurality of columns. The pixel array 511 may sense light incident through a lens, may generate photocharges through photoelectric conversion, and may output a pixel signal PS based on the photocharges.

[0063] The ramp generator 555 may generate a ramp signal VRAMP whose voltage level changes in a scheduled manner at each unit time interval at which the image sensor 500 operates.

[0064] The analog-to-digital converter circuit 513 may generate a digital code based on a result of comparing the pixel signal PS with the ramp signal VRAMP, and may output the digital code as a digital signal DS.

[0065] In an embodiment, the pixel array 511, the analog-to-digital converter circuit 513 and the ramp generator 555 may constitute Figure 1 The analog signal processing circuit 110, the readout circuit 531 and the image signal processor 533 may correspond to Figure 1 The digital data processing circuit 130, and the timing controller 551, the row driver 553 and the column driver 557 can constitute Figure 1 The control circuit 150. However, the present disclosure is not limited thereto.

[0066] In an embodiment, the timing controller 551 may receive operation mode information OPMDI and operation schedule information OPSI from the outside, and may control the row driver 553 and the column driver 557 based on the operation mode information OPMDI and the operation schedule information OPSI. In particular, the timing controller 551 may output a control signal CTL1 to control the analog signal processing circuit 510, and may output a control signal CTL2 to control the digital data processing circuit 530.

[0067] Figure 4A It is shown that the Figure 3 A circuit diagram of an embodiment of a pixel in a pixel array. Figure 4B It is shown that the Figure 3 A block diagram of an embodiment of an analog-to-digital converter circuit and a comparison circuit and a counter circuit corresponding to one pixel. Figure 4C It is shown Figure 3 Circuit diagram of an embodiment of a ramp generator.

[0068] Reference Figure 3 and Figure 4A , the pixel array 511 may include a plurality of pixels, and Figure 4A One of the multiple pixels (e.g., 511-1) is shown in FIG.

[0069] Pixel 511-1 may include a photoelectric conversion element PD, a transfer transistor TX, a reset transistor RX, a dual conversion transistor DCX, a drive transistor DX, and a selection transistor SX. For example, pixel 511-1 may be a dual conversion gain pixel capable of operating a "dual conversion gain" operation. For example, the size of the conversion gain, which is the ratio of the photocharge accumulated in the floating diffusion region by the pixel 511-1 into the pixel signal PSa, may be adjusted according to changes in the illumination environment. For example, the size of the conversion gain of pixel 511-1 may be reduced in a high illumination environment and may be increased in a low illumination environment.

[0070] The reset transistor RX may initialize a voltage level of the floating diffusion region based on the control signal RS. The photoelectric conversion element PD may generate photocharges whose amount is proportional to the amount of incident light, and the transfer transistor TX may transfer the photocharges to the floating diffusion region based on the control signal TS.

[0071] The size of the capacitance of the floating diffusion region can be changed according to whether the dual conversion transistor DCX is turned on or off. For example, the dual conversion transistor DCX can be turned on by the control signal DCS in a high illumination environment, and can be turned off by the control signal DCS in a low illumination environment. For example, in a high illumination environment, the floating diffusion regions FD1 and FD2 can be electrically connected so that the size of the capacitance increases; in a low illumination environment, the floating diffusion regions FD1 and FD2 can be electrically disconnected so that the size of the capacitance decreases.

[0072] The drive transistor DX may amplify a voltage signal corresponding to the amount of photocharge accumulated in the floating diffusion region, and the selection transistor SX may transfer the voltage signal from the drive transistor DX to the column line CLa based on the control signal SEL so that the voltage signal VOUT is output as the pixel signal PSa.

[0073] In an embodiment, since the pixel 511-1 performs a "dual conversion gain" operation, the image sensor can operate in one or more reset time intervals and one or more signal time intervals. For example, in one or more reset time intervals, the reset transistor RX can be turned on; in one or more signal time intervals, the drive transistor DX and the select transistor SX can be turned on.

[0074] Reference Figure 3 and Figure 4B , the analog-to-digital converter circuit 513 may include one or more analog-to-digital converters, and Figure 4B One of the one or more analog-to-digital converters (eg, 513a) is shown.

[0075] The analog-to-digital converter 513 a may include a comparison circuit 513 - 1 and a counter circuit 513 - 3 .

[0076] The comparison circuit 513-1 may output a comparison signal CMPSa based on the auto-zero control signal AZa, the pixel signal PSa, and the ramp signal VRAMPa. The counter circuit 513-3 may output a digital code DCDa based on the counter enable signal CEa, the counter clock signal CCLKa, and the comparison signal CMPSa.

[0077] In an embodiment, the comparison circuit 513 - 1 may adjust the voltage level of the pixel signal PSa and the voltage level of the ramp signal VRAMPa based on the auto-zero control signal AZa, and may compare the pixel signal PSa and the ramp signal VRAMPa to output a comparison signal CMPSa.

[0078] In an embodiment, the counter circuit 513 - 3 may be driven based on the counter enable signal CEa and the counter clock signal CCLKa, and may output the digital code DCDa based on the comparison signal CMPSa until a given time point.

[0079] Reference Figure 3 and Figure 4C , the ramp generator 555a may correspond to the ramp generator 555, may include a variable ramp current source Irmp, a variable offset current source Iofs and a ramp resistor Rrmp, and may also include an output resistor Ro and an output capacitor Co.

[0080] The ramp generator 555a can generate a ramp signal VRAMPa by adjusting the magnitude (or level) of the current generated by the variable ramp current source Irmp and the variable offset current source Iofs. In an embodiment, the ramp generator 555a can adjust the slope of the ramp signal VRAMPa according to the change of the conversion gain. For example, when the conversion gain changes from a low conversion gain corresponding to a high illumination environment to a high conversion gain corresponding to a low illumination environment, the ramp generator 555a can switch the sign of the slope of the ramp signal VRAMPa from "negative (-)" to "positive (+)" or from "positive (+)" to "negative (-)". For example, when the conversion gain changes from a low conversion gain to a high conversion gain, the ramp generator 555a can increase or decrease the slope of the ramp signal VRAMPa.

[0081] Figure 5 Is used to describe Figure 3 A timing diagram of the operation of the image sensor.

[0082] Reference Figure 3 , Figure 4A , Figure 4B , Figure 4C and Figure 5 , the image sensor 500 may output the digital code DCDa over time based on the control signals AZa, CEa and CCLKa, the ramp signal VRAMPa and the pixel signal PSa. For example, the time interval from t0 to t7 may be a "1H time interval" in which the image sensor 500 processes the pixel signals generated from the pixels corresponding to one row of the pixel array 511. For example, the "1H time interval" may be a reference to Figure 1 The unit time interval described.

[0083] In an embodiment, the image sensor 500 can operate in multiple time intervals. For example, during the time interval from t0 to t1, the voltage level of the pixel signal PSa and the voltage level of the ramp signal VRAMPa can be adjusted to be substantially the same as each other based on the auto-zero control signal AZa. During the time interval from t1 to t2, the voltage level of the ramp signal VRAMPa can be adjusted to increase a preset size (e.g., Vofs). During the time interval from t2 to t4 and the time interval from t5 to t7, the voltage level of the ramp signal VRAMPa can be adjusted to change with a preset slope (e.g., SLP). The pixel signal PSa can indicate a reset level during the time interval from t0 to t4, and can indicate a signal level corresponding to the amount of photocharge accumulated in the pixel array during the time interval from t4 to t7.

[0084] In an embodiment, the time interval from t0 to t1 may be referred to as an “auto-zero interval”, the time interval from t1 to t2 and the time interval from t4 to t5 may be referred to as an “offset interval”, and the time interval from t2 to t4 and the time interval from t5 to t7 may be referred to as an “A / D conversion interval”.

[0085] In an embodiment, in the A / D conversion interval, the image sensor 500 may generate a digital code DCDa including a plurality of bits. For example, the image sensor 500 may output a digital code DCDa corresponding to a time interval from a time point when the counter enable signal CEa and the counter clock signal CCLKa are enabled to a time point when the voltage level of the pixel signal PSa is substantially the same as the voltage level of the ramp signal VRAMPa. In this case, in the A / D conversion interval, a time interval (e.g., from t2 to t3) during which the pixel signal PSa indicates a reset level may be referred to as a "reset time interval", and a time interval (e.g., from t5 to t6) during which the pixel signal PSa indicates a signal level may be referred to as a "signal time interval".

[0086] Fig. 6A , Figure 6B and Figure 6C Is used to describe Figure 3 A timing diagram of a sequence of one or more operations of an image sensor.

[0087] exist Fig. 6A , Figure 6B and Figure 6C, “1H time intervals” 1H_TINTV1, 1H_TINTV2, and 1H_TINTV3 are shown in which the image sensor 500 processes pixel signals generated from pixels corresponding to a row of the pixel array 511, and a ramp signal generated by the ramp generator 555 is shown in each of the 1H time intervals 1H_TINTV1, 1H_TINTV2, and 1H_TINTV3.

[0088] Reference Fig. 6A During the 1H time interval 1H_TINTV1 (e.g., from t11 to t15), the image sensor 500 may operate in a reset time interval RTINV1 and a signal time interval STINV1. For example, the image sensor 500 may operate in the reset time interval RTINV1 and in the signal time interval STINV1 after the reset time interval RTINV1; in this case, the operation sequence OPSEQ1 indicating (or defining) the operation of the image sensor 500 may be represented by "reset time interval-signal time interval (RS)". In this case, the ramp signal in the reset time interval RTINV1 and the ramp signal in the signal time interval STINV1 may have the same slope (e.g., SLP1), but the present disclosure is not limited thereto.

[0089] Reference Figure 6B , during the 1H time interval 1H_TINTV2 (e.g., from t31 to t35), the image sensor 500 may operate in one reset time interval RTINV2 and two signal time intervals STINV21 and STINV22. For example, the image sensor 500 may operate in the reset time interval RTINV2, in the signal time interval STINV21 after the reset time interval RTINV2, and in the signal time interval STINV22 after the signal time interval STINV21; in this case, the operation sequence OPSEQ2 indicating the operation of the image sensor 500 may be represented by "reset time interval-signal time interval-signal time interval (RSS)". In this case, the ramp signal in the reset time interval RTINV2, the ramp signal in the signal time interval STINV21, and the ramp signal in the signal time interval STINV22 may have the same slope (e.g., SLP1), but the present disclosure is not limited thereto.

[0090] Reference Figure 6CDuring the 1H time interval 1H_TINTV3 (e.g., from t51 to t55), the image sensor 500 may operate in two reset time intervals LRTINV3 and HRTINV3 and two signal time intervals HSTINV3 and LSTINV3. For example, the image sensor 500 may operate in the reset time interval LRTINV3, in the reset time interval HRTINV3 after the reset time interval LRTINV3, in the signal time interval HSTINV3 after the reset time interval HRTINV3, and in the signal time interval LSTINV3 after the signal time interval HSTINV3; in this case, the operation sequence OPSEQ3 indicating the operation of the image sensor 500 may be represented by "reset time interval-reset time interval-signal time interval-signal time interval (RRSS)". In the operation sequence OPSEQ3, the ramp signal in the reset time interval LRTINV3 and the ramp signal in the signal time interval LSTINV3 may have the same slope (e.g., SLP2), the ramp signal in the reset time interval HRTINV3 and the ramp signal in the signal time interval HSTINV3 may have the same slope (e.g., SLP1), and the slope SLP2 and the slope SLP1 may have the same sign but may be different values. However, the present disclosure is not limited thereto.

[0091] Reference Figure 2 and FIG. 6A to FIG. 6C The operation scheduling information OPSI may include one or more operation sequences (eg, OPSEQ1 to OPSEQ3), and a first operation sequence among the one or more operation sequences may indicate a time sequence of a first reset time interval and a first signal time interval.

[0092] Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7E Is used to describe Figure 3 A diagram of one or more control time intervals associated with one or more operation sequences of an image sensor.

[0093] Reference Figure 2 , Fig. 7A , Figure 7B , Figure 7C , Fig.7D and Fig. 7E , each of the one or more operation sequences may include a control time interval, and the control time interval may include a portion of a reset time interval or a portion of a signal time interval. 7A to 7EIn the figure, a "1H time interval 1H_TINTV" is shown, and a reset time interval RTINVa and a signal time interval STINVa that can be set by an operation sequence (e.g., OPSEQ) are shown. The control time interval can be divided into one or more parts on the time axis, and each of the parts divided in this way can be referred to as a "control part".

[0094] In an embodiment, the reset time interval RTINVa may be referenced to FIG. 6A to FIG. 6C The reset time intervals RTINV1, RTINV2, LRTINV3, and HRTINV3 described above may be one of the reset time intervals RTINV1, RTINV2, LRTINV3, and HRTINV3, and the signal time interval STINVa may be a reference to FIG. 6A to FIG. 6C Described is one of the signal time intervals STINV1, STINV21, STINV22, HSTINV3 and LSTINV3.

[0095] Reference Fig. 7A , the control time interval TSa1 may be set to include a part of the reset time interval RTINVa. For example, the control time interval TSa1 may be set to be included in the reset time interval RTINVa but not included in the signal time interval STINVa.

[0096] Reference Figure 7B , the control time interval TSa2 may be set to include a part of the signal time interval STINVa. For example, the control time interval TSa2 may be set to be included in the signal time interval STINVa but not included in the reset time interval RTINVa.

[0097] Reference Figure 7C , the control time interval TSa31 may be set to include the entire reset time interval RTINVa, and the control time interval TSa32 may be set to include the entire signal time interval STINVa. For example, the control time interval TSa31 may be set to be substantially the same as the reset time interval RTINVa, and the control time interval TSa32 may be set to be substantially the same as the signal time interval STINVa.

[0098] Reference Fig.7D , each of the control time intervals TSa41, TSa42, and TSa43 may be set to include a portion of the signal time interval STINVa. For example, each of the control time intervals TSa41, TSa42, and TSa43 may be set to be included in the signal time interval STINVa, but not included in the reset time interval RTINVa.

[0099] Reference Fig. 7E, the control time interval TSa51 may be set to include a portion of the reset time interval RTINVa, and the control time interval TSa52 may be set to include the entire signal time interval STINVa. For example, a portion of the control time interval TSa51 may be set to be included in the reset time interval RTINVa, and a portion of the control time interval TSa52 may be set to be included in the signal time interval STINVa. For example, the control time interval TSa51 may also include a time interval (e.g., AT1) immediately before the reset time interval RTINVa, and the control time interval TSa52 may also include a time interval (e.g., AT2) immediately before the signal time interval STINVa and a time interval (e.g., AT3) immediately after the signal time interval STINVa. The time intervals AT1, AT2, and AT3 may be set to prevent instantaneous changes in power consumption in the digital data processing circuit.

[0100] Reference Figure 2 , FIG. 6A to FIG. 6C and 7A to 7E The operation scheduling information OPSI may include one or more operation sequences (eg, OPSEQ1 to OPSEQ3), and a first operation sequence among the one or more operation sequences may indicate a time sequence of a first reset time interval and a first signal time interval.

[0101] In an embodiment, the operation scheduling information OPSI may include a first control time interval associated with the first operation sequence, and the first control time interval may include a portion of the first reset time interval or a portion of the first signal time interval.

[0102] In an embodiment, the first control time interval may include the entire first reset time interval or the entire first signal time interval.

[0103] In an embodiment, the first control time interval may include a time interval immediately before the first reset time interval or a time interval immediately after the first reset time interval, and may include a time interval immediately before the first signal time interval or a time interval immediately after the first signal time interval.

[0104] Figure 8 , Fig. 9 and Fig.10 It is used to describe how to define 7A to 7E A diagram of one or more control time intervals.

[0105] exist Figure 8 , Fig. 9 and Fig.10 In FIG. 1 , a control time interval TSx is shown. The control time interval TSx may be a reference to 7A to 7EOne of the control time intervals TSa1, TSa2, TSa31, TSa32, TSa41, TSa42, TSa43, TSa51 and TSa52 is described.

[0106] Reference Figure 8 , can be based on reference Figure 4B The control time interval TSx is set by one or more ( CTLS1 ) of the auto-zero control signal AZa, the counter enable signal CEa, and the counter clock signal CCLKa as described above.

[0107] In an embodiment, the control time interval TSx may be set based on one or more of the time point tstr1 at which the auto-zero control signal AZa is disabled, the time point tstr2 at which the counter enable signal CEa is enabled, and the time point tstr3 at which the counter clock signal CCLKa is applied. For example, the control time interval TSx may range from the time point tx_str to the time point tx_end. When the control time interval TSx is set based on the auto-zero control signal AZa, the control time interval TSx may be set by using the time distance from the time point tstr1 to the time point tx_str (e.g., td11) and the time distance from the time point tstr1 to the time point tx_end (e.g., td12). When the control time interval TSx is set based on the counter enable signal CEa, the control time interval TSx may be set by using the time distance from the time point tstr2 to the time point tx_str (e.g., td21) and the time distance from the time point tstr2 to the time point tx_end (e.g., td22). When the control time interval TSx is set based on the counter clock signal CCLKa, the control time interval TSx can be set by using the time distance from the time point tstr3 to the time point tx_str (e.g., td31) and the time distance from the time point tstr3 to the time point tx_end (e.g., td32). For example, the control time interval TSx can have a time interval tdx1 from tx_str to tx_end.

[0108] In an embodiment, the operation scheduling information OPSI may include a first control time interval (e.g., TSx) associated with a first operation sequence, and the first control time interval may be set based on a time distance (e.g., td11, td12, td21, td22, td31, and td32) from one or more of a first time point (e.g., tstr1), a second time point (e.g., tstr2), and a third time point (e.g., tstr3).

[0109] Reference Fig. 9 , can be based on reference Figure 4CThe ramp signal VRAMPa (CTLS2) described above is used to set the control time interval TSx.

[0110] In an embodiment, the control time interval TSx can be set based on the time point tstr4 at which the slope of the ramp signal VRAMPa changes. For example, the range of the control time interval TSx can be from the time point tx_str to the time point tx_end. When the control time interval TSx is set based on the ramp signal VRAMPa, the control time interval TSx can be set by using the time distance (e.g., td41) from the time point tstr4 to the time point tx_str and the time distance (e.g., td42) from the time point tstr4 to the time point tx_end. For example, the control time interval TSx can have a time interval tdx2 from tx_str to tx_end, and the control time interval TSx can be set by using the time distance td41 and the time distance tdx2.

[0111] In an embodiment, based on the reference Figure 3 and Figure 5 The time interval tdx2 of the control time interval TSx can be adjusted by adjusting the length of each of the reset time interval and the signal time interval described. For example, the time interval tdx2 of the control time interval TSx can be set to be inversely proportional to the absolute value of the slope SLP of the ramp signal VRAMPa. For example, as the absolute value of the slope SLP of the ramp signal VRAMPa increases, the time interval tdx2 can be shortened; as the absolute value of the slope SLP of the ramp signal VRAMPa decreases, the time interval tdx2 can be lengthened.

[0112] In an embodiment, the operation scheduling information OPSI may include a first control time interval (e.g., TSx) associated with the first operation sequence, and the first control time interval may be set based on a fourth time point (e.g., tstr4). In this case, the length of the first control time interval may be inversely proportional to the absolute value of the slope of the ramp signal.

[0113] Reference Fig.10 , the control time interval TSx may be set based on the ramp signal VRAMPa and one ( CTLS3 ) of the auto-zero control signal AZa, the counter enable signal CEa, and the counter clock signal CCLKa.

[0114] In an embodiment, the control time interval TSx may be set based on the time point tstr1 at which the auto-zero control signal AZa is disabled. For example, the control time interval TSx may be set by using the time distance from the time point tstr1 to the time point tx_str (e.g., td11) and the time distance from the time point tstr1 to the time point tx_end (e.g., td12).

[0115] In an embodiment, the time interval tdx2 of the control time interval TSx may be set to be inversely proportional to the absolute value of the slope SLP of the ramp signal VRAMPa. For example, as the absolute value of the slope SLP of the ramp signal VRAMPa increases, the time interval tdx2 may become shorter; as the absolute value of the slope SLP of the ramp signal VRAMPa decreases, the time interval tdx2 may become longer.

[0116] In reference Figure 8 and Fig. 9 In the described embodiments, reference is made to Fig.10 An embodiment is described in which the control time interval TSx is set based on a combination of the auto-zero control signal AZa and the ramp signal VRAMPa; however, an alternative embodiment in which the control time interval TSx is set based on a combination of the ramp signal VRAMPa and one of the counter enable signal CEa and the counter clock signal CCLKa may also meet the needs.

[0117] Fig.11A It is used to describe the Figure 1 A diagram of the operation of one or more digital circuits in a digital data processing circuit. Fig. 11B is a diagram for describing power consumption of a digital data processing circuit.

[0118] exist Fig.11A 600 is shown in FIG. The image sensor 600 may include a digital data processing circuit 630 and a control circuit 650. The image sensor 600 may correspond to Figure 1 The image sensor 100, the digital data processing circuit 630 and the control circuit 650 may correspond to Figure 1 The digital data processing circuit 130 and the control circuit 150. The image sensor 600 may correspond to Figure 3 The image sensor 500, the digital data processing circuit 630 and the control circuit 650 may correspond to Figure 3 The digital data processing circuit 530 and the control circuit 550 are provided.

[0119] Reference Fig.11A , the digital data processing circuit 630 may include one or more digital circuits 631-11, 631-12, 631-13, 631-21, 631-22, and 631-23. The one or more digital circuits 631-11, 631-12, 631-13, 631-21, 631-22, and 631-23 may be processed from an analog signal processing circuit (e.g., Figure 1 110 or Figure 3For example, one or more digital circuits 631-11, 631-12, 631-13, 631-21, 631-22, and 631-23 may temporarily store digital signals, and may generate digital signals by performing image signal processing for enhancing image quality with respect to the digital signals.

[0120] The control circuit 650 may provide a control signal CTL2 to the digital data processing circuit 630. The control signal CTL2 may include one or more clock signals CLK11, CLK12, CLK13, CLK21, CLK22, and CLK23 and one or more power signals PWR11, PWR12, PWR13, PWR21, PWR22, and PWR23, and as Fig.11A As shown, one or more clock signals CLK11 to CLK13 and CLK21 to CLK23 and one or more power signals PWR11 to PWR13 and PWR21 to PWR23 may be provided to one or more digital circuits 631-11 to 631-13 and 631-21 to 631-23. However, the present disclosure is not limited thereto.

[0121] In an embodiment, the image sensor 600 may be in reference to Figure 2 Each unit time interval described performs a pre-scheduled operation. For example, the image sensor 600 may operate in one or more reset time intervals and one or more signal time intervals included in the unit time interval.

[0122] In an embodiment, each of the operation sequences may indicate a time sequence of one or more reset time intervals and one or more signal time intervals. Each of the one or more control time intervals may include a portion of the reset time interval included in the corresponding operation sequence or a portion of the signal time interval included in the corresponding operation sequence. Each of the one or more control time intervals may include the entire reset time interval or the entire signal time interval. Each of the one or more control time intervals may include a time interval immediately before the reset time interval or a time interval immediately after the reset time interval, and may include a time interval immediately before the signal time interval or a time interval immediately after the signal time interval. For example, each of the one or more control time intervals may be a reference to Figure 1 , Figure 2 and 7A to 7E One of the control time intervals described.

[0123] In an embodiment, in each of one or more control time intervals, the control circuit 650 may block some or all of one or more clock signals CLK11 to CLK13 and CLK21 to CLK23 or some or all of one or more power signals PWR11 to PWR13 and PWR21 to PWR23 based on the control signal CTL2.

[0124] In an embodiment, one or more digital circuits 631-11 to 631-13 and 631-21 to 631-23 may be classified into a first digital circuit block (e.g., TDC) and a second digital circuit block (e.g., nTDC) based on a statistical analysis associated with the noise characteristics of the analog signal processing circuit by the operation of the one or more digital circuits 631-11 to 631-13 and 631-21 to 631-23 or the spatial distance from the analog signal processing circuit. For example, when the operation of a specific circuit that affects the operation of the analog signal processing circuit among the one or more digital circuits 631-11 to 631-13 and 631-21 to 631-23 has a negative impact on the noise characteristics at a given level or higher, the specific circuit that has a negative impact on the noise characteristics at a given level or higher may be classified as a first digital circuit block. For example, when a specific circuit among one or more digital circuits 631-11 to 631-13 and 631-21 to 631-23 is arranged inside the semiconductor chip within a given distance or less from the analog signal processing circuit, the specific circuit arranged within a given distance or less from the analog signal processing circuit can be classified as a first digital circuit block. In this case, in each of the one or more control time intervals, the control circuit 650 can block the clock signal or power signal provided only to the first digital circuit block, and can not block the clock signal or power signal provided to the second digital circuit block.

[0125] In an embodiment, when the operation sequence of the image sensor 600 is changed by changing the operation mode of the image sensor 600, the control circuit 650 may control the operation of one or more digital circuits 631-11 to 631-13 and 631-21 to 631-23 based on a control time interval associated with the changed operation sequence.

[0126] For example, based on the reference Figure 1 The external application processor (eg, 300) receives the new operation mode information OPMDI to perform a change in the operation mode of the image sensor 600. Figure 2When the change of the operation mode (e.g., from OPM1 to OPM2) causes the change of the operation sequence (e.g., from OPSEQ1 to OPSEQ2), the change of the operation sequence may cause the change of the control time interval (e.g., from CTINV1 to CTINV2). Therefore, when the change of the control time interval is performed by the change of the operation mode, the time interval for controlling the operation of one or more digital circuits 631-11 to 631-13 and 631-21 to 631-23 may also be changed, and the control time interval may be changed by referring to FIG. 6A to FIG. 6C , 7A to 7E and Figures 8 to 10 The configuration or operation described is to perform detailed operations associated with controlling the operation of one or more digital circuits 631-11 to 631-13 and 631-21 to 631-23.

[0127] Reference Fig.11A and Fig. 11B , the power consumption DDPC_PWR of the digital data processing circuit 630 may change over time. The time intervals TSx1, TSx2, and TSx3 may correspond to one or more control time intervals; as the clock signal or power signal provided to the first digital circuit block is blocked in the time intervals TSx1, TSx2, and TSx3, the power consumption DDPC_PWR may be reduced, and the noise characteristics of the analog signal processing circuit may be improved.

[0128] Fig. 12A and Fig. 12B It is shown Figure 1 A diagram of an embodiment of operation scheduling information.

[0129] exist Fig. 12A and Fig. 12B It is shown in Figure 2 The operation scheduling information OPSI shown is different from the operation scheduling information OPSIa and OPSIb.

[0130] Reference Fig.11A and Fig. 12A , the operation scheduling information OPSIa may include an operation mode, an operation sequence, and a control time interval.

[0131] In an embodiment, the operation mode may include operation modes OPM1, OPM2, OPM3, OPM4, and OPM5, the operation sequence may include operation sequences OPSEQ1 and OPSEQ2, and the control time interval may include control time intervals CTINV1 and CTINV2. Fig. 12A, the operation sequence OPSEQ1 may correspond to the operation modes OPM1 and OPM2 , the operation sequence OPSEQ2 may correspond to the operation modes OPM3 to OPM5 , and the control time intervals CTINV1 and CTINV2 may correspond to the operation sequences OPSEQ1 and OPSEQ2 , respectively.

[0132] In an embodiment, when the operation order of the image sensor 600 is changed by changing the operation mode of the image sensor 600, the control circuit 650 may control the operation of one or more digital circuits 631-11 to 631-13 and 631-21 to 631-23 based on a control time interval associated with the changed operation order.

[0133] For example, even if the operation mode of the image sensor 600 is changed (e.g., from OPM1 to OPM2), the operation sequence of the image sensor 600 may be maintained (e.g., OPSEQ1 is maintained); the operation sequence of the image sensor 600 may be changed (e.g., from OPSEQ1 to OPSEQ2) by changing the operation mode of the image sensor 600 (e.g., from OPM2 to OPM3). When the operation sequence is maintained, the control time interval may also be maintained; when the operation sequence is changed, the control time interval may be changed.

[0134] Reference Fig. 11B and Fig. 12B , the operation scheduling information OPSIb may include an operation mode, an operation sequence, and a control time interval, and may also include a target digital circuit.

[0135] In an embodiment, the target digital circuit may be a result of classifying one or more digital circuits 631-11 to 631-13 and 631-21 to 631-23 into a first digital circuit block and a second digital circuit block based on one or more of a result of a statistical analysis associated with a noise characteristic of an analog signal processing circuit and a result of calculating a spatial distance on the analog signal processing circuit. For example, the target digital circuit may indicate only a digital circuit included in a first digital circuit block.

[0136] In an embodiment, the operation modes may include operation modes OPM1 , OPM2 , and OPM3 , the operation sequences may include operation sequences OPSEQ1 , OPSEQ2 , and OPSEQ3 , and the control time interval may include control time intervals CTINV1 , CTINV2 , and CTINV3 .

[0137] In an embodiment, a target digital circuit may be indicated by indexes "1" to "6" capable of independently identifying one or more digital circuits 631-11 to 631-13 and 631-21 to 631-23; regarding control time interval CTINV1, the target digital circuit may be indicated by indexes "1", "2", and "4" indicating digital circuits 631-11, 631-12, and 631-21; regarding control time interval CTINV2, the target digital circuit may be indicated by indexes "1" and "2" indicating digital circuits 631-11 and 631-12; regarding control time interval CTINV3, the target digital circuit may be indicated in a manner similar to that of each of control time intervals CTINV1 and CTINV2. For example, when the target digital circuit is controlled by each of control time intervals CTINV1 to CTINV3, one or more clock signals or one or more power signals provided to the digital circuit indicated by the target digital circuit may be blocked in each of control time intervals CTINV1 to CTINV3.

[0138] Fig.13 and Fig.14 is a flowchart illustrating an operating method of an image sensor according to an embodiment of the present disclosure.

[0139] exist Fig.13 and Fig.14 Each operation can be controlled by a control circuit (e.g., Figure 1 150) or an application processor (e.g., Figure 1 300) is executed.

[0140] Reference Fig.13 , in the operating method of the image sensor, an operating mode of the image sensor may be identified ( S100 ).

[0141] The operation sequence may be determined based on the operation mode ( S300 ).

[0142] Operation of one or more digital circuits may be controlled based on operation scheduling information including a control time interval associated with an operation sequence ( S500 ).

[0143] In an embodiment, controlling the operation of the one or more digital circuits may include blocking only a clock signal or a power signal provided to a first digital circuit block.

[0144] Reference Fig.13 and Fig.14 , in the operating method of the image sensor, operation scheduling information may be generated before performing operation S100 , operation S300 , and operation S500 ( S10 ).

[0145] A statistical analysis associated with noise characteristics of the analog signal processing circuit may be performed ( S30 ).

[0146] A spatial distance between the analog signal processing circuit and the one or more digital circuits may be calculated (S50).

[0147] Based on one or more of the result of the statistical analysis and the calculation result of the spatial distance, the one or more digital circuits may be classified into a first digital circuit block and a second digital circuit block ( S70 ).

[0148] Fig.15 is a block diagram illustrating a computing system including an image sensor according to an embodiment of the present disclosure.

[0149] Reference Fig.15 , computing system 700 may include processor 710, memory device 720, storage device 730, image sensor 740, input / output (I / O) device 750, and power supply 760. Computing system 700 may communicate with a video card, sound card, memory card, USB device, etc., or may also include a port capable of communicating with any other electronic device.

[0150] Processor 710 may perform specific calculations or tasks. In an embodiment, processor 710 may be a microprocessor or a central processing unit (CPU). For example, processor 710 may include an application processor (e.g., Figure 1 300). Therefore, the processor 710 may provide the operation mode information OPMDI to the image sensor 740, and may receive the digital data DD from the image sensor 740.

[0151] The processor 710 may communicate with the memory device 720 , the storage device 730 , the image sensor 740 , and the input / output device 750 through an address bus, a control bus, and a data bus.

[0152] In an embodiment, processor 710 may also be connected to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

[0153] The memory device 720 may store data necessary for the operation of the computing system 700. For example, the memory device 720 may be implemented using dynamic RAM (DRAM), mobile DRAM, static RAM (SRAM), phase change RAM (PRAM), ferroelectric RAM (FRAM), resistive RAM (RRAM), and / or magnetoresistive RAM (MRAM).

[0154] The storage device 730 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The input / output device 750 may include an input device such as a keyboard, a keypad, and a mouse, and an output device such as a printer and a display. The power supply 760 may supply an operating voltage necessary for the operation of the computing system 700.

[0155] The image sensor 740 may be connected to the processor 710 through a bus or any other communication link and may perform communication. The image sensor 740 may be based on a reference Figure 1 , Figure 3 and Figure 5 Describes the configuration and operations to operate.

[0156] Fig.16 is a block diagram illustrating an electronic system including an image sensor according to an embodiment of the present disclosure.

[0157] Reference Fig.16 , the electronic system 1000 may be implemented using a data processing device capable of using or supporting a MIPI interface, and may include an application processor 1010, an image sensor 1040, a display 1050, etc. The electronic system 1000 may also include an RF chip 1060, a GPS 1020, a storage 1070, a microphone 1180, a DRAM 1085, and a speaker 1090, and may perform communication by using UWB 1110, WLAN 1100, WIMAX 1030, etc.

[0158] The application processor 1010 may refer to a controller or a processor that controls the operation of the image sensor 1040 and the display 1050. The application processor 1010 may correspond to Figure 1 The application processor 300 is configured to:

[0159] The application processor 1010 may include a display serial interface (DSI) host 1011 that communicates with a display serial interface (DSI) device 1051 of the display 1050, a CSI host 1012 that communicates with a camera serial interface (CSI) device 1041 of the image sensor 1040, a PHY that exchanges data with a PHY 1061 of the RF chip 1060 in accordance with DigRF, and a DigRF master device that controls a DigRF slave device 1062 of the RF chip 1060.

[0160] In an embodiment, the DSI host 1011 may include an optical serializer SER, and the DSI device 1051 may include an optical deserializer DES. In an embodiment, the CSI host 1012 may include an optical deserializer DES, and the CSI device 1041 may include an optical serializer SER.

[0161] The image sensor 1040 may be an image sensor according to an embodiment of the present disclosure, and may be operated based on an operating method according to an embodiment of the present disclosure.

[0162] In an embodiment, the electronic system 1000 may be an electronic system such as a personal computer (PC), a workstation, a laptop computer, a cellular phone, a smart phone, an MP3 player, a PDA (personal digital assistant), a PMP (portable multimedia player), a digital TV, a digital camera, a portable game console, a navigation system, a wearable device, an IoT (Internet of Things) device, an IoE (Internet of Everything) device, an e-book, a VR (virtual reality) device, an AR (augmented reality) device, or a drone.

[0163] As described above, the image sensor according to the embodiment of the present disclosure can improve the noise characteristics of the analog signal processing circuit by blocking one or more clock signals or one or more power signals to be provided to the digital data processing circuit of the image sensor during the control time interval.

[0164] The image sensor may perform a pre-scheduled operation at each given time interval (e.g., a "unit time interval") until the operation mode or operation sequence is changed, and the control time interval may be pre-defined as a part of the unit time interval. Therefore, according to the pre-defined schedule, the image sensor according to the embodiment of the present disclosure may improve the noise characteristics of the analog signal processing circuit and may reduce power consumption without checking the detailed states of various circuits included in the analog signal processing circuit or the digital data processing circuit in real time.

[0165] An image sensor according to an embodiment of the present disclosure may improve noise characteristics of an analog signal processing circuit by blocking one or more clock signals or one or more power signals to be provided to a digital data processing circuit of the image sensor during a control time interval.

[0166] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the present disclosure as set forth in the following claims.

Claims

1. An image sensor, comprising: an analog signal processing circuit configured to process the analog signal and output a digital signal; a digital data processing circuit comprising one or more digital circuits configured to process the digital signal; as well as A control circuit is configured to control the operation of the one or more digital circuits based on operation scheduling information, wherein the operation scheduling information includes one or more control time intervals associated with one or more operation sequences of the image sensor.

2. The image sensor according to claim 1, wherein: The image sensor is configured to operate in one or more reset time intervals and one or more signal time intervals, and Each of the one or more operation sequences indicates a time sequence of the one or more reset time intervals and the one or more signal time intervals.

3. The image sensor according to claim 2, wherein: A first operation sequence among the one or more operation sequences indicates a time sequence of a first reset time interval among the one or more reset time intervals and a first signal time interval among the one or more signal time intervals, The operation scheduling information includes a first control time interval among the one or more control time intervals, and the first control time interval is associated with the first operation sequence, and The first control time interval includes a portion of the first reset time interval or a portion of the first signal time interval.

4. The image sensor according to claim 3, wherein: The analog signal processing circuit includes one or more analog-to-digital converters configured to generate the digital signal, wherein the control circuit is configured to provide an auto-zero control signal, a counter enable signal and a counter clock signal to each of the one or more analog-to-digital converters, and The first control time interval is set based on one or more of the auto-zero control signal, the counter enable signal and the counter clock signal.

5. The image sensor according to claim 4, wherein: The first control time interval is set based on one or more of a first time point when the auto-zero control signal is disabled, a second time point when the counter enable signal is enabled, and a third time point when the counter clock signal is applied.

6. The image sensor according to claim 5, wherein: The first control time interval is set based on a time distance from one or more of the first time point, the second time point, and the third time point.

7. The image sensor according to claim 3, wherein: The analog signal processing circuit includes a ramp generator configured to generate a ramp signal, and Wherein, the first control time interval is set based on the ramp signal.

8. The image sensor according to claim 7, wherein: The first control time interval is set within the first reset time interval or the first signal time interval based on a first time point when the slope of the ramp signal changes.

9. The image sensor according to claim 8, wherein: The length of the first control time interval is inversely proportional to the absolute value of the slope of the ramp signal.

10. The image sensor according to claim 3, wherein: The first control time interval also includes a time interval immediately before the first reset time interval or a time interval immediately before the first signal time interval.

11. The image sensor according to claim 1, wherein: The control circuit is further configured to: providing one or more clock signals to the one or more digital circuits; and At least one of the one or more clock signals is blocked in each of the one or more control time intervals.

12. The image sensor according to claim 11, wherein: classifying the one or more digital circuits into first digital circuit blocks and second digital circuit blocks based on a statistical analysis associated with noise characteristics of the analog signal processing circuit, and The control circuit is further configured to block only the clock signal to be provided to the first digital circuit block.

13. The image sensor according to claim 11, wherein: classifying the one or more digital circuits into a first digital circuit block and a second digital circuit block based on a spatial distance between each of the one or more digital circuits and the analog signal processing circuit, and The control circuit is further configured to block only the clock signal to be provided to the first digital circuit block among the one or more clock signals.

14. The image sensor according to claim 11, wherein: The operation scheduling information also includes results of classifying the one or more digital circuits into a first digital circuit block and a second digital circuit block based on one or more results of a statistical analysis associated with the noise characteristics of the analog signal processing circuit and a calculation result of a spatial distance between each of the one or more digital circuits and the analog signal processing circuit.

15. The image sensor according to claim 1, wherein: The control circuit is further configured to: based on the operation sequence of the image sensor being changed by a change in an operation mode of the image sensor, control the operation of the one or more digital circuits based on a control time interval associated with the changed operation mode.

16. A method of operating an image sensor, the method comprising: identifying an operating mode of the image sensor; determining an operation sequence based on the operation mode; as well as Operation of one or more digital circuits of the image sensor is controlled based on operation scheduling information including a control time interval associated with the operation sequence.

17. The method according to claim 16, further comprising: performing a statistical analysis associated with noise characteristics of analog signal processing circuitry of the image sensor; calculating a spatial distance between the analog signal processing circuit and the one or more digital circuits; as well as Based on one or more of a result of the statistical analysis and a result of calculating the spatial distance, the one or more digital circuits are classified into a first digital circuit block and a second digital circuit block.

18. The method according to claim 17, wherein: Controlling the operation of the one or more digital circuits comprises: Only the clock signal to be provided to the first digital circuit block is blocked.

19. The method according to claim 16, wherein: The image sensor is configured to operate in one or more reset time intervals and one or more signal time intervals, and The operation sequence indicates a time sequence of the one or more reset time intervals and the one or more signal time intervals.

20. An image sensor, comprising: An analog signal processing circuit, the analog signal processing circuit comprising: Pixel array; analog-to-digital converter circuit; and Ramp generator; a digital data processing circuit comprising one or more digital circuits; and Control circuit, The analog signal processing circuit is configured to process the analog signal generated by the pixel array and output a digital signal. wherein the one or more digital circuits are configured to store the digital signal and perform image signal processing to enhance characteristics of the digital signal, wherein the one or more digital circuits are classified into a first digital circuit block and a second digital circuit block based on a statistical analysis associated with a noise characteristic of the analog signal processing circuit, and Wherein, the control circuit is configured as follows: controlling the operation of the one or more digital circuits based on operation schedule information, wherein the operation schedule information includes one or more control time intervals associated with one or more operation sequences of the image sensor, providing one or more clock signals to the one or more digital circuits, and A clock signal to be provided to the first digital circuit block is blocked.

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