Column ramp buffer design to improve ADC range in CIS

Abstract

The invention relates to a column ramp buffer design to improve ADC range in a CIS. An imaging system includes an array of pixels and readout circuitry coupled to the array of pixels. The readout circuitry includes a ramp generator and a plurality of column unit cells, each column unit cell including a column ramp buffer and a column comparator, and each column of ramp buffers includes an input node coupled to receive a ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator; and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit includes a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors, and particularly, but not exclusively, to complementary metal oxide semiconductor (CMOS) image sensors. Background Art

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance the functionality, performance metrics, and so forth of the image sensors in as many ways as possible (e.g., resolution, power consumption, dynamic range), both through device architecture design and image acquisition processing. The technology used to manufacture image sensors has continued to advance rapidly. For example, the demand for higher resolution and lower power consumption has driven further miniaturization and integration of these devices.

[0003] A typical image sensor operates in response to image light from an external scene being incident on the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charges upon absorbing the image light. The image charge generated by the pixel light can be measured as an analog output image signal on a column bit line that varies as a function of the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, and the image charge is read out from the column bit line as an analog image signal and converted to a digital value to generate a digital image (e.g., image data) representing the external scene. The analog image signals on the bit lines are coupled to a readout circuit that includes an input stage having an analog-to-digital conversion (ADC) circuit to convert those analog image signals from the pixel array into digital image signals. Summary of the invention

[0004] One aspect of the present application discloses an imaging system, comprising: a pixel array configured to generate a plurality of image charge voltage signals in response to incident light; and a readout circuit system coupled to the pixel array, the readout circuit system comprising a ramp generator configured to generate a ramp signal, and a plurality of column unit cells coupled to receive the ramp signal from the ramp generator and the image charge voltage signal from the pixel array, wherein each column unit cell comprises a column ramp buffer and a column comparator, and wherein each column ramp buffer comprises: an input node coupled to receive a ramp signal from the ramp generator; The invention relates to a method for generating a plurality of linear actuators for transmitting the ramp signal from the ramp generator; a transistor having a gate terminal coupled to the input node and a drain terminal coupled to the power line; an output node coupled between a source terminal of the transistor and the column comparator; and an alternating current (AC) coupling unit coupled between the input node and the transistor, the AC coupling unit comprising: a capacitor coupled between the input node and the gate terminal of the transistor; and a reset switch coupled between the input node and the gate terminal of the transistor, wherein the reset switch is coupled in parallel to the capacitor.

[0005] Another aspect of the present application discloses an imaging system, comprising: a pixel array configured to generate a plurality of image charge voltage signals in response to incident light; and a readout circuit system coupled to the pixel array, the readout circuit system including a ramp generator configured to generate a ramp signal, and a plurality of column unit cells coupled to receive the ramp signal from the ramp generator and the image charge voltage signal from the pixel array, wherein each column unit cell comprises a column ramp buffer and a column comparator, and wherein each column ramp buffer comprises: an input node coupled to receive the ramp signal from the ramp generator; a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line; an output node coupled between a source terminal of the transistor and the column comparator; and an alternating current (AC) coupling unit coupled between the input node and the transistor, the AC coupling unit comprising: a capacitor coupled between the input node and the gate terminal of the transistor; and a reset switch coupled between the gate terminal of the transistor and the power line.

[0006] Another aspect of the present application discloses an imaging system, comprising: a pixel array configured to generate a plurality of image charge voltage signals in response to incident light; and a readout circuit system coupled to the pixel array, the readout circuit system including a ramp generator configured to generate a ramp signal, and a plurality of column unit cells coupled to receive the ramp signal from the ramp generator and the image charge voltage signal from the pixel array, wherein each column unit cell comprises a column ramp buffer and a column comparator, and wherein each column ramp buffer comprises: an input node coupled to receive the ramp signal from the ramp generator; a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line; an output node coupled between a source terminal of the transistor and the column comparator; and an alternating current (AC) coupling unit coupled between the input node and the transistor, the AC coupling unit comprising: a capacitor coupled between the input node and the gate terminal of the transistor; and a reset switch coupled between the gate terminal of the transistor and an adjustable bias voltage source. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0008] Figure 1 An example of an imaging system including a pixel array according to the teachings of the present disclosure is illustrated.

[0009] Figure 2 A schematic diagram illustrating a portion of an exemplary readout circuit in accordance with the teachings of the present disclosure is illustrated.

[0010] Figure 3 Illustrated is a readout timing diagram of an exemplary readout circuit in accordance with the teachings of the present disclosure.

[0011] Figure 4 A schematic diagram of an exemplary column ramp buffer in accordance with the teachings of the present disclosure is illustrated.

[0012] Figure 5 Illustrated is a readout timing diagram of an exemplary column ramp buffer in accordance with the teachings of the present disclosure.

[0013] Figure 6 A schematic diagram of another exemplary column ramp buffer in accordance with the teachings of the present disclosure is illustrated.

[0014] Figure 7 An exemplary reset switch included in a column ramp buffer according to the teachings of the present disclosure is illustrated.

[0015] Figure 8A schematic diagram of another exemplary column ramp buffer in accordance with the teachings of the present disclosure is illustrated.

[0016] Fig. 9 Illustrated is another exemplary column ramp buffer readout timing diagram in accordance with the teachings of the present disclosure.

[0017] Fig.10 Illustrated is another exemplary column ramp buffer readout timing diagram in accordance with the teachings of the present disclosure.

[0018] Throughout the several views of the drawings, corresponding reference characters indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some of the elements in the various figures may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present disclosure. In addition, common and well-known elements that are useful or necessary in commercially feasible embodiments are generally not depicted in order to facilitate a less obstructed view of these various embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] An example of an imaging system with a ramp buffer that provides an improved analog-to-digital conversion (ADC) range is disclosed. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, a person skilled in the relevant art will recognize that the techniques described herein may be practiced without one or more of the specific details or may be practiced with other methods, components, materials, etc. In other examples, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring certain aspects.

[0020] References throughout this specification to "one example" or "one embodiment" mean that a particular feature, structure, or characteristic described in conjunction with the example is included in at least one example of the present disclosure. Thus, the appearance of the phrase "in one example" or "in one embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0021] Spatially relative terms (e.g., "below," "below," "above," "below," "above," "upper," "top," "bottom," "left," "right," "center," "middle," etc.) may be used herein for ease of description to describe the relationship of one element or feature to another element or feature illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device when in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is rotated or flipped, then the elements described as being "below" or "below" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "below" may encompass both the above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly. In addition, it will also be understood that when an element is referred to as being "between" two other elements, the element may be the only element between the two other elements, or one or more intervening elements may also be present.

[0022] Throughout this specification, several technical terms are used. These terms will assume their ordinary meaning in the art to which they belong, unless otherwise specifically defined herein or the context in which they are used clearly implies otherwise. It should be noted that in this document, element names and symbols are used interchangeably (e.g., Si and silicon); however, the two have the same meaning.

[0023] As will be discussed, various examples of an imaging system having a ramp buffer that provides an improved analog-to-digital conversion (ADC) range are disclosed. In an image sensor, the ADC range is an important value that determines whether the image sensor can achieve a larger full well capacity. The ADC range can be affected by the pixel bit line signal range, the column ADC comparator operating range, the ramp generator output voltage range, the column ramp buffer output voltage range, etc. In addition, in some cases, in order to reduce power consumption, the voltage output by the power line coupled to the column ramp buffer is reduced, thereby further limiting the ADC range.

[0024] In various examples of the present disclosure, a column ramp buffer includes one or more alternating current (AC) coupling paths between input and output. One or more switches can be toggled to control the path taken by the ramp signal and boost the output voltage, thereby improving signal range and reducing process, voltage and temperature (PVT) variations.

[0025] In various examples, an imaging system includes a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and a readout circuit system coupled to the pixel array. The readout circuit system includes a ramp generator configured to generate a ramp signal, and a plurality of column unit cells coupled to receive the ramp signal from the ramp generator and the image charge voltage signal from the pixel array. Each column unit cell includes a column ramp buffer and a column comparator, and each column ramp buffer includes an input node coupled to receive the ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator, and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit includes a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor. The reset switch may be coupled to the capacitor in parallel.

[0026] In various examples, the AC coupling unit includes a capacitor coupled between the input node and a gate terminal of the transistor, and a reset switch coupled between the gate terminal of the transistor and the power line.

[0027] In various examples, the AC coupling unit includes a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the gate terminal of the transistor and an adjustable bias voltage source.

[0028] For illustration purposes, Figure 1 One example of an imaging system 100 having a readout circuit 106 including a column unit cell 122 is shown in accordance with the teachings of the present disclosure. In particular, Figure 1 1 illustrates an imaging system 100 including a pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and function logic 108. In one example, pixel array 102 is a two-dimensional (2D) array including a plurality of pixel circuits 104 (e.g., P1, P2, ..., Pn) arranged in rows (e.g., R1 to Ry) and columns (e.g., C1 to Cx) to acquire image data of a person, place, object, etc., which can then be used to reproduce an image of the person, place, object, etc.

[0029] In various examples, the readout circuit 106 may be configured to read out the image charge voltage signal through the column bit line 112. As will be discussed, in various examples, the readout circuit 106 may include an analog-to-digital converter (ADC). As shown in the depicted example, the ADC 118 is coupled to the column bit line 112 and is configured to convert the analog signal from the column bit line 112 to a digital signal. In various examples, a column amplifier may also be included and the column amplifier may be coupled to the column bit line 112 to amplify the analog signal received from the column bit line 112 for conversion to a digital signal by the ADC 118. In various examples, the ADC 118 includes a ramp generator 114 and a column unit cell 122. The ramp generator 114 has a ramp generator output from which a ramp signal is provided to the column unit cell 122 via a ramp signal line 120. In an example, the digital image data value generated by the column unit cell 122 may then be received by the function logic 108. Function logic 108 may simply store the digital image data or even manipulate the digital image data by applying post image effects (eg, cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or otherwise).

[0030] In one example, control circuit 110 is coupled to pixel array 102 to control the operation of a plurality of photodiodes in pixel array 102. For example, control circuit 110 may generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with a lighting effect such as a flash.

[0031] In one example, the imaging system 100 may be included in a digital camera, a mobile phone, a laptop computer, an endoscope, a security camera, or an imaging device for an automobile, etc. In addition, the imaging system 100 may be coupled to other pieces of hardware, such as a processor (general purpose or otherwise), a memory element, an output (USB port, wireless transmitter, HDMI port, etc.), a light / flash, an electrical input (keyboard, touch display, track pad, mouse, microphone, etc.), and / or a display. The other pieces of hardware may deliver instructions to the imaging system 100, extract image data from the imaging system 100, or manipulate the image data supplied by the imaging system 100.

[0032] Figure 2 A schematic diagram illustrating a portion of an exemplary readout circuit 206 according to the teachings of the present disclosure is shown. It should be understood that Figure 2 The readout circuit 206 may be included in Figure 1 1. An example of readout circuitry 106 in imaging system 100 is shown in FIG. 1, and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0033] The readout circuit 206 may include a global ramp generator 214 configured to generate a ramp signal. As shown in the depicted example, a ramp signal line 220 spans across several columns of the pixel array 202 to provide a ramp signal to a plurality of column unit cells 222. Each column unit cell 222 may include a column comparator 216, a column counter 226, and a column ramp buffer 230. Each column comparator 216 may be coupled to receive an image charge voltage signal from the pixel array 202 via one of the plurality of bit lines 212 and receive the ramp signal from the ramp signal line 220 through one of the column ramp buffers 230. Each column comparator 216 may then compare the image charge voltage signal to the ramp signal and provide a digital representation of the image charge voltage signal in response. The output of each comparator 216 is coupled to one of the column counters 226 that is configured to respond to when the comparator 216 flips, indicating when the image charge voltage signal from the bit line 212 crosses the ramp signal from the ramp signal line 220 .

[0034] Figure 3 The following is a readout timing diagram illustrating an exemplary readout circuit according to the teachings of the present disclosure. It should be understood that Figure 3 The timing diagram can be as follows Figure 2 2. An exemplary timing diagram of the readout circuit 206 is shown in FIG. 2, and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0035] In the illustrated timing diagram, at t1, the ramp signal 320 is offset by an offset voltage V_offset, for example, to improve the linearity of the ramp signal 320. Between times t2 and t3, the ramp signal 320 ramps down so that the pixels from the pixel array (eg, Figure 2 2. The ramp signal 320 is reset to a reset level of a signal of the pixel array 202 in FIG. 2. After the ramp signal 320 returns to the offset voltage V_offset at time t3, the image signal from the pixel array is read out through one or more bit lines 312 starting at time t4. In various examples, the bit lines 312 may carry both the image signal V_signal and the dark current signal V_dc. Although the offset voltage V_offset is positive and the ramp signal 320 is ramped down in the illustrated embodiment, the offset voltage V_offset may be negative and the ramp signal 320 may be ramped up in other embodiments.

[0036] By time t5, the image signal on bit line 312 has stabilized and ramp signal 320 begins to ramp down so that the image signal on bit line 312 can be compared (e.g., by comparator 216) to ramp signal 320. In the illustrated embodiment, there is sufficient ADC range and ramp signal 320 intersects the image signal on bit line 312 at time t6. Between times t6 and t7, ramp signal 320 may continue to ramp as the comparator makes the comparison, resulting in additional voltage difference V_cmpdly associated with the comparator delay.

[0037] Therefore, in order to have sufficient ADC range, the ramp signal 320 received by the comparator may need to have a voltage range large enough to cover the sum of the offset voltage V_offset, the image signal V_signal, the dark current signal V_dc, and the comparator delay voltage difference V_cmpdly. Depending on the size of the image signal V_signal and other factors, this may be challenging for an imaging system that includes a conventional ramp buffer. The ramp buffer may be advantageously used to adjust the ramp signal generated by a global ramp generator (e.g., ramp generator 214) to make it more suitable for use by downstream components. For example, the ramp buffer may provide amplification, level shifting, and / or filtering of the ramp signal. However, the use of the ramp buffer may also result in a range loss compared to the ramp signal provided by the global ramp generator. As will be described in further detail below, various examples of the present disclosure are intended to improve the ADC range by, for example, reducing the range loss due to the ramp buffer.

[0038] Figure 4 A schematic diagram of an exemplary column ramp buffer 430 is illustrated in accordance with the teachings of the present disclosure. It should be appreciated that Figure 4 The ramp buffer 430 may be as follows Figure 2 , and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0039] The ramp buffer 430 may include an input node 432 coupled to receive a ramp signal generated by the global ramp generator 414. The voltage at the input node 432 may be represented as Vramp_gl. The ramp buffer 430 may also include a transistor 434 having a gate terminal coupled to the input node 432, a drain terminal coupled to the power line AVDD 460, a source terminal coupled to an output node 436, and a body terminal coupled to the source terminal. In various examples, the transistor 434 is a low threshold transistor (LVT). In various examples, the transistor 434 is an NMOS or PMOS transistor. The output node 436 may be coupled to a component downstream of the readout circuit, such as the comparator 416. The voltage at the output node 436 may be represented as Vramp_lc. The ramp buffer 430 may further include a current source 438 coupled between the output node 436 and ground. In the example where transistor 434 is a PMOS transistor, power line AVDD 460 and ground are interchangeable such that the drain terminal of PMOS transistor 434 is coupled to ground and current source 438 is coupled between output node 436 and power line AVDD 460 .

[0040] The transistor 434 and / or the output node 436 may be coupled to the input node 432 via an alternating current (AC) coupling unit 440. The AC coupling unit 440 may include a first capacitor C1 442 coupled between the input node 432 and an AC coupling node 443. The AC coupling node 443 may be coupled to a gate terminal of the transistor 434. The voltage at the AC coupling node 443 may be represented as Vramp_ac. The AC coupling unit 440 may also include a first reset switch rst1 444 coupled between the AC coupling node 443 and a voltage source node 441. In the illustrated embodiment, the voltage source node 441 is coupled to the input node 432 such that the first reset transistor rst1 444 is coupled in parallel to the first capacitor C1 442. In various examples, the voltage source node 441 may be coupled elsewhere, as will be described below with respect to Figure 6 and 7 Described in further detail.

[0041] The AC coupling unit 440 may include a boost switch bst446 coupled between the input node 432 and the first capacitor C1 442. The boost switch bst 446 and the first capacitor C1 442 define a node 445 therebetween. The AC coupling unit 440 may also include a second reset switch rst2 447 coupled between the node 445 and the output node 436. The first reset switch rst1 444 and the second reset switch rst2 447 may be independently controlled (e.g., by two different switch control signals) or controlled together (e.g., by a shared switch control signal). In various examples, the AC coupling unit 440 may further include a second capacitor C2 448 coupled between the input node 432 and the AC coupling node 443. In the illustrated embodiment, the second capacitor C2 448 is coupled in parallel to the first capacitor C1 442 and is also coupled in parallel to the first reset switch rst1 444. In various examples, one or more of the first reset switch rst1 444, the second reset switch rst2 447, and the boost switch bst 446 may include a transistor. Figure 5 Described in further detail, by controlling the first reset switch RST1 444, the second reset switch RST2 447, and the boost switch BST 446, the AC coupling unit 440 can switch back and forth between the direct path and the AC coupling path to allow the ramp signal to travel through.

[0042] Figure 5 The following is a readout timing diagram of an exemplary column ramp buffer according to the teachings of the present disclosure. It should be understood that Figure 5 The timing diagram can be as follows Figure 4 0048] An exemplary timing diagram of a ramp buffer 430 is shown in FIG. 10, and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0043] In the illustrated timing diagram, the reset switch control signal rst 544 is configured to be turned on before time t1 (eg, at time t8 of the previous ADC cycle) and turned off at time t1. In various examples, the reset switch control signal rst 544 may be used to control Figure 4 444 and the second reset switch rst2 447 illustrated in FIG. 546. The boost switch control signal bst 546 is configured to remain off until time t2. Figure 4 and 5, when the first reset switch rst1 444 is turned on and the boost switch bst 446 is turned off (i.e., before time t1), the first reset switch rst1 444 provides a direct path between the input node 432 and the AC coupling node 443. Therefore, Vramp_gl 532 (i.e., the voltage level at the input node 432) and Vramp_ac 543 (i.e., the voltage level at the AC coupling node 443) are tied together.

[0044] At time t2, when the boost switch control signal bst 546 is turned on and the reset switch control signal rst 544 remains off, the ramp signal from the ramp generator 414 must travel through the AC coupling path formed by the first capacitor C1 442 (and the second capacitor C2 448, if present). At this time, Vramp_gl is connected to the left plate of the first capacitor C1 442 (and the second capacitor C2 448, if present) and Vramp_ac will be boosted by:

[0045] Vboost=Vgs*C_2 / (C_1+C_2)

[0046] Where Vgs is the gate-source voltage of transistor 434, C_1 is the capacitance of first capacitor C1 442, and C_2 is the capacitance of second capacitor C2 448. In various examples, if both first capacitor C1 442 and second capacitor C2 448 are present and capacitance C_1 is sufficiently greater than capacitance C_2 (e.g., C2 / (C1+C2)>=0.9), then Vboost may exceed 0.22V. In various examples, C_1 and C_2 may have a ratio of approximately 1:9 (e.g., C_1 and C_2 are 20fF and 180fF, respectively). In various examples, Vgs may range between 100mV and 600mV. In other embodiments, C_1, C_2, and Vgs may have other values ​​depending on the constraints and requirements of the imaging system. In various examples, Vboost may also compensate for PVT variations of transistor 434 to make the signal range more independent of PVT variations.

[0047] like Figure 5, when the boost switch control signal bst 546 is turned on, Vramp_ac 543 is boosted to Vboost 552, and this difference from Vramp_gl 532 is maintained while the boost switch control signal bst 546 remains on until time t7. The gate-source voltage Vgs of transistor 434 (which is also the difference between Vramp_ac 543 and Vramp_lc 536) can be kept constant so that the boosted Vramp_ac 543 also boosts Vramp_lc 536. As shown in the following example, this effectively increases the range of Vramp_lc 536 (i.e., the difference between the highest voltage level and the lowest voltage level) and improves the signal range of ramp buffer 430. At time t3, the ramp signal is offset to improve linearity, for example. Between times t4 and t5, the reset level is read out, and between times t6 and t7, the image signal is read out. At time t7, the boost switch control signal bst 546 is turned off again. At time t8, the reset switch control signal rst 544 is turned on in the next ADC cycle.

[0048] In various instances, Figure 4 The power line AVDD 460 illustrated in may be configured to provide a voltage level of 2.8 V. The following table illustrates an exemplary set of voltage values ​​during a readout cycle.

[0049] AVDD=2.8V Before boost After boost V_signal(range) 1 V 1.1V V_ramp(range) 2V 2.23V Vramp_gl High / Low 2.4V / 0.4V 2.4V / 0.18V Vramp_lc high / low 2.15V / 0.15V 2.38V / 0.15V

[0050] As shown, the ramp signal range V_ramp (ie, the difference between Vramp_lc high and low) may increase by 0.22 V, while the image signal range V_signal may increase by 0.1 V. Furthermore, under PVT variations, the voltage margin of the current source 438 may increase by 150 mV.

[0051] The power line AVDD 460 can be a significant source of power consumption. In various examples, the power line AVDD 460 can be configured to provide a lower voltage level of 2.2V in order to save power. The following table illustrates an exemplary set of voltage values ​​during a readout cycle.

[0052] AVDD=2.2V Before boost After boost V_signal(range) 0.7 V 0.8V V_ramp(range) 1.42V 1.65V Vramp_gl High / Low 1.8V / 0.4V 1.8V / 0.18V Vramp_lc high / low 1.55V / 0.15V 1.78V / 0.15V

[0053] As shown, the ramp signal range V_ramp (ie, the difference between Vramp_lc high and low) may increase by 0.22 V, while the image signal range V_signal may increase by 0.1 V. Furthermore, under PVT variations, the voltage margin of the current source 438 may be fixed at 150 mV.

[0054] Figure 6A schematic diagram of another exemplary column ramp buffer 630 is illustrated in accordance with the teachings of the present disclosure. It should be appreciated that Figure 6 The ramp buffer 630 may be as follows Figure 2 , and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0055] The ramp buffer 630 may include an input node 632 coupled to receive a ramp signal generated by a global ramp generator (not shown). The voltage at the input node 632 may be represented as Vramp_gl. The ramp buffer 630 may also include a transistor 634 having a gate terminal coupled to the input node 632, a drain terminal coupled to the power line AVDD660, a source terminal coupled to an output node 636, and a body terminal coupled to the source terminal. In various examples, the transistor 634 is a low threshold transistor (LVT). In various examples, the transistor 634 is an NMOS or PMOS transistor. The output node 636 may be coupled to a component downstream of the readout circuit (e.g., the comparator 216). The voltage at the output node 636 may be represented as Vramp_lc. The ramp buffer 630 may further include a current source 638 coupled between the output node 636 and ground. In the example where transistor 634 is a PMOS transistor, power line AVDD 660 and ground are interchangeable such that the drain terminal of PMOS transistor 634 is coupled to ground and current source 638 is coupled between output node 636 and power line AVDD 660 .

[0056] The transistor 634 and / or the output node 636 may be coupled to the input node 632 through an alternating current (AC) coupling unit 640. The AC coupling unit 640 may include a capacitor C1 642 coupled between the input node 632 and an AC coupling node 643. The AC coupling node 643 may be coupled to the gate terminal of the transistor 634. The voltage at the AC coupling node 643 may be represented as Vramp_ac. The AC coupling unit 640 may also include a reset switch rst 644 coupled between the AC coupling node 643 and a voltage source node 641. In the illustrated embodiment, the voltage source node 641 is coupled to the power line AVDD 660.

[0057] In various examples, the reset switch rst 644 may include a transistor. In various examples, the upper limit of Vramp_ac may be AVDD+0.1V, and thus to avoid leakage through the reset switch rst 644, the body terminal of the reset switch 644 may be coupled to another power line that provides a voltage level higher than the voltage level provided by the power line AVDD 660. Although the ramp buffer 630 is not PVT-invariant, it may have a sufficient voltage range.

[0058] Figure 7 An exemplary reset switch 744 included in a column ramp buffer according to the teachings of the present disclosure is illustrated. It should be appreciated that Figure 7 The reset switch 744 may be as follows Figure 6 , and similarly named and numbered elements described above are similarly coupled and function similarly hereinafter.

[0059] In the illustrated embodiment, reset switch 744 is a PMOS transistor having a source terminal coupled to voltage source node 741, a drain terminal coupled to AC coupling node 743, a gate terminal coupled to control signal node 766, and a body terminal coupled to power line HVDD. Voltage source node 741 can be coupled to a different power line (e.g., power line AVDD 660). AC coupling node 743 can be coupled to a gate terminal of another transistor (e.g., transistor 634) and has a voltage level Vramp_ac. Control signal node 766 can be coupled to receive a reset switch control signal for controlling reset switch 744. In various examples, power line HVDD can be configured to provide a higher voltage level than another power line (e.g., power line AVDD 660) in the column ramp buffer, which can reduce or prevent leakage through reset switch 744.

[0060] Figure 8 A schematic diagram of another exemplary column ramp buffer 830 is illustrated in accordance with the teachings of the present disclosure. It should be appreciated that Figure 8 The ramp buffer 830 may be as follows Figure 2 , and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0061] The ramp buffer 830 may include an input node 832 coupled to receive a ramp signal generated by a global ramp generator (not shown). The voltage at the input node 832 may be represented as Vramp_gl. The ramp buffer 830 may also include a transistor 834 having a gate terminal coupled to the input node 832, a drain terminal coupled to the power line AVDD860, a source terminal coupled to an output node 836, and a body terminal coupled to the source terminal. In various examples, the transistor 834 is a low threshold transistor (LVT). In various examples, the transistor 834 is an NMOS or PMOS transistor. The output node 836 may be coupled to a component downstream of the readout circuit (e.g., the comparator 216). The voltage at the output node 836 may be represented as Vramp_lc. The ramp buffer 830 may further include a current source 838 coupled between the output node 836 and ground.

[0062] The transistor 834 and / or the output node 836 may be coupled to the input node 832 via an alternating current (AC) coupling unit 840. The AC coupling unit 840 may include a capacitor C1 842 coupled between the input node 832 and an AC coupling node 843. The AC coupling node 843 may be coupled to the gate terminal of the transistor 834. The voltage at the AC coupling node 843 may be represented as Vramp_ac. The AC coupling unit 840 may also include a reset switch rst 844 coupled between the AC coupling node 843 and a voltage source node 841. In the illustrated embodiment, the voltage source node 841 is coupled to a bias voltage source Vrst 862. In various examples, the bias voltage source Vrst 862 may be adjusted so that the leakage through the reset switch rst 844 is not excessive while still providing a sufficient voltage range.

[0063] Fig. 9 The following is a readout timing diagram of another exemplary column ramp buffer according to the teachings of the present disclosure. It should be understood that Fig. 9 The timing diagram can be as follows Figure 6 and 8 1 and 2. An exemplary timing diagram of ramp buffers 630 and 830 is shown in FIG. 1 , and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0064] In the illustrated timing diagram, the reset switch control signal rst 944 may be used to control the reset switch (eg, reset switch 644 or 844). The reset switch control signal rst 944 may be configured to be turned on before time t1 (eg, at time t7 of the previous ADC cycle) and turned off at time t1. Figure 6 , 8 9, when the reset switch control signal RST 944 is high, the reset switch RST 644 / 844 provides a direct path between the AC coupling node 643 / 843 and the power line AVDD 660 or the bias voltage source Vrst 862. Therefore, Vramp_ac 943 (e.g., the voltage level at the AC coupling node 643 / 843) and the voltage level provided by the power line AVDD 660 or the bias voltage source Vrst 862 are tied together.

[0065] Thus, Vramp_ac 943 may be at AVDD 660 or Vrst 862 at time t1 and jump to AVDD+V_offset 956 or Vrst+V_offset 956 at time t2. In various examples, V_offset may be set to approximately 0.1V. Vramp_ac 943 and Vramp_gl 932 may accordingly remain separated by Vboost 952. The following table illustrates the voltages for Vramp_ac 943 and Vramp_gl 932 when Vrst is set to Vramp_gl+0.225V at t1 and AVDD 660 provides voltages of 2.8V (minimum 2.6V) and 2.2V (minimum 2V), respectively. Figure 8 Several sets of exemplary voltage values ​​during a readout cycle of the ramp buffer 830 are shown in FIG.

[0066]

[0067]

[0068]

[0069] Note that the Vramp_lc high value after boosting may correspond to Vrst+V_offset-Vgs.

[0070] Fig.10 The following is a readout timing diagram of another exemplary column ramp buffer according to the teachings of the present disclosure. It should be understood that Fig.10 The timing diagram can be as follows Figure 6 and 8 1 and 2. An exemplary timing diagram of ramp buffers 630 and 830 is shown in FIG. 1 , and similarly named and numbered elements described above are similarly coupled and function hereinafter.

[0071] In the illustrated timing diagram, the comparator (e.g., comparator 216) may be automatically zeroed at time t1. At time t2, the ramp signal may be offset by V_offset 1056 for improved linearity. Thereafter, the reset switch control signal rst 1044 may be pulsed between times t2 and t3 to toggle the reset switch (e.g., reset switch 644 or 844) on and off. Figure 6 , 810, when the reset switch control signal rst 1044 is high, the reset switch rst 644 / 844 provides a direct path between the AC coupling node 643 / 843 and the power line AVDD 660 or the bias voltage source Vrst 862. Therefore, Vramp_ac 1043 (e.g., the voltage level at the AC coupling node 643 / 843) and the voltage level provided by the power line AVDD 660 or the bias voltage source Vrst 862 are tied together while the reset switch control signal rst 1044 is pulsed and / or Vramp_ac is at its maximum voltage level (i.e., between time t2 and t3, and / or between time t4 and t5).

[0072] Thus, it may not be necessary to couple the bulk terminal of reset switch 644 to another power line that provides a voltage level higher than the voltage level provided by power line AVDD 660, as described above with respect to Figure 6 Vramp_ac 1043 and Vramp_gl 1032 can remain separated by Vboost 1052. The following table illustrates the voltage difference between Vrst and Vramp_gl when Vrst is set to Vramp_gl + 0.225V at t2-t3 and AVDD 660 provides 2.8V (minimum 2.6V) and 2.2V (minimum 2V) respectively. Figure 8 Several sets of exemplary voltage values ​​during a readout cycle for the configuration shown in FIG.

[0073]

[0074]

[0075] Note that the Vramp_lc high value after boosting may correspond to Vrst-Vgs.

[0076] The above description of the illustrated examples of the present disclosure, including the contents described in the above tables and the Abstract of the Invention, is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Although specific examples of the present disclosure are described herein for illustrative purposes, various modifications may be made within the scope of the present disclosure as will be appreciated by those skilled in the relevant art.

[0077] These modifications may be made to the present disclosure in light of the above detailed description. The terms used in the appended claims should not be understood to limit the present disclosure to the specific examples disclosed in this specification. Instead, the scope of the present disclosure will be determined entirely by the appended claims, which will be interpreted according to established claim interpretation principles.

Claims

1. An imaging system, comprising: a pixel array configured to generate a plurality of image charge voltage signals in response to incident light; as well as a readout circuitry coupled to the pixel array, the readout circuitry comprising a ramp generator configured to generate a ramp signal, and a plurality of column unit cells coupled to receive the ramp signal from the ramp generator and the image charge voltage signal from the pixel array, wherein each column unit cell comprises a column ramp buffer and a column comparator, and wherein each column ramp buffer comprises: an input node coupled to receive the ramp signal from the ramp generator; a transistor having a gate terminal coupled to the input node and a drain terminal coupled to the power line; an output node coupled between a source terminal of the transistor and the column comparator; and An AC coupling unit is coupled between the input node and the transistor, and the AC coupling unit includes: a capacitor coupled between the input node and the gate terminal of the transistor; and A reset switch is coupled between the input node and the gate terminal of the transistor, wherein the reset switch is coupled in parallel to the capacitor. 2 . The imaging system according to claim 1 , wherein the AC coupling unit further comprises a boost switch coupled between the input node and the capacitor.

3. The imaging system of claim 2, wherein the reset switch is configured to be turned off at a first time, wherein the boost switch is configured to be turned on at a second time after the first time, and wherein the ramp generator is configured to generate the ramp signal at a third time after the second time.

4. The imaging system of claim 3, wherein the ramp generator is configured to stop generating the ramp signal at a fourth time after the third time, wherein the boost switch is configured to be turned off at the fourth time, and wherein the reset switch is configured to be turned on at a fifth time after the fourth time. 5 . The imaging system of claim 1 , wherein the reset switch is a first reset switch, and wherein the AC coupling unit further comprises a second reset switch coupled between the capacitor and the output node. 6 . The imaging system of claim 5 , wherein the first reset switch and the second reset switch are configured to be controlled by a shared reset control signal.

7. The imaging system according to claim 1, wherein the reset switch is a first reset switch, and wherein the AC coupling unit further comprises: a boost switch coupled between the input node and the capacitor; a boost node coupled between the boost switch and the capacitor; and A second reset switch is coupled between the boost node and the output node.

8. The imaging system of claim 1 , wherein the capacitor is a first capacitor, and wherein the AC coupling unit further comprises: A second capacitor is coupled between the input node and the gate terminal of the transistor.

9. The imaging system of claim 8, wherein the second capacitor is coupled in parallel to the first capacitor, and wherein the second capacitor is coupled in parallel to the reset switch.

10. The imaging system of claim 1, wherein each column ramp buffer further comprises a current source coupled between the output node and ground.

11. An imaging system comprising: a pixel array configured to generate a plurality of image charge voltage signals in response to incident light; as well as a readout circuitry coupled to the pixel array, the readout circuitry comprising a ramp generator configured to generate a ramp signal, and a plurality of column unit cells coupled to receive the ramp signal from the ramp generator and the image charge voltage signal from the pixel array, wherein each column unit cell comprises a column ramp buffer and a column comparator, and wherein each column ramp buffer comprises: an input node coupled to receive the ramp signal from the ramp generator; a transistor having a gate terminal coupled to the input node and a drain terminal coupled to the power line; an output node coupled between a source terminal of the transistor and the column comparator; and An AC coupling unit is coupled between the input node and the transistor, and the AC coupling unit includes: a capacitor coupled between the input node and the gate terminal of the transistor; and A reset switch is coupled between the gate terminal of the transistor and the power line. 12 . The imaging system of claim 11 , wherein the reset switch is configured to be turned off at a first time, wherein the ramp generator is configured to generate the ramp signal at a second time after the first time.

13. The imaging system of claim 12, wherein the ramp generator is configured to stop generating the ramp signal at a third time after the second time, and wherein the reset switch is configured to be turned on at a fourth time after the third time.

14. The imaging system of claim 11, wherein the column comparator is configured to automatically zero at a first time, wherein the reset switch is configured to be pulsed at a second time after the first time, and wherein the ramp generator is configured to generate the ramp signal at a third time after the second time.

15. The imaging system of claim 14, wherein the ramp signal is configured to be offset by an offset voltage between the first time and the second time.

16. The imaging system of claim 11, wherein the power line is a first power line, wherein the reset switch comprises a reset transistor having a body terminal coupled to a second power line, and wherein the second power line is configured to provide a voltage level greater than a voltage level provided by the first power line.

17. An imaging system comprising: a pixel array configured to generate a plurality of image charge voltage signals in response to incident light; as well as a readout circuitry coupled to the pixel array, the readout circuitry comprising a ramp generator configured to generate a ramp signal, and a plurality of column unit cells coupled to receive the ramp signal from the ramp generator and the image charge voltage signal from the pixel array, wherein each column unit cell comprises a column ramp buffer and a column comparator, and wherein each column ramp buffer comprises: an input node coupled to receive the ramp signal from the ramp generator; a transistor having a gate terminal coupled to the input node and a drain terminal coupled to the power line; an output node coupled between a source terminal of the transistor and the column comparator; and An AC coupling unit is coupled between the input node and the transistor, and the AC coupling unit includes: a capacitor coupled between the input node and the gate terminal of the transistor; and A reset switch is coupled between the gate terminal of the transistor and an adjustable bias voltage source.

18. The imaging system of claim 17, wherein the reset switch is configured to be turned off at a first time, wherein the ramp generator is configured to generate the ramp signal at a second time after the first time.

19. The imaging system of claim 18, wherein the ramp generator is configured to stop generating the ramp signal at a third time after the second time, and wherein the reset switch is configured to be turned on at a fourth time after the third time.

20. The imaging system of claim 17, wherein the column comparator is configured to automatically zero at a first time, wherein the reset switch is configured to be pulsed at a second time after the first time, and wherein the ramp generator is configured to generate the ramp signal at a third time after the second time.

Images