Residual pulse stretching interpolation quantization column-level ADC, CMOS image sensor

Abstract

The present application relates to a residual pulse stretching interpolation quantization type column-level ADC and a CMOS image sensor, wherein the residual pulse stretching interpolation quantization type column-level ADC includes: a comparator, a residual extraction circuit, a pulse stretching circuit, a coarse quantization counter, a fine quantization counter, and an error correction circuit; the comparator is used to compare a ramp signal and a pixel signal, and the output of the comparator is connected to the input of the residual extraction circuit and the input of the coarse quantization counter through a first AND gate; the residual extraction circuit is used to extract the time difference between the output falling edge of the first AND gate and the first rising edge of the clock after itself, and the output of the residual extraction circuit is connected to the input of the pulse stretching circuit and the input of the error correction circuit; the pulse stretching circuit is used to stretch the output of the residual extraction circuit, and the output of the pulse stretching circuit is connected to the input of the fine quantization counter. This solves the problems of slow quantization speed and low time accuracy of current SSADCs.

Description

Technical Field

[0001] The present application relates to the field of image sensors, and in particular to a residual pulse stretching interpolation quantization type column-level ADC and a CMOS image sensor. Background Art

[0002] CMOS image sensors have developed rapidly in recent years. Compared to CCDs, CMOS image sensors (CIS) offer significant advantages in imaging, including low power consumption, low production costs, high integration, fast readout speeds, and a wide dynamic range. These advantages have made CMOS image sensors a hot research topic for researchers both domestically and internationally. The speed of the A / D converter directly determines the overall performance of an image sensor. Consequently, the requirements for ADC (analog-to-digital converter) speed and power consumption are increasing. However, these two requirements are often conflicting. SSADCs (single slope ADCs) are the most widely used in CIS due to their column sharing and high consistency. However, two issues limit improvements in ADC speed and accuracy.

[0003] First, SSADC directly uses the one-to-one correspondence between the counter value and the ramp voltage, and records the counter value when the comparator flips. Therefore, the single quantization cycle of SSADC is 2 n CLK. To increase the circuit's quantization speed without changing the circuit structure, the only way to increase the clock speed is to brute-force increase the clock frequency. However, the clock frequency cannot be increased indefinitely, which increases the design difficulty of the entire circuit, especially the comparator and counter. Another influencing factor is that the comparator flipping moment does not always align with the clock edge. The flipping moment will have a time margin with the previous clock edge. The loss of quantization due to this time margin limits further improvement of the ADC resolution. One common solution is to introduce a higher-frequency clock to improve the ADC resolution, but this will have the same impact as the previous problem.

[0004] Although there are some solutions to the above problems, there is no particularly good solution to achieve the goal of picosecond time resolution. Summary of the Invention

[0005] The present invention provides a residual pulse stretching interpolation quantization type column-level ADC to solve the problems of slow quantization speed and low time precision of the current SSADC.

[0006] The present invention provides a residual pulse stretching interpolation quantization type column-level ADC, comprising: a comparator, a residual extraction circuit, a pulse stretching circuit, a coarse quantization counter, a fine quantization counter and an error correction circuit;

[0007] The comparator is used to compare the ramp signal and the pixel signal, and the output end of the comparator is connected to the input end of the residual extraction circuit and the input end of the coarse quantization counter through a first AND gate;

[0008] The residual error extraction circuit is used to extract the time difference between the output falling edge of the first AND gate and the first clock rising edge after the first AND gate, and the output end of the residual error extraction circuit is connected to the input end of the pulse stretching circuit and the input end of the error correction circuit;

[0009] The pulse stretching circuit is used to stretch the output of the residual extraction circuit, and the output end of the pulse stretching circuit is connected to the input end of the fine quantization counter;

[0010] The carry output terminal and the sign output terminal of the fine quantization counter are both connected to the input terminal of the error correction circuit;

[0011] The output end of the error correction circuit is connected to the input end of the coarse quantization counter. The error correction circuit is used to generate an error correction signal according to the carry output and sign output of the fine quantization counter and the output of the residual extraction circuit.

[0012] Compared with the related art, the present invention divides the quantization process into coarse quantization and fine quantization by interpolation, which can improve the quantization speed. For example, in the case of 7-bit coarse quantization and 4-bit fine quantization, the present invention can 11 The quantization cycle is shortened to 2 7 +2 4 quantization cycles (fine quantization has one redundant correction bit), a 93% reduction. Furthermore, due to its pulse stretching properties, this circuit improves its tolerance to high-speed quantization. Furthermore, the two-step ADC design ensures that the fine quantization counter only requires 16 clock cycles, reducing power consumption and addressing the current issues of slow quantization speed and low time accuracy of SSADCs.

[0013] Compared with related technologies, the present invention unifies some pulse stretching operations into one after coarse quantization is completed, thereby achieving column sharing of the first capacitor of the pulse stretching circuit and effectively saving circuit area.

[0014] Compared with the related art, the present invention proposes an RC integral pulse stretching circuit, which enables the ADC to have higher time resolution.

[0015] The details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is the circuit architecture of a residual pulse stretching interpolation quantization column-level ADC in one embodiment of the present invention;

[0017] Figure 2 is a circuit diagram of a comparator in one embodiment of the present invention;

[0018] Figure 3 is a circuit diagram of a residual error extraction circuit in one embodiment of the present invention;

[0019] Figure 4 is a signal timing diagram of a residual error extraction circuit in one embodiment of the present invention;

[0020] Figure 5 is a circuit diagram of a pulse stretching circuit in one embodiment of the present invention;

[0021] Figure 6 is an integral schematic diagram of a pulse stretching circuit in one embodiment of the present invention;

[0022] Figure 7 is a signal timing diagram of a pulse stretching circuit in one embodiment of the present invention;

[0023] Figure 8 1 is a resistance equivalent schematic diagram of a pulse stretching circuit in one embodiment of the present invention;

[0024] Figure 9 1. It is a schematic diagram of the splicing of the coarse quantization counting result and the fine quantization counting structure in one embodiment of the present invention;

[0025] Figure 10 is a circuit diagram of a fine quantization counter in one embodiment of the present invention;

[0026] Figure 11 is a circuit diagram of a coarse quantization counter in one embodiment of the present invention;

[0027] Figure 12 is a schematic diagram of carry and misalignment in one embodiment of the present invention;

[0028] Figure 13 1 is a timing diagram of a counter rollover error in one embodiment of the present invention;

[0029] Figure 14 is a circuit diagram of a signal generating circuit in one embodiment of the present invention;

[0030] Figure 15 is a circuit diagram of a pulse selection circuit in one embodiment of the present invention;

[0031] Figure 16 is a timing diagram of error correction in one embodiment of the present invention;

[0032] Figure 17FIG. 4 is an operating timing diagram of a residual pulse stretching interpolation quantization column-level ADC according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0034] Unless otherwise defined, technical or scientific terms used in this application shall have the ordinary meanings as understood by persons of ordinary skill in the art to which this application belongs. The terms "a," "an," "the," "these," and similar expressions in this application do not denote limitations on quantity and may be singular or plural. The terms "comprise," "include," "have," and any variations thereof, as used in this application, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include unlisted steps or modules (units) or other steps or modules (units) inherent to the process, method, product, or device. The terms "connected," "connected," "coupled," and similar expressions used in this application are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. As used in this application, "plurality" means two or more. "And / or" describes an association between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone; A and B exist simultaneously; or B exists alone. Generally, the character " / " indicates that the objects in the preceding and following relationship are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0035] In an embodiment of the present invention, a residual pulse stretching interpolation quantization type column-level ADC is provided.

[0036] like Figure 1 As shown, in this embodiment, the ADC includes: a comparator, a residual extraction circuit (Tresidue), a pulse stretching circuit (TA), a coarse quantization counter, a fine quantization counter and an error correction circuit.

[0037] The comparator is used to compare the ramp signal V ramp and pixel signal V pixleThe output of the comparator is connected to the input of the residual error extraction circuit and the input of the coarse quantization counter via a first AND gate. The two inputs of the first AND gate are connected to the comparator output and the comparator enable signal Comoen, respectively. When the comparator output flips, the output signal Φcomp of the first AND gate also flips. The comparator enable signal Comoen can then select and control the flip signal of the comparator, masking the invalid flip interval and generating the output signal Φcomp of the first AND gate.

[0038] In this embodiment, the comparator uses an input offset storage circuit to store the offset voltage. Figure 2 Specifically, the comparator is a continuous time comparator, which includes a cascaded first operational amplifier OPA1 and a second operational amplifier OPA2; the in-phase input terminal and the inverting input terminal of the first operational amplifier OPA1 are respectively used to access the ramp signal V ramp and pixel signal V pixle The non-inverting output terminal of the second operational amplifier OPA2 is the output terminal of the continuous-time comparator; the non-inverting input terminal and the inverting output terminal of the first operational amplifier OPA1, as well as the inverting input terminal and the non-inverting output terminal, are connected through the first control switch S1, and the non-inverting input terminal and the inverting output terminal of the second operational amplifier OPA2, as well as the inverting input terminal and the non-inverting output terminal, are connected through the second control switch S2; the current sources of the first operational amplifier OPA1 and the second operational amplifier OPA2 both adopt a cascode structure.

[0039] In the initial state of the comparator, the first control switch S1 and the second control switch S2 are turned on at the same time. After sampling the input signal (ramp signal and pixel signal), the first control switch S1 and the second control switch S2 are turned off in sequence to reduce the impact of charge injection. The first operational amplifier OPA1 and the second operational amplifier OPA2 have the same structure. The two-stage cascade forms a continuous time hysteresis structure, which can effectively improve the gain. The use of a continuous time comparator is determined by the principle of this circuit. This is because the flip point of the dynamic comparator is discrete, and the extracted time margin is basically a fixed value, which is not applicable to the interpolation principle of the present invention. The current source of the two operational amplifiers uses a cascode structure to improve the current replication accuracy. The ramp signal V ramp With the pixel signal V pixle The range is in the "sweet spot" of the comparator. This is done to make the comparator's flip delay at different reversal points as consistent as possible, thereby reducing the impact on INL (integral nonlinearity error).

[0040] The internal structure of the comparator in this embodiment is as follows Figure 2As shown, the current source adopts a cascode structure (a first transistor M1 and a second transistor M2). The drain of the first transistor M1 is connected to the source of the second transistor M2. The lower transistor is diode-connected, and the gate of the other transistor is connected to the drain of the opposite transistor, forming a positive feedback structure. It should be noted that the internal structure of the comparator is a mature circuit structure. The present invention focuses on the selection of the current source structure, and does not provide a detailed description of other parts of the structure. Please refer to Figure 3 Compared with other types of comparators, this comparator structure can achieve a shorter and more consistent time delay in the quantization interval while achieving a larger gain.

[0041] The residue extraction circuit is used to extract the time difference between the falling edge of the output of the first AND gate (the falling edge of Φcomp) and the first rising edge of the clock signal CLK following the first AND gate (referring to the falling edge of the output of the first AND gate) (the pulse width of the output signal Tr of the residue extraction circuit represents this time difference). The output end of the residue extraction circuit (output signal Tr) is connected to the input end of the pulse stretching circuit and the input end of the error correction circuit.

[0042] In this embodiment, referring to Figure 3 The residual error extraction circuit includes a first D flip-flop and a NOR gate; the D terminal of the first D flip-flop is connected to the output terminal of the first AND gate (for receiving the output signal Φcomp of the first AND gate), the CK terminal of the first D flip-flop is used to receive the clock signal CLK, the QB terminal of the first D flip-flop is connected to the first input terminal of the NOR gate, the second input terminal of the NOR gate is connected to the output terminal of the first AND gate (for receiving the output signal Φcomp of the first AND gate), and the output terminal of the NOR gate becomes the output terminal of the residual error extraction circuit after passing through a buffer.

[0043] In this embodiment, the input end of the residual error extraction circuit is composed of a D flip-flop and a NOR gate in series. The waveforms of the output signal Tr and related signals of the residual error extraction circuit are as follows: Figure 4 , where TA_en is the TA enable signal, which is used to control the pulse stretching operation when fine quantization starts after coarse quantization ends.

[0044] The pulse stretching circuit is used for stretching the output of the residual error extraction circuit, and the output end of the pulse stretching circuit is connected to the input end of the fine quantization counter.

[0045] In this embodiment, the coarse quantization counter is used to implement 7-bit counting, the fine quantization counter is used to implement 4-bit counting, and the pulse stretching circuit is used to implement 16-fold pulse stretching.

[0046] Reference Figure 5Specifically, the pulse stretching circuit includes a first RC integration circuit, a second RC integration circuit and a third operational amplifier OPA3 connected in parallel; the first RC integration circuit includes a first resistor R1 and a first capacitor C1, the first end of the first resistor R1 is connected to the first end of the first capacitor C1 through a first series switch (the control signal is the output signal Tr of the residual extraction circuit), and the control end of the first series switch is connected to the output end of the residual extraction circuit; the second RC integration circuit includes a second resistor R2 and a second capacitor C2, the first end of the second resistor R2 is connected to the first end of the second capacitor C2 through a second series switch (the control signal is the TA enable signal), and the control end of the second series switch is used to access the TA enable signal; the second ends of the first resistor R1 and the second resistor R2 are both connected to the positive power supply VDD, and the first capacitor C1 and the second end of the second capacitor C2 are both connected to the negative power supply VSS; the first end and the second end of the first capacitor C1 are also connected through a first return-to-zero switch, the first end and the second end of the second capacitor C2 are also connected through a second return-to-zero switch, the in-phase input terminal and the reverse output terminal, as well as the reverse input terminal and the in-phase output terminal of the third operational amplifier OPA3 are all connected through a third return-to-zero switch, and the control ends of the first return-to-zero switch, the second return-to-zero switch and the third return-to-zero switch are all used to access the return-to-zero signal Φaz; the first end of the first capacitor C1 is connected to the in-phase input terminal of the third operational amplifier OPA3, the first end of the second capacitor C2 is connected to the reverse input terminal of the third operational amplifier OPA3, and the in-phase output terminal of the third operational amplifier OPA3 is the output terminal of the pulse stretching circuit; the size ratio of the first capacitor and the second capacitor is 16 / 1.

[0047] The structure of the pulse stretching circuit in the present invention is as follows Figure 5 On the left are two RC integrator circuits, including the top resistor, two integrating capacitors connected to the current source, and four switches. The capacitor sizes are 16C and 1C. On the right is a static comparator, which uses the same Figure 2 The same structure as the comparator in .

[0048] The working process is as follows: Figure 6 、 Figure 7 and Figure 8 First, when Φaz is at a high level, the comparator and integrating capacitor are automatically reset to zero. When the output signal Tr (the pulse duration in the signal is Tr) of the residual extraction circuit arrives, the 1C capacitor on the right (the second capacitor) is charged via RC. After time Tr, it reaches voltage V1, which is then stored. After the coarse quantization cycle for all columns is complete, TA_en is set high, and the fine quantization counter is started, charging the 16C capacitor on the left. Since the two capacitors have a 16:1 ratio, the time constant τ is also 16:1. Therefore, it takes 16Tr for the 16C capacitor (the first capacitor) to reach the same voltage. The derivation process is as follows:

[0049]

[0050] These two capacitors are directly connected to the hysteresis comparator. When the output voltages Vn and Vp cross at voltage V1, the comparator flips, causing the fine-quantization counter latch signal φstretch (the output signal of the pulse stretching circuit) to flip. The comparator's own delay is Δt, which is eliminated as a fixed error in double-sampling operation.

[0051] Since the 16C capacitor is quite large (about 4pF), it is shared by the columns. The 16 columns of readout circuits share the 16C capacitor, so each column only needs to introduce a capacitor of about 0.25pF, which significantly saves area consumption.

[0052] In addition, the traditional constant current source integral type TA cannot achieve fast charging of the integral capacitor in a short time. When the integral capacitor is a certain value, a larger current source is needed for higher frequency application scenarios. In order to reduce the influence of the switch resistance voltage divider on the integral voltage, the switch size needs to be larger. However, when the current source is started, the charge injection and clock feedthrough from the switch will also affect the initial value of the integral voltage, which limits the use of TA in higher frequency circuits. For the RC type TA (the pulse stretching circuit used in the present invention), the switch resistance Rs itself can be used as part of the integral resistance R (the resistance of R1 and R2), so there is no need to use a larger switch size. In this design, an nmos switch is used with an integration range of 0-1.2V. Obviously, when the switch resistance works in this range, there will be a resistance change ΔRs, such as Figure 8 , considering its influence on the integral curve, the following deduction is made:

[0053] Assuming that the final integral voltage V1 is a minimum value v1, then in the minimum voltage interval (0, v1), it can be approximately considered that Rs increases by ΔRs1. According to the above formula, 1C capacitor and 16C capacitor use Δt1 and 16*Δt1 respectively to reach v1. Similarly, in the minimum interval (v1, v2), the two use Δt2 and 16*Δt2 to integrate from voltage v1 to voltage v2. Therefore, in any sub-interval (v1) from 0 to V1, i , v i+1), the two-point integration time is Δti and 16*Δti respectively, then for any final integral value V1, the integration time of the 16C capacitor is 16 times that of the 1C integration capacitor. In other words, although the change in switch resistance ΔRs will cause the charging curve to be a pseudo-RC curve, since the relative resistance of the two branches has not changed, the relative charging time of the two branches will only be related to the charging capacitance, which is obviously what the present invention expects. Therefore, when designing the switch size, it is only necessary to use two switches of the same size, and it is only necessary to make the parasitic capacitance of the switch much smaller than the charging capacitance C. The channel length is the minimum process size, and the channel width is 3 to 5 times the minimum process size.

[0054] The carry output terminal (output signal Co) and the sign output terminal (output signal Sign) of the fine quantization counter are both connected to the input terminal of the error correction circuit; the output terminal (output signal pulse) of the error correction circuit is connected to the input terminal of the coarse quantization counter. The error correction circuit is used to generate an error correction signal based on the carry output signal Co and the sign output signal Sign of the fine quantization counter and the output signal Tr of the residual extraction circuit.

[0055] Reference Figure 10 and Figure 11 In this embodiment, the fine quantization counter includes a second AND gate and six groups of flip-flop components connected in series, and the coarse quantization counter includes a latch, a first two-to-one MUX, and seven groups of flip-flop components connected in series.

[0056] Each group of trigger components includes a second D trigger and a second two-to-one MUX. The Q and QB ends of the second D trigger are connected to the D end through the second two-to-one MUX (the selection signal is LOCK); the Q and QB ends of the previous second D trigger are also connected to the CK end of the next second D trigger through a third two-to-one MUX (the selection signal is UDLSB in the fine quantization counter and UDMSB in the coarse quantization counter).

[0057] The output end of the pulse stretching circuit is connected to the CK end of the first second D flip-flop in the fine quantization counter through a second AND gate. The other input end of the second AND gate is used to receive the clock signal CLK. In the fine quantization counter, the Q end of each second D flip-flop serves as four count output ends, a carry output end, and a sign output end (used to output signals CNT0, CNT1, CNT2, CNT3, Co, and Sign, respectively).

[0058] In the coarse quantization counter, the G terminal of the latch is connected to the output terminal of the first AND gate, the D terminal of the latch is used to access the clock signal CLK, the Q terminal of the latch (for outputting the signal DDR) and the output terminal of the error correction circuit are connected to the CK terminal of the first second D flip-flop through the first two-to-one MUX (the selection signal is Calib), and the Q terminals of each second D flip-flop are respectively seven counting output terminals (for outputting signals CNT4, CNT5, CNT6, CNT7, CNT8, CNT9, and CNT10, respectively).

[0059] In summary, if Figure 10 The fine-quantization counter consists of six D-type flip-flops connected asynchronously in series. Two binary multiplexers are connected between each D-type flip-flop. The outputs are connected to the clock input of the next D-type flip-flop and the D terminal of the current D-type flip-flop, respectively. These are used to select the counting direction (increment or subtraction, controlled by the UD signal) and to lock the current data (locking is required before switching the counting direction; otherwise, the previous count value will change after the flip-flop, controlled by the LOCK signal). The count value is determined by the number of rising clock edges at the clock input of the first D-type flip-flop. The left AND input of the fine-quantization counter is connected to CLK and φstretch. When φstretch is high, it selects the number of rising clock edges of the input clock. Ideally, during the fine-quantization stage, the counter count value will only be 00001111. However, in practice, the static comparator has a hysteresis after the voltage crossing point. In addition, due to pulse stretching, process variations and comparator delays, Tr cannot be stretched exactly 16 times. It could also be 16.5 or 17 times. If only a four-bit counter is used, overflow may occur. For example, after counting 1111, the counter will return to 0000, which is obviously undesirable in this invention. Therefore, an overflow bit is introduced, and the last D flip-flop serves as a sign bit (Sign) because the count value may be less than 0 during the double sampling process. For example, the first upward count is from 000000 → 000010, and the second downward count is from 000010 → 111110 (+2 → +10 → -31 → -30).

[0060] like Figure 11 As shown in FIG, the coarse quantization counter is composed of 7 D flip-flops connected asynchronously in series. A latch is connected to the front end. One of the input terminals is the counter clock. The output signal φcomp from the comparator is used as the latch control signal of the front latch to control the number of rising edges of the input clock, thereby controlling the number of flips of the D flip-flops connected in series at the rear. In addition, the present invention adds an error correction unit in front of the coarse quantization counter, such as Figure 11This error correction unit uses a two-or-one multiplexer (MUX) to select between the clock signal at its input and the correction pulse signal (the output signal of the error correction circuit). When the control signal Calib = 0, the circuit operates in normal counting mode. When Calib = 1, the pulse is connected to the input of the first D-type flip-flop. By inputting a rising edge in the counter's add or subtract state, the coarse quantization counter is incremented or decremented by 1, thereby correcting the error value. After correction, Calib is reset to 0, preparing for the next quantization. Furthermore, to implement an increment by 2 operation, only two rising edge pulses are required.

[0061] In addition, the counting directions of the coarse quantization counter and the fine quantization counter are opposite, because the time residue extraction circuit extracts the time between the falling edge of Φcomp and the rising edge of the next clock (Tr, residue), while the time residue we actually need is the time between the falling edge of Φcomp and the rising edge of the previous clock (Treal_residue). There is the following relationship between the two:

[0062] Tresidue + Treal_residue = 1CLK

[0063] Therefore, the final coarse quantization count value and fine quantization count value cannot be directly spliced ​​together. The two need to be subtracted. This process is achieved by inverting the counting direction control bit (UD) of the fine quantization counter. In addition, this process will cause borrows and carries. The fine quantization counter can be corrected through Co and Sign to achieve carry and borrow. Figure 9 The diagram shows how to add the coarse quantization result and the fine quantization result. Here, CNT0, CNT1, CNT2, and CNT3 are used as the first four bits, and CNT4, CNT5, CNT6, CNT7, CNT8, CNT9, and CNT10 are used as the last seven bits. Co and Sign are added to CNT4 and CNT5, respectively, and DDR is added to CNT3. Figure 12 The specific situations of carry and borrow in the fine quantization process are given, where the falling edge of φcomp1 and φcomp2 and the first rising edge of the clock signal CLK after themselves are the fine quantization residuals of the quantization reset signal and the exposure signal respectively. Table 1 shows the situations of carry and borrow in the fine quantization counter.

[0064] Table 1 shows the carry and borrow of the fine quantization counter.

[0065] Sign Co Carry / Borrow 0 0 0 0 1 Carry 1MSB 1 0 Borrow 2MSB 1 1 Borrow 1MSB

[0066] In some embodiments, the error correction circuit includes: a signal generating circuit (for generating a signal Flag, referring to Figure 14 ) and pulse selection circuit (refer to Figure 15 ). The signal generating circuit includes a third AND gate, a fourth AND gate, a third D flip-flop and a fourth D flip-flop, the two input ends of the third AND gate are respectively connected to the output end of the residue extraction circuit (access signal Tr) and the clock signal CLK, the output end of the third AND gate is connected to the CK end of the third D flip-flop, the D end and QB end of the third D flip-flop are both connected to the CK end of the fourth D flip-flop, the two input ends of the fourth AND gate are respectively connected to the Q end of the fourth D flip-flop and the QB end of the latch (access signal DDRB), the output end of the fourth AND gate is the output end of the signal generating circuit, and the D end of the fourth D flip-flop is connected to the 1.2V positive power supply VCC12; the pulse selecting circuit includes a fifth AND gate, a sixth AND gate, The seventh AND gate and the XOR gate, the two input ends of the XOR gate are respectively connected to the carry output and the sign output of the fine quantization counter (respectively connected to the signals Co and Sign), the two input ends of the fifth AND gate are respectively connected to the output of the signal generation circuit and the first pulse signal pulse1, the two input ends of the sixth AND gate are respectively connected to the output of the XOR gate and the second pulse signal pulse2, the two input ends of the seventh AND gate are respectively connected to the sign output of the fine quantization counter and the third pulse signal pulse3, the output ends of the fifth, sixth and seventh AND gates together constitute the output end of the error correction circuit, and the pulse selection circuit will select one of the three pulse signals for output. Among them, the three pulse signals need to be input during the Calib=1 period, and the first pulse signal pulse1 needs to be input during the sub _ En is input before the rising edge, the second pulse signal pulse2 and the third pulse signal pulse3 are input before the rising edge of sub _ en=1 input. They are column-shared signals and are uniformly input by external digital circuits.

[0067] Specifically, there is a flip error in the quantization process that needs to be corrected, such as Figure 13 When the falling edge of Φcomp is very close to the next clock rising edge, the residual error extraction circuit may recognize Φcomp as after the current clock rising edge and extract a time residual close to one clock cycle. However, the coarse quantization counter will recognize Φcomp as before the current clock rising edge. Therefore, it can be considered that the counter has rolled over once less, and a flag bit needs to be generated to perform an error correction with 1MSB added. Figure 13 、 Figure 4 The timing diagram of error generation and the flag bit judgment circuit (signal generation circuit) are given respectively.

[0068] When it happens Figure 13 When the flip error in Figure 14The time margin Tr and CLK will generate two high-level pulse signals after passing through an AND gate. A D-type flip-flop connected as a counter will record the number of rising edges. After flipping twice, the output of the second flip-flop will be set to high. If and only if the two input terminals of the last AND gate are high at the same time after an erroneous flip, the Flag will be set to 1.

[0069] After obtaining the flag, error correction will be performed after quantization. Since digital double sampling is required, flip errors may occur in both quantization processes, so correction needs to be performed immediately after each quantization. After the double sampling process is completed, carry and borrow correction is performed uniformly. The two error correction processes are performed by inputting a high-level pulse at the MSB input. If two MSBs need to be corrected, two pulses need to be input. Addition and subtraction are controlled by the sign signal Sign. The structure of the entire correction circuit is as follows Figure 15 、 Figure 16 By selecting the flag bit and inputting the MSB counter input of pulse1, pulse2, and pulse3 respectively, the quantization result can be corrected. Figure 15 , the signal UDMSB is generated according to the signals Sign, suben and UD through the NAND gate and the AND gate.

[0070] In summary, the present invention provides a residual pulse stretching interpolation quantization column-level ADC. In one embodiment, the signal changes during its operation are as follows: Figure 17 As shown in the figure, after auto-zeroing (φaz), coarse quantization begins. The coarse quantization counter starts, and the ramp generator voltage begins to decrease. The ramp signal is compared with the pixel signal in the comparator, generating a comparator flip signal Φcomp, which stops the coarse quantization counter. After the coarse quantization process, the residual extraction circuit (Tr) extracts the time margin between the comparator flip signal Φcomp and the next clock rising edge. This time margin is converted into a corresponding voltage and stored. After coarse quantization of all columns is completed, the TA stretches the time margin (Tresidue) and then performs quantization using the clock. The quantized code value becomes the value of the fine quantization counter. After fine quantization, the digital correction circuit (EC) corrects the final result using the flag bits generated during the counting process to obtain the quantized result.

[0071] It can be seen from the above embodiments that the residual pulse stretching interpolation quantization column-level ADC provided by the present invention has the following technical effects:

[0072] In the case of 7-bit coarse quantization and 4-bit fine quantization, the present invention can 11 The quantization cycle is shortened to 2 7 +2 4quantization cycles (fine quantization has one redundant correction bit), a 93% reduction. Furthermore, due to its pulse stretching properties, this circuit improves its tolerance to high-speed quantization. Furthermore, the two-step ADC design ensures that the fine quantization counter only requires 16 clock cycles, reducing power consumption and addressing the current issues of slow quantization speed and low time accuracy of SSADCs.

[0073] The present invention further provides a CMOS image sensor, comprising the residual pulse stretching interpolation quantization type column-level ADC provided by the present invention.

[0074] It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0075] Obviously, the accompanying drawings are merely examples or embodiments of the present application. A person skilled in the art can also apply the present application to other similar situations based on these drawings without inventive effort. Furthermore, it is understandable that, although the work involved in this development process may be complex and lengthy, certain design, manufacturing, or production changes based on the technical content disclosed in this application are merely routine technical means for a person skilled in the art and should not be considered to constitute a deficiency in the disclosure of the present application.

Claims

1. A residual pulse stretching interpolation quantization type column-level ADC, characterized in that: include: Comparator, residual extraction circuit, pulse stretching circuit, coarse quantization counter, fine quantization counter and error correction circuit; The comparator is used to compare the ramp signal and the pixel signal, and the output end of the comparator is connected to the input end of the residual extraction circuit and the input end of the coarse quantization counter through a first AND gate; The residual error extraction circuit is used to extract the time difference between the output falling edge of the first AND gate and the first clock rising edge after the first AND gate, and the output end of the residual error extraction circuit is connected to the input end of the pulse stretching circuit and the input end of the error correction circuit; The pulse stretching circuit is used to stretch the output of the residual extraction circuit, and the output end of the pulse stretching circuit is connected to the input end of the fine quantization counter; The carry output terminal and the sign output terminal of the fine quantization counter are both connected to the input terminal of the error correction circuit; The output end of the error correction circuit is connected to the input end of the coarse quantization counter. The error correction circuit is used to generate an error correction signal according to the carry output and sign output of the fine quantization counter and the output of the residual extraction circuit.

2. The residual pulse stretching interpolation quantization column-level ADC according to claim 1, characterized in that: The comparator is a continuous time comparator, and the continuous time comparator includes a first operational amplifier and a second operational amplifier connected in cascade; The non-inverting input terminal and the inverting input terminal of the first operational amplifier are respectively used to receive the ramp signal and the pixel signal, and the non-inverting output terminal of the second operational amplifier is the output terminal of the continuous-time comparator; The non-inverting input terminal and the inverting output terminal, as well as the inverting input terminal and the non-inverting output terminal of the first operational amplifier are connected via a first control switch, and the non-inverting input terminal and the inverting output terminal, as well as the inverting input terminal and the non-inverting output terminal of the second operational amplifier are connected via a second control switch.

3. The residual pulse stretching interpolation quantization column-level ADC according to claim 2, characterized in that: The current sources of the first operational amplifier and the second operational amplifier both adopt a cascode structure.

4. The residual pulse stretching interpolation quantization column-level ADC according to claim 1, characterized in that: The residual error extraction circuit includes a first D flip-flop and a NOR gate; The D end of the first D flip-flop is connected to the output end of the first AND gate, the CK end of the first D flip-flop is used to access the clock signal, the QB end of the first D flip-flop is connected to the first input end of the NOR gate, the second input end of the NOR gate is connected to the output end of the first AND gate, and the output end of the NOR gate is the output end of the residual extraction circuit after passing through the buffer.

5. The residual pulse stretching interpolation quantization column-level ADC according to claim 1, characterized in that: The coarse quantization counter and the fine quantization counter have opposite counting directions.

6. The residual pulse stretching interpolation quantization column-level ADC according to claim 5, characterized in that: The coarse quantization counter is used to implement 7-bit counting, the fine quantization counter is used to implement 4-bit counting, and the pulse stretching circuit is used to implement 16-fold pulse stretching.

7. The residual pulse stretching interpolation quantization column-level ADC according to claim 6, characterized in that: The pulse stretching circuit includes a first RC integration circuit, a second RC integration circuit and a third operational amplifier connected in parallel; The first RC integration circuit includes a first resistor and a first capacitor, a first end of the first resistor is connected to a first end of the first capacitor via a first series switch, and a control end of the first series switch is connected to an output end of the residual error extraction circuit; The second RC integration circuit includes a second resistor and a second capacitor, a first end of the second resistor is connected to the first end of the second capacitor via a second series switch, and a control end of the second series switch is used to receive a TA enable signal; The second ends of the first resistor and the second resistor are both connected to a positive power supply, and the second ends of the first capacitor and the second capacitor are both connected to a negative power supply; The first end and the second end of the first capacitor are further connected via a first return-to-zero switch, the first end and the second end of the second capacitor are further connected via a second return-to-zero switch, the non-inverting input terminal and the inverting output terminal, as well as the inverting input terminal and the non-inverting output terminal of the third operational amplifier are all connected via the third return-to-zero switch, and the control ends of the first return-to-zero switch, the second return-to-zero switch, and the third return-to-zero switch are all used to receive a return-to-zero signal; The first end of the first capacitor is connected to the non-inverting input terminal of the third operational amplifier, the first end of the second capacitor is connected to the inverting input terminal of the third operational amplifier, and the non-inverting output terminal of the third operational amplifier is the output terminal of the pulse stretching circuit; The size ratio of the first capacitor to the second capacitor is 16 / 1.

8. The residual pulse stretching interpolation quantization column-level ADC according to claim 6, characterized in that: The fine quantization counter includes a second AND gate and six groups of flip-flop components connected in series, and the coarse quantization counter includes a latch, a first two-to-one MUX and seven groups of flip-flop components connected in series; Each group of the trigger components includes a second D trigger and a second two-to-one MUX, and the Q terminal and QB terminal of the second D trigger are connected to the D terminal through the second two-to-one MUX; The Q end and the QB end of the upper second D flip-flop are further connected to the CK end of the lower second D flip-flop through a third two-to-one MUX; The output end of the pulse stretching circuit is connected to the CK end of the first second D flip-flop in the fine quantization counter through the second AND gate. In the fine quantization counter, the Q end of each second D flip-flop serves as four counting output ends, the carry output end, and the sign output end respectively. In the coarse quantization counter, the G end of the latch is connected to the output end of the first AND gate, the D end of the latch is used to access the clock signal, the Q end of the latch and the output end of the error correction circuit are connected to the CK end of the first second D flip-flop through the first two-to-one MUX, and the Q ends of each second D flip-flop are 7 counting output ends in sequence.

9. The residual pulse stretching interpolation quantization column-level ADC according to claim 8, characterized in that: The error correction circuit includes: a signal generation circuit and a pulse selection circuit; The signal generating circuit includes a third AND gate, a fourth AND gate, a third D flip-flop and a fourth D flip-flop, wherein the two input terminals of the third AND gate are respectively connected to the output terminal of the residue extraction circuit and the clock signal, the output terminal of the third AND gate is connected to the CK terminal of the third D flip-flop, the D terminal and the QB terminal of the third D flip-flop are both connected to the CK terminal of the fourth D flip-flop, the two input terminals of the fourth AND gate are respectively connected to the Q terminal of the fourth D flip-flop and the QB terminal of the latch, and the output terminal of the fourth AND gate is the output terminal of the signal generating circuit; The pulse selection circuit includes a fifth AND gate, a sixth AND gate, a seventh AND gate and an XOR gate. The two input ends of the XOR gate are respectively connected to the carry output end and the sign output end of the fine quantization counter. The two input ends of the fifth AND gate are respectively connected to the output end of the signal generating circuit and the first pulse signal pulse1. The two input ends of the sixth AND gate are respectively connected to the output end of the XOR gate and the second pulse signal pulse2. The two input ends of the seventh AND gate are respectively connected to the sign output end of the fine quantization counter and the third pulse signal pulse3. The output ends of the fifth AND gate, the sixth AND gate and the seventh AND gate together constitute the output end of the error correction circuit.

10. A CMOS image sensor, characterized in that: include: The residual pulse stretching interpolation quantization column-level ADC according to any one of claims 1 to 9.

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