Storage array, memory and electronic equipment

Abstract

The embodiment of the invention provides a storage array, a memory and electronic equipment. The storage array comprises a substrate, a plurality of word lines, a plurality of bit lines, a plurality of back grid lines and a plurality of storage units, wherein the word lines, the bit lines and the back grid lines are arranged on the substrate; each storage unit is in contact with one word line, one bit line and one back grid line; each memory unit comprises a double-gate transistor and a capacitor, the double-gate transistor comprises a first gate, a second gate, a first pole, a second pole and a channel, the material for forming the channel is an oxide semiconductor OS, and the double-gate transistor is a planar transistor; wherein in each storage unit, the first grid electrode is connected with the corresponding word line, the second grid electrode is connected with the corresponding back grid line, the first electrode is connected with the corresponding bit line, the second electrode is connected with one electrode of the capacitor, and the other electrode of the capacitor is grounded or connected with direct current bias. By implementing the embodiment of the invention, the deviation of the threshold voltage Vt of the prepared OS transistor can be reduced, and the storage performance is improved.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a storage array, a memory and an electronic device. Background Art

[0002] Volatile memory refers to memory in which the stored information disappears when the current or voltage is interrupted, such as common dynamic random access memory (DRAM) and static random access memory (SRAM). DRAM has the advantages of simple structure, low manufacturing cost and high capacity density. With the development of technology, the application of DRAM memory is becoming more and more extensive.

[0003] The current DRAM is mainly based on the storage structure of 1-transistor-1-capacitor (1T1C). As the process size of DRAM is gradually reduced and to avoid the row-hammer characteristics of the front-end transistor, the current DRAM often chooses transistors with oxide semiconductor (OS) as the channel material. The OS transistor can be based on the characteristics of row-hammer free, extremely low off-state current, and can achieve back-end integration. It is very suitable as a transistor in the current DRAM storage structure, so as to further reduce the process size of DRAM. However, for the preparation process of OS transistors, due to the influence of the preparation process temperature during the preparation process, the conductive properties of the channel material will change, so that the threshold voltage V of the OS transistor after preparation is completed. t Deviations also occur, thereby reducing the sensing margin of the sense amplifier circuit used to amplify the signal in the DRAM, resulting in a decrease in storage performance.

[0004] Therefore, how to reduce the threshold voltage V of the OS transistor after fabrication? t To reduce the deviation and improve the storage performance of memory chips is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The present invention provides a memory array, a memory and an electronic device to reduce the threshold voltage V of the prepared OS transistor. t deviation and improve the storage performance of the memory chip.

[0006] In the first aspect, an embodiment of the present application provides a storage array, comprising: a substrate, a plurality of word lines, a plurality of bit lines, a plurality of back gate lines arranged on the substrate, and a plurality of storage cells distributed in an array; each of the storage cells is in contact with one of the word lines, one of the bit lines, and one of the back gate lines; each of the storage cells comprises a dual-gate transistor and a capacitor, the dual-gate transistor comprises a first gate, a second gate, a first electrode, a second electrode, and a channel, the material forming the channel is an oxide semiconductor OS, and the dual-gate transistor is a planar transistor; wherein the first gate in each of the storage cells is connected to the corresponding word line, the second gate is connected to the corresponding back gate line, the first electrode is connected to the corresponding bit line, the second electrode is connected to one electrode of the capacitor, and the other electrode of the capacitor is grounded or connected to a DC bias.

[0007] The OS transistor of the 1T1C storage cell in the current storage array (i.e., the transistor whose channel material is an oxide semiconductor OS) is prone to change in the conductive properties of the channel of the OS transistor due to the high process temperature during the preparation process, resulting in a threshold voltage V corresponding to the prepared OS transistor. t In this regard, an embodiment of the present application provides a storage array, in which the OS transistor of the 1T1C storage unit is a dual-gate transistor, and the back gate (i.e., the second gate) of the dual-gate transistor can receive a voltage signal (e.g., a back gate driving voltage), and the threshold voltage V of the dual-gate transistor is adjusted by regulating the voltage applied to the back gate of the dual-gate transistor. t, so that the threshold voltage with deviation is restored to the preset threshold voltage, thereby improving the sensing margin (Sensing Margin) of the sensing amplifier SA in the peripheral circuit and improving the storage performance of the storage array. Specifically, each 1T1C storage unit (i.e., a storage unit including a dual-gate transistor and a capacitor) will contact one of the word lines, one of the bit lines and one of the back-gate lines, the first gate of the dual-gate transistor can be connected to the corresponding word line, the second gate can be connected to the corresponding back-gate line, the first electrode can be connected to the corresponding bit line, and the second electrode can be connected to an electrode of the capacitor. Among them, the first electrode can be a drain, and the corresponding second electrode can be a source; the first electrode can also be a source, and the corresponding second electrode can be a drain. The above capacitor includes two electrodes, one of which is connected to the second electrode of the dual-gate transistor, and the other electrode can be grounded or connected to a DC bias. During the storage process, the second gate can receive the back-gate drive voltage through the corresponding back-gate line to adjust the threshold voltage of the dual-gate transistor, and then the first gate can control the conduction or disconnection of the dual-gate transistor through the voltage signal received by the corresponding word line to realize data storage. This method of adjusting the threshold voltage of the OS transistor by applying a voltage to the second gate can ensure that the threshold voltage of the OS transistor does not deviate during storage, thereby ensuring the storage efficiency of the storage array during the storage process. In addition, since the dual-gate transistor is a planar transistor, it is smaller in size and easier to integrate than the trench transistor in some embodiments, and does not have a serious Row-hammer characteristic, it can reduce the probability of the device being misoperated, which is conducive to further improving the storage performance of the storage array.

[0008] In a possible implementation, the plurality of back gate lines correspond to the plurality of word lines one by one, and each of the back gate lines is arranged in parallel with each of the word lines, and each of the back gate lines is arranged vertically with each of the bit lines.

[0009] In an embodiment of the present application, a simple and efficient arrangement structure is provided, in which a plurality of back gate lines and a plurality of word lines in a storage array are arranged in parallel in a one-to-one correspondence, which can be better electrically connected to the dual-gate transistors in the storage cells to ensure the storage performance of the storage array.

[0010] In a possible implementation, in a direction perpendicular to the substrate, the multiple back gate lines and the multiple word lines are respectively located on the upper and lower sides of the channel; wherein a first gate oxide dielectric layer is arranged between each of the back gate lines and the channel, and a second gate oxide dielectric layer is arranged between each of the word lines and the channel.

[0011] In the embodiment of the present application, a plurality of back gate lines and a plurality of word lines can be respectively located on the upper and lower sides of the channel, for example: the back gate line is located above the channel and the word line is located below the channel; the back gate line is located below the channel and the corresponding word line is located above the channel. In addition, there is a first gate oxide dielectric layer between each back gate line and the channel, and a second gate oxide dielectric layer is provided between each word line and the channel, which can isolate the back gate line and the word line from the channel to prevent leakage, so as to ensure the storage performance of the storage array.

[0012] In a possible implementation, one end of each of the back gate lines is electrically connected via a back gate control line, the back gate control line is used to receive a back gate driving voltage, and the back gate control line is arranged in parallel with each of the bit lines.

[0013] In the embodiment of the present application, at the side of the memory array, for example, at one end of the plurality of back gate lines, all the back gate lines are connected by a back gate control line to receive a back gate drive voltage, so as to adjust the threshold voltage of the dual-gate transistor. Moreover, by connecting all the back gate lines at the side of the memory array, the manufacturing process can be simplified and the difficulty of manufacturing the memory array can be reduced.

[0014] In a possible implementation, in a direction perpendicular to the substrate, the plurality of bit lines are located above the channel, and each of the bit lines is connected to the channel via a bit line contact BLC.

[0015] In an embodiment of the present application, multiple bit lines are located above the channel, and also above multiple back gate lines and multiple word lines. The bit line contact portion of each bit line can electrically connect the bit line to the channel. The bit line contact portion can be regarded as the first electrode of the dual-gate transistor. The material forming the bit line contact portion can be the same as or different from the material of the bit line.

[0016] In a possible implementation, in a direction perpendicular to the substrate, the plurality of bit lines are located below the channel, and each of the bit lines is connected to the channel via a bit line contact BLC.

[0017] In the embodiment of the present application, a plurality of bit lines are located below the channel, and are also located below a plurality of back gate lines and a plurality of word lines. The bit line contact portion of each bit line can electrically connect the bit line to the channel. The bit line contact portion can be regarded as the first electrode of the dual-gate transistor. The material forming the bit line contact portion can be the same as or different from the material of the bit line. Moreover, when the bit line is located below the channel, the structure set between the channel and the capacitor can be made smaller, thereby making the volume of the memory array smaller and easier to integrate, thereby improving the storage density.

[0018] In a possible implementation manner, in a direction perpendicular to the substrate, the channel is connected upward to the capacitor through a storage node contact SNC.

[0019] In the embodiment of the present application, the channel is connected upward to the capacitor through a storage node contact SNC. The storage node contact SNC can be regarded as the second electrode of the dual-gate transistor. The material forming the storage node contact SNC can be the same as or different from the material of the bit line contact.

[0020] In a possible implementation manner, the material of the plurality of back gate lines includes one of tungsten W, molybdenum Mo, ruthenium Ru, copper Cu or aluminum Al.

[0021] In the embodiment of the present application, the material of the back gate line includes one of tungsten W, molybdenum Mo, ruthenium Ru, copper Cu or aluminum Al, so as to facilitate the electrical connection of the dual-gate transistor. In addition, the material of the back gate line can be the same as or different from the material of the second gate of the dual-gate transistor.

[0022] In a second aspect, an embodiment of the present application provides a memory, comprising a controller and a storage array as described in any one of the first aspect mentioned above, wherein the controller is connected to the storage array, and the controller is used to send read and write instructions to the storage array, and the read and write instructions are used to instruct the storage array to perform read and write operations.

[0023] In an embodiment of the present application, the memory includes a controller and a storage array connected to the controller, and the controller can be used to send read and write instructions to the storage array to instruct the storage array to perform read and write operations. Among them, the channel in the storage cell of the storage array is an oxide semiconductor. Based on the characteristics of row-hammer free, extremely low off-state current, and back-end integration, the process size of the memory can be further reduced and the storage performance of the memory can be improved. Moreover, since the transistors in the storage cells of the storage array are dual-gate transistors, they can be adjusted when the threshold voltage deviates to ensure the storage performance of the memory.

[0024] In a possible implementation, the controller includes a back gate driving circuit; the back gate driving circuit is used to output a back gate driving voltage to all back gate lines in the storage array through a back gate control line.

[0025] In an embodiment of the present application, the controller includes a back gate driving circuit, so that during the storage process, the back gate driving circuit outputs a back gate driving voltage to all back gate lines in the storage array through a back gate control line to adjust the threshold voltage of the dual-gate transistor. Furthermore, the storage unit can control the conduction or shutdown of the dual-gate transistor through the voltage signal received by the corresponding word line to realize data storage.

[0026] In a possible implementation, in a direction perpendicular to a substrate in the memory array, the back gate driving circuit is disposed below the memory array.

[0027] In an embodiment of the present application, the back gate driving circuit is arranged below the memory array, for example, it can be arranged between the sensor amplifier circuit and the memory array. This arrangement can realize the voltage adjustment of the second gate when the memory is working without increasing the memory process size, thereby greatly reducing the area overhead of the back gate driving circuit and further improving the storage density.

[0028] In a third aspect, an embodiment of the present application provides a chip, characterized in that it includes a control circuit and a storage array as described in any one of the first aspect mentioned above, the control circuit is connected to the storage array, the control circuit is used to send read and write instructions to the storage array, and the read and write instructions are used to instruct the storage array to perform read and write operations.

[0029] In a fourth aspect, an embodiment of the present application provides an electronic device, characterized in that the electronic device comprises: a circuit board and a memory as described in any one of the items involved in the first aspect above; the circuit board is electrically connected to the memory.

[0030] It should be understood that the chip provided in the third aspect and the electronic device provided in the fourth aspect of the present application are consistent with the technical solution of the first aspect of the present application. Their specific contents and beneficial effects can be referred to the storage array provided in the above-mentioned first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0032] Figure 1 It is a schematic diagram of the storage structure of a 1T1C storage unit provided in an embodiment of the present application.

[0033] Figure 2 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application.

[0034] Figure 3 It is a schematic diagram of the structure of a memory provided for an embodiment of the present application.

[0035] Figure 4 It is a circuit structure schematic diagram of a back gate driving circuit provided for an embodiment of the present application.

[0036] Figure 5A and Figure 5B It is a structural schematic diagram of a group of storage arrays provided in an embodiment of the present application.

[0037] Figure 6 It is a structural schematic diagram of a storage unit provided in an embodiment of the present application.

[0038] Figure 7 It is a schematic diagram of adjusting the back gate voltage provided in an embodiment of the present application.

[0039] Figure 8 It is a schematic diagram of the structure of another storage unit provided in an embodiment of the present application.

[0040] Figures 9 and 10 It is a schematic diagram of a method for preparing a storage array according to an embodiment of the present application.

[0041] Description of reference numerals:

[0042] 200 electronic device, 205 bus, 210 system on chip, 211 application processor, 212 image processing unit, 213 first random access memory, 220 second random access memory, 230 communication chip, 240 power management chip;

[0043] 300 memory, 400 storage unit, 310 storage array, 320 controller, 3201 sensor amplifier circuit, 3202 decoder, 3203 word line driving circuit, 3204 back gate driving circuit, 3205 timing controller;

[0044] P1 is one end of the switch tube, P2 is the other end of the switch tube; T is a double-gate transistor, G1 is the first gate, G2 is the second gate, K1 is the first electrode, K2 is the second electrode, and C is a capacitor;

[0045] WL, WL1, WL2 and WL3 word lines, BL, BL1, BL2 and BL3 bit lines, BGL, BGL1, BGL2 and BGL3 back gate lines;

[0046] 600 substrate, 601 channel, 602 back gate line, 603 word line, 604 first gate oxide dielectric layer, 605 second gate oxide dielectric layer, 606 dielectric material layer, 607 bit line, 608 bit line contact portion, 609 storage node contact portion. DETAILED DESCRIPTION

[0047] The embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0048] The terms "first" and "second" and the like in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

[0049] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0050] For ease of description, the embodiments of the present application may use spatial relationship words such as "under", "below", "below", "below", "above", "on", etc. to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship words are intended to include other directions of the device in use or operation, in addition to the directions depicted in the drawings. For example, if the device in the drawings is turned over, the direction of the element described as being "under" or "under" or "below" other elements or features will be changed to "above" the other elements or features. Thus, the exemplary words "under" and "below" can include both the upper and lower directions. The device may also have other orientations (rotated 90 degrees or in other directions), so the spatial relationship descriptors used here should be interpreted accordingly. In addition, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there may be one or more layers in between.

[0051] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0052] First, in order to facilitate understanding of the embodiments of the present application, the technical problems that need to be solved by the embodiments of the present application are analyzed in detail below.

[0053] Memories can be classified into volatile memory and non-volatile memory according to volatility. Among them, volatile memory refers to memory in which the stored information disappears when the current or voltage is interrupted, such as common dynamic random access memory (DRAM) and static random access memory (SRAM). Among them, DRAM has the advantages of simple structure, low manufacturing cost and high capacity density. With the development of technology, DRAM is increasingly widely used.

[0054] The storage cells in the current DRAM storage array are mainly based on the storage structure of 1-transistor-1-capacitor (1T1C), and due to the difference in channels, the storage structure is often divided into two types. In one storage structure, the transistor of the 1T1C storage cell is a recessed channel, and the channel material is silicon. This storage structure uses a buried word line to set the word line, wherein the gate of the transistor is connected to the word line, and the drain and source of the transistor are connected to the bottom electrode and bit line (BL) of the capacitor through a storage node contact (Storage Node Contact, SNC) and a bit line contact (Bit Line Contact, BLC), respectively. However, due to the need to limit the size of the memory, the peripheral circuit cannot be placed under the storage array formed by the storage structure, and the array efficiency of the memory cannot be further improved. In addition, the transistors in the storage structure are front-end transistors, and the front-end transistors have serious Row-hammer characteristics, which makes the device easily misoperated.

[0055] In this regard, another storage structure is provided in some embodiments, please refer to the attached Figure 1 , Figure 1It is a schematic diagram of the storage structure of a 1T1C storage unit provided in an embodiment of the present application. The transistor of the 1T1C storage unit in the storage structure is a back-end transistor, and its channel material is an oxide semiconductor (Oxide Semiconductor, OS), and the bit line BL and word line WL in the storage structure are respectively located above and below the OS channel. The gate of the transistor is connected to the above-mentioned word line, and the drain and source of the transistor are respectively connected to the bottom electrode and the bit line (Bit Line, BL) of the capacitor through a storage node contact (Storage Node Contact, SNC) and a bit line contact (Bit Line Contact, BLC), and the transistor is a back-end transistor, and there is no serious Row-hammer characteristic, which can reduce the probability of the device being misoperated. However, the storage array composed of the storage structure is prone to changes in the conductive properties of the oxide semiconductor channel of the prepared transistor due to the presence of a high process temperature (Thermal) during the process preparation, which in turn causes the threshold voltage V of the transistor to change. t The deviation occurs, which reduces the sensing margin (Sensing Margin) of the sensing amplifier circuit (Sensing Amplifier, SA) used to amplify the signal in the DRAM. That is, due to the threshold voltage V t Deviations may cause the voltage applied to the transistor gate to fail to reach the turn-on voltage of the transistor in time during the period when the SA circuit is in a working state under the control of the timing signal, causing the transistor to remain in an off state. The transistor is turned on only after the turn-on voltage is reached, causing the sensor amplifier circuit to receive or read fewer valid electrical signals under the original timing control, and thus fail to amplify the electrical signal well (such as amplifying it to 1 or 0), resulting in storage errors and reduced storage performance.

[0056] In this regard, the embodiments of the present application provide a storage array, a memory and an electronic device. In one storage array, the OS transistor (wherein the OS transistor is a transistor whose channel material is an oxide semiconductor) of a 1T1C storage cell is a dual-gate transistor, and the back gate of the dual-gate transistor can receive a back gate drive voltage when the storage array is working or detecting, so as to adjust the threshold voltage V of the prepared OS transistor. t , thereby increasing the sensing margin read by the sensing amplifier circuit. This method reduces the threshold voltage V of the OS transistor after fabrication by adjusting the voltage of the back gate in the dual-gate transistor. t The deviation method can improve the storage performance of the storage chip using the storage array, wherein the specific implementation method can also refer to the relevant description of the following embodiment, and the embodiments of the present application are not described in detail here.

[0057] Secondly, based on the technical problems raised above and to facilitate understanding of the embodiments of the present application, one of the electronic devices on which the embodiments of the present application are based is described below.

[0058] Please refer to the attached Figure 2 , Figure 2 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application.

[0059] like Figure 2 As shown, the electronic device 200 may be a terminal device that needs to store data, such as a mobile phone, a tablet personal computer, a laptop computer, a personal digital assistant (PDA), a camera, a personal computer, a notebook computer, a vehicle-mounted device, a wearable device, augmented reality (AR) glasses, an AR helmet, virtual reality (VR) glasses or a VR helmet, etc., and the specific form of the electronic device is not specifically limited in the embodiment of the present application.

[0060] The electronic device 200 may include a bus 205 and a system on chip (SoC) 210 connected to the bus 205. The SoC 210 may be used to process data, for example, to process application data, process image data, and cache temporary data.

[0061] In some embodiments, SoC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and a first random access memory (RAM) 213 for caching data.

[0062] The first RAM 213 may be a static random access memory (SRAM) or an embedded flash (eflash), etc. The AP 211, GPU 212 and the first RAM 213 may be integrated into one die, or may be separately arranged in a plurality of dies.

[0063] In addition, in some embodiments, the first RAM 213 may include a storage array, which includes: a substrate, a plurality of word lines, a plurality of bit lines, a plurality of back gate lines and a plurality of storage cells distributed in an array arranged on the substrate; each storage cell is in contact with a word line, a bit line and a back gate line; each storage cell includes a dual-gate transistor and a capacitor, the dual-gate transistor includes a first gate, a second gate, a first electrode, a second electrode and a channel, the material forming the channel is an oxide semiconductor OS, and the dual-gate transistor is a planar transistor; wherein the first gate in each storage cell is connected to the corresponding word line, the second gate is connected to the corresponding back gate line, the first electrode is connected to the corresponding bit line, the second electrode is connected to one electrode of the capacitor, and the other electrode of the capacitor is grounded or connected to a DC bias. The implementation of the embodiments of the present application can reduce the threshold voltage V of the OS transistor after preparation. t The deviation is improved to improve the storage performance of the storage array, wherein the specific implementation method of the storage array can also refer to the following related embodiments, and the embodiments of the present application are not described in detail here.

[0064] The electronic device 200 may further include a second RAM 220 connected to the SOC 210 via the bus 205. The second RAM 220 may be a dynamic random access memory. The second RAM 220 may be used to store volatile data, such as temporary data generated by the SOC 210. In addition, the second RAM 220 may also include the storage array involved in the first RAM 213.

[0065] In addition, the electronic device 200 may also include a communication chip 230 and a power management chip 240 connected to the SOC 210 via the bus 205. The communication chip 230 may be used for processing the protocol stack, or amplifying and filtering analog radio frequency signals, or performing the above functions simultaneously. The power management chip 240 may be used to power other chips.

[0066] The electronic device 200 may further include a printed circuit board (PCB), which is not shown in the figure. The PCB may encapsulate one or more of the above-mentioned packaging structures, such as the SOC 210 and the second RAM 220, etc. The packaging structure may be electrically connected to the circuit board.

[0067] In one embodiment, the SOC 210 and the second RAM 220 may be packaged in a packaging structure, for example, using 2.5D (dimension) or 3D packaging, etc., to obtain a faster data transmission rate between chips. The SOC 210 and the second RAM 220 may also be packaged in different packaging structures, which is not specifically limited in the present embodiment of the application.

[0068] In another implementation, the electronic device may further include other discrete devices, which is not specifically limited in the embodiments of the present application.

[0069] It should be noted that the above Figure 2 The structure of the electronic device is only an exemplary implementation in the embodiments of the present application. The electronic devices in the embodiments of the present application include but are not limited to the above electronic devices.

[0070] Please refer to the attached Figure 3 , Figure 3 It is a schematic diagram of the structure of a memory provided for an embodiment of the present application.

[0071] like Figure 3 As shown, the memory 300 may be as described above. Figure 2 The first RAM 213 shown may also be as described above. Figure 2 The second RAM 220 is shown. The embodiment of the present application does not limit the application scenario of the memory 300.

[0072] like Figure 3 As shown, the memory 300 includes a storage array 310 and a controller 320. The controller 320 may be electrically connected to the storage array 310, and the controller 320 is used to send read and write instructions to the storage array 310, and the read and write instructions are used to instruct the storage array to perform read and write operations.

[0073] In one embodiment, the memory array 310 includes a plurality of memory cells 400 arranged in an array, wherein each memory cell 400 can be used to store 1 bit or multiple bits of data, and each memory cell includes a dual-gate transistor and a capacitor, and the dual-gate transistor is a planar transistor. In the memory cell of the 1T1C structure, when the capacitor is full of positive charge, it is represented as 1; otherwise, it is 0. The memory array 310 may also include a plurality of word lines (WL), a plurality of bit lines (BL) and a plurality of back gate lines (BGL). Each of the memory cells is in contact with a word line WL, a bit line BL and a back gate line BGL. Different memory cells 400 may also be electrically connected through word lines WL, bit lines BL or back gate lines BGL.

[0074] One or more of the above-mentioned word lines WL and bit lines BL can receive the control level or control signal (equivalent to the read and write instruction) output by the controller 320, select the storage cell 400 to be read and written in the storage array, so as to change the charge on the capacitor in the storage cell 400, thereby realizing the read and write operation of the data. One or more of the above-mentioned back gate lines BGL can be used to adjust the threshold voltage of the transistor in the corresponding storage cell to be read and written by receiving the back gate drive voltage output by the controller 320, so as to ensure the success rate of the read and write operation. Among them, the specific implementation method of the storage array can also refer to the following related embodiments, and the embodiments of the present application are not repeated here. In addition, for convenience, the above-mentioned WL, BL and BGL can also be collectively referred to as signal lines in the embodiments of the present application.

[0075] The controller 320 can be used to output control levels or control signals to the above-mentioned multiple word lines WL and multiple bit lines BL to control the storage array to read and write data. It can also output back gate drive voltages to the above-mentioned multiple back gate lines BGL to adjust the threshold voltage of the transistor in the storage unit to ensure the success rate of the read and write operations.

[0076] In one embodiment, the controller 320 may be referred to as a peripheral control circuit and may be disposed around the storage array 310 (eg, Figure 3 The storage array 310 and the controller may be integrated into one chip or integrated into multiple chips.

[0077] like Figure 3 As shown in (2), the controller 320 may include: a sensor amplifier circuit 3201, a decoder 3202, a word line driving circuit 3203, a back gate driving circuit 3204, and a timing controller 3205, or one or more circuit structures.

[0078] The sensor amplifier circuit (SA) 3201 can be connected to the capacitor in the storage unit 400 and can be used to amplify the electrical signal in the capacitor. For example, a positive charge is amplified to "1" and a negative charge is amplified to "0" to correspond to the 1 and 0 stored in the storage unit. The sensor amplifier circuit can be arranged above and / or below the storage array 310.

[0079] The decoder 3202 can be used to decode the address of the storage unit 400. The decoder 3202 is used to decode according to the received address to determine the storage unit 400 that needs to be accessed.

[0080] The sub word line driver (SWD) 3203 can be used to control the level of the signal line according to the decoding result generated by the decoder 3202 , thereby achieving access to the designated storage unit 400 .

[0081] The back gate driver (BGD) 3204 can be used to output a back gate driving voltage to all back gate lines in the memory array through the signal line, for example, to correct the threshold voltage of the specified memory cell 400 according to the decoding result generated by the decoder 3202 .

[0082] The word line driving circuit 3203 and the back gate driving circuit 3204 may be integrated into one structure, for example, integrated into a driver, or may be integrated into multiple structures respectively, which is not specifically limited in the embodiment of the present application.

[0083] The timing controller 3205 can be used to control the word line driving circuit 3203 and the back gate driving circuit 3204 to drive the signal lines in the memory array 310 to realize the reading and writing of data.

[0084] The controller 320 may further include an input / output driver (not shown), which may be used to drive transmission signals, for example, to drive received data signals and to drive data signals to be sent, so that the data signals may be transmitted over long distances.

[0085] The controller 320 may also include a buffer (not shown) for caching the read data before reading and writing the data, for example, a FIFO (first-in first-out) may be used for caching. In addition, the timing controller 3205 may also be used to control the timing of the buffer.

[0086] It should be noted that the above Figure 3 The memory structure in is only an exemplary implementation in the embodiments of the present application. The memory structure in the embodiments of the present application includes but is not limited to the above memory structure.

[0087] In addition, as mentioned above Figure 3 As shown in (1), the back gate driving circuit 3204 can be placed below or above the memory array 310, such as between the sensor amplifier circuit 3201 and the memory array 310. Alternatively, the back gate driving circuit 3204 can be placed in the corners around the memory array 310, such as the switch corner (SWC) area shown in the figure.

[0088] In one embodiment, in a direction perpendicular to the substrate in the memory array 310, the back gate driving circuit 3204 can be arranged below the memory array 310. Further, it can also be arranged below the memory array 310 and above the sensor amplification circuit 3201, for example, the back gate driving circuit 3204 can be arranged between the sensor amplification circuit 3201 and the memory array 310. This arrangement can achieve voltage regulation of the second gate when the memory is working without increasing the process size of the memory, greatly reducing the area overhead of the back gate driving circuit, and further improving the storage density.

[0089] In another embodiment, please refer to the attached Figure 4 , Figure 4 Schematic diagram of the circuit structure of a back gate driving circuit provided in the embodiment of the present application. Figure 4 As shown, the back gate driving circuit 3204 may include a switch tube, and the switch tube includes a control terminal VBGEn, and the control terminal VBGEn may be connected to a timing controller 3205 or other control circuits to control the on or off of the switch tube. One end P1 of the switch tube may be connected to a back gate control line in the storage array 310 to control multiple back gate lines; the other end P2 of the switch tube may be connected to a power supply signal VBG, so that voltage adjustment may be performed during device testing or operation.

[0090] It should be noted that the switch tube can be an N-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) or a P-type MOS tube.

[0091] It should also be noted that one end P1 of the switch tube may be a source, and the other end P2 of the corresponding switch tube may be a drain. Alternatively, one end P1 of the switch tube may be a drain, and the other end P2 of the corresponding switch tube may be a source.

[0092] It should be understood that the above Figure 2-Figure 4 The storage array involved in the electronic device or memory provided in the embodiment shown is related to the following Figure 5A-Figure 8 The storage arrays involved in the related embodiments shown are consistent, and their specific contents and beneficial effects can be referred to as follows Figure 5A-Figure 8 The storage array involved in the related embodiments shown will not be described in detail here.

[0093] Based on the above Figure 2-Figure 4 The electronic device or memory provided in the illustrated embodiment, the embodiment of the present application exemplarily describes the storage array in the electronic device or memory.

[0094] Please refer to the attached Figure 5A and Figure 5B, Figure 5A and Figure 5B It is a structural schematic diagram of a group of storage arrays provided in an embodiment of the present application.

[0095] like Figure 5A As shown, the memory array 310 includes: a substrate (not shown) and a plurality of word lines WL, a plurality of bit lines BL, a plurality of back gate lines BGL and a plurality of memory cells 400 arranged on the substrate. Each memory cell 400 is in contact with a word line WL, a bit line BL and a back gate line BGL. The memory array 310 may be the memory array 310 mentioned in the above-mentioned related embodiments, and the memory cell 400 may also be the memory cell 400 mentioned in the above-mentioned related embodiments. For example, the plurality of word lines WL include: Figure 5A The word lines WL1, WL2 and WL3 shown in FIG. 1 and the plurality of bit lines BL include: Figure 5A The bit lines BL1, BL2, BL3, and the plurality of back gate lines BGL include: Figure 5A The back gate lines BGL1, BGL2 and BGL3 are shown.

[0096] In addition, the substrate is used to carry or support a plurality of word lines WL, a plurality of bit lines BL, a plurality of back gate lines BGL and a plurality of memory cells 400 distributed in an array stacked on the substrate, wherein the stacking order between the plurality of word lines WL, the plurality of bit lines BL, the plurality of back gate lines BGL and the plurality of memory cells 400 distributed in an array is not fixed and can be set accordingly. For example, the substrate can be a single-layer structure. In this case, the material constituting the substrate can include semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the material constituting the substrate can include non-conductive materials such as glass, plastic or sapphire, etc. For another example, the above-mentioned substrate can also be a multi-layer structure. Among them, the layer farthest from the stacked structure on the substrate can adopt the above-mentioned semiconductor material or non-conductive material, and the remaining film layers can be patterned as needed to form other circuit structures.

[0097] It should be noted that the above-mentioned patterning process may include a photolithography process, or include a photolithography process and an etching step, and may also include other processes such as printing and inkjet for forming a predetermined pattern. The corresponding patterning process can be selected according to the structure formed in the embodiment of the present application, and the embodiment of the present application does not specifically limit this. The above-mentioned photolithography process refers to a process for forming a pattern using a photoresist, a mask, an exposure machine, etc., including a process of film formation, exposure, and development.

[0098] like Figure 5BAs shown, each storage unit 400 includes a dual-gate transistor T and a capacitor C. The dual-gate transistor T is a planar transistor, including a first gate G1, a second gate G2, a first electrode K1, a second electrode K2 and a channel (not shown). The material forming the channel is an oxide semiconductor OS. Exemplarily, the oxide semiconductor material can be one of indium gallium zinc oxide IGZO, intergranular oxide IGO, and indium zinc oxide IZO. The embodiment of the present application specifically defines the type of oxide semiconductor material.

[0099] Among them, Figure 5B As shown, the first gate G1 in each storage unit 400 is connected to the corresponding word line WL, the second gate G2 is connected to the corresponding back gate line BGL, the first pole K1 is connected to the corresponding bit line BL, the second pole K2 is connected to one electrode of the capacitor C, and the other electrode of the capacitor C is grounded or connected to a DC bias. The magnitude of the DC bias can be the magnitude of all or part of the power supply voltage. During the storage process, the first gate G1 can control the conduction or disconnection of the dual-gate transistor T through the voltage signal received by the corresponding word line WL to realize the storage of data. At the same time, the second gate G2 can receive the back gate drive voltage through the corresponding back gate line BGL to adjust the threshold voltage of the dual-gate transistor to ensure that the dual-gate transistor T can be normally turned on after the first gate G1 applies a control signal or a control voltage, so as to improve the storage performance of the storage array 310. This method of adjusting the threshold voltage of the OS dual-gate transistor by applying a voltage to the second gate G2 can reduce the deviation between the threshold voltage corresponding to the dual-gate transistor T in the working state and the preset threshold voltage as much as possible, avoid the impact of the process preparation process on the performance of the devices in the storage array, and improve the storage performance of the storage array 310.

[0100] In addition, since the dual-gate transistor is a planar transistor, it is smaller in size and easier to integrate than the trench transistor in some embodiments, and does not have serious Row-hammer characteristics, it can reduce the probability of device misoperation, which is beneficial to further improve the storage performance of the storage array.

[0101] It should be noted that the first electrode K1 of the dual-gate transistor T in each storage unit 400 may be a source electrode, and the corresponding second electrode K2 may be a drain electrode. Alternatively, the first electrode K1 of the dual-gate transistor T in each storage unit 400 may be a drain electrode, and the corresponding second electrode K2 may be a source electrode. In addition, the dual-gate transistor T in each storage unit 400 may be an N-type MOS tube or a P-type MOS tube, and this is not specifically limited in the embodiments of the present application.

[0102] In other embodiments, the connection relationship between the first gate G1 and the second gate G2 of the dual-gate transistor T in each storage unit 400 can be interchangeable, for example: the first gate G1 is connected to the corresponding back gate line BGL, and the second gate G2 is connected to the corresponding word line WL, which is not specifically limited in the embodiments of the present application.

[0103] It should also be noted that the embodiment of the present application does not specifically limit the type of capacitor in each storage unit 400. For example, the capacitor may be a stacked capacitor.

[0104] In one implementation, the plurality of back gate lines correspond to the plurality of word lines one by one, and each of the back gate lines is arranged in parallel with each of the word lines, and each of the back gate lines is arranged vertically with each of the bit lines.

[0105] As mentioned above Figure 5A As shown, the embodiment of the present application provides a simple and efficient arrangement structure, in which multiple back gate lines BGL and multiple word lines WL in the storage array 310 are arranged in parallel in a one-to-one correspondence, which can be better electrically connected to the dual-gate transistor T in the storage cell 400 to ensure the storage performance of the storage array.

[0106] In one implementation, in a direction perpendicular to the substrate, the multiple back gate lines and the multiple word lines are respectively located on the upper and lower sides of the channel; wherein a first gate oxide dielectric layer is arranged between each of the back gate lines and the channel, and a second gate oxide dielectric layer is arranged between each of the word lines and the channel.

[0107] Please refer to the attached Figure 6 , Figure 6 is a schematic diagram of a storage unit provided in an embodiment of the present application. Figure 6 The X, Y, and Z coordinate systems are established in the figure, and the coordinate systems are also applicable to the relevant embodiments of the above or following figures. Figure 6 The plane where the substrate 600 is located may be an XY plane. Figure 6 Taking the substrate 600 as a rectangle as an example, the X-axis may be the length direction of the substrate 600, the Y-axis may be the width direction of the substrate 600, and the Z-axis may be a direction perpendicular to or approximately perpendicular to the substrate 600 within a manufacturing tolerance range.

[0108] like Figure 6 As shown, in the direction perpendicular to the substrate 600 (Z-axis direction), a plurality of back gate lines BGL and a plurality of word lines WL may be respectively located at the upper and lower sides of the channel 601, for example, the back gate line 602 is located above the channel 601, and the word line 603 is located below the channel 601. A first gate oxide dielectric layer 604 is provided between the back gate line 602 and the channel 601, and a second gate oxide dielectric layer 605 is provided between the word line 603 and the channel 601.

[0109] In addition, in some other embodiments, the back gate line 602 and the first gate oxide dielectric layer 604 may be located below the channel 601, and the corresponding word line 603 and the second gate oxide dielectric layer 605 may be located above the channel 601, which is not specifically limited in the embodiments of the present application.

[0110] Among them, the first gate oxide dielectric layer 604 and the second gate oxide dielectric layer 605 can also be called gate insulating film layers (Gate insulator, GI). The first gate oxide dielectric layer 604 can be used to insulate the back gate line 602 and the channel 601, and the second gate oxide dielectric layer 605 can be used to insulate the word line 603 and the channel 601, isolating the back gate line and the word line from the channel to prevent leakage, so as to ensure the storage performance of the storage array 310.

[0111] It should be noted that the materials of the first gate oxide dielectric layer 604 and the second gate oxide dielectric layer 605 may be the same or different, for example, the materials of the first gate oxide dielectric layer 604 and the second gate oxide dielectric layer 605 may both be one of silicon carbon nitride SiCN, hafnium oxide HfO2, etc. This embodiment of the application does not specifically limit this.

[0112] In addition, the thickness of the first gate oxide dielectric layer 604 and the second gate oxide dielectric layer 605 in the direction perpendicular to the substrate 600 is not specifically limited in the embodiment of the present application. For example, the thickness of the first gate oxide dielectric layer 604 and the second gate oxide dielectric layer 605 can be between 2-10 nm. The width of the first gate oxide dielectric layer 604 in the direction parallel to the substrate is consistent with the corresponding back gate line 602, which can be between 40-200 nm, and the embodiment of the present application does not specifically limit this; the width of the second gate oxide dielectric layer 605 in the direction parallel to the substrate 600 (such as the X-axis direction) is consistent with the corresponding word line 603, which can be between 40-200 nm, and the embodiment of the present application does not specifically limit this.

[0113] It should also be noted that, in order to better illustrate the structure of the storage unit 400, the channel 601 is a rectangular parallelepiped that is generally parallel to the surface of the substrate 600 in the diagram, but has an angle with both the X-axis direction and the Y-axis direction. For example, the channel 601 is located on the diagonal line of the substrate in the X-axis direction and the Y-axis direction. The embodiment of the present application does not make any specific limitation on this.

[0114] It should also be noted that, in order to better support and isolate the various structures inside the memory cell 400, the memory cell 400 further includes a dielectric material layer 606, which is used to fill the gaps between the various structures inside the memory cell 400 and to isolate the various semiconductor structures. The material of the dielectric material layer 606 can be an insulating material, such as silicon oxide.

[0115] In one implementation, one end of each of the back gate lines is electrically connected via a back gate control line, the back gate control line is used to receive a back gate driving voltage, and the back gate control line is arranged in parallel with each of the bit lines.

[0116] As mentioned above Figure 5A As shown, at the side of storage array 310, one end of each back gate line can be electrically connected by a back gate control line, and the back gate control line is used to receive a back gate drive voltage, and in a direction parallel to substrate (such as the Y-axis direction), the back gate control line is arranged in parallel with each bit line. All back gate lines are connected with a back gate control line at one end of multiple back gate lines, and the back gate drive voltage is received, so that the threshold voltage of the dual-gate transistor can be adjusted. And all back gate lines are connected at the side of storage array, so that the preparation process can be made simpler, and the preparation difficulty of storage array is reduced.

[0117] Please refer to the attached Figure 7 , Figure 7 Schematic diagram of adjusting back gate voltage provided by an embodiment of the present application. Figure 7 As shown, before the back gate control line receives the back gate drive voltage, that is, before the back gate drive voltage is applied to the back gate line, that is, when BG=0, the threshold voltage of the dual gate transistor T is V1, and after the back gate control line receives the back gate drive voltage, that is, after the back gate drive voltage is applied to the back gate line, that is, when BG=1, the threshold voltage of the dual gate transistor T is V2. It can be seen that after the back gate drive voltage is applied to the back gate line, the threshold voltage of the dual gate transistor T can be adjusted to reduce the deviation between the threshold voltage in the storage process and the preset threshold voltage.

[0118] It should be noted that the embodiment of the present application does not impose any specific restrictions on the material and size of the back gate control line. For example, the material of the back gate control line can be a material with good conductivity or transmission efficiency, or a material consistent with the back gate line. For another example, the width of the back gate control line can be less than or equal to the width of the back gate line.

[0119] In one implementation, in a direction perpendicular to the substrate, the plurality of bit lines are located above the channel, and each of the bit lines is connected to the channel via a bit line contact BLC.

[0120] A plurality of bit lines are located above the channel, and also above a plurality of back gate lines and a plurality of word lines, for example: Figure 6As shown, the bit line 607 is located above the channel 601, and is also located above the back gate line 602 and the word line 603. The bit line 607 is connected to the channel 601 through a bit line contact (Bit Line Contact, BLC) 608, and a portion of the bit line contact 608 or the contact portion between the bit line contact 608 and the channel can serve as the first electrode of the dual-gate transistor T (not shown). In addition, the material forming the bit line contact 608 can be the same as or different from the material of the bit line 607. The width of the bit line contact 608 in a direction parallel to the substrate 600 (such as the X-axis direction) can be 15-100nm, which is not specifically limited in the embodiment of the present application. The thickness of the bit line contact 608 in a direction perpendicular to the substrate 600 (Z-axis direction) is greater than the sum of the thickness of the word line 603 and the second gate oxide dielectric layer 605.

[0121] In one implementation, in a direction perpendicular to the substrate, the plurality of bit lines are located below the channel, and each of the bit lines is connected to the channel via a bit line contact BLC.

[0122] In the embodiments of this application, please refer to the attached Figure 8 , Figure 8 is a schematic diagram of the structure of another storage unit provided in an embodiment of the present application. Figure 8 As shown, the bit line 607 is located below the channel 601, and is also located below the back gate line 602 and the word line 603. The bit line contact (Bit Line Contact, BLC) 608 connected to the bit line 607 is connected to the channel 601 upwardly, and the bit line contact 608 can also be regarded as the first pole of the double-gate transistor. The material forming the bit line contact 608 can be the same as or different from the material of the bit line 607. The width of the bit line contact 608 in the direction parallel to the substrate 600 (such as the X-axis direction) can be 15-100nm, which is not specifically limited in the embodiment of the present application. The thickness of the bit line contact 608 in the direction perpendicular to the substrate 600 (Z-axis direction) is greater than the sum of the thickness of the back gate line 602 and the first gate oxide dielectric layer 604. Moreover, when the bit line is located below the channel, the structure set between the channel and the capacitor can be made smaller, thereby making the volume of the storage array smaller and easier to integrate.

[0123] In one implementation, in a direction perpendicular to the substrate, the channel is connected upward to the capacitor through a storage node contact SNC.

[0124] As mentioned above Figure 6 or Figure 8As shown, the channel 601 is connected upward to an electrode (e.g., the lower electrode) of the capacitor C through a storage node contact (Storage Node Contact, SNC) 609. A portion of the storage node contact 609 or a contact portion between the storage node contact 609 and the channel can serve as the second electrode (not shown) of the dual-gate transistor T. The material forming the storage node contact SNC can be the same as or different from the material of the electrode connected to the capacitor, and the embodiments of the present application do not make any specific limitation on this.

[0125] The width of the storage node contact portion 609 in a direction parallel to the substrate 600 (such as the X-axis direction) may be 15-100 nm, which is not specifically limited in the present embodiment. It should be noted that in a direction perpendicular to the substrate 600 (such as the Z-axis direction), Figure 8 The storage node contact SNC of the memory cell shown in FIG. Figure 7 The height of the storage node contact portion SNC of the memory cell is shorter, so that the volume of the memory array is smaller and easier to integrate.

[0126] In one implementation, the material of the plurality of back gate lines includes one of tungsten W, molybdenum Mo, ruthenium Ru, copper Cu or aluminum Al. Exemplarily, the material forming the back gate line can be one of tungsten W, molybdenum Mo, ruthenium Ru, copper Cu or aluminum Al, as described above. Figure 6 As shown, in the direction parallel to the substrate 600 (such as the X-axis direction), the width of each back gate line BGL can be consistent with the width of each word line WL, for example, can be between 40-200nm. In addition, the material of the back gate line and the material of the second gate of the dual-gate transistor can be the same or different.

[0127] In summary, in a memory array provided in an embodiment of the present application, the OS transistor of the 1T1C memory cell in the memory array is a dual-gate transistor. During the storage process, the back gate (i.e., the second gate) of the dual-gate transistor can receive a voltage signal (e.g., a back gate driving voltage). By regulating the voltage applied to the back gate of the dual-gate transistor, the threshold voltage V of the dual-gate transistor can be adjusted. t , so that the threshold voltage with deviation is restored to the preset threshold voltage, thereby improving the sensing margin of the sensing amplifier SA in the peripheral circuit. This method of adjusting the threshold voltage of the OS transistor by applying a voltage to the second gate can ensure that the threshold voltage of the OS transistor will not deviate during storage, thereby ensuring the storage efficiency of the storage array during the storage process.

[0128] Secondly, based on the above Figure 6The memory cell structure shown in the figure, the embodiment of the present application exemplarily provides a method for preparing a memory array, which can solve the problem of low storage efficiency caused by the deviation of the threshold voltage of the 1T1C memory cell of the OS channel.

[0129] Please refer to the attached Figures 9 and 10 , Figures 9 and 10 It is a schematic diagram of a method for preparing a storage array according to an embodiment of the present application.

[0130] Step 1: Fig. 9 As shown in (1), a back gate line layer and a first gate oxide dielectric layer are sequentially deposited on a substrate 600 by chemical vapor deposition (CVD).

[0131] Step 2: If Fig. 9 As shown in (2), a plurality of back gate lines 602 and a plurality of first gate oxide dielectric layers 604 are prepared. The back gate line layer and the first gate oxide dielectric layer are etched to form a plurality of back gate lines 602 and a plurality of first gate oxide dielectric layers 604; then a dielectric material layer 606 is deposited to fill the gaps between adjacent back gate lines 602 and the first gate oxide dielectric layers 604, and chemical mechanical polishing (CMP) is performed to smooth the gaps until the plurality of back gate lines 602 and the plurality of first gate oxide dielectric layers 604 are exposed.

[0132] Step 3: If Fig. 9 As shown in (3), channels corresponding to multiple memory cells are prepared. The semiconductor structure obtained in step 2 is subjected to atomic layer deposition (ALD) to deposit IGZO to form an oxide semiconductor film layer; the oxide semiconductor film layer is etched to form channels 601, and a dielectric material layer 606 is deposited at the intervals to fill the gaps.

[0133] Step 4: Fig.10 As shown in (1), a plurality of word lines 603 and a plurality of second gate oxide dielectric layers 605 are prepared. In the above step 3, the surface of the semiconductor structure is subjected to chemical vapor deposition, and etching is performed to form a plurality of word lines 603 and a plurality of second gate oxide dielectric layers 605. Then, a dielectric material layer 606 is deposited to fill the gaps between adjacent word lines 603 and the second gate oxide dielectric layers 605, and chemical mechanical polishing is performed to flatten the gaps. At this time, the plurality of word lines 603 and the plurality of second gate oxide dielectric layers 605 do not need to be exposed.

[0134] Step 5: Fig.10As shown in (2), a plurality of bit lines 607 and bit line contacts 608 are prepared. In the above step 4, a bit line contact BLC hole (which may be square) is etched on the surface of the semiconductor structure obtained, wherein the bottom of each bit line contact BLC hole exposes the corresponding channel 601, and a conductive material (e.g., tungsten W) is filled in each bit line contact BLC hole until it covers the surface of the semiconductor structure obtained in the above step 4 to form a bit line layer. The bit line layer is etched and a dielectric material layer 606 is deposited to form a plurality of bit lines 607 and bit line contacts 608.

[0135] Step 6: Fig.10 As shown in (3), a plurality of storage node contacts SNC are prepared. In the above step 5, the surface of the semiconductor structure is etched to obtain a plurality of storage node contact SNC holes (which may be square), the bottom of each storage node contact SNC hole exposes a corresponding channel 601, and a conductive material (e.g., tungsten W) is filled inside each storage node contact SNC hole.

[0136] Step 7: Based on the above step 6, the semiconductor structure is obtained to perform the manufacturing process steps of the capacitor, and finally the above Figure 6 The storage array structure shown.

[0137] It should be understood that the manufacturing method of the storage array or the electronic device provided in the embodiments of the present application is similar to the above Figure 2-Figure 8 The storage arrays involved in the related embodiments shown are consistent, and their specific contents and beneficial effects can be referred to above Figure 2-Figure 8 The storage array involved in the related embodiments shown will not be described in detail here.

[0138] Based on the above Figure 8 The memory cell structure shown in the figure, the embodiment of the present application below exemplarily provides another method for preparing a memory array, which can solve the problem of low storage efficiency caused by the deviation of the threshold voltage of the 1T1C memory cell in the OS channel.

[0139] Step 1: Prepare a plurality of bit lines 607 and corresponding bit line contacts 608 on a substrate 600. Deposit a bit line layer on the surface of the substrate 600, and etch the bit line layer to form a plurality of bit lines 607 and corresponding bit line contacts 608. Fill the gap with a dielectric material layer 606 and perform chemical mechanical polishing until the bit line contacts 608 are exposed.

[0140] Step 2: Prepare multiple back gate lines 602 and multiple first gate oxide dielectric layers 604. The surface of the semiconductor structure obtained in step 1 is etched to obtain multiple grooves, and the bottom of each groove does not expose the bit line 607. Chemical vapor deposition is sequentially performed inside each groove, and chemical mechanical polishing is performed to form multiple back gate lines 602 and multiple first gate oxide dielectric layers 604.

[0141] Step 3: Prepare channels corresponding to multiple memory cells. Perform atomic layer deposition (ALD) on the semiconductor structure obtained in step 2 to deposit IGZO to form an oxide semiconductor film layer; etch the oxide semiconductor film layer to form channels 601, and deposit a dielectric material layer 606 at the intervals to fill the gaps.

[0142] Step 4: Prepare multiple word lines 603 and multiple second gate oxide dielectric layers 605. Chemical vapor deposition is performed on the surface of the semiconductor structure obtained in the above step 3, and etching is performed to form multiple word lines 603 and multiple second gate oxide dielectric layers 605. Then, a dielectric material layer 606 is deposited to fill the gaps between adjacent word lines 603 and the second gate oxide dielectric layers 605, and chemical mechanical polishing is performed to flatten the gaps. At this time, it is not necessary to expose the multiple word lines 603 and the multiple second gate oxide dielectric layers 605.

[0143] Step 5: Prepare multiple storage node contacts SNC. The surface of the semiconductor structure obtained in step 4 is etched to obtain multiple storage node contact SNC holes (which may be square), the bottom of each storage node contact SNC hole exposes the corresponding channel 601, and a conductive material (such as tungsten W) is filled inside each storage node contact SNC hole.

[0144] Step 6: Based on the above step 5, the semiconductor structure is obtained to perform the manufacturing process steps of the capacitor, and finally the above Figure 8 The storage array structure shown.

[0145] It should be understood that the method for preparing the storage array provided in the embodiment of the present application can also refer to the above Figure 9-10 The method for preparing the storage array will not be described in detail here.

[0146] It should be noted that the above-mentioned method for preparing the storage array is only a simple exemplary method provided in the embodiment of the present application, and the embodiment of the present application does not make any specific limitation to this.

[0147] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0148] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0149] In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the above-mentioned units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0150] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0151] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0152] If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc., specifically a processor in a computer device) to perform all or part of the steps of the above-mentioned methods of each embodiment of the present application. Among them, the aforementioned storage medium may include: U disk, mobile hard disk, magnetic disk, optical disk, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and other media that can store program codes.

[0153] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A storage array, characterized in that: include: A substrate, a plurality of word lines, a plurality of bit lines, a plurality of back gate lines and a plurality of memory cells distributed in an array arranged on the substrate; each of the memory cells is in contact with one of the word lines, one of the bit lines and one of the back gate lines; Each of the storage cells includes a double-gate transistor and a capacitor, the double-gate transistor includes a first gate, a second gate, a first electrode, a second electrode and a channel, the material forming the channel is an oxide semiconductor OS, and the double-gate transistor is a planar transistor; Among them, the first gate in each of the storage cells is connected to the corresponding word line, the second gate is connected to the corresponding back gate line, the first electrode is connected to the corresponding bit line, the second electrode is connected to one electrode of the capacitor, and the other electrode of the capacitor is grounded or connected to a DC bias.

2. The storage array according to claim 1, characterized in that: The plurality of back gate lines correspond to the plurality of word lines one by one, and each of the back gate lines is arranged in parallel with each of the word lines, and each of the back gate lines is arranged vertically with each of the bit lines.

3. The storage array according to claim 2, characterized in that: In a direction perpendicular to the substrate, the plurality of back gate lines and the plurality of word lines are respectively located at upper and lower sides of the channel; Wherein, a first gate oxide dielectric layer is arranged between each of the back gate lines and the channel, and a second gate oxide dielectric layer is arranged between each of the word lines and the channel.

4. The storage array according to claim 2 or 3, characterized in that: One end of each of the back gate lines is electrically connected via a back gate control line, the back gate control line is used to receive a back gate driving voltage, and the back gate control line is arranged in parallel with each of the bit lines.

5. The storage array according to any one of claims 1 to 4, characterized in that: In a direction perpendicular to the substrate, the plurality of bit lines are located above the channel, and each of the bit lines is connected to the channel via a bit line contact BLC.

6. The storage array according to any one of claims 1 to 4, characterized in that: In a direction perpendicular to the substrate, the plurality of bit lines are located below the channel, and each of the bit lines is connected to the channel via a bit line contact BLC.

7. The storage array according to any one of claims 1 to 6, characterized in that: In a direction perpendicular to the substrate, the channel is connected upward to the capacitor through a storage node contact SNC.

8. The storage array according to any one of claims 1 to 7, characterized in that: The material of the plurality of back gate lines includes one of tungsten W, molybdenum Mo, ruthenium Ru, copper Cu or aluminum Al.

9. A memory, characterized in that: It comprises a controller and a storage array as described in any one of claims 1 to 8, wherein the controller is connected to the storage array, and the controller is used to send read and write instructions to the storage array, and the read and write instructions are used to instruct the storage array to perform read and write operations.

10. The memory according to claim 9, characterized in that: The controller comprises a back-gate driving circuit; the back-gate driving circuit is used to output a back-gate driving voltage to all back-gate lines in the storage array through a back-gate control line.

11. The memory according to claim 9, characterized in that: In a direction perpendicular to the substrate in the memory array, the back gate driving circuit is arranged below the memory array.

12. A chip, characterized in that: It comprises a control circuit and a storage array as described in any one of claims 1 to 8, wherein the control circuit is connected to the storage array, and the control circuit is used to send read and write instructions to the storage array, and the read and write instructions are used to instruct the storage array to perform read and write operations.

13. An electronic device, characterized in that: The electronic device comprises: a circuit board and a memory as described in any one of claims 9 to 11; the circuit board is electrically connected to the memory.

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