Semiconductor device and preparation method thereof, and storage system

CN119451097AActive Publication Date: 2025-02-14YANGTZE MEMORY TECH CO LTD
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Patent Information

Application Number
CN202310983724.1
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2023-08-04
Publication Date
2025-02-14
Estimated Expiration
2043-08-04

AI Technical Summary

Technical Problem

In three-dimensional integrated DRAM, how to increase the process window to improve the flexibility and reliability of the preparation process.

Method used

By designing gate line structures of different heights in the array region and gate partition region of the semiconductor device, in particular, the height of the second gate line structure is smaller and the height of the first gate line structure is larger, thereby optimizing the semiconductor body the lead-out process window.

Benefits of technology

This design not only increases the process window introduced by the semiconductor body, reduces the difficulty of the etching process, but also improves the yield and reliability of the product.

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Abstract

The invention discloses a semiconductor device and a preparation method thereof, and a storage system. The semiconductor device comprises an array region and a gate partition region adjacent to the array region in a first direction. The semiconductor device comprises semiconductor cylinders and a grid line structure, and the semiconductor cylinders are arranged in an array mode in the first direction and the second direction and extend in the third direction. The grid line structures extend in the third direction and are located between two adjacent rows of semiconductor cylinders in the second direction. The grid line structure comprises a first grid line structure located in the grid partition area and a second grid line structure located in the array area. Wherein the height of the first grid line structure in the third direction is greater than that of the second grid line structure in the third direction. Therefore, when one end of the semiconductor main body adjacent to the second grid line structure is led out as a source electrode, the led-out contact is not easy to contact with the second grid line structure, so that a process window led out of the semiconductor main body can be enlarged.
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Citation Information

Patent Citations

  • Semiconductor structure and manufacturing method thereof

    CN112652624A

  • Semiconductor device and preparation method thereof

    CN113990872A

  • Semiconductor Devices Including Guard Ring Structures

    US20130248997A1

  • Method of manufacturing a semiconductor device

    US20150111360A1

  • Methods of forming an array of gated devices

    US9209187B1