A semiconductor device and its fabrication method, and a storage system thereof.

Abstract

This application discloses a semiconductor device and its fabrication method, as well as a memory system. The semiconductor device includes an array region and a gate isolation region adjacent to the array region in a first direction. The semiconductor device includes semiconductor pillars and gate line structures. The semiconductor pillars are arranged in an array in a first direction and a second direction, extending along a third direction. The gate line structures extend along the third direction and are located between two adjacent rows of semiconductor pillars in the second direction. The gate line structures include a first gate line structure located in the gate isolation region and a second gate line structure located in the array region. The height of the first gate line structure in the third direction is greater than the height of the second gate line structure in the third direction. Therefore, when one end of the semiconductor body adjacent to the second gate line structure is led out as a source, the contact point is less likely to contact the second gate line structure, thereby increasing the process window for the semiconductor body.

Description

Technical Field

[0001] This application generally relates to the field of electronic devices, and more specifically, to a semiconductor device and its fabrication method and a storage system. Background Technology

[0002] Transistors in semiconductor structures are widely used in integrated circuits as switching devices or driving devices. For example, the storage cells of Dynamic Random Access Memory (DRAM) may include transistors and capacitor structures, with the transistors controlling the writing or reading of data from the capacitor structures.

[0003] However, in three-dimensional integrated DRAM, a transistor and a capacitor structure constitute a memory cell. In the fabrication process, how to increase the process window is an urgent problem to be solved.

[0004] Application content

[0005] The purpose of this application is to provide a semiconductor device and its fabrication method, as well as a memory system, which aims to reduce the height of the second gate line structure in the array region in order to increase the process window brought out from the semiconductor body.

[0006] On one hand, this application provides a semiconductor device, the semiconductor device including an array region and a gate isolation region adjacent to the array region in a first direction, the semiconductor device comprising:

[0007] Semiconductor pillars are arranged in an array in the first direction and the second direction and extend along a third direction, wherein the first direction, the second direction and the third direction intersect each other;

[0008] A gate line structure extends along the third direction and is located between two adjacent rows of semiconductor pillars in the second direction. The gate line structure includes a first gate line structure located in the gate isolation region and a second gate line structure located in the array region.

[0009] Wherein, the height of the first gate line structure in the third direction is greater than the height of the second gate line structure in the third direction.

[0010] In some embodiments, the first gate line structure includes:

[0011] A first insulating layer is disposed along the first direction;

[0012] A first gate surrounds the sidewall of the first insulating layer and is located between the first insulating layer and the semiconductor pillar;

[0013] A gate-blocking structure extends along the third direction and disconnects the first gate.

[0014] In some embodiments, the second gate line structure includes:

[0015] The second insulating layer is adjacent to the first insulating layer along the first direction;

[0016] The second gate surrounds the sidewall of the second insulating layer and is located between the second insulating layer and the semiconductor pillar;

[0017] Wherein, the height of the first gate in the third direction is greater than the height of the second gate in the third direction; the height of the first insulating layer in the third direction is greater than the height of the second insulating layer in the third direction.

[0018] In some embodiments, the gate isolation region includes a first gate isolation region and a second gate isolation region located on both sides of the array region along the first direction;

[0019] The gate isolation structure includes:

[0020] A first gate isolation structure located in the first gate isolation region;

[0021] The second gate isolation structure is located in the second gate isolation region;

[0022] The first gate isolation structure and the second gate isolation structure are located on both sides of the insulating layer along the second direction.

[0023] In some embodiments, the semiconductor device further includes:

[0024] A barrier-derived structure is located on the gate barrier structure;

[0025] The width of the isolation derivative structure along the second direction is greater than the width of the gate isolation structure along the second direction.

[0026] In some embodiments, the gate isolation structure includes an isolation gap.

[0027] In some embodiments, the portion of the isolation gap connected to the isolation derivative structure is filled with an isolation layer, the material of which is the same as that of the isolation derivative structure.

[0028] In some embodiments, the semiconductor device further includes:

[0029] A gate shielding structure extends along the third direction and is located between two adjacent rows of semiconductor pillars in the second direction, wherein the gate shielding structure and the gate line structure are alternately arranged along the second direction.

[0030] In some embodiments, the gate shielding structure includes:

[0031] Shielding metal;

[0032] A third insulating layer is located on the shielding metal;

[0033] A fourth insulating layer surrounds the shielding metal and the third insulating layer.

[0034] In some embodiments, the semiconductor pillar includes:

[0035] Virtual semiconductor pillars are arrayed in the gate isolation region along the first direction and the second direction;

[0036] The array of semiconductor pillars is arranged in the array region along the first direction and the second direction.

[0037] In some embodiments, the semiconductor device further includes:

[0038] A contact point is brought out and connected to one end of the array semiconductor pillar along the third direction.

[0039] On the other hand, this application provides a method for fabricating a semiconductor device, the semiconductor device including an array region and a gate isolation region adjacent to the array region in a first direction, the method for fabricating the semiconductor device including:

[0040] Semiconductor pillars are formed by arraying along the first direction and the second direction and extending along the third direction, wherein the first direction, the second direction and the third direction intersect each other;

[0041] A gate line structure extending along the third direction is formed, the gate line structure being located between two adjacent rows of semiconductor pillars in the second direction, the gate line structure including a first gate line structure located in the gate isolation region and a second gate line structure located in the array region;

[0042] Wherein, the height of the first gate line structure in the third direction is greater than the height of the second gate line structure in the third direction.

[0043] In some embodiments, the step of forming the gate line structure extending along the third direction includes:

[0044] A gate trench is formed that extends along the third direction and is located between two rows of semiconductor pillars adjacent to each other in the second direction;

[0045] An initial gate insulating layer, an initial gate layer, and an initial insulating layer are sequentially formed in the gate trench. The initial insulating layer includes a first initial insulating layer located in the gate isolation region and a second initial insulating layer located in the array region. The initial gate layer includes a first initial gate located in the gate isolation region and a second initial gate located in the array region.

[0046] A protective layer is formed on the first initial insulating layer;

[0047] The second initial insulating layer is etched for the first time, so that the height of the second initial insulating layer along the third direction is less than the height of the first initial insulating layer along the third direction.

[0048] The protective layer is removed, and the first initial insulating layer and the second initial insulating layer are etched a second time to form the first insulating layer and the second insulating layer, respectively. The height of the second insulating layer along the third direction is less than the height of the first insulating layer along the third direction.

[0049] The first initial gate layer and the second initial gate layer are etched to form a first gate and a second gate, respectively, and the height of the second gate along the third direction is less than the height of the first gate along the third direction.

[0050] Wherein, the first insulating layer and the first gate constitute the first gate line structure, the second insulating layer and the second gate constitute the second gate line structure, and the first gate line structure and the second gate line structure constitute the gate line structure.

[0051] In some embodiments, the method for fabricating the semiconductor device further includes:

[0052] A first filling insulating layer is formed in the gate trench, covering the first gate and the first insulating layer;

[0053] An opening is formed by etching the first filling insulating layer, and a gate isolation structure is formed by etching the first gate through the opening. The gate isolation structure extends along the third direction and disconnects the first gate.

[0054] A partition derivative structure is formed in the opening, the width of the partition derivative structure along the second direction being greater than the width of the gate partition structure along the second direction.

[0055] In some embodiments, the method for fabricating the semiconductor device further includes:

[0056] A gate shielding trench is formed that extends along the third direction and is located between two rows of semiconductor pillars adjacent to each other in the second direction, the gate shielding trench and the gate line structure being alternately arranged along the second direction;

[0057] A fourth insulating layer is formed in the gate shielding trench;

[0058] A shielding metal and a third insulating layer are sequentially formed on the surface of the fourth insulating layer to form a grid shielding structure, wherein the third insulating layer is located on the shielding metal.

[0059] In some embodiments, the step of etching the first filling insulating layer to form an opening, and then etching the first gate through the opening to form a gate barrier structure, includes:

[0060] The first filling insulating layer and the third insulating layer are etched to form openings to expose the top of the first gate adjacent to the shielding metal.

[0061] The first gate adjacent to the shielding metal is etched to form an isolation gap that extends through the first gate along the third direction.

[0062] The gate isolation structure includes the isolation gap.

[0063] In some embodiments, the method for fabricating the semiconductor device further includes:

[0064] A second filling insulating layer is formed in the gate trench, located on the second gate and the second insulating layer;

[0065] Lead-out contacts are formed at the top of the semiconductor pillar.

[0066] Furthermore, this application provides a storage system, comprising:

[0067] Semiconductor devices in any of the above embodiments;

[0068] A controller, coupled to the semiconductor device, is used to control the semiconductor device to store data.

[0069] This application provides a semiconductor device and its fabrication method, as well as a memory system. The semiconductor device includes an array region and a gate isolation region adjacent to the array region in a first direction. The semiconductor device includes semiconductor pillars and gate line structures. The semiconductor pillars are arranged in an array in a first direction and a second direction, extending along a third direction, with the first, second, and third directions intersecting each other. The gate line structures extend along the third direction and are located between two adjacent rows of semiconductor pillars in the second direction. The gate line structures include a first gate line structure located in the gate isolation region and a second gate line structure located in the array region. The height of the first gate line structure in the third direction is greater than the height of the second gate line structure in the third direction. In this application, the height of the second gate line structure in the array region is smaller, while one end of the semiconductor body in the array region needs to be led out as a source. Therefore, when the end of the semiconductor body adjacent to the second gate line structure is led out as a source, the led-out contact is less likely to contact the second gate line structure, thereby increasing the process window for the semiconductor body. Furthermore, the height of the first gate line structure in the gate isolation region is larger, so the isolation-derived structure is less likely to contact the adjacent gate shielding structure, thereby increasing the process window for the isolation-derived structure. Attached Figure Description

[0070] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0071] Figure 1 These are schematic diagrams of the structure of semiconductor devices provided in some embodiments of this application;

[0072] Figure 2 This is provided by some embodiments of this application. Figure 1 A schematic diagram of the cross-sectional structure of the middle gate line structure, semiconductor pillars and gate shielding structure along the XY plane;

[0073] Figure 3 This is provided by some embodiments of this application. Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor device along A-A1;

[0074] Figure 4 This is provided by some embodiments of this application. Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor device along B-B1;

[0075] Figure 5 This is a schematic flowchart of a method for fabricating a semiconductor device provided in some embodiments of this application;

[0076] Figures 6a-6m These are schematic diagrams illustrating the structure of semiconductor devices during fabrication according to some embodiments of this application;

[0077] Figure 7This is a schematic cross-sectional view of a semiconductor device along the XZ plane at the insulating layer when forming the first insulating layer and the second insulating layer, provided in some embodiments of this application.

[0078] Figure 8 This is a schematic diagram of the structure of a storage system provided in some embodiments of this application. Detailed Implementation

[0079] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0080] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of this application.

[0081] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0082] As used herein, the term "layer" refers to a portion of material including a third region. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper layer structure, or may have a range smaller than that of the lower or upper layer structure. Furthermore, a layer may be a region of a third, uniform or non-uniform continuous structure smaller than a third continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers (where contacts, interconnects, and one or more dielectric layers are formed).

[0083] This paper uses Cartesian coordinates to represent directions, where "X" represents the first direction, "Y" represents the second direction, and "Z" represents the third direction. The first, second, and third directions intersect each other, that is, X, Y, and Z intersect each other, for example, they can be perpendicular to each other or form a certain angle.

[0084] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0085] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in some embodiments of this application. The semiconductor device 100 can be a memory or a part of a memory. The semiconductor device 100 can be used as computer memory in a memory system or as a cache in a memory system.

[0086] In some embodiments, the semiconductor device 100 can be used in conjunction with a solid-state drive (SSD) to improve read and write speeds. Currently, high-end SSDs often incorporate dynamic random access memory (DRAM) to enhance performance and improve random read / write speeds. For example, during file writing, especially small file writing, the small file is processed by DRAM before being stored in flash memory, resulting in higher SSD storage efficiency and faster speeds.

[0087] Semiconductor device 100 includes an array region 101 and a gate-isolated region 102 adjacent to the array region 101 in a first direction (X). The semiconductor device in array region 101 may include actual storage cells, and the semiconductor device in gate-isolated region 102 may include an isolation structure. The specific structures in the semiconductor devices of array region 101 and gate-isolated region 102 will be described in detail below.

[0088] Semiconductor device 100 includes semiconductor pillars 10 and gate line structures 20. The semiconductor pillars 10 are arranged in a first direction (X) and a second direction (Y) and extend along a third direction (Z). The gate line structure 20 extends along the third direction (Z) and is located between two adjacent rows of semiconductor pillars 10 in the second direction (Y). Therefore, the gate line structure 20 also extends along the first direction (X). In other words, the semiconductor pillars originally extended along the second direction (Y), but the gate line structure 20 extends along the first direction (X) and interrupts the original semiconductor pillars. Therefore, both sides of the gate line structure 20 are connected to a row of semiconductor pillars 10.

[0089] The gate line structure 20 includes a first gate line structure 21 located in the gate isolation region 102 and a second gate line structure 22 located in the array region 101. The first gate line structure 21 and the second gate line structure 22 are simply gate line structures located in different regions. The first gate line structure 21 is a partial gate line structure located in the gate isolation region 102, and the second gate line structure 22 is a partial gate line structure located in the array region 101.

[0090] In some embodiments, the material of the semiconductor pillar 10 may include silicon or polysilicon. The semiconductor pillar 10 includes a dummy semiconductor pillar 10a and an array of semiconductor pillars 10b. The dummy semiconductor pillars 10a are arrayed along a first direction (X) and a second direction (Y) in the gate isolation region 102, and the array of semiconductor pillars 10b are arrayed along the first direction (X) and the second direction (Y) in the array region 101. One end of the array of semiconductor pillars 10b along the third direction (Z) is connected to the bit line via a drain contact DC, while the dummy semiconductor pillars 10a do not need to be connected to the bit line. The other end of the array of semiconductor pillars 10b along the third direction (Z) can serve as a source and is led out via a lead-out contact (i.e., a source lead-out contact). The structure of the lead-out contact will be described below. The semiconductor device 100 may also include a capacitor structure (not shown) connected to the lead-out contact to achieve connection between the capacitor structure and the array of semiconductor pillars 10b.

[0091] In some embodiments, one end of the gate line structure 20 located in the gate isolation region 102 can be led out through the gate contact GC to connect to the gate control signal.

[0092] In some embodiments, the semiconductor device 100 further includes a gate shielding structure 30, which extends along the third direction (Z) and is located between two adjacent rows of semiconductor pillars 10 in the second direction (Y). That is, the semiconductor pillars 10 are arranged in multiple rows along the second direction (Y), with a gate line structure 20 or a gate shielding structure 30 between adjacent rows of semiconductor pillars 10. Figure 1 As shown, the gate shielding structure 30 and the gate line structure 20 are arranged alternately along the second direction (Y), that is, one gate shielding structure 30 is located between two adjacent gate line structures 20, which is used to shield the signal interference between the gate line structures 20.

[0093] In some embodiments, one end of the gate shielding structure 30 located in the gate isolation region 102 can be led out through the shielding contact SC to connect the shielding signal.

[0094] Please combine Figure 2 , Figure 2 Some embodiments provided in this application Figure 1A schematic diagram of the cross-sectional structure of the gate line structure, semiconductor pillars, and gate shielding structure along the XY plane. Figure 2 The specific structure of a grid line structure 20 in different regions is shown.

[0095] In some embodiments, the semiconductor device 100 includes a gate isolation region 102 and an array region 101 disposed adjacent to each other along a first direction (X). The gate isolation region 102 includes a first gate isolation region 1021 and a second gate isolation region 1022 located on both sides of the array region 101 along the first direction (X).

[0096] In some embodiments, of two adjacent gate shielding structures 30, one gate shielding structure 30 is led out through a shielding contact SC at one end of the first gate isolation region 1021, and the other gate shielding structure 30 is led out through another shielding contact SC at one end of the second gate isolation region 1022. Figure 1 As shown, multiple gate shielding structures 30 are led out at intervals in a gate isolation region 102.

[0097] The gate line structure 20 may include an insulating layer 201, a gate 202, and a gate isolation structure 203. The insulating layer 201 extends along a first direction (X), and the gate 202 surrounds the sidewall of the insulating layer 201 and is located between the insulating layer 201 and the semiconductor pillar 10. The gate isolation structure 203 extends along a third direction (Z) and disconnects the gate 202. The gate isolation structure 203 includes a first gate isolation structure 2031 and a second gate isolation structure 2032. The first gate isolation structure 2031 is located in a first gate isolation region 1021, and the second gate isolation structure 2032 is located in a second gate isolation region 1022. That is, there can be two gate line isolation structures 203. The first gate isolation structure 2031 and the second gate isolation structure 2032 are located on opposite sides of the insulating layer 201 along the second direction (Y). Therefore, the first gate isolation structure 2031 and the second gate isolation structure 2032 isolate the gate 202 into two gate electrodes, one of which is connected to the second gate. Figure 2 The upper row of semiconductor pillars 10 is connected, and another gate electrode is connected to... Figure 2 The lower row of semiconductor cylinders 10 are connected.

[0098] The insulating layer 201 is made of materials including, but not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The gate 202 can be one or more conductive materials such as poly-Si (p-Si, polycrystalline silicon), TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver).

[0099] In some embodiments, the semiconductor device 100 further includes a gate insulating layer 40 located between the gate 202 and the semiconductor pillar 10. Specifically, the gate insulating layer 40 surrounds the sidewall of the gate 202, which is located between the gate insulating layer 40 and the insulating layer 201. The material of the gate insulating layer 40 includes, but is not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0100] In this configuration, the semiconductor pillar 10 serves as a channel, forming a transistor together with the gate 202 and the gate insulating layer 40. Specifically, on one side of the insulating layer 201 along the second direction (Y), a gate electrode, a semiconductor pillar 10 connected to the gate electrode, and the gate insulating layer 40 between them form a plurality of transistors T1. On the other side of the insulating layer 201 along the second direction (Y), another gate electrode, a semiconductor pillar 10 connected to the gate electrode, and the gate insulating layer 40 between them form a plurality of transistors T2. A voltage is applied through the gate 202 to control the conduction of the transistors. One end of the semiconductor pillar 10 (i.e., the source of the transistor) is connected to a capacitor structure through lead-out contacts. A transistor and a capacitor structure can constitute a dynamic random access memory (DRAM) cell.

[0101] To compare the height of the gate line structure 20 along the third direction (Z) in different regions (gate isolation region 102 and array region 101), the insulating layer 201 and gate 202 in different regions are divided. Specifically, the insulating layer 201 is divided into a first insulating layer 2011 located in the gate isolation region 102 and a second insulating layer 2012 located in the array region 101, and the gate 202 is divided into a first gate 2021 located in the gate isolation region 102 and a second gate 2022 located in the array region 101.

[0102] Please see Figure 3 and Figure 4 , Figure 3 This is provided by some embodiments of this application. Figure 1 A schematic diagram of the cross-sectional structure of a semiconductor device along A-A1. Figure 4 This is provided by some embodiments of this application. Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor device along B-B1. The area from A-A1 belongs to the gate isolation region 102, and the area from B-B1 belongs to the array region 101.

[0103] Figure 3 and Figure 4 Both diagrams illustrate a grid line structure 20 and a grid shielding structure 30. The height of the first grid line structure 21 in the third direction (Z) is greater than the height of the second grid line structure 22 in the third direction (Z).

[0104] Combination Figure 2 and Figure 3The first gate structure 21 may include a first insulating layer 2011, a first gate 2021, and a gate isolation structure 203. The first insulating layer 2011 is disposed along the first direction (X), and the first gate 2021 surrounds the sidewall of the first insulating layer 2011 and is located between the first insulating layer 2011 and the semiconductor pillar 10. The gate isolation structure 203 extends along the third direction (Z) and disconnects the first gate 2021.

[0105] In some embodiments, the gate isolation structure 203 includes an isolation gap.

[0106] In some embodiments, such as Figure 3 As shown, the semiconductor device 100 also includes a barrier derivative structure 50, which is located on the gate barrier structure 203. Specifically, the barrier derivative structure 50 also covers the semiconductor pillar 10, with the semiconductor pillar 10 under the barrier derivative structure 50 located between the first gate line structure 21 and the gate shield structure 30. To increase the process window, the barrier derivative structure 50 may also cover part of the gate shield structure 30.

[0107] The width W1 of the isolation derivative structure 50 along the second direction (Y) is greater than the width W2 of the gate isolation structure 203 along the second direction (Y). The isolation derivative structure 50 is a structure formed during the fabrication process to form the gate isolation structure 203. Therefore, the larger width of the isolation derivative structure 50 is to better form the gate isolation structure 203. For details, please refer to the semiconductor device fabrication method below.

[0108] In some embodiments, the portion of the isolation gap connected to the partition derivative structure 50 may be filled with an isolation layer (not shown), the material of which is the same as that of the partition derivative structure 50, for example, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0109] Combination Figure 2 and Figure 4 The second gate structure 22 may include a second insulating layer 2012 and a second gate 2022. The second insulating layer 2012 is adjacent to the first insulating layer 2011 along the first direction (X). The second gate 2022 surrounds the sidewall of the second insulating layer 2012 and is located between the second insulating layer 2012 and the semiconductor pillar 10.

[0110] In some embodiments, the height H1 of the first gate 2021 in the third direction (Z) is greater than the height H2 of the second gate 2022 in the third direction (Z). Furthermore, the height h1 of the first insulating layer 2011 in the third direction (Z) is greater than the height h2 of the second insulating layer 2012 in the third direction (Z).

[0111] Specifically, taking the semiconductor pillar 10 as a standard, the position of the first gate 2021 relative to the semiconductor pillar 10 is higher than the position of the second gate 2022 relative to the semiconductor pillar 10; the position of the first insulating layer 2011 relative to the semiconductor pillar 10 is higher than the position of the second insulating layer 2012 relative to the semiconductor pillar 10.

[0112] like Figure 3 and Figure 4 As shown, the gate shielding structure 30 may include a shielding metal 31, a third insulating layer 32, and a fourth insulating layer 33. The shielding metal 31 extends in a third direction (Z), the third insulating layer 32 is located on the shielding metal 31, and the fourth insulating layer 33 surrounds the shielding metal 31 and the third insulating layer 32. Specifically, the fourth insulating layer 33 surrounds the sidewalls of the third shielding metal 31 and the third insulating layer 32, as well as the bottom of the shielding metal 31. The shielding metal 31 includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), or other metallic materials.

[0113] In some embodiments, the lead-out contact 11 is located on the array semiconductor pillar 10b, connecting the array semiconductor pillar 10b to the capacitor structure (not shown) above it.

[0114] Typically, the first gate line structure 21 and the second gate line structure 22 are formed in the same process and have the same height. In this embodiment, the first gate line structure 21 and the second gate line structure 22 have different heights because the conditions in the gate isolation region 102 and the array region 101 are different. For example, a gate isolation structure 203 and an isolation derivative structure 50 can be formed in the gate isolation region 102. If the height of the first gate line structure 21 is too low, the gate isolation structure 203 in the first gate line structure 21 will also be correspondingly low, and the isolation derivative structure 50 on the gate isolation structure 203 will also be low. Therefore, the isolation derivative structure 50 is prone to contact with the shielding metal 31 below, causing defects. In the array region 101, lead-out contacts 11 can be formed on the array semiconductor pillar 10b. If the height of the second gate line structure 22 is too high, the lead-out contacts 11 can easily penetrate and touch the second gate 2022, causing defects. Based on this, the heights of the first gate line structure 21 and the second gate line structure 22 in the embodiments of this application are not the same, and the height of the first gate line structure 21 is greater than the height of the second gate line structure 22. This can reduce the poor contact between the isolation derivative structure 50 and the gate shielding structure 30 in the gate isolation region 102, and also reduce the poor contact between the lead-out contact 11 and the first gate line structure 21 in the array region 101. In this way, the process window of the isolation derivative structure 50 and the lead-out contact 11 can be increased, and the difficulty of the etching process can be reduced.

[0115] Please see Figure 5 , Figure 5 This is a schematic flowchart illustrating the fabrication method of a semiconductor device provided in some embodiments of this application. Please also refer to... Figures 6a-6m , Figures 6a-6m This is a schematic diagram of the semiconductor device provided in some embodiments of this application during the fabrication process. This embodiment uses the fabrication of the above-mentioned semiconductor device 100 as an example to illustrate the fabrication method of the semiconductor device 100; therefore, please refer to [the provided text]. Figure 1-4 .in, Figure 6a , Figure 6c , Figure 6e , Figure 6g , Figure 6i , Figure 6k and Figure 6m This is a schematic cross-sectional view of the semiconductor device 100 along the YZ direction at the gate isolation structure 203 in the gate isolation region 102. Figure 6b , Figure 6d , Figure 6f , Figure 6h , Figure 6j and Figure 6l This is a schematic cross-sectional view of the semiconductor device 100 along the YZ direction in the array region 101. The fabrication method of the semiconductor device 100 includes the following steps S1-S2.

[0116] Step S1: Form semiconductor pillars 10 arranged in an array along the first direction (X) and the second direction (Y) and extending along the third direction (Z), wherein the first direction (X), the second direction (Y) and the third direction (Z) intersect each other.

[0117] Step S2: Form a gate line structure 20 extending along the third direction (Z), the gate line structure 20 being located between two adjacent rows of semiconductor pillars 10 in the second direction (Y), the gate line structure 20 including a first gate line structure 21 located in the gate isolation region 102 and a second gate line structure 22 located in the array region 101; wherein, the height of the first gate line structure 21 in the third direction (Z) is greater than the height of the second gate line structure 22 in the third direction (Z).

[0118] In some embodiments, the method for fabricating the semiconductor device 100 further includes: forming a gate shielding structure 30 extending along the third direction (Z) and located between two adjacent rows of semiconductor pillars 10 in the second direction (Y). Specifically, a gate shielding trench 30T extending along the third direction (Z) and located between two adjacent rows of semiconductor pillars 10 in the second direction (Y) is first formed, and then a fourth insulating layer 33 is formed in the gate shielding trench 30T. Finally, a shielding metal 31 and a third insulating layer 32 located on the shielding metal 31 are sequentially formed on the surface of the fourth insulating layer 33 to form the gate shielding structure 30. The gate shielding trench and the gate line structure 20 are alternately arranged along the second direction (Y).

[0119] In some embodiments, step S2 may include the following steps.

[0120] 1) A gate trench 20T is formed that extends along the third direction (Z) and is located between two rows of semiconductor pillars 10 adjacent to each other in the second direction (Y).

[0121] In some embodiments, the gate trench 20T and the semiconductor pillar 10 in step S1 can be formed together. For example, see... Figure 1 and Figure 2First, a semiconductor body is provided, the material of which may include silicon or polysilicon. Then, the semiconductor body is etched to form multiple rows of first initial semiconductor pillars extending along a third direction (Z) and spaced apart along a first direction (X). The first initial semiconductor pillars extend along a second direction (Y). Next, the multiple rows of first initial semiconductor pillars are etched to form gate trenches 20T extending along the first direction (X), thereby dividing the multiple rows of first initial semiconductor pillars into multiple arrays of second initial semiconductor pillars. Alternatively, the multiple second initial semiconductor pillars can be etched to form gate shielding trenches 30T, which are arranged alternately with the gate trenches 20T along the second direction (Y), thereby dividing the multiple second initial semiconductor pillars into multiple arrays of semiconductor pillars 10, i.e., dividing one row of second initial semiconductor pillars into two rows of semiconductor pillars 10. In other words, there is one row of gate shielding trenches 30T between two adjacent rows of gate trenches 20T.

[0122] It should be noted that the gate shielding structure 30 can be formed during the process of forming the gate line structure 20, or it can be formed after the gate line structure 20 is formed. This application does not limit the fabrication node of the gate shielding structure 30.

[0123] It should be noted that, see Figure 6a and Figure 6b The depth of the gate trench 20T along the third direction (Z) is less than the depth of the semiconductor body along the third direction (Z). The semiconductor body between the gate trenches 20T becomes the semiconductor pillar 10, while the bottom of the gate trench 20T still retains the semiconductor body 10S.

[0124] 2) A gate insulating layer 40, an initial gate layer 202a, and an initial insulating layer 201a are sequentially formed in the gate trench 20T. The initial insulating layer 201a includes a first initial insulating layer 2011a located in the gate isolation region 102 and a second initial insulating layer 2012a located in the array region 101. The initial gate layer 202a includes a first initial gate 2021a located in the gate isolation region 102 and a second initial gate 2022a located in the array region 101.

[0125] like Figure 6a and Figure 6b As shown, before forming the gate insulating layer 40, the initial gate layer 202a, and the initial insulating layer 201a, an isolation structure 60 can be formed at the bottom of the gate trench 20T to isolate the subsequently formed gate line structure 20 from the underlying semiconductor body 10S. The gate insulating layer 40, the initial gate layer 202a, and the initial insulating layer 201a are located on the isolation structure 60 and are formed sequentially on the sidewalls of the gate trench 20T. In the deposition process, the gate insulating layer 40, the initial gate layer 202a, and the initial insulating layer 201a are also formed above the semiconductor pillar 10.

[0126] 3) A protective layer 70 is formed on the first initial insulating layer 2011a.

[0127] like Figure 6a As shown, the first protective layer 70 may include photoresist for protecting the underlying first initial insulating layer 2011a from etching during subsequent etching processes.

[0128] 4) The second initial insulating layer 2012a is etched for the first time so that the height of the second initial insulating layer 2012a along the third direction (Z) is less than the height of the first initial insulating layer 2011a along the third direction (Z).

[0129] See Figure 6c and Figure 6d First, the first initial insulating layer 2011a is protected, and the second initial insulating layer 2012a is etched for the first time to reduce the height of the second initial insulating layer 2012a along the third direction (Z).

[0130] 5) Remove the protective layer 70 and perform a second etching on the first initial insulating layer 2011a and the second initial insulating layer 2012a.

[0131] See Figure 6e and Figure 6f The protective layer 70 can be removed by an ashing process.

[0132] See Figure 6g and Figure 6h The second etching process involves etching the first initial insulating layer 2011a and the second initial insulating layer 2012a together to expose the first initial gate 2021a and the second initial gate 2022a. After the second etching process, the first initial insulating layer 2011a becomes the first insulating layer 2011, and the second initial insulating layer 2012a becomes the second insulating layer 2012. The first insulating layer 2011 and the second insulating layer 2012 constitute... Figure 2 The insulating layer 201 is shown. The height of the second insulating layer 2012 along the third direction (Z) is less than the height of the first insulating layer 2011 along the third direction (Z).

[0133] The second etching process can have the same etching depth for the first initial insulating layer 2011a and the second initial insulating layer 2012a. However, since the first initial insulating layer 2011a has an additional first etching process, the first insulating layer 2011 and the second insulating layer 2012 with different heights can be formed. The purpose is to allow the formation of the first gate 2021 and the second gate 2022 with different heights in the future.

[0134] 6) The first initial gate layer 202a and the second initial gate layer 202a are etched to form a first gate 2021 and a second gate 2022, respectively, and the height of the second gate 2022 along the third direction (Z) is less than the height of the first gate 2021 along the third direction (Z).

[0135] See Figure 6i and Figure 6j After the first initial gate layer 202a and the second initial gate layer 202a are exposed, an etching process makes the first initial gate layer 202a become the first gate 2021 and the second initial gate layer 202a become the second gate 2022. The first gate 2021 and the second gate 2022 constitute Figure 2 The gate 202 is shown. Furthermore, the top of the first gate 2021 is close to the top of the first insulating layer 2011, and the top of the second gate 2022 is close to the top of the second insulating layer 2012.

[0136] Specifically, the height of the first gate 2021 can be less than or equal to the height of the first insulating layer 2011, and the height of the second gate 2022 can be less than or equal to the height of the second insulating layer 2012. The height difference between the first gate 2021 and the first insulating layer 2011 can be equal to the height difference between the second gate 2022 and the second insulating layer 2012, and the height of the first insulating layer 2011 is greater than the height of the second insulating layer 2012. Therefore, the height of the first gate 2021 is greater than the height of the second gate 2022.

[0137] Please see Figure 7 , Figure 7 This is a schematic cross-sectional view of a semiconductor device along the XZ plane when forming a first insulating layer and a second insulating layer, as provided in some embodiments of this application. Figure 7 This is also a cross-sectional structural diagram of the semiconductor device 100 during its fabrication process, and is consistent with... Figure 6g and Figure 6h The corresponding states are the structures formed when the first insulating layer 2011 and the second insulating layer 2012 are formed. Figure 7 This is to show the height of the insulating layer 201 in different regions, that is, the height of the first insulating layer 2011 in the gate isolation region 102 is greater than the height of the second insulating layer 2012 in the array region 101.

[0138] In some embodiments, the height of the first insulating layer 2011 near the array region 101 gradually decreases until the height of the first insulating layer 2011 is equal to the height of the second insulating layer 2012 at the junction of the gate isolation region 102 and the array region 101.

[0139] The method for fabricating the semiconductor device 100 also includes the following steps.

[0140] 7) See Figure 6k A first filling insulating layer 81 is formed in the gate trench 20T, covering the first gate 2021 and the first insulating layer 2011. See also Figure 4 A second filling insulating layer 82 is formed in the gate trench 20T on the second gate 2022 and the second insulating layer 2012.

[0141] In some embodiments, such as Figure 4 As shown, the fabrication method of the semiconductor device 100 may further include forming a lead-out contact 11 at the top of the semiconductor pillar 10. The semiconductor pillar 10 includes a virtual semiconductor pillar 10a and an array of semiconductor pillars 10b, and the lead-out contact 11 is connected to the end of the array of semiconductor pillars 10b away from the isolation structure 60. Because the height of the second gate 2022 is relatively low, the lead-out contact 11 is not easily in contact with the second gate 2022 even if it is penetrated, which can increase the process window of the lead-out contact 11.

[0142] At this point, the relevant structures of the second gate line structure 22 have been formed. The gate isolation structure 203 still needs to be formed in the first gate line structure 21.

[0143] 8) The first filling insulating layer 81 is etched to form an opening, and the first gate 2021 is etched through the opening to form a gate isolation structure 203, the gate isolation structure 203 extending along the third direction (Z) and disconnecting the first gate 2021.

[0144] For details, see Figure 6l First, above the first gate 2021 (reference) Figure 2 Forming a 90° opening in the photoresist. See also... Figure 6m Then, the first filling insulating layer 81 and the third insulating layer 32 are etched to form an opening 501 to expose the top of the first gate 2021 adjacent to the shielding metal 31, so that the first gate 2021 at this location can be removed along the third direction (Z) in a subsequent step. Next, the first gate 2021 adjacent to the shielding metal 31 is etched to form an isolation gap penetrating the first gate 2021 along the third direction (Z). The gate isolation structure 203 includes the isolation gap. To facilitate the etching process of the first gate 2021, the width W1 of the opening 501 along the second direction (Y) is greater than the width W2 of the gate isolation structure 203 along the second direction (Y).

[0145] The first insulating layer 2011, the first gate 2021 and the gate isolation structure 203 constitute the first gate line structure 21, the second insulating layer 2012 and the second gate 2022 constitute the second gate line structure 22, and the first gate line structure 21 and the second gate line structure 22 constitute the gate line structure 20.

[0146] 9) See Figure 3 An isolation derivative structure 50 is formed in the opening 501, and the width W1 of the isolation derivative structure 50 along the second direction (Y) is greater than the width W2 of the gate isolation structure 203 along the second direction (Y).

[0147] In some embodiments, the isolation derivative structure 50 can be an insulating material, such as silicon oxide. Since the first gate 2021 is relatively high, the isolation derivative structure 50 is less likely to come into contact with the shielding metal 31, which can increase the process window of the isolation derivative structure 50, that is, increase the process window of the opening 501 and reduce the process difficulty of etching the opening 501.

[0148] The method for fabricating the semiconductor device 100 provided in this application protects the first initial insulating layer 2011a before the second etching process of the first initial insulating layer 2011a and the second initial insulating layer 2012a, and adds a first etching process for the second initial insulating layer 2012a. Therefore, the height of the second insulating layer 2012 is smaller than the height of the first insulating layer 2011, and consequently the height of the second gate 2022 is also smaller than the height of the first gate 2021. This ensures that the height of the second gate 2022 in the array region 101 is small, thus providing a large etching process window for the lead-out contacts 11 of the array semiconductor pillars 10 / 10b, while also ensuring that the height of the first gate 2021 in the gate isolation region 102 is large, providing a large etching process window for the isolation derivative structure 50. It also reduces the difficulty of the etching process and improves the product yield.

[0149] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of a storage system provided in some embodiments of this application. The storage system 600 includes a semiconductor device 601 and a controller 602. The semiconductor device 601 may include any of the semiconductor devices 100 described in the above embodiments, and the semiconductor device 601 may be a memory or part of a memory. The controller 602 is coupled to the semiconductor device 601 and is used to control the semiconductor device 601 to store data. The semiconductor device 601 can perform data storage operations based on the control of the controller 602.

[0150] The semiconductor device 601 includes: an array region and a gate isolation region adjacent to the array region in a first direction. The semiconductor device includes: semiconductor pillars arranged in an array in the first and second directions and extending along a third direction, wherein the first direction, the second direction, and the third direction intersect each other; and a gate line structure extending along the third direction and located between two adjacent rows of semiconductor pillars in the second direction. The gate line structure includes a first gate line structure located in the gate isolation region and a second gate line structure located in the array region. The height of the first gate line structure in the third direction is greater than the height of the second gate line structure in the third direction.

[0151] The above description of the embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application; those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes an array region and a gate isolation region adjacent to the array region in a first direction, the semiconductor device comprising: Semiconductor pillars are arranged in an array in the first direction and the second direction and extend along a third direction, wherein the first direction, the second direction and the third direction intersect each other; A gate line structure extends along the third direction and is located between two adjacent rows of semiconductor pillars in the second direction. The gate line structure includes a first gate line structure located in the gate isolation region and a second gate line structure located in the array region. Wherein, the height of the first gate line structure in the third direction is greater than the height of the second gate line structure in the third direction.

2. The semiconductor device according to claim 1, characterized in that, The first gate structure includes: A first insulating layer is disposed along the first direction; A first gate surrounds the sidewall of the first insulating layer and is located between the first insulating layer and the semiconductor pillar; A gate-blocking structure extends along the third direction and disconnects the first gate.

3. The semiconductor device according to claim 2, characterized in that, The second gate structure includes: The second insulating layer is adjacent to the first insulating layer along the first direction; The second gate surrounds the sidewall of the second insulating layer and is located between the second insulating layer and the semiconductor pillar; Wherein, the height of the first gate in the third direction is greater than the height of the second gate in the third direction; the height of the first insulating layer in the third direction is greater than the height of the second insulating layer in the third direction.

4. The semiconductor device according to claim 2, characterized in that, The gate isolation region includes a first gate isolation region and a second gate isolation region located on both sides of the array region along the first direction. The gate isolation structure includes: A first gate isolation structure located in the first gate isolation region; The second gate isolation structure is located in the second gate isolation region; The first gate isolation structure and the second gate isolation structure are located on both sides of the insulating layer along the second direction.

5. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes: A barrier-derived structure is located on the gate barrier structure; The width of the isolation derivative structure along the second direction is greater than the width of the gate isolation structure along the second direction.

6. The semiconductor device according to claim 5, characterized in that, The gate isolation structure includes an isolation gap.

7. The semiconductor device according to claim 6, characterized in that, The portion of the isolation gap connected to the isolation derivative structure is filled with an isolation layer, the material of which is the same as that of the isolation derivative structure.

8. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A gate shielding structure extends along the third direction and is located between two adjacent rows of semiconductor pillars in the second direction, wherein the gate shielding structure and the gate line structure are alternately arranged along the second direction.

9. The semiconductor device according to claim 8, characterized in that, The gate shielding structure includes: Shielding metal; A third insulating layer is located on the shielding metal; A fourth insulating layer surrounds the shielding metal and the third insulating layer.

10. The semiconductor device according to claim 1, characterized in that, Semiconductor pillars include: Virtual semiconductor pillars are arrayed in the gate isolation region along the first direction and the second direction; The array of semiconductor pillars is arranged in the array region along the first direction and the second direction.

11. The semiconductor device according to claim 10, characterized in that, The semiconductor device further includes: A contact point is brought out and connected to one end of the array semiconductor pillar along the third direction.

12. A method for fabricating a semiconductor device, characterized in that, The semiconductor device includes an array region and a gate isolation region adjacent to the array region in a first direction. The method for fabricating the semiconductor device includes: Semiconductor pillars are formed by arraying along the first direction and the second direction and extending along the third direction, wherein the first direction, the second direction and the third direction intersect each other; A gate line structure extending along the third direction is formed, the gate line structure being located between two adjacent rows of semiconductor pillars in the second direction, the gate line structure including a first gate line structure located in the gate isolation region and a second gate line structure located in the array region; Wherein, the height of the first gate line structure in the third direction is greater than the height of the second gate line structure in the third direction.

13. The method for fabricating a semiconductor device according to claim 12, characterized in that, The step of forming the gate line structure extending along the third direction includes: A gate trench is formed that extends along the third direction and is located between two rows of semiconductor pillars adjacent to each other in the second direction; An initial gate insulating layer, an initial gate layer, and an initial insulating layer are sequentially formed in the gate trench. The initial insulating layer includes a first initial insulating layer located in the gate isolation region and a second initial insulating layer located in the array region. The initial gate layer includes a first initial gate located in the gate isolation region and a second initial gate located in the array region. A protective layer is formed on the first initial insulating layer; The second initial insulating layer is etched for the first time, such that the height of the second initial insulating layer along the third direction is less than the height of the first initial insulating layer along the third direction. The protective layer is removed, and the first initial insulating layer and the second initial insulating layer are etched a second time to form the first insulating layer and the second insulating layer, respectively. The height of the second insulating layer along the third direction is less than the height of the first insulating layer along the third direction. The first initial gate layer and the second initial gate layer are etched to form a first gate and a second gate, respectively, and the height of the second gate along the third direction is less than the height of the first gate along the third direction. Wherein, the first insulating layer and the first gate constitute the first gate line structure, the second insulating layer and the second gate constitute the second gate line structure, and the first gate line structure and the second gate line structure constitute the gate line structure.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, The method for fabricating the semiconductor device further includes: A first filling insulating layer is formed in the gate trench, covering the first gate and the first insulating layer; An opening is formed by etching the first filling insulating layer, and a gate isolation structure is formed by etching the first gate through the opening. The gate isolation structure extends along the third direction and disconnects the first gate. An isolation derivative structure is formed in the opening, the width of the isolation derivative structure along the second direction being greater than the width of the gate isolation structure along the second direction.

15. The method for fabricating a semiconductor device according to claim 14, characterized in that, The method for fabricating the semiconductor device further includes: A gate shielding trench is formed that extends along the third direction and is located between two rows of semiconductor pillars adjacent to each other in the second direction, the gate shielding trench and the gate line structure being alternately arranged along the second direction; A fourth insulating layer is formed in the gate shielding trench; A shielding metal and a third insulating layer are sequentially formed on the surface of the fourth insulating layer to form a grid shielding structure, wherein the third insulating layer is located on the shielding metal.

16. The method for fabricating a semiconductor device according to claim 15, characterized in that, The step of etching the first filling insulating layer to form an opening, and then etching the first gate through the opening to form a gate isolation structure, includes: The first filling insulating layer and the third insulating layer are etched to form openings to expose the top of the first gate adjacent to the shielding metal. The first gate adjacent to the shielding metal is etched to form an isolation gap that extends through the first gate along the third direction. The gate isolation structure includes the isolation gap.

17. The method for fabricating a semiconductor device according to claim 13, characterized in that, The method for fabricating the semiconductor device further includes: A second filling insulating layer is formed in the gate trench, located on the second gate and the second insulating layer; Lead-out contacts are formed at the top of the semiconductor pillar.

18. A storage system, characterized in that, include: The semiconductor device according to claims 1-11; A controller, coupled to the semiconductor device, is used to control the semiconductor device to store data.

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