Memory component and method of manufacturing the same

Abstract

The present disclosure provides a memory component and a method of manufacturing the same. The memory component includes a plurality of active regions defined in a semiconductor substrate in an isolation structure, wherein the plurality of active regions are arranged in an array along a first and a second direction and extend along a third direction, and a plurality of word lines passing through the plurality of active regions along the second direction in the semiconductor substrate. The plurality of active regions are arranged in pairs along the second direction, active regions in a same pair being immediately adjacent to each other with a first distance, and two adjacent pairs of active regions being spaced apart from each other with a second distance larger than the first distance. A feature portion of each active region under a passed word line has a first side immediately adjacent to another active region in the same pair with the first distance and a second side spaced apart from another pair of active regions with the second distance, and has a sloped upper surface climbing from the second side to the first side.

Description

Technical Field

[0001] This invention relates to a semiconductor component and its manufacturing method, and more particularly to a memory component and its manufacturing method. Background Technology

[0002] DRAM is a widely used type of volatile memory. Each DRAM cell includes a transistor and a storage capacitor connected to that transistor. With advancements in DRAM technology, the integration density of DRAM has continuously increased. This increase in integration density includes reducing the spacing between the active regions of the transistors. By densely arranging DRAM cells, more DRAM cells can be placed in a given area, thus increasing the storage density of DRAM. Furthermore, to further improve DRAM performance, it is desirable to enhance the performance of the access transistors while increasing the DRAM integration density. Summary of the Invention

[0003] One embodiment of this disclosure provides a memory component including: a plurality of active regions defined in a semiconductor substrate by an isolation structure, wherein the plurality of active regions are arrayed along a first direction and a second direction and extend along a third direction intersecting the first direction and the second direction; and a plurality of word lines formed in the semiconductor substrate and passing through the plurality of active regions along the second direction, wherein the plurality of active regions are arranged in pairs in the second direction, the active regions of the same pair are adjacent to each other at a first distance, and the active regions of adjacent pairs are spaced apart from each other at a second distance greater than the first distance, and a characteristic portion of each active region located below at least one of the multiple word lines has a first side adjacent to another active region of the same pair at the first distance and a second side spaced apart from the active regions of another pair at the second distance, and has an inclined upper surface rising from the second side to the first side.

[0004] Another embodiment of this disclosure provides a method for manufacturing a memory component, comprising: defining a plurality of active regions separated from each other in a semiconductor substrate using an isolation structure, wherein the plurality of active regions are arranged in an array along a first direction and a second direction and extend along a third direction interleaved with the first direction and the second direction, the plurality of active regions are arranged in pairs in the second direction, the active regions of the same pair are adjacent to each other with a first distance, and the active regions of two adjacent pairs are spaced apart from each other with a second distance greater than the first distance; forming a mask pattern on the semiconductor substrate, wherein the mask pattern has along... Multiple openings extending in the second direction; multiple etching processes performed using the mask pattern as a mask to form multiple trenches passing through the isolation structure and the multiple active areas, wherein after the multiple etching processes, the feature portion of each active area located below at least one of the multiple trenches has a first side adjacent to another active area in the same pair at the first distance and a second side spaced apart from the active areas of another pair at the second distance, and has an inclined upper surface rising from the second side to the first side; and multiple letter lines are filled in the multiple trenches. Attached Figure Description

[0005] Figure 1A This is a plan view of a memory component according to some embodiments of the present disclosure;

[0006] Figure 1B It is along Figure 1A A cross-sectional view of the tangent A-A';

[0007] Figure 1C Book edge Figure 1A A cross-sectional view of the tangent B-B';

[0008] Figure 2 This is a flowchart of a method for manufacturing active regions and word lines according to some embodiments of the present disclosure;

[0009] Figures 3A to 3J yes Figure 2 Cross-sectional schematic diagram of the intermediate structures at each stage of the manufacturing process. Detailed Implementation

[0010] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0011] Figure 1A This is a plan view of a memory component 10 according to some embodiments of the present disclosure. The memory component 10 is, for example, a DRAM array including a plurality of DRAM cells. Each DRAM cell includes an access transistor and a storage capacitor connected to the access transistor. For simplicity, Figure 1A The storage capacitor located above the access transistor is not shown. In addition, Figure 1A Most of the insulating components are not shown. At least some insulating components will be referenced. Figure 1B and Figure 1C illustrate.

[0012] Please refer to Figure 1A The memory component 10 includes multiple active regions 100. Each active region 100 may be a semiconductor substrate (see reference 100). Figure 1B , Figure 1C A portion of the semiconductor substrate 114 described. An isolation structure 102 formed in the semiconductor substrate laterally surrounds each active region 100 to electrically isolate adjacent active regions 100 from each other.

[0013] The active regions 100 in each column are arranged along direction D1, and the active regions 100 in each row are arranged along direction D2, which is interleaved (e.g., orthogonal to) direction D1. The active regions 100 in each column may be offset relative to the active regions 100 in adjacent columns. Similarly, the active regions 100 in each row may be offset relative to the active regions 100 in adjacent rows. Furthermore, each active region 100 may extend along direction D3, which is interleaved with directions D1 and D2. A plurality of separate insulating structures 104 are embedded in the isolation structure 102 and are respectively located between two adjacent active regions 100 in direction D3. In some embodiments, each insulating structure 104 is concave corresponding to the active regions 100 on both sides, forming a double concave shape.

[0014] Multiple word lines 106 traverse an array of active regions 100 along direction D2. The access transistors of each DRAM cell are defined at the intersection of a word line 106 and an active region 100. For each access transistor, the word line 106 it passes through serves as the gate, and the portion of the active region 100 located on either side of this word line 106 serves as the drain and source. To allow two access transistors to share an active region 100, each active region 100 is interleaved with a pair of word lines 106. In this way, the portion of each active region 100 located between the interleaved word lines 106 can serve as the common drain / source of the two shared access transistors.

[0015] Multiple bit lines 108 extend above the semiconductor substrate along direction D1 and are intersected by a row of active regions 100. The common-drain / source portion of each active region 100 can be connected to the upper bit line 108 via a bit line contact structure 110. As described above, the common-drain / source portion of each active region 100 can be the portion located between the intersecting two word lines 106. Therefore, the portion of each active region 100 located between the intersecting two word lines 106 overlaps the upper bit line contact structure 110 and the bit line 108.

[0016] On the other hand, the portions of each active region 100 located on both sides of the intersecting two word lines 106 are connected to an upper storage capacitor (not shown) via a capacitor contact structure 112. In other words, each active region 100 overlaps the two capacitor contact structures 112 at both ends. Although not shown, multiple storage capacitors connected to a capacitor contact structure 112 can be disposed on the bit line contact structure 110, the capacitor contact structure 112, and the bit line 108. These storage capacitors can have multiple lower electrodes that are separate from each other and respectively connected to a capacitor contact structure 112, while sharing a dielectric layer and an upper electrode.

[0017] Based on a staggered configuration, each word line 106 intersects with some active regions 100 and overlaps with the isolation structure 102 and insulation structure 104 between these active regions 100. The active regions 100 intersected by each word line 106 are adjacent to each other in pairs. Looking along each word line 106, each pair of adjacent active regions 100 is arranged between two insulation structures 104, and is separated from the two adjacent pairs of active regions 100 by a large interval through these two insulation structures 104. Specifically, below each word line 106, the active regions 100 in the same pair are adjacent to each other at a distance S1, and each pair of active regions 100 is separated from the two adjacent pairs of active regions 100 by a distance S2 greater than the distance S1. Thus, each active region 100 is separated from the two active regions 100 adjacent in direction D2 by different distances S1 and S2. As will be described in more detail, when forming the word lines 106, this asymmetrical spacing will cause the portion of each active region 100 extending along the bottom surface of the intersecting word lines 106 to have a slope that rises from the side with the longer spacing to the side with the shorter spacing. Correspondingly, the section of each word line 106 that passes through the active region 100 also has a sloped bottom surface.

[0018] Figure 1B It is along Figure 1A A cross-sectional view of the tangent A-A', and Figure 1C It is along Figure 1A A cross-sectional view of the tangent line B-B'. It should be noted that... Figure 1B and Figure 1C Components located on the semiconductor substrate, including bit line contact structure 110, capacitor contact structure 112, and bit line 108, are omitted from the diagram.

[0019] Please refer to the schematic diagram showing the cross-section along the extension direction (third direction D3) of the active region 100. Figure 1BThe isolation structure 102 extends from the top surface of the semiconductor substrate 114 into the semiconductor substrate 114, surrounding each active region 100. Furthermore, the insulating structures 104 located at both ends of each active region 100 extend from the top surface of the isolation structure 102 into the isolation structure 102, such that the isolation structure 102 covers the insulating structure 104. In some embodiments, the isolation structure 102 and the insulating structure 104 embedded in the isolation structure 102 are made of different insulating materials. For example, the isolation structure 102 may be made of silicon oxide, while the insulating structure 104 may be made of silicon nitride.

[0020] from Figure 1B It is understood that the word line 106 is embedded in the semiconductor substrate 114 and can pass through the active region 100, the isolation structure 102, and the insulating structure 104 embedded in the isolation structure 102. Furthermore, the word line 106 can be formed at the bottom of trenches extending into the semiconductor substrate 114, and the upper part of these trenches is filled with an insulating plug 116. Moreover, the sections of each trench passing through the active region 100 can be lined with a gate dielectric layer 118, so that the word line 106 and the insulating plug 116 located in the trench are separated from the active region 100 by the gate dielectric layer 118. On the other hand, the sections of each trench passing through the isolation structure 102 and the insulating structure 104 can have a greater depth than the sections passing through the active region 100 and are not lined with the gate dielectric layer 118. This causes the portions of the word lines 106 located in the trenches passing through the isolation structure 102 and the insulating structure 104 to extend to a deeper depth than the portions of the word lines 106 located in the trenches passing through the active region 100. Furthermore, the portions of the word lines 106 and the insulator plugs 116 located in the trenches passing through the isolation structure 102 and the insulating structure 104 are not covered by the gate dielectric layer 118. In some embodiments, the insulating liner 120 extends along the top surface of the semiconductor substrate 114, the isolation structure 102, and the insulating structure 104. In these embodiments, the trenches accommodating the word lines 106 and the insulator plugs 116 extend through the insulating liner 120 into the active region 100, the isolation structure 102, and the insulating structure 104. Moreover, although not shown, each word line 106 may have a conductive material body and a conductive barrier layer covering the conductive material body.

[0021] Figure 1C The cross-section along line 106 is schematically shown. From Figure 1CIt can be seen that the sections of each word line 106 that pass through the isolation structure 102 and the insulating structure 104 extend to a deeper depth than the sections that pass through the active regions 100. This causes the portions of each active region 100 located below the intersecting word lines 106 to protrude more than the portions of the isolation structure 102 and the insulating structure 104 located below the intersecting word lines 106. Furthermore, the active regions 100 where the word lines 106 intersect are arranged in pairs along the extension direction (direction D2) of the word lines 106. Among them, the active regions 100 in the same pair (e.g., active regions 100a and 100b) are adjacent to each other at a distance S1 and separated by the isolation structure 102. In addition, each pair of active regions 100 (e.g., active regions 100a and 100b) is spaced apart from an adjacent pair of active regions 100 (e.g., a pair of active regions 100 including active region 100c or another pair of active regions 100 including active region 100d) by a distance S2 greater than the distance S1, and an isolation structure 102 and an insulating structure 104 are filled between adjacent pairs of active regions 100.

[0022] As a result, the portion of each active region 100 located below the intersecting word lines 106 has a first side spaced apart from the adjacent active region 100 by a shorter distance S1, and a second side spaced apart from another active region 100 by a longer distance S2. Based on etching differences, the portion of each active region 100 located below the intersecting word lines 106 has an inclined upper surface 100s that rises from the second side to the first side along the direction D2. Accordingly, viewed in cross-section along the direction D2, the portion of each active region 100 located below the intersecting word lines 106 has a shape similar to the end of a utility knife. Correspondingly, each word line 106 has an inclined lower surface 106s extending along the inclined upper surface 100s of the lower active region 100, and has a first depth DP1 at the first side corresponding to the lower active region 100, and a second depth DP2 greater than the first depth DP1 at the second side corresponding to the lower active region 100. In addition, the gate dielectric layer 118 between each word line 106 and the intersecting active regions 100 also extends along the inclined upper surface 100s of these active regions 100.

[0023] The active regions 100, which are intersected by the word lines 106, are arranged periodically in pairs along direction D2, and the two active regions 100 in the same pair (e.g., active regions 100a and 100b) are symmetrical about the central axis between them. In this way, the inclined upper surface 100s of the two active regions 100 in the same pair (e.g., active regions 100a and 100b) rises toward the central axis between them. Alternatively, each active region 100 can also be symmetrical about another active region 100 (e.g., active regions 100b and 100c or active regions 100a and 100d) separated by a distance S2, so that the inclined upper surface 100s of these two active regions 100 (active regions 100b and 100c or active regions 100a and 100d) descends toward the central axis between them.

[0024] On the other hand, the portions of the isolation structure 102 and the insulation structure 104 located below each word line 106 are not limited to having an upper surface inclined along direction D2, and the portions of each word line 106 located above the isolation structure 102 and the insulation structure 104 may have a corresponding lower surface. For example, these portions of the isolation structure 102 and the insulation structure 104 may have a generally flat surface or a recessed upper surface in direction D2, and the portions of each word line 106 located above the isolation structure 102 and the insulation structure 104 may correspondingly have a generally flat surface or a convex lower surface in direction D2.

[0025] Furthermore, the portions of each active region 100 that do not intersect with the word lines 106 are not limited to having an upper surface that is inclined along direction D2. For example, these portions of each active region 100 may have an upper surface that is generally flat, convex, or concave in direction D2.

[0026] The special structure of the active area 100 and the word line 106 is derived from the arrangement and manufacturing method of the active area 100. The manufacturing method of the active area 100 and the word line 106 will be explained below.

[0027] Figure 2 This is a flowchart of a method for manufacturing an active region 100 and a word line 106 according to some embodiments of this disclosure. Figures 3A to 3J yes Figure 2 Cross-sectional schematic diagrams of intermediate structures at each stage of the manufacturing process. Among them, Figure 3A , Figure 3C , Figure 3E , Figure 3G , Figure 3I It is a cross section along the extension direction (direction D3) of an active region 100. Figure 3B , Figure 3D , Figure 3F , Figure 3H , Figure 3J It is the cross section along the extension direction (direction D2) of line 106.

[0028] Please refer to Figure 2 , Figure 3A and Figure 3B In step S200, an isolation structure 102 and an insulating structure 104 are formed in the semiconductor substrate 114, and an insulating liner 120 extending along the top surface of the semiconductor substrate 114, the isolation structure 102, and the insulating structure 104 is formed. Specifically, the isolation structure 102 may be formed in the semiconductor substrate 114 first, followed by the insulating structure 104 formed in the isolation structure 102. After performing a possible planarization process, the insulating liner 120 is formed on the semiconductor substrate 114, the isolation structure 102, and the insulating structure 104. The isolation structure 102 defines a plurality of active regions 100 in the semiconductor substrate 114. Figure 3B As shown, in direction D2, the active regions 100 are arranged in pairs, adjacent to each other. For example, active regions 100a and 100b in the same pair are adjacent to each other at a distance S1, while each pair of active regions 100 (e.g., active regions 100a and 100b) is separated from another pair of active regions 100 (e.g., a pair of active regions 100 including active region 100c or another pair of active regions 100 including active region 100d) by a distance S2 greater than the distance S1.

[0029] Please refer to Figure 2 , Figure 3C and Figure 3D In step S202, a mask pattern 300 is formed on the insulating liner 120. The mask pattern 300 has a plurality of openings W. 300 These openings W 300 Used to define the channel for accommodating word line 106 in subsequent steps. That is, the opening W 300 The position and width define the position and width of the character line 106. Because... Figure 3D This shows a cross section along the subsequently formed line 106, therefore Figure 3D Above the insulating liner 120 is a continuously extending opening W. 300 (Represented by dashed outline). In some embodiments, the mask pattern 300 may be a rigid mask, such as a rigid mask made of diamond-like carbon (DLC).

[0030] Please refer to Figure 2 , Figure 3E and Figure 3F In step S204, a first etching process is performed using the mask pattern 300 as a mask. This forms multiple trenches TR that penetrate the insulating liner 120 and enter the active region 100, the isolation structure 102, and the insulating structure 104. Figure 3E The cross-sections of some trenches (TR) can be seen, and from... Figure 3FA longitudinal section of a trench TR (shown as a dashed outline) can be seen. By selecting an appropriate etchant, the first etching process primarily targets the isolation structure 102 and the insulating structure 104. As a result, the section of the trench TR penetrating the isolation structure 102 and the insulating structure 104 is deeper than the section penetrating the active region 100. By controlling the etching time, the section of each trench TR penetrating each active region 100 can have a depth DP3, and the section of each trench TR penetrating the isolation structure 102 and the insulating structure 104 can have a depth DP4 significantly greater than the depth DP3.

[0031] In addition, such as Figure 3F As shown, a deep slit with a depth DP greater than the first distance S1 is formed between a pair of active regions 100 adjacent to each other at a first distance S1 in direction D2 (e.g., active regions 100a and 100b). On the other hand, a wide groove with a depth DP' greater than the first distance S1 and a width greater than the aforementioned deep slit is formed between two pairs of active regions 100 separated by a second distance S2 in direction D2 (e.g., active regions 100a and 100b and a pair of active regions 100 including active region 100c or a pair of active regions 100 including active region 100d). In this way, each active region 100 is separated from the adjacent active regions 100 on both sides in direction D2 by the deep slit and the wide groove, respectively. This will cause the portion of each active region 100 located below the through trench TR to be etched with an inclined surface. As an example, the etching result can be achieved when the aspect ratio of the deep slit (the ratio of depth DP to the first distance S1) is in the range of 1.5 to 2.5 and the aspect ratio of the wide groove (the ratio of depth DP' to the second distance S2) is in the range of 0.6 to 1.2. As another example, the etching result can be achieved when the aspect ratio of the deep slit is greater than 1.5 and the aspect ratio of the wide groove is less than 1.2. It is worth mentioning that, in one embodiment, the ratio of the depth DP of the deep slit to the depth DP' of the wide groove can be further controlled to be between 0.9 and 1 to achieve the etching result.

[0032] Additionally, below each ditch TR (such as...) Figure 3F As shown, the active region 100 protrudes relative to the isolation structure 102 and the insulation structure 104. Furthermore, viewed along direction D2, the portion of each active region 100 located below the trench TR it passes through can be shaped into a convex surface with an arcuate shape. In other embodiments, viewed along direction D2, the portion of each active region 100 located below the trench TR it passes through can also be shaped into other convex surfaces with bilateral symmetry.

[0033] Please refer to Figure 2 , Figure 3G and Figure 3HIn step S206, a second etching process is performed using the mask pattern 300 as a mask. By selecting an appropriate etchant, the second etching process can be specifically targeted at the active region 100. As a result, the depth of each trench TR penetrating the active region 100 increases, while the depth of the section approaching the depth of each trench TR penetrating the isolation structure 102 and the insulating structure 104 is approximately equal to or slightly greater than the reference depth. Figure 3E , Figure 3F The described depth is DP4.

[0034] For reference Figure 3F As described, the portions of each active region 100 located below the trench TR are separated from adjacent active regions 100 on both sides by deep slits and wide grooves. This will cause the portions of each active region 100 located below the traversed trench TR to be etched with different amounts on the wide groove side and the deep slit side in the current step, resulting in an asymmetric structure. Figure 3H As shown, below each trench TR, the etching amount on the wide groove side of each active region 100 is greater than the etching amount on the deep slit side. As a result, the arcuate convex surface of the portion of each active region 100 located below the trench TR is modified into an inclined upper surface 100s that rises from the wide groove side to the deep slit side. In this way, each trench TR has a depth DP5 corresponding to the deep slit side of the active region 100 below, and a depth DP6 greater than the depth DP5 corresponding to the wide groove side of the active region 100. Furthermore, in direction D2, adjacent active regions have inclined upper surfaces 100s with different inclination directions, and the inclined upper surfaces 100s of adjacent active regions 100 can be symmetrical with respect to their respective central axes.

[0035] Please refer to Figure 2 , Figure 3I and Figure 3J In step S208, a third etching process is performed using the mask pattern 300 as a mask. By selecting an appropriate etchant, the third etching process can be specifically targeted at etching the isolation structure 102 and the insulating structure 104. As a result, the depth of each trench TR penetrating the isolation structure 102 and the insulating structure 104 increases, and it has a greater depth than the reference trench. Figure 3E , Figure 3G The depth DP4 is described as the depth DP7. On the other hand, the depth of each ditch TR passing through the active zone 100 remains roughly unchanged or increases slightly, that is, in reference... Figure 3H The depth range DP5 to DP6 described is within or slightly larger than this range. As a result, the depth difference between the sections of each trench TR passing through the isolation structure 102 and the insulation structure 104 and the sections of each trench TR passing through the active region 100 is increased.

[0036] like Figure 3JAs shown, below each trench TR, each active region 100 protrudes more relative to the isolation structure 102 and the insulating structure 104, exhibiting a shape similar to the tip of a utility knife. At this time, the deep slit side of the portion of each active region 100 located below the trench TR it passes through protrudes from the isolation structure 102 at a greater height than the wide groove side, and the inclined upper surface 100s connects the deep slit side and the wide groove side.

[0037] After the third etching process is completed, the mask pattern 300 can be removed before proceeding to the next process step.

[0038] Please refer to Figure 2 , Figure 1B and Figure 1C Subsequently, at step S210, a gate dielectric layer 118 is formed to selectively line the section of the trench TR that passes through the active region 100. In some embodiments, the gate dielectric layer 118 is selectively formed at the section of the trench TR that passes through the active region 100 by a thermal oxidation process. Next, at step S212, word lines 106 and insulator plugs 116 are filled into the trench TR.

[0039] At this point, the fabrication of the active region 100 and word line 106 is complete. Although not shown, subsequent process steps will be used to form structures such as bit line contact structure 110, capacitor contact structure 112, bit line 108, and storage capacitor located on the semiconductor substrate 114.

[0040] In summary, this disclosure provides a memory component and a method for manufacturing the same. The memory component is a DRAM, including a plurality of access transistors defined at the intersection of multiple active regions and multiple word lines, and a plurality of storage capacitors respectively connected to each access transistor. Along each word line, the active regions are arranged in pairs. Two active regions in the same pair are adjacent to each other at a first distance, while adjacent pairs of active regions are spaced apart by a second distance greater than the first distance. Thus, the portion of each active region located below the word line it passes through has a first side adjacent to one active region at the first distance, and two sides spaced apart from another active region by a second distance. Based on this configuration and the control of the etching process, the portion of each active region located below the word line it passes through is formed into an asymmetrical structure similar to the tip of a utility knife, and has an inclined upper surface that rises from the second side to the first side. Furthermore, below each word line, the two active regions adjacent to each other at the first distance are symmetrical with respect to the central axis between them, such that the inclined upper surfaces of these two active regions rise towards the central axis between them. On the other hand, below each character line, two active regions spaced apart from each other by a second distance are also symmetrical with respect to the central axis between them, such that the inclined surfaces of these two active regions extend downward toward the central axis between them.

[0041] Based on this special structure, the access transistor exhibits a larger on-current and a smaller sub-threshold swing. Consequently, the access transistor has stronger driving force and better switching characteristics. This effectively improves access to the storage capacitor in the operation of memory components.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory component, characterized in that, include: Multiple active regions defined in a semiconductor substrate by an isolation structure, wherein the multiple active regions are arranged in an array along a first direction and a second direction, and extend along a third direction that is interleaved with the first direction and the second direction; as well as Multiple word lines are formed in the semiconductor substrate and pass through the multiple active regions along the second direction. The plurality of active regions are arranged in pairs in the second direction, with the active regions in the same pair being adjacent to each other at a first distance, and the active regions in two adjacent pairs being spaced apart from each other at a second distance greater than the first distance. The characteristic portion of each active region located below at least one of the plurality of word lines has a first side that is adjacent to the other active region in the same pair at the first distance and a second side that is spaced apart from the active regions in another pair at the second distance, and has an inclined upper surface that rises from the second side to the first side. The plurality of first segments of the plurality of word lines passing through the plurality of active regions are less in depth than the plurality of second segments of the plurality of word lines passing through the isolation structure, and the first segment of each word line has a lower surface that is inclined in the second direction.

2. The memory component according to claim 1, characterized in that, The characteristic portion of each active region protrudes compared to the portion of the isolation structure located below the multiple word lines.

3. The memory component according to claim 1, characterized in that, The characteristic portion of each active region has an asymmetric structure.

4. The memory component according to claim 1, characterized in that, The characteristic portions of two adjacent active regions are symmetrical with respect to the central axis between them.

5. A method for manufacturing a memory component, characterized in that, include: Multiple active regions are defined in a semiconductor substrate by an isolation structure, wherein the multiple active regions are arranged in an array along a first direction and a second direction and extend along a third direction that is interleaved with the first direction and the second direction, the multiple active regions are arranged in pairs in the second direction, the active regions in the same pair are adjacent to each other with a first distance, and the active regions in two adjacent pairs are spaced apart from each other with a second distance greater than the first distance. A mask pattern is formed on the semiconductor substrate, wherein the mask pattern has a plurality of openings extending along the second direction; Multiple etching processes are performed using the mask pattern as a mask to form multiple trenches passing through the isolation structure and the plurality of active regions. After the multiple etching processes, a feature portion of each active region located below at least one of the trenches has a first side adjacent to another active region in the same pair at a first distance and a second side spaced apart from the active regions of the other pair at a second distance, and has an inclined upper surface rising from the second side to the first side; and Multiple lines were filled into the aforementioned ditches.

6. The method for manufacturing a memory component according to claim 5, characterized in that, The multiple etching processes sequentially include a first etching process, a second etching process, and a third etching process.

7. The method for manufacturing a memory component according to claim 6, characterized in that, The first etching process and the third etching process selectively etch the isolation structure, while the second etching process selectively etches the plurality of active regions.

8. The method for manufacturing a memory component according to claim 7, characterized in that, As a result of the first etching process, deep slits with an aspect ratio of 1.5 to 2.5 are defined between the same pair of active regions, and wide grooves with an aspect ratio of 0.6 to 1.2 are defined between two adjacent pairs of active regions.

9. The method for manufacturing a memory component according to claim 7, characterized in that, The second etching process results in different etching amounts on the first and second sides of the feature portions of each active region, thus creating the tilted upper surface.

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