Insulated gate bipolar transistor and method for manufacturing the same

Abstract

The present application discloses an insulated gate bipolar transistor and a preparation method thereof, and relates to the field of semiconductor technology. The insulated gate bipolar transistor of the present application comprises: a substrate and a drift layer arranged on the substrate, the drift layer comprises an N-type drift region and a P-type drift region arranged in a close relationship, the upper surface of the N-type drift region is flush with the upper surface of the P-type drift region, a gate structure and an N-type doped first barrier region are formed on the upper surface of the N-type drift region, an N-type doped second barrier region is arranged on the P-type drift region, the first barrier region and the second barrier region are arranged in a close relationship, and the N-type doping concentration of the first barrier region is greater than the N-type doping concentration of the second barrier region, a P-type base region is arranged on the first barrier region and the second barrier region, and an N-type heavily doped region and a P-type heavily doped region are arranged on the P-type base region. The insulated gate bipolar transistor and the preparation method thereof provided by the present application can improve the turn-off loss on the basis of reducing the turn-on loss.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an insulated gate bipolar transistor and a method for preparing the same. Background Art

[0002] The insulated gate bipolar transistor (IGBT) device is a device composed of a MOS transistor and a bipolar transistor. Its input pole is a MOS transistor and its output pole is a PNP transistor. It combines the advantages of these two devices. It has the advantages of low driving power and fast switching speed of MOS transistors, and the advantages of low saturation voltage and large capacity of bipolar transistors. It has been increasingly widely used in modern power electronics technology, especially occupying a dominant position in the application of high-frequency large and medium-power tubes.

[0003] At present, the main development direction of IGBT is based on the trench gate junction, combined with the positive carrier storage technology. The basic structure of the existing trench IGBT device is to set an N-type carrier storage layer between the P-type structure and the N-type voltage-resistant layer. When the device is turned on, the N-type carrier storage layer can block the holes from flowing to the P-type base region, which can increase the carrier concentration at the top of the device and enhance the carrier storage effect at the top. This structure can reduce the on-state voltage drop of the device, thereby reducing the turn-on loss; but it will also greatly increase the saturation current of the device, thereby reducing the short-circuit resistance of the device; and when the effect of the N-type carrier storage layer is enhanced, more carriers are present in the IGBT. When the IGBT is turned off, the turn-off speed of the IGBT is reduced, thereby increasing the turn-off loss of the IGBT. Summary of the invention

[0004] The purpose of the present application is to provide an insulated gate bipolar transistor and a method for preparing the same, which can improve the turn-off loss while reducing the turn-on loss.

[0005] On the one hand, an embodiment of the present application provides an insulated gate bipolar transistor, comprising: a substrate and a drift layer arranged on the substrate, the drift layer comprising an N-type drift region and a P-type drift region arranged in close contact, the upper surface of the N-type drift region is flush with the upper surface of the P-type drift region, a gate structure and an N-type doped first barrier region are formed on the upper surface of the N-type drift region, an N-type doped second barrier region is arranged on the P-type drift region, the first barrier region and the second barrier region are arranged in close contact, and the N-type doping concentration of the first barrier region is greater than the N-type doping concentration of the second barrier region, a P-type base region is arranged on the first barrier region and the second barrier region, and an N-type heavily doped region and a P-type heavily doped region are arranged on the P-type base region; wherein the first barrier region is used to block holes from flowing to the P-type base region when the insulated gate bipolar transistor is turned on, and the second barrier region is used to reduce the barrier height between the P-type drift region and the second barrier region when the insulated gate bipolar transistor is turned off.

[0006] As an practicable manner, the doping concentration of the N-type drift region gradually decreases in a direction away from the substrate.

[0007] As an practicable manner, the doping concentration of the P-type drift region gradually decreases in a direction away from the substrate.

[0008] As an implementable manner, the N-type drift region includes an N+ doped region, an N doped region, and an N- doped region which are sequentially arranged in a direction away from the substrate.

[0009] As an practicable method, the doping concentration of the N-doped region is 1e 14 / cm 3 -1e 16 / cm 3 The doping concentration of the N+ doping region is 1-1.2 times the doping concentration of the N doping region, and the doping concentration of the N- doping region is 0.8-1 times the doping concentration of the N doping region.

[0010] As an implementable manner, the P-type drift region includes a P+ doped region, a P doped region, and a P- doped region which are sequentially arranged in a direction away from the substrate.

[0011] As an practicable method, the doping concentration of the P-doped region is 1e 14 / cm 3 -1e 16 / cm 3 The doping concentration of the P+ doping region is 1-1.2 times the doping concentration of the P doping region, and the doping concentration of the P- doping region is 0.8-1 times the doping concentration of the P doping region.

[0012] As an practicable manner, the cross section of the P-type drift region gradually decreases in a direction away from the substrate.

[0013] On the other hand, an embodiment of the present application provides a method for preparing an insulated gate bipolar transistor, which is used to prepare the above-mentioned insulated gate bipolar transistor, including: providing an N-type substrate, and performing P-type doping ion implantation on one side of the N-type substrate to form a P-type drift region, and the region where the P-type doping ion implantation is not performed is the N-type drift region; epitaxially growing an N-type layer on the upper surfaces of the P-type drift region and the N-type drift region, and forming a first barrier region and a second barrier region on the N-type layer, the first barrier region is located on the N-type drift region, the second barrier region is located on the P-type drift region, the first barrier region and the second barrier region are arranged in contact with each other, and the doping concentration of the first barrier region is greater than the doping concentration of the second barrier region; epitaxially growing a base region layer on the upper surface of the N-type layer and doping to form a P-type base region, the P-type base region is located on the first barrier region and the second barrier region; forming an N-type heavily doped region and a P-type heavily doped region on the P-type base region, and forming a gate structure on the other side of the P-type base region layer, the gate structure extending downward to the N-type drift region; doping the other side of the N-type substrate to form a P-type substrate.

[0014] As an implementable method, an N-type substrate is provided, and P-type doping ions are implanted from one side of the N-type substrate to form a P-type drift region, and the region where the P-type doping ions are not implanted is the N-type drift region, including: three times of P-type doping ion implantation from one side of the N-type substrate, the depth of the three times gradually decreases, and the concentration of the ion implantation gradually decreases to form a P+ doping region, a P doping region and a P- doping region, and the projections of the P+ doping region, the P doping region and the P- doping region on the substrate overlap; three times of N-type doping ion implantation from one side of the N-type substrate, the depth of the three times gradually decreases, and the concentration of the ion implantation gradually decreases to form an N+ doping region, an N doping region and an N- doping region, and the projections of the N+ doping region, the N doping region and the N- doping region on the substrate overlap.

[0015] Epitaxially growing an N-type layer on the upper surfaces of a P-type drift region and an N-type drift region, and forming a first barrier region and a second barrier region on the N-type layer include: epitaxially growing an N-type layer on the upper surfaces of a P-type drift region and an N-type drift region; ion implanting a side of the N-type layer located on the N-type drift region close to the P-type drift region to form a first barrier region; ion implanting a portion of the N-type layer located on the P-type drift region to form a second barrier region, the first barrier region and the second barrier region being arranged in contact with each other, and the doping concentration of the first barrier region is greater than the doping concentration of the second barrier region.

[0016] The beneficial effects of the embodiments of the present application include:

[0017] The insulated gate bipolar transistor provided by the present application comprises: a substrate and a drift layer arranged on the substrate, the drift layer comprises an N-type drift region and a P-type drift region arranged in a close relationship, the upper surface of the N-type drift region is flush with the upper surface of the P-type drift region, the upper surface of the N-type drift region forms a gate structure and an N-type doped first barrier region, the first barrier layer is arranged on the N-type drift region, when the IGBT is turned on, it can reduce the conduction voltage drop of the device, thereby reducing the turn-on loss; an N-type doped second barrier region is arranged on the P-type drift region, the first barrier region and the second barrier region are arranged in a close relationship, and the N-type doping concentration of the first barrier region is greater than the N-type doping concentration of the second barrier region, that is, the N-type doping concentration of the second barrier region is lower. The second barrier region is arranged on the P-type drift region, and when the doping concentration of the second barrier region is lower, the barrier height between the P-type drift region and the second barrier region can be reduced. A P-type base region is arranged on the first barrier region and the second barrier region, and an N-type heavily doped region and a P-type heavily doped region are arranged on the P-type base region. When the IGBT is turned off, since the barrier height between the P-type drift region and the second blocking region is low, the PNP transistor is easier to turn on, thereby reducing the turn-off loss. Therefore, the IGBT provided in the present application can improve the turn-off loss on the basis of reducing the turn-on loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 One of the structural schematic diagrams of an insulated gate bipolar transistor provided in an embodiment of the present application;

[0020] Figure 2 A second structural schematic diagram of an insulated gate bipolar transistor provided in an embodiment of the present application;

[0021] Figure 3 A third structural schematic diagram of an insulated gate bipolar transistor provided in an embodiment of the present application;

[0022] Figure 4 A flow chart of a method for preparing an insulated gate bipolar transistor provided in an embodiment of the present application;

[0023] Figure 5 One of the state diagrams of a method for preparing an insulated gate bipolar transistor provided in an embodiment of the present application;

[0024] Figure 6 A second state diagram of a method for preparing an insulated gate bipolar transistor provided in an embodiment of the present application;

[0025] Figure 7 A third state diagram of a method for preparing an insulated gate bipolar transistor provided in an embodiment of the present application;

[0026] Figure 8 A fourth state diagram of a method for manufacturing an insulated gate bipolar transistor provided in an embodiment of the present application;

[0027] Fig. 9 A fifth state diagram of a method for preparing an insulated gate bipolar transistor provided in an embodiment of the present application;

[0028] Fig.10 One of the performance curves of the insulated gate bipolar transistor of the prior art and the embodiment of the present application;

[0029] Fig.11 The second performance curve diagram of the insulated gate bipolar transistor of the prior art and the embodiment of the present application;

[0030] Fig.12 The third performance curve diagram of the insulated gate bipolar transistor of the prior art and the embodiment of the present application;

[0031] Fig.13 One of the performance curves of the insulated gate bipolar transistor of the embodiment of the present application;

[0032] Fig.14 The second performance curve diagram of the insulated gate bipolar transistor of the embodiment of the present application;

[0033] Fig.15 The third performance curve diagram of the insulated gate bipolar transistor of the embodiment of the present application;

[0034] Fig.16 The fourth performance curve diagram of the insulated gate bipolar transistor of the embodiment of the present application;

[0035] Fig.17 This is the fifth performance curve diagram of the insulated gate bipolar transistor according to the embodiment of the present application.

[0036] Icon: 100-insulated gate bipolar transistor; 110-substrate; 120-drift layer; 121-N-type drift region; 122-P-type drift region; 123-N+ doped region; 124-N-doped region; 125-N-doped region; 126-P+ doped region; 127-P-doped region; 128-P-doped region; 131-gate structure; 132-first barrier region; 133-second barrier region; 141-P-type base region; 151-N-type heavily doped region; 152-P-type heavily doped region; 160-buffer layer; 170-emitter; 190-collector. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0038] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0039] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0040] IGBT is an integrated MOS transistor and bipolar transistor, and has the advantages of both devices, such as low driving power, fast switching speed, low saturation voltage, and large capacity. In order to reduce the on-state voltage drop of the device in the prior art, an N-type carrier storage layer is set between the P-type structure and the N-type voltage-resistant layer of the bipolar transistor. However, the N-type carrier storage layer stores more carriers, so that when the IGBT is turned off, more carriers need to be extracted, which reduces the turn-off speed and increases the turn-off loss.

[0041] The present application embodiment provides an insulated gate bipolar transistor 100, such as Figure 1 As shown, it includes: a substrate 110 and a drift layer 120 arranged on the substrate 110, the drift layer 120 includes an N-type drift region 121 and a P-type drift region 122 which are arranged in a close relationship, the upper surface of the N-type drift region 121 is flush with the upper surface of the P-type drift region 122, a gate structure 131 and an N-type doped first barrier region 132 are formed on the upper surface of the N-type drift region 121, an N-type doped second barrier region 133 is arranged on the P-type drift region 122, the first barrier region 132 and the second barrier region 133 are arranged in a close relationship, and the N-type doping concentration of the first barrier region 132 is greater than the N-type doping concentration of the second barrier region 133, a P-type base region 141 is arranged on the first barrier region 132 and the second barrier region 133, and an N-type heavily doped region 151 and a P-type heavily doped region 152 are arranged on the P-type base region 141.

[0042] The insulated gate bipolar transistor 100 provided in the embodiment of the present application includes a substrate 110 and a drift layer 120 arranged on the substrate 110, wherein the drift layer 120 includes an N-type drift region 121 and a P-type drift region 122 embedded in the N-type drift region 121, and the N-type drift region 121 and the P-type drift region 122 form a super junction structure. The setting of the super junction structure makes the electric field distribution in the drift layer 120 tend to be uniform, and the charges between the N-type drift region 121 and the P-type drift region 122 compensate each other, thereby improving the breakdown voltage of the insulated gate bipolar transistor.

[0043] In the embodiment of the present application, a gate structure 131 and a first barrier region 132 are formed on the upper surface of the N-type drift region 121, and a second barrier region 133 is arranged on the P-type drift region 122, wherein the first barrier region 132 is arranged on a side of the N-type drift region 121 close to the P-type drift region 122, and the second barrier region 133 is arranged on a side of the P-type drift region 122, so that the first barrier region 132 and the second barrier region 133 are arranged in close contact with each other, and a P-type base region 141 is arranged on the first barrier region 132 and the second barrier region 133, wherein the P-type base region 141 serves as the P terminal of the PNP transistor, so that the first barrier region 132 is located between the N-type drift region 121 and the P-type base region 141, and the first barrier region 132 is arranged in close contact with the gate structure 131, when a gate voltage is applied to the gate structure 131, the first barrier region 132 can block the holes, and the first barrier region 132 can reduce the conduction voltage drop of the device, thereby reducing the turn-on loss. In addition, the second barrier region 133 is located between the P-type base region 141 and the P-type drift region 122, wherein the doping concentration of the second barrier region 133 is less than the doping concentration of the first barrier region 132, so that the second barrier region 133 has a smaller doping concentration. In this way, the barrier height between the P-type drift region 122 and the second barrier region 133 can be reduced, and when the IGBT is turned off, the PNP transistor is easier to turn on, thereby reducing the turn-off loss of the IGBT.

[0044] In the embodiment of the present application, an N-type heavily doped region 151 and a P-type heavily doped region 152 are arranged on the P-type base region 141 as the emitter 170 of the IGBT. Figure 1 As shown, a metal layer is provided in the N-type heavily doped region 151 and the P-type heavily doped region 152 as a connection end of the emitter 170. The substrate 110 serves as the emitter 170 of the IGBT. In practical applications, a metal is provided on the side of the substrate 110 away from the drift layer 120 as a connection end of the collector 190.

[0045] In addition, those skilled in the art should know that the gate structure 131 is disposed on the oxide layer of the sidewall of the gate trench as an isolation layer of the gate, and polysilicon is disposed in the space surrounded by the oxide layer, such as Figure 1In practical applications, a buffer layer 160 may be disposed between the substrate 110 and the drift layer 120 .

[0046] It can be understood that the embodiment of the present application is an insulated gate bipolar transistor 100 with a PNP transistor as the output electrode, wherein the P-type base region 141 serves as a P terminal, the drift layer 120 serves as an N terminal, and the substrate 110 serves as another P terminal of the PNP transistor. Therefore, the substrate 110 is P+ doped.

[0047] The insulated gate bipolar transistor 100 provided in the present application includes: a substrate 110 and a drift layer 120 arranged on the substrate 110, the drift layer 120 includes an N-type drift region 121 and a P-type drift region 122 arranged in contact with each other, the upper surface of the N-type drift region 121 is flush with the upper surface of the P-type drift region 122, the P-type drift region 122 and the N-type drift region 121 form a super junction structure, and a gate structure 131 and a first barrier region 132 are formed on the upper surface of the N-type drift region 121. The first barrier region 132 is arranged on the N-type drift region 121, and when the IGBT is turned on, it can reduce the conduction voltage drop of the device, thereby reducing the turn-on loss; a second barrier region 133 is arranged on the P-type drift region 122, the first barrier region 132 and the second barrier region 133 are arranged in contact with each other, and the doping concentration of the first barrier region 132 is greater than the doping concentration of the second barrier region 133, that is, the doping concentration of the second barrier region 133 is lower. The second barrier region 133 is arranged on the P-type drift region 122. When the doping concentration of the second barrier region 133 is low, the barrier height between the P-type drift region 122 and the second barrier region 133 can be reduced. The P-type base region 141 is arranged on the first barrier region 132 and the second barrier region 133, and the N-type heavily doped region 151 and the P-type heavily doped region 152 are arranged on the P-type base region 141. When the IGBT is turned off, since the barrier height between the P-type drift region 122 and the second barrier region 133 is low, the PNP transistor is more easily turned on, thereby reducing the turn-off loss. Therefore, the IGBT provided in the present application can improve the turn-off loss on the basis of reducing the turn-on loss.

[0048] Optionally, the doping concentration of the N-type drift region 121 gradually decreases in a direction away from the substrate 110 .

[0049] When the doping concentration of the N-type drift region 121 gradually decreases in the direction away from the substrate 110, the top of the N-type drift region 121 has a smaller doping concentration. In this way, the doping concentration is the smallest at the position where the N-type drift region 121 contacts the first barrier region 132. In this way, when the IGBT is turned on, the potential barrier at the top of the N-type drift region 121 is higher, which can more easily block the outflow of holes and reduce conduction losses.

[0050] In one achievable manner of the embodiment of the present application, the doping concentration of the P-type drift region 122 gradually decreases in a direction away from the substrate 110 .

[0051] When the doping concentration of the P-type drift region 122 gradually decreases in the direction away from the substrate 110, the top of the P-type drift region 122 has a smaller doping concentration. In this way, the doping concentration is the smallest at the position where the P-type drift region 122 contacts the second blocking region 133. In this way, when the IGBT is turned off, the potential barrier at the top of the P-type drift region 122 is lower, so that holes can flow out more easily, thereby further reducing the turn-off loss.

[0052] Optional, such as Figure 2 As shown, the N-type drift region 121 includes an N+ doping region 123 , an N doping region 124 and an N− doping region 125 which are sequentially arranged in a direction away from the substrate 110 .

[0053] The doping concentrations of the N+ doping region 123, the N doping region 124, and the N- doping region 125 are gradually reduced, and are arranged in a direction away from the substrate 110, so as to reduce the conduction loss. Further, the N-type drift region 121 is divided into a plurality of regions, which is easier to implement in terms of process. Specifically, the thickness of each region is used as the doping region, and different concentrations of doping are performed in each region, so as to form the N+ doping region 123, the N doping region 124, and the N- doping region 125 in the N-type drift region 121.

[0054] In one achievable manner of the embodiment of the present application, the doping concentration of the N-doped region 124 is 1e 14 / cm 3 -1e 16 / cm 3 The doping concentration of the N+ doping region 123 is 1-1.2 times the doping concentration of the N-doping region 124 , and the doping concentration of the N− doping region 125 is 0.8-1 times the doping concentration of the N-doping region 124 .

[0055] The above-mentioned setting of the doping concentration makes the doping concentration of each region have a certain difference, and the difference is not very large. In this way, the concentration difference of each region can be reduced while reducing the conduction loss, which is easier to control in production.

[0056] Optional, such as Figure 2 As shown, the P-type drift region 122 includes a P+ doping region 126 , a P doping region 127 and a P− doping region 128 which are sequentially arranged in a direction away from the substrate 110 .

[0057] The doping concentrations of the P+ doping region 126, the P doping region 127, and the P- doping region 128 are gradually reduced, and are arranged in a direction away from the substrate 110, so as to reduce the turn-off loss. Further, the P-type drift region 122 is divided into a plurality of regions, which is easier to implement in terms of process. Specifically, the thickness of each region is used as the doping region, and different concentrations of doping are performed in each region, so as to form the P+ doping region 126, the P doping region 127, and the P- doping region 128 in the P-type drift region 122.

[0058] In one achievable method of the embodiment of the present application, the doping concentration of the P-doped region 127 is 1e 14 / cm 3 -1e 16 / cm 3 The doping concentration of the P+ doping region 126 is 1-1.2 times the doping concentration of the P doping region 127 , and the doping concentration of the P− doping region 128 is 0.8-1 times the doping concentration of the P doping region 127 .

[0059] The above-mentioned setting of the doping concentration makes the doping concentration of each region have a certain difference, and the difference is not very large. In this way, the concentration difference of each region can be reduced while reducing the turn-off loss, which is easier to control in production.

[0060] Optional, such as Figure 3 As shown, the cross-section of the P-type drift region 122 gradually decreases in the direction away from the substrate 110, so that the cross-section of the P-type drift region 122 and the second barrier region 133 decreases, thereby reducing the holes that need to be extracted from the P-type drift region 122 when the IGBT is turned off, thereby reducing the turn-off loss.

[0061] Another aspect of the present application provides a method for preparing an insulated gate bipolar transistor 100, which is used to prepare the insulated gate bipolar transistor 100. Figure 4 As shown, including:

[0062] S10: Figure 5 As shown, an N-type substrate is provided, and P-type dopant ions are implanted from one side of the N-type substrate to form a P-type drift region 122, and a region where the P-type dopant ions are not implanted is an N-type drift region 121;

[0063] In this way, a P-type drift region 122 and an N-type drift region 121 are formed in the N-type substrate as a super junction structure. When the IGBT includes a plurality of P-type drift regions 122 , the plurality of P-type drift regions 122 are embedded in the N-type drift region 121 at intervals.

[0064] S20: Figure 6As shown, an N-type layer is epitaxially grown on the upper surfaces of the P-type drift region 122 and the N-type drift region 121, and a first barrier region 132 and a second barrier region 133 are formed on the N-type layer. The first barrier region 132 is located on the N-type drift region 121, and the second barrier region 133 is located on the P-type drift region 122. The first barrier region 132 and the second barrier region 133 are arranged in contact with each other, and the doping concentration of the first barrier region 132 is greater than the doping concentration of the second barrier region 133.

[0065] The doping concentration of the first barrier region 132 is set to be greater than the doping concentration of the second barrier region 133, so that the second barrier region 133 has a smaller doping concentration. In this way, the barrier height between the P-type drift region 122 and the second barrier region 133 can be reduced. When the IGBT is turned off, the PNP transistor is easier to conduct, thereby reducing the turn-off loss.

[0066] S30: Figure 7 As shown, a base region layer is epitaxially grown on the upper surface of the N-type layer and doped to form a P-type base region 141, and the P-type base region 141 is located on the first barrier region 132 and the second barrier region 133;

[0067] The P-type base region 141 serves as a P terminal of the PNP transistor.

[0068] S40: Figure 8 and Fig. 9 As shown, an N-type heavily doped region 151 and a P-type heavily doped region 152 are formed on the P-type base region 141, and a gate structure 131 is formed on the other side of the P-type base region 141 layer, and the gate structure 131 extends downward to the N-type drift region 121;

[0069] The N-type heavily doped region 151 and the P-type heavily doped region 152 serve as the emitter 170 of the IGBT. In practical applications, Figure 1 As shown, a metal layer is disposed in the N-type heavily doped region 151 and the P-type heavily doped region 152 as a connection terminal of the emitter 170 .

[0070] Specifically, a trench can be formed by etching downward from the upper surface of the base layer on one side of the N-type drift region 121, and an oxide layer can be formed on the bottom wall and sidewall of the trench as an isolation layer for isolating the gate from other components, and then polysilicon is arranged in the space surrounded by the oxide layer as a connection point of the gate. The trench extends to the N-type drift region 121, so that the gate structure 131 extends into the N-type drift region.

[0071] S50: Fig. 9 As shown, the other side of the N-type substrate is doped to form a P-type substrate 110 .

[0072] The insulated gate bipolar transistor 100 prepared by the method for preparing the insulated gate bipolar transistor 100 provided in the embodiment of the present application can reduce the barrier height between the P-type drift region 122 and the second blocking region 133, making it easier for the PNP transistor to turn on when the IGBT is turned off, thereby reducing the turn-off loss.

[0073] Optionally, an N-type substrate is provided, and P-type dopant ions are implanted from one side of the N-type substrate to form a P-type drift region 122, and a region where the P-type dopant ions are not implanted is an N-type drift region 121, including:

[0074] S11: performing three P-type doping ion implantations from one side of the N-type substrate, the depth of the three implantations gradually decreases, and the concentration of the ion implantations gradually decreases to form a P+ doping region 126, a P doping region 127, and a P- doping region 128, and the projections of the P+ doping region 126, the P doping region 127, and the P- doping region 128 on the substrate 110 overlap;

[0075] Specifically, the thickness of each region is used as the doping region, and different concentrations of doping are performed in each region, so as to form an N+ doping region 123 , an N doping region 124 and an N− doping region 125 in the N-type drift region 121 .

[0076] The doping concentrations of the N+ doping region 123 , the N doping region 124 , and the N− doping region 125 gradually decrease, and they are arranged in a direction away from the substrate 110 , thereby reducing conduction loss.

[0077] S12: N-type doping ion implantation is performed three times from one side of the N-type substrate, the depth of the three times gradually decreases, and the concentration of the ion implantation gradually decreases to form an N+ doping region 123, an N-doping region 124 and an N-doping region 125, and the projections of the N+ doping region 123, the N-doping region 124 and the N-doping region 125 on the substrate 110 overlap.

[0078] Specifically, the thickness of each region is used as the doping region, and different concentrations of doping are performed in each region, so as to form a P+ doping region 126 , a P doping region 127 and a P− doping region 128 in the P-type drift region 122 .

[0079] The doping concentrations of the P+ doping region 126 , the P doping region 127 , and the P− doping region 128 gradually decrease, and they are arranged in a direction away from the substrate 110 , thereby reducing turn-off loss.

[0080] In one achievable manner of the embodiment of the present application, epitaxially growing an N-type layer on the upper surfaces of the P-type drift region 122 and the N-type drift region 121, and forming a first barrier region 132 and a second barrier region 133 on the N-type layer include:

[0081] S21: epitaxially growing an N-type layer on the upper surfaces of the P-type drift region 122 and the N-type drift region 121;

[0082] S22: Implanting ions into the N-type layer on one side of the N-type drift region 121 close to the P-type drift region 122 to form a first blocking region 132;

[0083] S23 : implanting ions into a portion of the N-type layer on the P-type drift region 122 to form a second barrier region 133 . The first barrier region 132 and the second barrier region 133 are arranged in close contact with each other, and the doping concentration of the first barrier region 132 is greater than the doping concentration of the second barrier region 133 .

[0084] In order to further verify the beneficial effects of the present application, the insulated gate bipolar transistor 100 of the embodiment of the present application and the insulated gate bipolar transistor 100 of the prior art are tested. Specifically, the second barrier region 133 has a doping concentration less than that of the first barrier region 132 as the second embodiment; the second barrier layer is an oxide as the first embodiment; and the comparative example without the second barrier layer is used as an example for comparison. Table 1 shows the static characteristics and reverse recovery related parameters of the three structures. Table 1 is as follows:

[0085] Table 1 Static characteristics and reverse recovery related parameters of three structures

[0086]

[0087] The present application also tests the output characteristics and transfer characteristics of the three structures. The results are as follows: Fig.10 and Fig.11 As shown, Fig.10 is the output characteristic curve, Fig.11 is the transfer characteristic curve, from Table 1, Fig.10 as well as Fig.11 It can be seen that the static parameters of the three structures are basically unchanged. The switching loss in the embodiment of the present application is low and the breakdown voltage is high. Therefore, the embodiment of the present application can improve the turn-off loss and increase the breakdown voltage, thereby improving the performance of the IGBT. In addition, to further verify the breakdown voltage of each structure, the present application tests each structure, and the results are as follows Fig.12 As shown by Fig.12 It can be seen that the embodiment of the present application has a larger breakdown voltage. Specifically, due to the provision of the second barrier region 133, the collision ionization rate of the IGBT changes, thereby making the electric field distribution inside the device more uniform, thereby improving the breakdown voltage of the device.

[0088] In order to study the influence of the position of the second barrier region 133 on the performance of the IGBT, the embodiment of the present application tests the positions of the second barrier regions 133 of three structures with different parameters for each structure, wherein the distance between the second barrier region 133 and the P-type drift region 122 is positive in the direction away from the substrate 110, as shown in Table 2:

[0089] Table 2. Related parameters of the positions of the second blocking areas of three different structures

[0090]

[0091] in, Fig.13 is the reverse recovery characteristic curve of each IGBT, Fig.14 is the conduction curve of each IGBT, Fig.15 is the turn-off curve of each IGBT. Fig.13 , Fig.14 as well as Fig.15 It can be seen that the position of the second blocking region 133 does not affect the turn-on time, but only increases the turn-on loss; for the turn-off loss, when the second blocking region 133 is located above the P-type drift region 122, the turn-off speed will be accelerated; when the second blocking region 133 extends into the P-type drift region 122, the turn-off speed will be reduced. On the whole, when the second blocking region 133 is located above the P-type drift region 122 and connected to the P-type offset region, the switching loss is the lowest and the switching time is moderate. Therefore, the second blocking region 133 of the embodiment of the present application is arranged above the P-type drift region 122.

[0092] In order to study the influence of the doping concentration of the second barrier region 133, the embodiment of the present application tests the performance of the IGBT with different doping concentrations in the second barrier region 133, wherein the specific doping concentrations are shown in Table 3:

[0093] Table 3 Loss parameters of different doping concentrations

[0094]

[0095] in, Fig.16 is the conduction curve of different doping concentrations, Fig.17 is the turn-off curve of different doping concentrations. Figure 6 as well as Fig.17 It can be seen that the higher the doping concentration of the second blocking region 133, the lower the conduction loss and the higher the turn-off loss. When the doping concentration is too high, the device is turned off and holes are difficult to extract. When the concentration is too low, it is difficult to block the outflow of holes during conduction, which increases the turn-on loss of the device. As the doping concentration increases, the impact on the turn-on time is small, but the turn-on loss will increase to a certain extent. The impact on the turn-off time is greater. The higher the doping, the longer the turn-off time.

[0096] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An insulated gate bipolar transistor, characterized in that: include: A substrate and a drift layer arranged on the substrate, wherein the drift layer comprises an N-type drift region and a P-type drift region which are arranged in close contact with each other, the upper surface of the N-type drift region is flush with the upper surface of the P-type drift region, a gate structure and an N-type doped first barrier region are formed on the upper surface of the N-type drift region, an N-type doped second barrier region is arranged on the P-type drift region, the first barrier region and the second barrier region are arranged in close contact with each other, and the N-type doping concentration of the first barrier region is greater than the N-type doping concentration of the second barrier region, a P-type base region is arranged on the first barrier region and the second barrier region, and an N-type heavily doped region and a P-type heavily doped region are arranged on the P-type base region; wherein the first barrier region is used to block holes from flowing to the P-type base region when the insulated gate bipolar transistor is turned on, and the second barrier region is used to reduce the barrier height between the P-type drift region and the second barrier region when the insulated gate bipolar transistor is turned off.

2. The insulated gate bipolar transistor according to claim 1, wherein: The doping concentration of the N-type drift region gradually decreases in a direction away from the substrate.

3. The insulated gate bipolar transistor according to claim 1, wherein: The doping concentration of the P-type drift region gradually decreases in a direction away from the substrate.

4. The insulated gate bipolar transistor according to claim 1, wherein: The N-type drift region includes an N+ doping region, an N doping region and an N- doping region which are sequentially arranged in a direction away from the substrate.

5. The insulated gate bipolar transistor according to claim 4, characterized in that: The doping concentration of the N-doped region is 1e 14 / cm 3 -1e 16 / cm 3 The doping concentration of the N+ doping region is 1-1.2 times the doping concentration of the N doping region, and the doping concentration of the N- doping region is 0.8-1 times the doping concentration of the N doping region.

6. The insulated gate bipolar transistor according to claim 1, wherein: The P-type drift region includes a P+ doping region, a P doping region and a P- doping region which are sequentially arranged in a direction away from the substrate.

7. The insulated gate bipolar transistor according to claim 6, characterized in that: The doping concentration of the P doping region is 1e 14 / cm 3 -1e 16 / cm 3 The doping concentration of the P+ doping region is 1-1.2 times the doping concentration of the P doping region, and the doping concentration of the P- doping region is 0.8-1 times the doping concentration of the P doping region.

8. The insulated gate bipolar transistor according to claim 1, wherein: Along the direction away from the substrate, the cross section of the P-type drift region gradually decreases.

9. A method for preparing an insulated gate bipolar transistor, characterized in that: For preparing the insulated gate bipolar transistor according to any one of claims 1 to 8, comprising: Providing an N-type substrate, and performing P-type doping ion implantation on one side of the N-type substrate to form a P-type drift region, and a region where the P-type doping ion implantation is not performed is an N-type drift region; Epitaxially growing an N-type layer on the upper surfaces of the P-type drift region and the N-type drift region, and forming a first barrier region and a second barrier region on the N-type layer, wherein the first barrier region is located on the N-type drift region, and the second barrier region is located on the P-type drift region, the first barrier region and the second barrier region are arranged in contact with each other, and the doping concentration of the first barrier region is greater than the doping concentration of the second barrier region; Epitaxially growing a base region layer on the upper surface of the N-type layer and doping to form a P-type base region, wherein the P-type base region is located on the first barrier region and the second barrier region; Forming an N-type heavily doped region and a P-type heavily doped region on the P-type base region, and forming a gate structure on the other side of the P-type base region layer, wherein the gate structure extends downward to the N-type drift region; The other side of the N-type substrate is doped to form a P-type substrate.

10. The method for preparing an insulated gate bipolar transistor according to claim 9, characterized in that: The method comprises providing an N-type substrate, and performing P-type doping ion implantation on one side of the N-type substrate to form a P-type drift region, wherein the region where the P-type doping ion implantation is not performed is the N-type drift region, and comprising: Performing three P-type doping ion implantations from one side of the N-type substrate, with the depth of the three implantations gradually decreasing and the concentration of the ions gradually decreasing to form a P+ doping region, a P doping region and a P- doping region, wherein the projections of the P+ doping region, the P doping region and the P- doping region on the substrate overlap; N-type doping ion implantation is performed three times from one side of the N-type matrix, the depth of the three times gradually decreases, and the concentration of the ion implantation gradually decreases to form an N+ doping area, an N doping area and an N- doping area, and the projections of the N+ doping area, the N doping area and the N- doping area on the substrate overlap.

11. The method for preparing an insulated gate bipolar transistor according to claim 9, characterized in that: The step of epitaxially growing an N-type layer on the upper surfaces of the P-type drift region and the N-type drift region, and forming a first barrier region and a second barrier region on the N-type layer comprises: Epitaxially growing an N-type layer on upper surfaces of the P-type drift region and the N-type drift region; Implanting ions into a side of the N-type layer located on the N-type drift region and close to the P-type drift region to form a first blocking region; A second barrier region is formed by implanting ions into a portion of the N-type layer located on the P-type drift region. The first barrier region and the second barrier region are arranged in close contact with each other, and the doping concentration of the first barrier region is greater than the doping concentration of the second barrier region.

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