Lateral diffused metal oxide semiconductor device and method of making same

Abstract

The application provides a lateral diffusion metal oxide semiconductor device and a manufacturing method thereof. The method comprises the following steps: forming a gate material layer and a silicon nitride mask layer on a substrate; etching the gate material layer to form a gate by taking the silicon nitride mask layer as a mask; forming a patterned photoresist layer with a first opening; performing high-energy ion implantation by taking the patterned photoresist layer and the silicon nitride mask layer as masks to form a first body region; trimming the patterned photoresist layer to form a second opening; performing low-energy ion implantation by taking the patterned photoresist layer and the silicon nitride mask layer as masks to form a second body region; and removing the patterned photoresist layer and the silicon nitride mask layer. After the gate is formed by taking the silicon nitride mask layer as a mask, the silicon nitride mask layer is not removed, but ion implantation is performed by taking the patterned photoresist layer and the silicon nitride mask layer as masks, so that the ions can not directly penetrate the patterned photoresist layer into the gate during high-energy ion implantation, and the resistance of the gate is not affected.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing technology, and particularly relates to a laterally diffused metal oxide semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] Laterally diffused metal oxide semiconductor (LDMOS) is a kind of high-voltage and high-power semiconductor device, which is widely used in power integrated circuit. LDMOS has the characteristics of high-voltage and high-current of high-isolation device, and also has the advantages of high-density intelligent logic control of low-voltage integrated circuit. Single chip can realize the functions that originally can be completed by multiple chips, which greatly reduces the area, reduces the cost, improves the energy efficiency, and meets the development direction of modern power electronic devices such as miniaturization, intelligence and low energy consumption.

[0003] LDMOS is usually laid out as a very wide strip, which is alternately formed by strip source regions and strip drain regions. There are heavily doped N+ and P+ regions in the strip source regions to contact the source regions and the body regions, respectively. There is a P-type shallow body region below the N+ and P+ regions, and the lateral diffusion of the P-type shallow body region below the polysilicon gate determines the channel of the LDMOS. The ion implantation for forming the shallow body region is very shallow, so that the polysilicon gate can form an effective ion implantation barrier, which means that the shallow body region can be self-aligned with the edge of the polysilicon gate.

[0004] In addition, a P-type deep body region is also needed in the strip source region to increase the curvature radius of the PN junction between the body region and the drain region, and to reduce the resistance value of the body region below the N+ source region, thereby preventing the device from being damaged due to the conduction of the parasitic NPN transistor under high drain voltage.

[0005] However, the ion implantation for forming the deep body region must have a projection range of up to 0.5 μm, while the thickness of the polysilicon gate of the LDMOS is usually 0.1 μm to 0.3 μm, which is not enough to block the deep body region ion implantation. Therefore, the deep body region must be realized by a special photolithography step using a photoresist layer with a thickness of at least 0.8 μm. However, the photoresist layer cannot completely block the ion implantation into the polysilicon gate, thereby affecting the resistance of the polysilicon gate and ultimately affecting the performance of the device. SUMMARY

[0006] The present application aims to provide a laterally diffused metal oxide semiconductor device and a manufacturing method thereof, which can avoid the ions directly penetrating the photoresist layer into the gate during high-energy ion implantation, and avoid the ion implantation affecting the resistance of the gate, thereby improving the performance of the device.

[0007] To solve the above technical problems, the application provides a manufacturing method of a lateral diffusion metal oxide semiconductor device, comprising the following steps:

[0008] A substrate is provided, and a gate material layer and a silicon nitride mask layer are sequentially formed on the substrate;

[0009] The gate material layer is etched with the silicon nitride mask layer as a mask to form a gate;

[0010] A patterned photoresist layer is formed, which covers the surface of the substrate, the sidewall of the gate, and the sidewall and top of the silicon nitride mask layer, and has a first opening exposing part of the substrate between adjacent gates;

[0011] High-energy ion implantation is performed through the first opening with the patterned photoresist layer and the silicon nitride mask layer as masks to form a first body region in the substrate between adjacent gates;

[0012] Part of the patterned photoresist layer on both sides of the first opening is trimmed to form a second opening exposing at least the sidewall of the gate;

[0013] Low-energy ion implantation is performed through the second opening with the patterned photoresist layer and the silicon nitride mask layer as masks to form a second body region in the substrate between adjacent gates; and

[0014] The patterned photoresist layer and the silicon nitride mask layer are removed.

[0015] Optionally, the thickness of the silicon nitride mask layer is greater than or equal to 200 nm and less than or equal to 400 nm.

[0016] Optionally, before the gate material layer is formed on the substrate, the method further comprises forming a gate oxide layer on the substrate.

[0017] Optionally, the thickness of the gate oxide layer is greater than or equal to 11 nm and less than or equal to 15 nm, and the thickness of the gate material layer is greater than or equal to 100 nm and less than or equal to 300 nm.

[0018] Optionally, the method for forming the silicon nitride mask layer comprises:

[0019] A silicon nitride material layer is formed on the gate material layer;

[0020] A photoresist layer is formed on the silicon nitride material layer, and the photoresist layer is exposed and developed to form a patterned photoresist layer;

[0021] The silicon nitride material layer is etched with the patterned photoresist layer as a mask to expose the gate material layer; and

[0022] removing the patterned photoresist layer.

[0023] Optionally, the ion dosage of the high-energy ion implantation is less than the ion dosage of the low-energy ion implantation.

[0024] Optionally, the lower surface of the first body region is lower than the lower surface of the second body region.

[0025] Optionally, after the low-energy ion implantation, the manufacturing method further comprises: performing a thermal annealing activation treatment.

[0026] Optionally, after the removal of the patterned photoresist layer and the silicon nitride mask layer, the manufacturing method further comprises: forming a side wall on the gate sidewall.

[0027] Correspondingly, the present application also provides a lateral diffusion metal oxide semiconductor device manufactured by the manufacturing method of the lateral diffusion metal oxide semiconductor device.

[0028] In summary, the lateral diffusion metal oxide semiconductor device and the manufacturing method thereof provided by the present application first provide a substrate, then form a gate material layer and a silicon nitride mask layer on the substrate in sequence, etch the gate material layer to form a gate by taking the silicon nitride mask layer as a mask, then form a patterned photoresist layer covering the surface of the substrate, the sidewall of the gate, and the sidewall and top of the silicon nitride mask layer, and having a first opening exposing part of the substrate between adjacent gates, then perform high-energy ion implantation through the first opening by taking the patterned photoresist layer and the silicon nitride mask layer as masks to form a first body region in the substrate between adjacent gates, then trim part of the patterned photoresist layer on both sides of the first opening to form a second opening exposing at least the sidewall of the gate, then perform low-energy ion implantation through the second opening by taking the patterned photoresist layer and the silicon nitride mask layer as masks to form a second body region in the substrate between adjacent gates, and finally remove the patterned photoresist layer and the silicon nitride mask layer. In the present application, the gate material layer is etched to form a gate by taking the silicon nitride mask layer as a mask, and after the formation of the gate, the silicon nitride mask layer is not removed, but ion implantation is performed by taking the patterned photoresist layer and the silicon nitride mask layer as masks, which can avoid the direct penetration of ions into the gate through the patterned photoresist layer during high-energy ion implantation, that is, the existence of the silicon nitride mask layer can avoid ion implantation into the gate, thereby avoiding the influence on the resistance of the gate, and thus improving the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1is a flow chart of a method for manufacturing a lateral diffusion metal oxide semiconductor device according to an embodiment of the present application.

[0030] Figure 2 is a schematic diagram of a structure after forming a silicon nitride material layer according to an embodiment of the present application.

[0031] Figure 3 is a schematic diagram of a structure after forming a silicon nitride mask layer according to an embodiment of the present application.

[0032] Figure 4 is a schematic diagram of a structure after forming a gate according to an embodiment of the present application.

[0033] Figure 5 is a schematic diagram of a structure after forming a first body region according to an embodiment of the present application.

[0034] Figure 6 is a schematic diagram of a structure after forming a second body region according to an embodiment of the present application.

[0035] Figure 7 is a schematic diagram of a structure after removing a silicon nitride mask layer according to an embodiment of the present application.

[0036] BRIEF DESCRIPTION OF DRAWINGS

[0037] 10 - substrate; 11 - gate oxide layer; 12 - gate material layer; 13 - silicon nitride material layer; 14 - silicon nitride mask layer; 15 - gate; 16 - patterned photoresist layer; 171 - first opening; 172 - second opening; 181 - first body region; 182 - second body region. DETAILED DESCRIPTION

[0038] In order to make the objects, advantages and features of the present application clearer, the following further describes the present application in detail with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are very simplified and not drawn according to scale, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application. In addition, the structures shown in the drawings are often a part of the actual structures. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0039] As used in the present application, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. As used in the present application, the term "or" is generally employed in its sense of "and / or" unless the content clearly dictates otherwise. As used in the present application, the term "plurality" is generally employed in its sense of "at least one" unless the content clearly dictates otherwise. As used in the present application, the term "at least two" is generally employed in its sense of "two or more" unless the content clearly dictates otherwise. In addition, the terms "first," "second," "third," are used merely for descriptive purposes and are not necessarily intended to signify relative importance or a quantity of the specified technical features. Thus, features defined with "first," "second," "third" can explicitly or implicitly include one or at least two of the features.

[0040] Figure 1 is a flow chart of a method for manufacturing a lateral diffusion metal oxide semiconductor device according to an embodiment of the present application. As shown in Figure 1 the method for manufacturing a lateral diffusion metal oxide semiconductor device includes the following steps:

[0041] S1: providing a substrate, and sequentially forming a gate material layer and a silicon nitride mask layer on the substrate;

[0042] S2: etching the gate material layer to form a gate electrode with the silicon nitride mask layer as a mask;

[0043] S3: forming a patterned photoresist layer, the patterned photoresist layer covering the surface of the substrate, the sidewall of the gate electrode, and the sidewall and top of the silicon nitride mask layer, and having a first opening exposing a portion of the substrate between adjacent gate electrodes;

[0044] S4: performing high-energy ion implantation through the first opening with the patterned photoresist layer and the silicon nitride mask layer as masks to form a first body region in the substrate between adjacent gate electrodes;

[0045] S5: trimming a portion of the patterned photoresist layer on both sides of the first opening to form a second opening exposing at least the sidewall of the gate electrode;

[0046] S6: performing low-energy ion implantation through the second opening with the patterned photoresist layer and the silicon nitride mask layer as masks to form a second body region in the substrate between adjacent gate electrodes; and

[0047] S7: removing the patterned photoresist layer and the silicon nitride mask layer.

[0048] Figures 2 to 7This is a schematic diagram illustrating the steps of a method for fabricating a laterally diffused metal-oxide-semiconductor device according to an embodiment of the present invention. Next, we will combine... Figure 1 and Figures 2 to 7 The fabrication method of the laterally diffused metal-oxide-semiconductor device provided in the embodiments of the present invention will be described in detail.

[0049] In step S1, please refer to Figure 3 As shown, a substrate 10 is provided, on which a gate material layer 12 and a silicon nitride mask layer 14 are sequentially formed.

[0050] The substrate 10 can be made of silicon, germanium, germanium-silicon, silicon carbide, gallium arsenide, or indium gallium arsenide, or it can be silicon-on-insulator or germanium-on-insulator; or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 10 is made of silicon.

[0051] In one embodiment of the present invention, please refer to Figure 2 As shown, before forming the gate material layer 12, a gate oxide layer 11 is formed on the substrate 10. Exemplarily, the gate oxide layer 11 is made of silicon oxide and can be formed using a thermal oxidation process, or using physical vapor deposition, chemical vapor deposition, atomic layer deposition, or a combination thereof.

[0052] Next, please continue to refer to... Figure 2 As shown, a gate material layer 12 is formed on the gate oxide layer 11, and the gate material layer 12 covers the gate oxide layer 11. The gate material layer 12 is, for example, polycrystalline silicon, and can be formed using methods known to those skilled in the art, such as pyrolysis, chemical vapor deposition, and silicon decomposition compound methods. For example, the pyrolysis method utilizes the chemical reaction of silicon gas and hydrogen gas to generate polycrystalline silicon, which has advantages such as simple preparation process and low cost; the chemical vapor deposition method utilizes silicon source gas, dopant gas, and dilution gas to generate polycrystalline silicon through a chemical reaction, which has advantages such as high purity, good uniformity, and porous film; the silicon decomposition compound method generates polycrystalline silicon through a solid-phase reaction in the presence of easily decomposable silicon compounds (such as silicon trichloride, silane, etc.), which has advantages such as simple preparation process and high purity; the specific fabrication method can be determined according to the specific requirements of the gate material layer 12.

[0053] Next, please continue to refer to... Figure 2As shown in the figure, a silicon nitride material layer 13 is formed on the gate material layer 12, and the silicon nitride material layer 13 covers the gate material layer 12. The silicon nitride material layer 13 is a silicon nitride layer, and is named as a silicon nitride material layer here for distinguishing from a subsequent silicon nitride mask layer. For example, the silicon nitride material layer 13 can be formed by a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process or a combination thereof.

[0054] Then, a photoresist layer (not shown) is formed on the silicon nitride material layer 13, the photoresist layer is exposed and developed to form a patterned photoresist layer, and then the silicon nitride material layer 13 is etched to expose the gate material layer 12 by using the patterned photoresist layer as a mask to form a silicon nitride mask layer 14, and the silicon nitride mask layer 14 exposes the gate material layer 12 which needs to be removed. For example, the silicon nitride material layer 13 can be etched by a wet etching method or a dry etching method. For example, the wet etching method can use hot phosphoric acid, and the dry etching method can use CF4 gas mixed with O2 and N2, but is not limited thereto.

[0055] That is, the silicon nitride material layer 13 is etched to form a silicon nitride mask layer 14, and the silicon nitride mask layer 14 is used as a mask layer for etching the gate material layer 12 to form a gate. Of course, after the silicon nitride mask layer 14 is formed, the patterned photoresist layer is removed. For example, the patterned photoresist layer can be removed by an ashing process or a wet etching process. Finally, a structure as shown in the figure is formed. Figure 3

[0056] In an embodiment of the present application, the thickness of the gate oxide layer 11 is greater than or equal to 11 nm and less than or equal to 15 nm, but is not limited thereto. The thickness of the gate oxide layer 11 can be determined according to actual requirements of a device. For example, the thickness of the gate oxide layer 11 is 11 nm, 13 nm or 15 nm, and preferably, the thickness of the gate oxide layer 11 is 13 nm.

[0057] The thickness of the gate material layer 12 is greater than or equal to 100 nm and less than or equal to 300 nm, and the thickness of the gate material layer 12 determines the thickness of a subsequently formed gate. The thickness of the gate material layer 12 is not limited thereto, and can be determined according to actual requirements of a device. For example, the thickness of the gate material layer 12 is 100 nm, 150 nm, 200 nm, 250 nm or 300 nm, and preferably, the thickness of the gate material layer 12 is 200 nm.

[0058] ​The thickness of the silicon nitride mask layer 14 is greater than or equal to 200 nm and less than or equal to 400 nm, for example, the thickness of the silicon nitride mask layer 14 is 200 nm, 250 nm, 300 nm, 350 nm or 400 nm, preferably, the thickness of the silicon nitride mask layer 14 is 300 nm. The silicon nitride mask layer 14 not only serves as a mask layer for etching the gate material layer 12, but also serves as a mask layer for subsequent high-energy ion implantation, and its thickness can be determined according to actual needs. For example, the thickness of the silicon nitride mask layer 14 cannot be too thin, and the thickness needs to ensure that high-energy ions cannot penetrate the silicon nitride mask layer 14 to protect the gate from ion intrusion, while the silicon nitride mask layer 14 cannot be too thick, which not only causes waste of materials, but also increases the difficulty of removal. Therefore, a suitable thickness can be selected according to actual conditions.

[0059] In step S2, please refer to Figure 4 The gate material layer 12 is etched with the silicon nitride mask layer 14 as a mask to form a gate 15.

[0060] For example, the gate material layer 12 can be etched by dry etching or wet etching. Dry etching mainly uses active particles in plasma to physically bombard and chemically react with polysilicon to remove the material. Wet etching uses chemical reaction to remove polysilicon material, usually using etching liquid, such as HNO3-HF etching liquid, whose etching principle involves the chemical reaction of oxidizing agent (such as HNO3) and complexing agent (such as HF) to form soluble SiO2, thereby achieving etching of polysilicon.

[0061] In this embodiment, the gate material layer 12 is etched with the silicon nitride mask layer 14 as a mask to expose the gate oxide layer 11, thereby forming the gate 15. For example, the etching of the gate material layer 12 can also include end point detection, which compensates for the changes in etching rate caused by fluctuations in material composition and thickness or changes in working parameters through direct macroscopic detection of the etching layer, light waves emitted from the etching layer, concentration of plasma etchant ions, etc. to compensate for process control and process judgment.

[0062] In step S3, please refer to Figure 5 A patterned photoresist layer 16 is formed, which covers the surface of the substrate 10, the sidewall of the gate 15 and the sidewall and top of the silicon nitride mask layer 14, and has a first opening 171 exposing part of the substrate 10 between adjacent gates 15.

[0063] For example, first, a photoresist layer is formed, which covers the substrate 10, the sidewalls of the gate 15, and the sidewalls and top of the silicon nitride mask layer 14, i.e. the photoresist layer covers the components on the entire surface of the substrate 10 and has a relatively thick thickness. Then, the photoresist layer is exposed and developed to form a first opening 171 exposing a portion of the substrate 10 between adjacent gates 15. The first opening 171 only exposes the substrate 10 between adjacent gates 15, and the patterned photoresist layer 16 covers the sidewalls of the gate 15.

[0064] In an embodiment of the present application, the distance of the first opening 171 from the two adjacent gates 15 can be equal, i.e. the thickness of the photoresist layer between the first opening 171 and the two adjacent gates 15 is consistent. Of course, in another embodiment of the present application, the distance of the first opening 171 from the two adjacent gates 15 can also be unequal, for example, the first opening 171 is close to the left gate 15 in the middle, or the first opening 171 is close to the right gate 15 in the middle, which is not limited in the present application and can be determined according to the required position of the first body region formed through the first opening 171. For example, if the first body region needs to be located in the middle area between the adjacent gates 15, i.e. the distance to the two adjacent gates 15 is the same, then the distance of the first opening 171 from the two adjacent gates 15 is equal, and if the first body region needs to be close to the left gate 15, then the first opening 171 is close to the left gate 15. Figure 5 In an embodiment of the present application, the distance of the first opening 171 from the two adjacent gates 15 can be equal, i.e. the thickness of the photoresist layer between the first opening 171 and the two adjacent gates 15 is consistent. Of course, in another embodiment of the present application, the distance of the first opening 171 from the two adjacent gates 15 can also be unequal, for example, the first opening 171 is close to the left gate 15 in the middle, or the first opening 171 is close to the right gate 15 in the middle, which is not limited in the present application and can be determined according to the required position of the first body region formed through the first opening 171. For example, if the first body region needs to be located in the middle area between the adjacent gates 15, i.e. the distance to the two adjacent gates 15 is the same, then the distance of the first opening 171 from the two adjacent gates 15 is equal, and if the first body region needs to be close to the left gate 15, then the first opening 171 is close to the left gate 15. Figure 5 In an embodiment of the present application, the distance of the first opening 171 from the two adjacent gates 15 can be equal, i.e. the thickness of the photoresist layer between the first opening 171 and the two adjacent gates 15 is consistent. Of course, in another embodiment of the present application, the distance of the first opening 171 from the two adjacent gates 15 can also be unequal, for example, the first opening 171 is close to the left gate 15 in the middle, or the first opening 171 is close to the right gate 15 in the middle, which is not limited in the present application and can be determined according to the required position of the first body region formed through the first opening 171. For example, if the first body region needs to be located in the middle area between the adjacent gates 15, i.e. the distance to the two adjacent gates 15 is the same, then the distance of the first opening 171 from the two adjacent gates 15 is equal, and if the first body region needs to be close to the left gate 15, then the first opening 171 is close to the left gate 15.

[0065] In the present embodiment, after the formation of the gate 15, the silicon nitride mask layer 14 is not removed, and the patterned photoresist layer 16 is directly formed on the silicon nitride mask layer 14. When high-energy ion implantation is subsequently performed, ion implantation is performed with the patterned photoresist layer 16 as a mask, and the silicon nitride mask layer 14 can also act as a mask layer, which can avoid high-energy ions penetrating the patterned photoresist layer 16 into the gate 15 and being implanted into the gate 15, thereby avoiding the impact of high-energy ion implantation on the gate 15.

[0066] In step S4, please continue to refer to Figure 5 The first body region 181 is formed in the substrate 10 between the adjacent gates 15 by high-energy ion implantation through the first opening 171 with the patterned photoresist layer 16 and the silicon nitride mask layer 14 as masks.

[0067] In this embodiment, high-energy ion implantation is performed using the patterned photoresist layer 16 as a mask. The high-energy ion implantation enters the substrate 10 from the first opening 171 and forms a first body region 181 in the substrate 10. During the ion implantation, the high-energy ions can penetrate the patterned photoresist layer 16, but cannot penetrate the silicon nitride mask layer 14 to implant into the gate 15 due to the presence of the silicon nitride mask layer 14. Therefore, the ion implantation is masked by the patterned photoresist layer 16 and the silicon nitride mask layer 14. The silicon nitride mask layer 14 serves as a protective layer for the gate 15 to protect the gate 15 from the ion implantation.

[0068] In one embodiment of the present application, the high-energy ion implantation includes boron ions. For example, the high-energy ion implantation can be divided into two ion implantations. The first ion implantation has an energy of 300 Kev and a dose of 2 x 1013 atoms / cm2. The second ion implantation has an energy of 100 Kev and a dose of 2.3 x 1013 atoms / cm2. Of course, the present application is not limited to this example. 13 atom / cm 2 13 atom / cm 2 The high-energy ion implantation is a high-energy low-dose ion implantation (where the low dose is relative to a low-energy ion implantation).

[0069] In step S5, as shown in FIG. 5, the patterned photoresist layer 16 on both sides of the first opening 171 is trimmed to form a second opening 172 that exposes at least the sidewall of the gate 15. Figure 5 Figure 6

[0070] In this embodiment, the trimming of the patterned photoresist layer 16 on both sides of the first opening 171 includes removing the patterned photoresist layer 16 on both sides of the first opening 171, i.e., the first opening 171 is enlarged to form the second opening 172. The cross-sectional size of the second opening 172 is larger than that of the first opening 171.

[0071] The second opening 172 exposes at least the sidewall of the gate 15. In one embodiment of the present application, the second opening 172 just exposes the sidewall of the gate 15, i.e., the sidewall of the second opening 172 coincides with the sidewall of the gate 15, or the sidewall of the patterned photoresist layer 16 is flush with the sidewall of the gate 15. In another embodiment of the present application, the second opening 172 exposes not only the sidewall of the gate 15 but also a portion of the top of the gate 15 (as shown in FIG. 6). Figure 6

[0072] ​​​​For example, the photoresist layer trimming step employs an isotropic plasma etching process. The photoresist layer trimming step includes etching the patterned photoresist layer 16 with an oxygen-containing plasma to expose the sidewalls of the gate 15 or to expose the sidewalls of the gate 15 and a portion of the top of the gate 15. In one embodiment, the photoresist layer trimming step employs O2 gas at a flow rate of 50-250 seem, a radio frequency power of 300-800 W, a bias power of 0-10 W, and a chamber pressure of 5-50 mtorr to accurately trim the width of the photoresist layer and to accurately expose the corresponding second opening 172.

[0073] In step S6, please continue to refer to Figure 6 The patterned photoresist layer 16 and the silicon nitride mask layer 14 are used as masks to perform low-energy ion implantation through the second opening 172 to form a second body region 182 in the substrate 10 between the adjacent gates 15.

[0074] In this embodiment, the patterned photoresist layer 16 and the silicon nitride mask layer 14 are used as masks to perform low-energy ion implantation. Since the cross-sectional dimension of the second opening 172 is greater than or equal to the dimension between the adjacent gates 15, the low-energy ion implantation is performed between the adjacent gates 15 to form the second body region 182.

[0075] In one embodiment of the present application, the ion dose of the high-energy ion implantation is less than the ion dose of the low-energy ion implantation. The lower surface 181a of the first body region 181 is lower than the lower surface 182a of the second body region 182. That is, the first body region 181 corresponds to a deep body region, and the second body region 182 corresponds to a shallow body region. In the horizontal direction of the substrate 10, Figure 6 the cross-sectional dimension W1 of the first body region 181 is less than the cross-sectional dimension W2 of the second body region 182, and in the vertical direction of the substrate 10, Figure 6 the cross-sectional dimension of the first body region 181 is greater than the cross-sectional dimension of the second body region 182.

[0076] For example, the low-energy ion implantation is divided into two ion implantations. In the first ion implantation, boron-containing ions are implanted at an energy of, for example, 30 Kev and a dose of, for example, 8.5 x 1013 atom / cm2. 13 2 In the second ion implantation, arsenic-containing ions are implanted at an energy of, for example, 15 Kev and a dose of, for example, 5 x 1013 atom / cm2. 14 2 ​​, of course, not limited to this. The present low energy ion implantation is a low energy high dose (wherein the high dose is relative to high energy ion implantation).

[0077] In one embodiment of the present application, after the low energy ion implantation, the manufacturing method further comprises: performing a thermal annealing activation process to activate the ions in the first body region 181 and / or the second body region 182.

[0078] In step S6, as shown in Figure 7 The patterned photoresist layer 16 and the silicon nitride mask layer 14 are removed.

[0079] In one embodiment of the present application, the patterned photoresist layer 16 is removed first, for example, the patterned photoresist layer 16 can be removed by using a gray ash process or a wet etching process. Then, the silicon nitride mask layer 14 is removed, which can be removed by using a wet etching process or a dry etching process.

[0080] In another embodiment of the present application, the patterned photoresist layer 16 and the silicon nitride mask layer 14 can be removed in the same process step, for example, the patterned photoresist layer 16 can be removed by using a wet etching process, and then the silicon nitride mask layer 14 is continuously removed.

[0081] After the patterned photoresist layer 16 and the silicon nitride mask layer 14 are removed, a side wall is formed on the side wall of the gate 15. Subsequently, a conventional process of re-doped ion implantation and annealing activation to form source / drain contact regions, body region contact regions, and contact holes and front metal is included, which is the same as the existing process and will not be described again.

[0082] The application provides a manufacturing method of a lateral diffusion metal oxide semiconductor device. The method comprises the following steps: providing a substrate 10; forming a gate material layer 12 and a silicon nitride mask layer 14 on the substrate 10; etching the gate material layer 12 to form a gate 15 by taking the silicon nitride mask layer 14 as a mask; forming a patterned photoresist layer 16, wherein the patterned photoresist layer 16 covers the surface of the substrate 10, the sidewall of the gate 15 and the sidewall and top of the silicon nitride mask layer 14, and has a first opening 171 exposing a part of the substrate 10 between adjacent gates 15; performing high-energy ion implantation through the first opening 171 by taking the patterned photoresist layer 16 and the silicon nitride mask layer 14 as masks to form a first body region 181 in the substrate 10 between adjacent gates 15; trimming a part of the patterned photoresist layer 16 on both sides of the first opening 171 to form a second opening 172 exposing at least the sidewall of the gate 15; performing low-energy ion implantation through the second opening 172 by taking the patterned photoresist layer 16 and the silicon nitride mask layer 14 as masks to form a second body region 182 in the substrate 10 between adjacent gates 15; and removing the patterned photoresist layer 16 and the silicon nitride mask layer 14. The silicon nitride mask layer 14 is taken as a mask to etch the gate material layer 12 to form the gate 15, and the silicon nitride mask layer 14 is not removed after the gate 15 is formed, but is taken as a mask to perform ion implantation together with the patterned photoresist layer 16, so that the ion implantation can not directly penetrate the patterned photoresist layer 16 to enter the gate 15, that is, the silicon nitride mask layer 14 can prevent the ion implantation into the gate 15, thereby avoiding affecting the resistance of the gate 15, and improving the performance of the device.

[0083] Correspondingly, the application further provides a lateral diffusion metal oxide semiconductor device manufactured by the manufacturing method of the lateral diffusion metal oxide semiconductor device. Figure 7 As shown in the drawings, the lateral diffusion metal oxide semiconductor device comprises:

[0084] a substrate 10;

[0085] a gate 15 on the substrate 10;

[0086] a first body region 181 and a second body region 182 in the substrate 10 between adjacent gates 15, and the cross-sectional dimension W2 of the second body region 182 is greater than the cross-sectional dimension W1 of the first body region 181 (wherein the cross-sectional dimension refers to the cross-sectional dimension in the horizontal direction). Figure 7

[0087] ​In one embodiment of the present application, a gate oxide layer 11 is formed between the substrate 10 and the gate 15, and the gate oxide layer 11 covers the substrate 10. The material of the gate oxide layer 11 is, for example, silicon oxide.

[0088] In one embodiment of the present application, the lower surface of the first body region 181 is lower than the lower surface of the second body region 182. That is, in the direction perpendicular to the substrate 10 (vertical direction), the cross-sectional size of the first body region 181 is larger than the cross-sectional size of the second body region 182. Figure 7

[0089] In summary, the lateral diffusion metal oxide semiconductor device and the manufacturing method thereof provided by the present application first provide a substrate, and then form a gate material layer and a silicon nitride mask layer on the substrate in sequence. The gate material layer is etched with the silicon nitride mask layer as a mask to form a gate. Then, a patterned photoresist layer is formed, which covers the surface of the substrate, the sidewall of the gate, and the sidewall and top of the silicon nitride mask layer, and has a first opening exposing part of the substrate between adjacent gates. Then, high-energy ion implantation is performed through the first opening with the patterned photoresist layer and the silicon nitride mask layer as masks to form a first body region in the substrate between adjacent gates. Then, part of the patterned photoresist layer on both sides of the first opening is trimmed to form a second opening exposing at least the sidewall of the gate. Then, low-energy ion implantation is performed through the second opening with the patterned photoresist layer and the silicon nitride mask layer as masks to form a second body region in the substrate between adjacent gates. Then, the patterned photoresist layer and the silicon nitride mask layer are removed. In the present application, the gate material layer is etched to form the gate with the silicon nitride mask layer as a mask. After the gate is formed, the silicon nitride mask layer is not removed, but is used as a mask for ion implantation with the patterned photoresist layer. This can avoid the ions directly penetrating the patterned photoresist layer into the gate during high-energy ion implantation, that is, the presence of the silicon nitride mask layer can avoid ion implantation into the gate, thereby avoiding affecting the resistance of the gate, and thus improving the performance of the device.

[0090] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application in any way. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present application without departing from the spirit and scope of the present application, using the methods and technical contents disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the technical solutions of the present application, are all within the protection scope of the present application.​

Claims

1. A method of fabricating a lateral diffused metal oxide semiconductor device, comprising: The method comprises the following steps: providing a substrate, and sequentially forming a gate material layer and a silicon nitride mask layer on the substrate; etching the gate material layer to form a gate electrode by taking the silicon nitride mask layer as a mask; forming a patterned photoresist layer, which covers the surface of the substrate, the sidewall of the gate electrode, and the sidewall and top of the silicon nitride mask layer, and has a first opening exposing part of the substrate between adjacent gate electrodes; forming a first body region in the substrate between adjacent gate electrodes by high-energy ion implantation through the first opening by taking the patterned photoresist layer and the silicon nitride mask layer as masks; trimming part of the patterned photoresist layer on both sides of the first opening to form a second opening exposing at least the sidewall of the gate electrode; forming a second body region in the substrate between adjacent gate electrodes by low-energy ion implantation through the second opening by taking the patterned photoresist layer and the silicon nitride mask layer as masks; and removing the patterned photoresist layer and the silicon nitride mask layer. The thickness of the silicon nitride mask layer is greater than or equal to 200 nm and less than or equal to 400 nm.

2. The method of fabricating a lateral diffusion metal oxide semiconductor device according to claim 1, wherein Before forming the gate material layer on the substrate, the method further comprises forming a gate oxide layer on the substrate.

3. The method of fabricating a lateral diffusion metal oxide semiconductor device according to claim 1, wherein The thickness of the gate oxide layer is greater than or equal to 11 nm and less than or equal to 15 nm, and the thickness of the gate material layer is greater than or equal to 100 nm and less than or equal to 300 nm.

4. The method of fabricating a lateral diffusion metal oxide semiconductor device according to claim 3, wherein The method for forming the silicon nitride mask layer comprises:

5. The method of fabricating a lateral diffusion metal oxide semiconductor device according to claim 1, wherein forming a silicon nitride material layer on the gate material layer; forming a photoresist layer on the silicon nitride material layer, and exposing and developing the photoresist layer to form a patterned photoresist layer; taking the patterned photoresist layer as a mask to etch the silicon nitride material layer to expose the gate material layer; and removing the patterned photoresist layer. The ion dose of the high-energy ion implantation is less than the ion dose of the low-energy ion implantation.

6. The method of fabricating a lateral diffusion metal oxide semiconductor device according to claim 1, wherein The lower surface of the first body region is lower than the lower surface of the second body region.

7. The method of fabricating a lateral diffusion metal oxide semiconductor device according to claim 6, wherein, After the low-energy ion implantation, the method further comprises performing a thermal annealing activation treatment.

8. The method of fabricating a lateral diffusion metal oxide semiconductor device according to any one of claims 1 to 7, wherein After removing the patterned photoresist layer and the silicon nitride mask layer, the method further comprises forming a sidewall on the sidewall of the gate electrode.

9. The method of fabricating a lateral diffusion metal oxide semiconductor device according to any one of claims 1 to 7, wherein The method is used for manufacturing a lateral diffusion metal oxide semiconductor device.

10. A lateral diffused metal oxide semiconductor device, characterized by, ​

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