A method of manufacturing a semiconductor device and a vertical stacked semiconductor device

Abstract

The present disclosure provides a method for manufacturing a semiconductor device and a vertical stacked semiconductor device, which can be applied to the technical field of semiconductor technology. The manufacturing method comprises: arranging a lower field effect transistor and an upper field effect transistor stacked in a vertical direction on a substrate; the upper surface of the substrate is connected with the lower surface of the lowermost gate stack and the lower surface of the source / drain layer in the lower field effect transistor; forming a full silicide layer on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor; patterning the full silicide layer to form an opening exposing the lower surface of the lowermost gate stack in the lower field effect transistor, and simultaneously forming a silicide layer pattern connected with the lower surface of the source / drain layer in the lower field effect transistor on both sides of the opening in a first direction; filling a dielectric material in the opening, so that the dielectric material filled in the opening is used as a lower isolation layer of the gate stack; and arranging a contact hole connected with the silicide layer pattern.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, to a method of manufacturing a semiconductor device and a vertical stacked semiconductor device. BACKGROUND

[0002] With the continuous development of the manufacturing process node and key technology of integrated circuits, NS-GAA FET (Nano-Sheet Gate-All-Around Field-Effect Transistor) will replace the existing Fin FET (Fin Field-Effect Transistor) technology at the 3 nm and below nodes. Further, three-dimensional stacked transistors will become the main technology roadmap after the 1 nm node. Among them, three-dimensional stacked transistors include three-dimensional stacked integrated transistors and VFET (Vertical Field-Effect Transistor), etc. Among them, three-dimensional stacked integrated transistors are 3DS FET, or also known as CFET (Complementary Field Effect Transistor).

[0003] The main process methods for implementing 3DS FET include two categories: one is sequential integration, and the other is self-aligned simultaneous (or single) integration. The former process method is simple, but is limited by performance and resources; the latter process method has high integration and superior performance, but this method is complex and has multiple process technology challenges. SUMMARY

[0004] In view of this, the present disclosure provides a method of manufacturing a semiconductor device and a vertical stacked semiconductor device.

[0005] According to an aspect of the present disclosure, a method of manufacturing a semiconductor device is provided, including: providing, on a substrate, a lower field effect transistor and an upper field effect transistor stacked in a vertical direction, and a device isolation layer interposed between the lower field effect transistor and the upper field effect transistor, wherein the lower field effect transistor and the upper field effect transistor each include: a plurality of channel layers stacked apart from each other in the vertical direction; a source / drain layer on both sides of the plurality of channel layers in a first direction and in contact with the channel layers; a gate stack extending in a second direction intersecting the first direction and surrounding the channel layers; an upper surface of the substrate in contact with a lower surface of a lowermost gate stack and a lower surface of a source / drain layer in the lower field effect transistor; etching the substrate to expose the lower surface of the lowermost gate stack and the lower surface of the source / drain layer in the lower field effect transistor; forming a full silicide layer on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor; patterning the full silicide layer to remove the full silicide layer on the lower surface of the lowermost gate stack in the lower field effect transistor to form an opening exposing the lower surface of the lowermost gate stack in the lower field effect transistor, while forming a silicided layer pattern on both sides of the opening in the first direction and in contact with the lower surface of the source / drain layer in the lower field effect transistor; filling a dielectric material in the opening, so that the dielectric material filled in the opening is used as a lower isolation layer of the gate stack; and providing a contact hole in contact with the silicided layer pattern.

[0006] According to an embodiment of the present disclosure, forming a full silicide layer on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor includes: inverting the lower field effect transistor and the upper field effect transistor so that the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor face upward; depositing a silicon layer on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor facing upward; and forming the full silicide layer by silicidizing the silicon layer with a metal.

[0007] According to an embodiment of the present disclosure, the metal includes at least one of Ti, Ni, Co, W, Pt, Al, Cu, and Ru.

[0008] According to an embodiment of the present disclosure, patterning the full silicide layer includes: etching the full silicide layer in the second direction according to a width of the gate stack surrounding the channel layer in the first direction to form an opening and a silicide pattern distributed on both sides of the opening.

[0009] According to an embodiment of the present disclosure, the method for manufacturing a semiconductor device further includes: forming a dielectric layer surrounding the lower field effect transistor and the upper field effect transistor; etching the dielectric layer from above to form a source / drain layer opening exposing a top surface of the source / drain layer of the upper field effect transistor, wherein a projection of the source / drain layer opening in a vertical direction protrudes beyond a projection of the source / drain layer of the upper field effect transistor in the vertical direction in a second direction; filling the source / drain layer opening with a conductive material, and sealing the filled source / drain layer opening with a dielectric material; etching the dielectric layer from below to form an opening exposing a bottom surface of the conductive material from a portion where the projection of the source / drain layer opening protrudes beyond the projection of the source / drain layer of the upper field effect transistor; and filling the opening exposing the bottom surface of the conductive material with a conductive material, thereby forming a contact hole connected to the source / drain layer of the upper field effect transistor.

[0010] According to an embodiment of the present disclosure, the contact hole is used to electrically connect the source / drain layer of the upper field effect transistor to a ground terminal; or the contact hole is used to electrically connect the source / drain layer of the upper field effect transistor to a bit line terminal.

[0011] According to an embodiment of the present disclosure, a substrate is provided with a lower field effect transistor and an upper field effect transistor stacked in a vertical direction, and a device isolation layer between the lower field effect transistor and the upper field effect transistor, including: sequentially arranging a lower stack structure, an intermediate layer, and an upper stack structure on the substrate, the upper stack structure and the lower stack structure each including alternately arranged channel layers and sacrificial layers; patterning the lower stack structure, the intermediate layer, and the upper stack structure together with an upper portion of the substrate to form a fin extending in a first direction; forming a sacrificial gate extending in a second direction on the substrate so as to cross the fin; forming a gate sidewall on a sidewall of the sacrificial gate; patterning the lower stack structure, the intermediate layer, and the upper stack structure using the sacrificial gate and the gate sidewall as a mask, so that the patterned lower stack structure, the intermediate layer, and the upper stack structure have exposed side surfaces in the first direction; replacing the intermediate layer with the device isolation layer; forming a source / drain layer of the lower field effect transistor connected to the exposed side surface of the channel layer in the lower stack structure and a source / drain layer of the upper field effect transistor connected to the exposed side surface of the channel layer in the upper stack structure; and replacing the sacrificial gate and the sacrificial layers with a gate stack.

[0012] According to another aspect of the present disclosure, a vertical stacked semiconductor device is provided, comprising: a lower field effect transistor and an upper field effect transistor stacked in a vertical direction; a device isolation layer between the lower field effect transistor and the upper field effect transistor; and a full silicide layer and a lower isolation layer alternately arranged at a lower surface of the lower field effect transistor; wherein the lower field effect transistor and the upper field effect transistor each comprise: a plurality of channel layers stacked apart from each other in the vertical direction; a source / drain layer on both sides of the plurality of channel layers in a first direction and connected to the channel layers; and a gate stack extending in a second direction intersecting the first direction and surrounding the channel layers; wherein a lower surface of a lowermost gate stack of the lower field effect transistor is covered by the lower isolation layer; a lower surface of the source / drain layer of the lower field effect transistor is covered by an upper surface of the silicide pattern, and a lower surface of the silicide pattern is connected to a contact hole.

[0013] According to an embodiment of the present disclosure, the contact hole connected to a lower surface of the silicide pattern is electrically connected to a power supply terminal; and the contact hole connected to an upper surface of the source / drain layer of the upper field effect transistor extends downward from one side of the upper field effect transistor, so as to be electrically connected to a bit line terminal or a ground terminal from a back side of the vertical stacked semiconductor device.

[0014] According to an embodiment of the present disclosure, the thickness of the silicide pattern ranges from 5 nm to 500 nm.

[0015] According to an embodiment of the present disclosure, a method for manufacturing a vertical stacked semiconductor device is provided, comprising: etching a substrate to expose a lower surface of a lowermost gate stack and a lower surface of a source / drain layer in a lower field effect transistor; and forming a full silicide layer covering an entire lower surface of the device on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor at one time. Then, the full silicide layer is patterned to remove the full silicide layer at the lower surface of the lowermost gate stack in the lower field effect transistor, so as to form an opening exposing the lower surface of the lowermost gate stack in the lower field effect transistor, and simultaneously form a silicide layer pattern connected to the lower surface of the source / drain layer in the lower field effect transistor on both sides of the opening in a first direction. Thus, the silicide layer pattern connected to the source / drain layer is formed in a self-aligned manner, and the photolithography overlay tolerance is avoided. Moreover, since the source / drain layer in the lower field effect transistor is electrically connected to the contact hole through the silicide layer pattern, the metal area and volume of the source / drain contact can be expanded through the silicide layer pattern.

[0016] And, by filling the openings between the above-mentioned siliconized layer patterns with a dielectric material, a lower isolation layer is formed, gate-under self-aligned dielectric isolation is achieved, and the nanosheet channel backside parasitic silicon channel caused by the substrate can be effectively removed, thereby avoiding additional leakage. Thus, the method for manufacturing a vertically stacked semiconductor device according to the present disclosure has a simple manufacturing process and the semiconductor device manufactured has good performance. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments thereof taken in conjunction with the accompanying drawings, in which:

[0018] Figure 1 A schematic diagram illustrating the development process of an integrated circuit according to an embodiment of the present disclosure is shown schematically.

[0019] Figure 2 A schematic diagram illustrating the evolution path of an integrated circuit core transistor structure according to an embodiment of the present disclosure is shown schematically.

[0020] Figure 3 A schematic diagram illustrating a sequential integration process according to an embodiment of the present disclosure is shown schematically.

[0021] Figure 4 A schematic diagram illustrating a self-aligned simultaneous integration process according to an embodiment of the present disclosure is shown schematically.

[0022] Figure 5 A flowchart illustrating a method for manufacturing a vertically stacked semiconductor device according to an embodiment of the present disclosure is shown schematically.

[0023] Figure 6 A schematic diagram illustrating an SRAM integrated circuit according to an embodiment of the present disclosure is shown schematically.

[0024] Figure 7 A schematic diagram illustrating a single-layer SRAM structure according to an embodiment of the present disclosure is shown schematically.

[0025] Figure 8A A schematic diagram illustrating the layer structure of a vertically stacked semiconductor device according to an embodiment of the present disclosure is shown schematically.

[0026] Figure 8B A schematic diagram illustrating the top layer structure in a vertically stacked semiconductor device according to an embodiment of the present disclosure is shown schematically.

[0027] Figure 8C A schematic diagram illustrating the bottom layer structure in a vertically stacked semiconductor device according to an embodiment of the present disclosure is shown schematically.

[0028] Figure 8D A schematic diagram illustrating the backside contact in a vertically stacked semiconductor device according to an embodiment of the present disclosure is shown schematically.

[0029] Figure 9A A schematic diagram of an axial view of a vertical stacked semiconductor device according to embodiments of the present disclosure is shown schematically.

[0030] Figure 9B A schematic diagram of an axial view of a vertical stacked semiconductor device according to embodiments of the present disclosure is shown schematically.

[0031] Figures 10A-10E A schematic diagram of an axial view of a vertical stacked semiconductor device according to embodiments of the present disclosure is shown schematically.

[0032] Figures 11A-49A Figures 11B-49B Figure 41C Figure 41D Figure 48C Figure 48D Figure 49C Figure 49D A schematic diagram of a cross-sectional view of a vertical stacked semiconductor device according to embodiments of the present disclosure is shown schematically.

[0033] Figures 46A'-49A' Figures 46B'-49B' Figure 48C' Figure 48D' Figure 49C' Figure 49D' A schematic diagram of a cross-sectional view of a semiconductor device in the related art is shown schematically.

[0034] Figure 50 A schematic diagram of a structure of a vertical stacked semiconductor device according to embodiments of the present disclosure is shown schematically.

[0035] Figure 51 A schematic diagram of an SRAM structure implemented based on a vertical stacked semiconductor device according to embodiments of the present disclosure is shown schematically. DETAILED DESCRIPTION

[0036] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it is to be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description of the embodiments of the present disclosure, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In addition, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0037] ​​​​​​​​​​​​The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0038] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0039] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0040] In this embodiment of the disclosure, Figure 1 The illustrated technology development roadmap serves as an example to demonstrate the progress of integrated circuit development. It should be noted that... Figure 1 In this context, "Tech Node" refers to a semiconductor process node, which can be used to represent the critical dimensions achievable in the manufacturing process of integrated circuits. Based on this, refer to... Figure 1 As shown in the technology development roadmap, the integrated circuit manufacturing processes are ordered from high to low according to the size represented by the semiconductor process nodes, namely Planar 11A (i.e., planar transistor structure), Fin FET 11B, NS-GAA FET 11C, VFET 11D, and StackedFET 11E. Specifically, the dimensions represented by Tech Node 12A of Planar 11A, from highest to lowest, are 90, 65, 45, 32, 28, and 20, in nm; the dimensions represented by Tech Node 12B of Fin FET 11B, from highest to lowest, are 14, 10, 7, 5, and 4, in nm; the dimensions represented by Tech Node 12C of NS-GAA FET 11C, from highest to lowest, are 3 and 2, in nm; and the dimensions represented by Tech Node 12D of VFET 11D and Stacked FET 11E, from highest to lowest, are 1 and 0.7, in nm.

[0041] Furthermore, such as Figure 2As shown in the evolution path of the transistor structure of the integrated circuit core, from the Fin FET 201 to the NS-GAA FET 202, the Forksheet (Forksheet transistor) 203, and further to the three-dimensional stacked integrated transistor in a single chip, i.e., the 3DS FET or CFET (Complementary Field Effect Transistor) 204, higher integration density and overall performance can be achieved.

[0042] As shown in FIG. 1A, the 3DS FET is implemented by stacking two transistors on top of each other. Figure 3 And Figure 4 As shown in FIG. 1B, the main process methods for implementing the 3DS FET include two categories: one is the sequential integration process (Sequential 3D), and the other is the self-aligned monolithic integration process (Monolithic 3D). Taking the two transistors stacked on top of each other as an example, in the case where the two transistors are fabricated using the sequential integration process, the channel materials of the two transistors can be different from each other; in the case where the two transistors are fabricated using the self-aligned monolithic integration process, the channel materials of the two transistors can be the same. For example, the operation of the sequential integration process can include: bonding a substrate 301 to the upper part of a bottom device 302 to obtain an intermediate device 303; based on the bonded substrate in the intermediate device, manufacturing a top device to obtain an integrated circuit 304. The self-aligned monolithic integration process can include growing a polysilicon layer 402 surrounding multiple channel layers directly on a fin structure 401, and then processing to obtain an integrated circuit 403.

[0043] Therefore, the sequential integration process method is simple, but is limited by performance and resources; the latter self-aligned monolithic integration process method has high integration and superior performance, but this method is complex and has various process technical challenges.

[0044] Specifically, the advantages of the sequential integration process include: flexible architecture design, adjustable channel materials on demand, flexible connection setting between transistors, etc. The disadvantages of the sequential integration process mainly include: high resource consumption, limitations in the manufacturing process, adhesion, N-P isolation space, heat budget, and lithography alignment.

[0045] The advantages of the self-aligned monolithic integration process include: low resource consumption, precise process control, such as self-aligned top and bottom devices, and narrow N-P isolation space, etc. The disadvantages mainly include: high process difficulty, such as processes with high aspect ratio and device-to-device interconnection, etc.

[0046] On this basis, the present disclosure provides a method of manufacturing a semiconductor device and a vertical stacked semiconductor device to obtain a high-integration CFET semiconductor device through a simple process, including: providing, on a substrate, a lower field effect transistor and an upper field effect transistor stacked in a vertical direction, and a device isolation layer interposed between the lower field effect transistor and the upper field effect transistor, wherein the lower field effect transistor and the upper field effect transistor each include: a plurality of channel layers stacked apart from each other in the vertical direction; a source / drain layer on both sides of the plurality of channel layers in a first direction and in contact with the channel layers; a gate stack extending in a second direction intersecting the first direction and surrounding the channel layers; and an upper surface of the substrate in contact with a lower surface of a lowermost gate stack of the lower field effect transistor and a lower surface of the source / drain layer. Etching the substrate to expose the lower surface of the lowermost gate stack of the lower field effect transistor and the lower surface of the source / drain layer. Forming a full silicide layer on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor. Patterning the full silicide layer to remove the full silicide layer on the lower surface of the lowermost gate stack of the lower field effect transistor to form an opening exposing the lower surface of the lowermost gate stack of the lower field effect transistor, while forming a silicided layer pattern in contact with the lower surface of the source / drain layer on both sides of the opening in the first direction. Filling a dielectric material in the opening, so that the dielectric material filled in the opening is used as a lower isolation layer of the gate stack. Providing a contact hole in contact with the silicided layer pattern.

[0047] Figure 5 A schematic diagram of a method of manufacturing a semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0048] As shown in Figure 5 the method of manufacturing a semiconductor device of this embodiment includes operations S501-S507.

[0049] In operation S501, a lower field effect transistor and an upper field effect transistor stacked in a vertical direction, and a device isolation layer interposed between the lower field effect transistor and the upper field effect transistor are provided on a substrate, wherein the lower field effect transistor and the upper field effect transistor each include: a plurality of channel layers stacked apart from each other in the vertical direction; a source / drain layer on both sides of the plurality of channel layers in a first direction and in contact with the channel layers; a gate stack extending in a second direction intersecting the first direction and surrounding the channel layers; and an upper surface of the substrate in contact with a lower surface of a lowermost gate stack of the lower field effect transistor and a lower surface of the source / drain layer.

[0050] In operation S502, the substrate is etched to expose the lower surface of the lowermost gate stack of the lower field effect transistor and the lower surface of the source / drain layer.

[0051] In operation S503, a full silicide layer is formed on a lower surface of the gate stack exposed in the lower field effect transistor and a lower surface of the source / drain layer exposed in the lower field effect transistor.

[0052] In operation S504, the full silicide layer is patterned to remove the full silicide layer on the lower surface of the lowermost gate stack in the lower field effect transistor, thereby forming an opening exposing the lower surface of the lowermost gate stack in the lower field effect transistor, and simultaneously forming a silicided layer pattern on both sides of the opening in the first direction and in contact with the lower surface of the source / drain layer in the lower field effect transistor.

[0053] In operation S505, a dielectric material is filled in the opening, so that the dielectric material filled in the opening is used as a lower isolation layer of the gate stack.

[0054] In operation S506, a contact hole is provided in contact with the silicided layer pattern.

[0055] According to embodiments of the present disclosure, the vertical stacked semiconductor device manufactured by the manufacturing method of the present disclosure can be used to implement an SRAM structure (Static Random-Access Memory). For example, a first group of field effect transistors and a second group of field effect transistors can be arranged along the second direction and spaced apart from each other. The first group of field effect transistors and the second group of field effect transistors each include two vertical stacked semiconductor devices. Each vertical stacked semiconductor device can include vertically stacked field effect transistors. On this basis, based on the two groups of stacked field effect transistors in the first group of field effect transistors and the two groups of stacked field effect transistors in the second group of field effect transistors, the above-mentioned SRAM structure can be implemented.

[0056] The manufacturing method of the vertical semiconductor device of the embodiments of the present disclosure is described below by taking the implementation of the SRAM structure as an example. It should be understood that the SRAM here is only an example, and those skilled in the art can implement other integrated circuit structures based on the vertical semiconductor device in the embodiments of the present disclosure according to needs.

[0057] As shown in Figure 6 , the SRAM is a core unit circuit of an integrated circuit, and continuously reducing the area of the SRAM unit is the main line of development of the integrated circuit. The use of a three-dimensional stacked structure of transistors (3DS-FET or CFET) can greatly reduce the area of the SRAM unit, and the reduced area of the SRAM unit is more than 30%. Referring to Figure 7 and Figure 8A , by comparing the single-layer SRAM structure of Figure 7 and the double-layer SRAM structure in Figure 8A , it can be seen that Figure 8A the area of the three-dimensional stacked structure (corresponding to the vertical stacked semiconductor device of the present disclosure) is less than Figure 7The area of ​​the two-dimensional structure. Furthermore, Figure 8A The three-dimensional stacked structure can be divided into a top-level structure, a bottom-level structure, and back-side contact pads. The top-level structure can be implemented based on NMOS, and the bottom-level structure can be implemented based on PMOS. Based on this, Figure 8B It shows Figure 8A The underlying structure of the three-dimensional stacked structure. Figure 8C It shows Figure 8A The top-level structure of the three-dimensional stacked structure. Figure 8D It shows Figure 8D The back contact of the three-dimensional stacked structure. It should be noted that the dimensions shown in the accompanying drawings are for illustrative purposes only and are not intended to limit the actual dimensions of the vertically stacked semiconductor devices in this disclosure.

[0058] Taking SRAM as an example, combined with Figure 9A and Figure 9B The various axes of the vertically stacked semiconductor device as defined in embodiments of this disclosure are shown. Figures 10A-10E An example is shown Figure 8A The image shows the various axes of the layer structure used to implement the vertically stacked semiconductor device SRAM. The X-X' axis extends along a first direction. The Y1-Y1', Y2-Y2', Y3-Y3', and Y4-Y4' axes extend along a second direction.

[0059] The following are cross-sectional views along various axes during the fabrication of vertically stacked semiconductor devices, i.e. Figures 11A-49A , Figures 11B-49B , Figure 41C , Figure 41D , Figure 48C , Figure 48D , Figure 49C and Figure 49D The following will describe the content of the embodiments disclosed herein. It should be noted that, as shown below... Figures 11A-49A , Figures 11B-49B , Figure 41C , Figure 41D , Figure 48C , Figure 48D , Figure 49C and Figure 49D In cases where multiple figures have the same numbers in their respective titles, the manufacturing processes corresponding to these figures are the same. Conversely, if multiple figures have the same numbers in their respective titles but different letters, the manufacturing processes corresponding to these figures are the same, but the axial directions they correspond to are different. For example, Figure 11A and Figure 11B These are cross-sectional views of two axes, representing the same manufacturing process.

[0060] According to an embodiment of the present disclosure, a lower field effect transistor and an upper field effect transistor stacked in a vertical direction and a device isolation layer 114 interposed between the lower field effect transistor and the upper field effect transistor are provided on a substrate SUB, and include: a lower stack structure, an intermediate layer 103, and an upper stack structure sequentially provided on the substrate SUB, the upper stack structure and the lower stack structure each including channel layers 101 and sacrificial layers 102 alternately provided. The upper portion of the substrate SUB along with the lower stack structure, the intermediate layer, and the upper stack structure is patterned to form a fin extending in a first direction. A sacrificial gate extending in a second direction so as to cross the fin is formed on the substrate. A gate sidewall 110 is formed on the sidewall of the sacrificial gate. The lower stack structure, the intermediate layer 103, and the upper stack structure are patterned with the sacrificial gate and the gate sidewall 110 as a mask, so that the patterned lower stack structure, the intermediate layer 103, and the upper stack structure have exposed side surfaces in the first direction. The intermediate layer 103 is replaced with the device isolation layer 114. A source / drain layer 117 of the lower field effect transistor in contact with the exposed side surface of the channel layer 101 in the lower stack structure and a source / drain layer 119 of the upper field effect transistor in contact with the exposed side surface of the channel layer 101 in the upper stack structure are formed. And the sacrificial gate and the sacrificial layer 102 are replaced with a gate stack.

[0061] Specifically, taking a set of stacked field effect transistors as an example, Figures 11A-12A is a cross-sectional view along the X-X' axis in the process of manufacturing a vertically stacked semiconductor device. Figures 11B-12B is a cross-sectional view along the Y4-Y4' axis in the process of manufacturing a vertically stacked semiconductor device. Refer to Figures 11A-12A , and Figures 11B-12B The material of the substrate SUB can include silicon or the like. The substrate SUB can be sequentially subjected to pretreatment operations such as well lithography, ion implantation, annealing, and cleaning. Then, the lower stack structure, the intermediate layer 103, and the upper stack structure are sequentially provided on the pretreated substrate SUB using an epitaxial growth process. The lower stack structure and the upper stack structure each include channel layers 101 and sacrificial layers 102 alternately provided. The material of the sacrificial layer 102 and the intermediate layer 103 can be consistent, such as SiGe or Si or the like. The material of the channel layer 101 can be doped silicon or the like. The channel layer 101 located above the intermediate layer 103 and the channel layer 101 located below the intermediate layer 103 can have the same or different doping elements.

[0062] In a first embodiment of the present disclosure, the material of the channel layer 101 above the intermediate layer 103 can be p-type doped silicon; the material of the channel layer 101 below the intermediate layer 103 can be n-type doped silicon. In a second embodiment of the present disclosure, the material of the channel layer 101 above the intermediate layer 103 can be n-type doped silicon; the material of the channel layer 101 below the intermediate layer 103 can be p-type doped silicon. In a third embodiment of the present disclosure, the material of the channel layer 101 above the intermediate layer 103 and the material of the channel layer 101 below the intermediate layer 103 can both be n-type doped silicon or both be p-type doped silicon.

[0063] Figures 13A-15A is a cross-sectional view along the X-X' axis in the process of manufacturing the vertical stacked semiconductor device. Figures 13B-15B is a cross-sectional view along the Y4-Y4' axis in the process of manufacturing the vertical stacked semiconductor device. Refer to Figures 13A-15A , and Figures 13B-15B The sidewall 104 can be formed by a sidewall transfer (SIT) process. The material of the sidewall 104 can be silicon nitride or the like. In an embodiment of the present disclosure, a core mold 105 can be formed on the upper stack structure, and the core mold 105 is patterned by a photolithography process to obtain a linear pattern extending along the X direction. The material of the core mold 105 can be polysilicon or amorphous silicon or the like. The sidewall 104 is formed in the above-mentioned region, and after the sidewall 104 is formed, the patterned core mold 105 is removed, so that only the sidewall 104 remains on the stack structure, thereby completing the manufacture of the sidewall 104. On this basis, the upper stack structure, the intermediate layer 103, the lower stack structure and the substrate SUB can be etched by an anisotropic etching process according to the pattern of the sidewall 104, to form a fin on the substrate SUB and a substrate etching region distributed on both sides of the fin along the first direction. In the substrate etching region, a dielectric material 106 is deposited, and the dielectric material 106 is etched to be lower than or equal to the upper surface of the lower fin composed of the substrate SUB by a back etching process, so that the dielectric material 106 serves as a shallow trench isolation. The dielectric material in an embodiment of the present disclosure can include silicon dioxide or silicon nitride or the like.

[0064] Figures 16A-20A is a cross-sectional view along the X-X' axis in the process of manufacturing the vertical stacked semiconductor device. Figures 16B-20B is a cross-sectional view along the Y4-Y4' axis in the process of manufacturing the vertical stacked semiconductor device. Refer to Figures 16A-20A , and Figures 16B-20BA sacrificial gate spanning the fin can be formed on the dielectric material 106 by thermal oxidation, chemical vapor deposition, sputtering, or other processes. The sacrificial gate includes, from bottom to top, a gate oxide layer 107, a silicon layer 108, and a mask layer 109. The gate oxide layer 107 can be made of SiO2 or other materials. The silicon layer 108 can be made of amorphous silicon or polysilicon. The mask layer 109 can be made of oxide, carbide, or organic material. A gate sidewall 110 can be formed on the sidewall of the sacrificial gate by a sidewall formation process. The sidewall can be made of SiCNO or other materials. The upper stack, the middle layer, and the lower stack can be etched according to the pattern of the sacrificial gate and the gate sidewall 110, so that the sidewalls of the upper stack, the middle layer, and the lower stack are exposed. The middle layer 103 and the sacrificial layer 102 can be configured to have different etching selectivity, so that the middle layer 103 can be etched faster than the sacrificial layer 102. After the middle layer 103 is etched, an opening 112 is formed. The end of the sacrificial layer 102 in the first direction is recessed relative to the channel layer 101, forming an opening 111. Based on this, the space released in the fin due to the selective etching of the sacrificial layer 102 and the middle layer 103 can be filled with a dielectric material. The part of the dielectric material filling at the end of the sacrificial layer 102 serves as an inner sidewall 113, and the part of the dielectric material filling between the lower stack and the upper stack serves as a device isolation layer 114. In this way, the inner sidewall 113 and the device isolation layer 114 are manufactured simultaneously, reducing the steps of the manufacturing process. Moreover, the inner sidewall 113 of the first field effect transistor and the second field effect transistor respectively manufactured by the above method has substantially aligned outer side surfaces. Since the outer side surfaces of the inner sidewall 113 in the upper stack and the inner sidewall 113 in the lower stack are substantially aligned in the vertical direction, the area of the horizontal cross section of the upper source / drain layer 119 of the above vertical stacked semiconductor device of the disclosure and the area of the horizontal cross section of the lower source / drain layer 117 are equal, avoiding the adverse consequences of the lateral misalignment of the upper field effect transistor and the lower field effect transistor in the vertical direction caused by the separate manufacturing of the inner sidewall 113 and the device isolation layer 114.

[0065] Figures 21A-27A is a cross-sectional view along the X-X' axis during the manufacturing of the vertical stacked semiconductor device. Figures 21B-27B is a cross-sectional view along the Y4-Y4' axis during the manufacturing of the vertical stacked semiconductor device. Refer to Figures 21A-27A , and Figures 21B-27BLower source / drain location defining layers 115 are formed on both sides of the channel layer 101 located below the inter-device isolation layer 114, contacting the channel layer 101. Sidewalls 116 are formed on the lower source / drain location defining layers 115 using a sidewall forming process. The material of the lower source / drain location defining layers 115 may include, but is not limited to, aC (amorphous carbon). The formation method of the lower source / drain location defining layers 115 includes, but is not limited to, spin coating. For example, after depositing aC, the deposited aC can be planarized, and the aC can be etched back to a position no higher than the middle of the inter-device isolation layer 114. The material of the sidewalls 116 includes, but is not limited to, SiN. x And so on. The sidewall 116 is used to protect the channel layer 101 located above the inter-device isolation layer, preventing source / drain growth at both ends of the channel layer 101 of the upper device during the source / drain growth process of the lower device. When the types of upper and lower devices are different, the source / drain materials of the upper and lower devices can be different.

[0066] After forming the sidewalls 116, the lower source / drain location defining layer 115 is removed to expose the sidewalls of the channel layer 101 located below the inter-device isolation layer 114. Source / drain materials are epitaxially grown and in-situ doped on the exposed sidewalls of the channel layer 101 to form a source / drain layer 117 connected to the lower stacked structure. The source / drain materials can be SiGe or Si. A dielectric material 118 can be deposited on the source / drain layer 117 and etched to a position no higher than the inter-device isolation layer 114 to electrically isolate the source / drain layers of the upper and lower devices. The sidewalls 116 can be selectively etched to expose the sidewalls of the channel layer 101 above the inter-device isolation layer 114. Source / drain materials are epitaxially grown and in-situ doped on the exposed sidewalls of the channel layer 101 to form a source / drain layer 119 connected to the upper stacked structure. Based on this, source / drain activation is performed on source / drain layers 117 and 119, resulting in activated source / drain layers 117 and 119.

[0067] Figures 28A-37A It is a cross-sectional view along the X-X' axis during the manufacturing process of vertically stacked semiconductor devices. Figures 28B-37B This is a cross-sectional view along the Y4-Y4' axis during the fabrication of vertically stacked semiconductor devices. (Reference) Figures 28A-37A ,as well as Figures 28B-37B A dielectric material 120 is formed on a substrate SUB and planarized. Planarization removes the mask layer 109 in the sacrificial gate, exposing the silicon layer 108. Then, using an etch-back process, the silicon layer 108 and the sacrificial layer 102 are etched, thereby forming cavities 121_1 exposed by etching at the original location of the silicon layer 108 and cavities 121_2 exposed by etching at the original location of the sacrificial layer 102, inside the sidewalls 110 and inner sidewalls 113.

[0068] A gate stack is formed around the channel layer 101 in the inner sidewalls of the cavities 121_1 and 121_2. The gate stack includes a gate dielectric layer 122 and a P-type work function layer 123. The material of the gate dielectric layer 122 can be a high-k dielectric material, where k represents the dielectric constant. The high-k dielectric material includes one or a combination of HfO2, HfSiOx, HfON, HfSiON, HfAlO x x , Al2O3, ZrO2, ZrSiO x , Ta2O5, or La2O3. The material of the P-type work function layer 123 can be titanium nitride or the like. A protective layer 124 is formed on the substrate SUB and is etched to a top surface between the top surface and the bottom surface of the device isolation layer 114, so as to shield the cavities for the underlying devices. The protective layer 124 protects the P-type work function layer 123 in the cavities below the device isolation layer 114, while exposing the P-type work function layer 123 in the cavities above the device isolation layer 114.

[0069] The P-type work function layer 123 above the device isolation layer 114 is etched by using a selective etching process, while the gate dielectric layer 122 above the device isolation layer 114 is retained. Then, an N-type work function layer 125 is formed around the gate dielectric layer 122 above the device isolation layer 114. Thus, different gate stacks are formed around the channel layer 101 above and below the device isolation layer 114, respectively. Thus, the channel layer 101, the gate stack, and the source / drain layer 119 above the device isolation layer 114 are configured as an N-type field effect transistor, and the channel layer 101, the gate stack, and the source / drain layer 117 above the device isolation layer 114 are configured as a P-type field effect transistor, thereby obtaining a stacked field effect transistor.

[0070] It should be understood that the above is only one embodiment of the present disclosure, and in the manufacturing process of other embodiments of the present disclosure, an N-type field effect transistor or a P-type field effect transistor can be formed as needed by changing the doping type of the source / drain layer and forming a corresponding type of work function layer. For example, the upper N-type field effect transistor can be formed as a P-type field effect transistor, and / or the lower P-type field effect transistor can be formed as an N-type field effect transistor.

[0071] ​After the N-type field effect transistor and the P-type field effect transistor are manufactured, the protective layer 124 is removed, thus releasing the cavities under the device isolation layer 114. Then, a conductive material is deposited in all the cavities 121_1 and all the cavities 121_2, forming a conductive layer 126, thus completing the manufacturing of the gate structure. The conductive material in the embodiments of the present disclosure can include tungsten or the like. After the conductive layer 126 is formed, the conductive layer 126 can be planarized, and a dielectric material is deposited on the planarized conductive layer 126. On this basis, a contact hole 127 can be formed in the dielectric material 120 to be connected to the source / drain layer 119.

[0072] Specifically, taking four field effect transistors in the first group of field effect transistors and four field effect transistors in the second group of field effect transistors as examples, Figures 38A-41A is a cross-sectional view along the X-X' axis in the process of manufacturing the vertically stacked semiconductor device. Figures 38B-41B is a cross-sectional view along the Y3-Y3' axis in the process of manufacturing the vertically stacked semiconductor device. Figure 41C is a cross-sectional view along the Y1-Y1' axis in the process of manufacturing the vertically stacked semiconductor device. Figure 41D is a cross-sectional view along the Y2-Y2' axis in the process of manufacturing the vertically stacked semiconductor device.

[0073] On this basis, Figures 38A-41A , Figures 38B-41B , Figure 41C and Figure 41DA cross-sectional schematic view of the structure integrated with the eight field effect transistors is shown. On the upper surface of the dielectric material 120, the dielectric material 120 is etched until the source / drain layer 119 is exposed, thereby forming the opening 128_1, the opening 128_2 and the opening 128_3 in the dielectric material 120. Among them, the opening 128_2 includes the opening 128_21 corresponding to the first group of field effect transistors and the opening 128_22 corresponding to the second group of field effect transistors. On this basis, taking the opening 128_2 as an example, the opening 128_2 is continuously etched according to the position of the source / drain layer 117 as a common layer, so that the opening 128_2 exposes the source / drain layer 119 and the source / drain layer 117 at the same time. The conductive material is filled in the opening 128_1, the opening 128_2 and the opening 128_3, thereby forming the contact hole 127_1, the contact hole 127_2 and the contact hole 127_3. Among them, the contact hole 127_2 includes the contact hole 127_21 formed by filling the opening 128_21 and the contact hole 127_22 formed by filling the opening 128_22. In a similar manner, the contact hole 127_1 can be formed. The contact hole 127_1 includes the contact hole 127_11 and the contact hole 127_12. The dielectric material is deposited on the contact hole 127_1, the contact hole 127_2 and the contact hole 127_3. It should be noted that, on the right side of the conductive layer 126 in Figure 41D , there is a structure protruding from the upper surface of the conductive layer 126. This structure serves as a connection line extending in the direction perpendicular to the paper (corresponding to the first direction). And, on the left side of the conductive layer 126 in Figure 41D , the conductive layer 126 extends to the left side, so as to lead out the pad for connecting the word line end from the back surface.

[0074] Figures 42A-45A is a cross-sectional view along the X-X' axis in the process of manufacturing a vertical stacked semiconductor device. Figures 42B-45B is a cross-sectional view along the Y4-Y4' axis in the process of manufacturing a vertical stacked semiconductor device. Refer to Figures 42A-45A , and Figures 42B-45B . It should be noted that, in Figures 42A-45A , and Figures 42B-45BIn some embodiments, the vertically stacked semiconductor devices are inverted. For ease of description, the following other figures are described with the vertically stacked semiconductor devices inverted. Note that "above" and "below" in the following description are described with respect to the vertically stacked semiconductor devices before inversion. After the field effect transistors are inverted, another substrate USUB can be bonded over the vertically stacked field effect transistors, which is the same material as the substrate SUB described above. In some embodiments of the disclosure, the first set of field effect transistors and the second set of field effect transistors each include a lower fin formed by etching the substrate SUB. The remaining portion of the substrate after etching connects between the lower fins of the first set of field effect transistors and the second set of field effect transistors, respectively. An intervening dielectric layer is formed around the first set of field effect transistors, the second set of field effect transistors, and the substrate SUB, including etching the portion of the substrate from below until the lower surfaces of the lower fins of the first set of field effect transistors and the second set of field effect transistors, respectively, are exposed. A dielectric material 129 is deposited on the lower surfaces of the lower fins of the first set of field effect transistors and the second set of field effect transistors, respectively. As a result, the lower fins of the first set of field effect transistors and the second set of field effect transistors, respectively, can be electrically isolated from each other.

[0075] In particular, a fully silicide layer Fully Silicide can be formed on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor. For example, the lower field effect transistor and the upper field effect transistor are inverted such that the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer 117 in the lower field effect transistor face upward. A silicon layer is deposited on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer 117 in the lower field effect transistor facing upward. A low temperature silicidation reaction is performed with a metal on the silicon layer to form the fully silicide layer Fully Silicide. For example, the metal includes at least one of Ti, Ni, Co, W, Pt, Al, Cu, and Ru.

[0076] The fully silicide layer is patterned to remove the fully silicide layer under the lowermost gate stack lower surface in the lower field effect transistor, so that the lowermost gate stack lower surface in the lower field effect transistor is not in contact with the fully silicide layer, thereby forming an opening exposing the lowermost gate stack lower surface in the lower field effect transistor, and simultaneously forming a silicide layer pattern FSP which is in contact with the lower surface of the source / drain layer 117 on both sides of the opening in the first direction. The lower isolation layer 129 can be obtained by filling the opening with a dielectric material. On this basis, the fully silicide layer can be patterned. For example, the fully silicide layer is etched in the second direction according to the width of the gate stack surrounding the channel layer 101 in the first direction, thereby forming an opening and a silicide layer pattern distributed on both sides of the opening. The etching method can include wet etching, dry etching, and physical etching. The length of the opening in the first direction between the two silicide layer patterns FSP is substantially equal to the length of the gate stack surrounding the channel layer 101 in the first direction, and the opening extends in the second direction. Thus, the opening can completely expose the lowermost gate stack lower surface in the lower field effect transistor.

[0077] Continuing with the example of four field effect transistors in the first group of field effect transistors and four field effect transistors in the second group of field effect transistors, Figures 46A-49A is a cross-sectional view along the X-X' axis during the process of manufacturing the vertically stacked semiconductor device. Figures 46B-49B is a cross-sectional view along the Y1-Y1' axis during the process of manufacturing the vertically stacked semiconductor device. Figure 48C is a cross-sectional view along the Y2-Y2' axis during the process of manufacturing the vertically stacked semiconductor device. Figure 48D is a cross-sectional view along the Y3-Y3' axis during the process of manufacturing the vertically stacked semiconductor device. Figure 49C is a cross-sectional view along the Y2-Y2' axis during the process of manufacturing the vertically stacked semiconductor device. Figure 49D is a cross-sectional view along the Y3-Y3' axis during the process of manufacturing the vertically stacked semiconductor device.

[0078] Reference Figures 46A-49A , Figures 46B-49B , Figure 48C , Figure 48D , Figure 49C and Figure 49DThe method for manufacturing the semiconductor device further includes forming a dielectric layer surrounding the lower field effect transistor and the upper field effect transistor. The dielectric layer is etched from above to form a source / drain layer opening exposing an upper surface of the source / drain layer 119 of the upper field effect transistor, wherein a projection of the source / drain layer opening in a vertical direction protrudes beyond a projection of the source / drain layer of the upper field effect transistor in the vertical direction in a second direction. The source / drain layer opening is filled with a conductive material, and the filled source / drain layer opening is closed with a dielectric material to form a contact hole 127_11 and a contact hole 127_12. The dielectric layer is etched from below to form an opening 132_1 and an opening 132_2 exposing a lower surface of the conductive material (i.e., the conductive material in the contact hole 127_11 and the contact hole 127_12) according to a portion where the projection of the source / drain layer opening protrudes beyond the projection of the source / drain layer of the upper field effect transistor. The openings exposing the lower surface of the conductive material are filled with a conductive material to form a contact hole connected to the source / drain layer 119 of the upper field effect transistor. The contact hole is used to electrically connect the source / drain layer 119 of the upper field effect transistor to a ground terminal. Alternatively, the contact hole is used to electrically connect the source / drain layer 119 of the upper field effect transistor to a bit line terminal. For example, one of the contact hole 133_1 and the contact hole 133_2 can electrically connect the source / drain layer 119 of the upper field effect transistor to the ground terminal, and the other can electrically connect the source / drain layer 119 of the upper field effect transistor to the bit line terminal.

[0079] In particular, a dielectric material is deposited under the substrate SUB and the dielectric material and the substrate SUB are subjected to lithography together to form an opening 131 exposing a lower surface of the silicide layer pattern FSP and openings 132_1 and 132_2 exposing the conductive material in contact with the upper source / drain layer. A conductive material is deposited in the openings 131, 132_1 and 132_2 to form a backside contact hole (BS CON) 130 electrically connected to a power supply terminal via the opening 131 exposing the lower surface of the silicide layer pattern FSP and backside via holes (BS VPR) 133_1 and 133_2 electrically connected to a ground terminal and a first bit line terminal, respectively, via the openings 132_1 and 132_2 exposing the conductive material in contact with the upper source / drain layer 119. After the deposition of the conductive material, the conductive material exposed outside the dielectric material is planarized.

[0080] On this basis, a plurality of contact holes can be formed on the back side of the device by a subsequent interconnection process. For example, the conductive material filled into the opening 134 forms a contact hole electrically connected to a second bit line terminal complementary to the first bit line terminal. Furthermore, the conductive material filled into the opening 135 forms a contact hole electrically connected to a third bit line terminal complementary to the second bit line terminal.Figure 49C The conductive layer 126 on the left side of the middle is led out from the back of the device, thereby being electrically connected to the word line end WL at the back of the device. On this basis, it can be known from Figures 46A'-49A' 、 Figures 46B'-49B' 、 Figure 48C' 、 Figure 48D' 、 Figure 49C' and Figure 49D' that, in the vertical stacked semiconductor device in the related art, since the substrate SUB is not completely etched, the siliconized layer pattern FSP and the medium of the lower isolation layer 129 between the siliconized layer patterns FSP are not formed, the substrate SUB will be in contact with the lower surface of the lowermost gate stack in the lower field effect transistor, resulting in a nanosheet channel back parasitic silicon channel, thereby causing leakage.

[0081] Based on this, the method for manufacturing a vertical stacked semiconductor device of the present disclosure is to etch the substrate SUB, thereby exposing the lower surface of the lowermost gate stack in the lower field effect transistor and the lower surface of the source / drain layer 117, and then forming a full silicide layer Fully Silicide covering the entire lower surface of the device on the exposed lower surface of the gate stack in the lower field effect transistor and the exposed lower surface of the source / drain layer 117 at one time. Then, the full silicide layer Fully Silicide is patterned to remove the full silicide layer Fully Silicide located at the lower surface of the lowermost gate stack in the lower field effect transistor, thereby forming an opening exposing the lower surface of the lowermost gate stack in the lower field effect transistor, and simultaneously forming a siliconized layer pattern FSP on both sides of the opening in the first direction and in contact with the lower surface of the source / drain layer 117 in the lower field effect transistor. In this way, the siliconized layer pattern FSP in contact with the source / drain layer 117 is formed in a self-aligned manner, avoiding the photolithography overlay tolerance. And since the source / drain layer 117 in the lower field effect transistor is electrically connected to the contact hole 130 through the siliconized layer pattern FSP, the metal area and volume of the source / drain contact can be expanded through the siliconized layer pattern.

[0082] And, by filling the openings between the silicide pattern FSPs with a dielectric material, a lower isolation layer 129 is formed, achieving gate-under self-aligned dielectric isolation, which effectively removes the nanosheet channel back parasitic silicon channel due to the substrate SUB, avoiding additional leakage. Thus, the method for manufacturing a vertical stacked semiconductor device of the present disclosure has a simple manufacturing process and produces a semiconductor device with good performance. It should be understood that, in the embodiments of the present disclosure, the dielectric material includes but is not limited to SiO2, SiNx, SiNO, SiCO, SiCNO, SiCN, and ploymer, a-C, and other dielectrics and combinations. The method of filling the dielectric includes but is not limited to ALD (Atomic Layer Deposition), CVD (Chemical Vapor Deposition), Spin (rotation), and the like. And, the etching method includes but is not limited to wet etching, RIE (Reactive Ion Etching), RPS (Remote Plasma Source) etching, Chemical Dry Etch (chemical dry etching), ALE (Atomic Layer Etching), and the like. The present disclosure does not limit this, and any method that can achieve the above manufacturing method of the present disclosure can be used.

[0083] Figure 50 A schematic diagram of a vertical stacked semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0084] As Figure 50 shown, the vertical stacked semiconductor device 5000 of this embodiment includes a lower field effect transistor 5001 and an upper field effect transistor 5002 stacked in a vertical direction. A device isolation layer 114 between the lower field effect transistor 5001 and the upper field effect transistor 5002. For example, since the device isolation layer 114 is manufactured at the same time as the adjacent inner sidewall 113, in the vertical stacked semiconductor device of the embodiments of the present disclosure, the device isolation layer 114 is integrated with the adjacent inner sidewall 113. And, a silicide pattern FSP and a lower isolation layer 129 are alternately arranged on the lower surface of the lower field effect transistor 5001. Wherein, the lower field effect transistor 5001 and the upper field effect transistor 5002 each include a plurality of channel layers 101 stacked apart from each other in a vertical direction. A source / drain layer 117 on both sides of the plurality of channel layers 101 in a first direction and in contact with the channel layer 101. A gate stack extending in a second direction intersecting the first direction and surrounding the channel layer 101. The gate stack surrounding the channel layer 101 corresponds to the gate structure G in Figure 50 Figure 50 ​In the perspective view, the lower surface of the lowermost gate stack in the lower field effect transistor 5001 is covered by the lower isolation layer 129. The lower surface of the source / drain layer 117 of the lower field effect transistor 5001 is covered by the upper surface of the silicide pattern FSP, and the lower surface of the silicide pattern FSP is connected to the contact hole 130.

[0085] For example, the contact hole 130 connected to the lower surface of the silicide pattern FSP is electrically connected to a power supply terminal. The contact hole (corresponding to the contact hole 133_1 and the contact hole 133_2 described above) connected to the upper surface of the source / drain layer 119 of the upper field effect transistor 5002 extends downward from one side of the upper field effect transistor 5002, so as to be electrically connected to a bit line terminal or a ground terminal from the back side of the vertically stacked semiconductor device 5000. The thickness of the full silicide layer ranges from 5 nm to 500 nm.

[0086] According to an embodiment of the present disclosure, in the upper field effect transistor, the gate stack includes a portion on the upper surface of the uppermost channel layer 101 among the plurality of channel layers 101 in the upper field effect transistor, and in the lower field effect transistor, the gate stack includes a portion on the lower surface of the lowermost channel layer 101 among the plurality of channel layers 101 in the lower field effect transistor. Thus, the manufacturing method of the present disclosure enables the gate stack to more comprehensively surround the channel layer 101, thereby improving the performance of the manufactured semiconductor device.

[0087] According to an embodiment of the present disclosure, the vertically stacked upper field effect transistor and the lower field effect transistor are in multiple groups, two groups of the vertically stacked field effect transistors in the multiple groups of the vertically stacked field effect transistors are configured as an inverter structure, and the multiple inverter structures are cross-coupled with each other in the vertically stacked semiconductor device to form an SRAM structure.

[0088] According to an embodiment of the present disclosure, for the two groups of the vertically stacked field effect transistors configured as the inverter structure, the drain layers of the two groups of the vertically stacked field effect transistors are shared, and the shared drain layers are electrically connected to a signal output terminal. In the two groups of the vertically stacked field effect transistors, the two source layers of one group of the vertically stacked field effect transistors are both electrically connected to a ground terminal, and the two source layers of the other group of the vertically stacked field effect transistors are respectively electrically connected to a bit line terminal and a power supply terminal.

[0089] Specifically, the structure of the vertically stacked semiconductor device of the present disclosure is described below with Figure 51 as an example. Figure 51 A schematic diagram of an SRAM structure realized based on a vertically stacked semiconductor device according to an embodiment of the present disclosure is schematically shown. It should be noted that, in the schematic diagram, the vertically stacked semiconductor device is not shown. Figure 51In this specification, the extension direction of the X-axis is defined as a first direction, the extension direction of the Y-axis is defined as a second direction intersecting the first direction, and the extension direction of the Z-axis is defined as a vertical direction. In one embodiment of this disclosure, the first direction and the second direction may be perpendicular to each other within the same horizontal plane. The vertical direction may be a direction perpendicular to the horizontal plane.

[0090] like Figure 51 As shown, the SRAM structure 5100 of this embodiment includes: the first group of field-effect transistors and the second group of field-effect transistors respectively arranged on the upper surface of the substrate SUB along a first direction, and a dielectric layer surrounding the substrate SUB, the first group of field-effect transistors and the second group of field-effect transistors.

[0091] exist Figure 51 Each field-effect transistor shown can be used as a transfer transistor or a pull-up transistor, etc., depending on actual needs. A transfer transistor can be used to transfer write data from a bit line. A pull-up transistor can include pull-up transistors and pull-down transistors. A pull-up transistor can be used to pull up node levels. A pull-down transistor can be used to pull down node levels. Furthermore, in... Figure 51 In order to avoid obscuring the SRAM structure 5100, Figure 51 The schematic diagram of the dielectric layer is omitted. It should be understood that the dielectric layer in the embodiments of this disclosure can be configured in the SRAM structure 5100 as needed.

[0092] Continue to refer to Figure 51 ,exist Figure 51 Two groups of field-effect transistors are shown arranged along a second direction. Each group of field-effect transistors includes multiple field-effect transistors integrated into a single structure. Therefore, for ease of description, the structures located in this disclosure will be referred to as... Figure 51 The multiple field-effect transistors on the substrate SUB at the lower left are defined as the first group of field-effect transistors mentioned above, and their... Figure 51 The space shown is located in front; and, will be located in Figure 51 The transistor on the upper right substrate is defined as the second group of field-effect transistors mentioned above, and its... Figure 51 The space shown is located at the rear.

[0093] The following will Figure 51 The field-effect transistors shown are defined as pull-out transistors or transport transistors to facilitate understanding of the SRAM structure 5100 of this disclosure embodiment. It should be understood that the following are merely examples, and those skilled in the art can configure the function of the field-effect transistors in the SRAM structure 5100 according to their needs.

[0094] Exemplarily, the transistor located at the upper left in the first group of field effect transistors is defined as a transfer transistor AC1; the transistor located at the upper right in the first group of field effect transistors is defined as a pull-down transistor PD1; and the transistor located at the lower right in the first group of field effect transistors is defined as a pull-up transistor PU1. Referring to Figure 51 It can be seen that the transfer transistor AC1 and the pull-down transistor PD1 are coupled through a common layer. Moreover, the common layer in the upper layer and the common layer in the lower layer of the first group of field effect transistors are coupled through a connection structure. Based on this, the electrical connection of the transfer transistor AC1, the pull-up transistor PU1 and the pull-down transistor PD1 can be realized. Moreover, the common layer for electrical connection between the transfer transistor AC1, the pull-up transistor PU1 and the pull-down transistor PD1 corresponds to the first source / drain layer of each of the transfer transistor AC1, the pull-up transistor PU1 and the pull-down transistor PD1. Among them, the transfer transistor AC1 can be electrically connected to the bit line end through the source layer contact hole connected to the second source / drain layer located on the other side of the gate structure of the transfer transistor AC1, and the transfer transistor AC1 can be electrically connected to the word line end through the gate contact hole connected to the gate structure G. The pull-up transistor PU1 can be electrically connected to the power supply end through the source layer contact hole connected to the second source / drain layer located on the other side of the gate structure of the pull-up transistor PU1; the pull-down transistor PD1 can be electrically connected to the ground end through the source layer contact hole connected to the second source / drain layer located on the other side of the gate structure of the pull-down transistor PD1. Based on this, the pull-up transistor PU1 can realize the level of the pull-up common layer, and the pull-down transistor PD1 can realize the level of the pull-down common layer.

[0095] Correspondingly, the transistor located at the upper right in the second group of field effect transistors is defined as a transfer transistor AC2; the transistor located at the lower left in the second group of field effect transistors is defined as a pull-down transistor PD2; and the transistor located at the upper left in the second group of field effect transistors is defined as a pull-up transistor PU2. Referring to Figure 51It can be known that the transmission transistor AC2 and the pull-down transistor PU2 are coupled through the common layer. Moreover, the common layer of the upper layer and the common layer of the lower layer in the second group of field effect transistors are coupled through the connection structure. Based on this, the electrical connection of the transmission transistor AC2, the pull-up transistor PU2 and the pull-down transistor PD2 can be realized. Moreover, the common layer for electrical connection among the transmission transistor AC2, the pull-up transistor PU2 and the pull-down transistor PD2 corresponds to the first source / drain layer of each of the transmission transistor AC2, the pull-up transistor PU2 and the pull-down transistor PD2. The transmission transistor AC2 can be electrically connected to the bit line end through the source layer contact hole connected to the second source layer on the other side of the gate structure of the transmission transistor AC2, and the transmission transistor AC2 can be electrically connected to the word line end through the gate contact hole connected to the gate structure G. The pull-up transistor PU2 can be electrically connected to the power supply end through the source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-up transistor PU2; the pull-down transistor PD2 can be electrically connected to the ground end through the source layer contact hole connected to the second source / drain layer on the other side of the gate structure of the pull-down transistor PD2. Based on this, the pull-up transistor PU2 can realize the level of the pull-up common layer, and the pull-down transistor PD2 can realize the level of the pull-down common layer.

[0096] In the embodiments of the present disclosure, the gate structure of the pull-up transistor PU1 and the pull-down transistor PD1 can be electrically connected to the common layer in the second group of field effect transistors through the contact hole, thereby being electrically connected to the second data output end; the gate structure of the pull-up transistor PU2 and the pull-down transistor PD2 can be electrically connected to the common layer in the first group of field effect transistors through the contact hole, thereby being electrically connected to the first data output end. The gate structure of the transmission transistor AC1 and the transmission transistor AC2 can be electrically connected to the word line end through the contact hole, thereby realizing the SRAM structure of the present disclosure. The contact hole for electrical connection between the gate structure and the common layer, and the contact hole for electrical connection between the transmission transistor and the word line end can be made through the above-mentioned back-end interconnection process, which will not be described here.

[0097] Those skilled in the art can understand that the features described in various embodiments of the present disclosure can be combined and / or integrated in various combinations, even if such combinations or integrations are not explicitly described in the present disclosure. In particular, the features described in various embodiments of the present disclosure can be combined and / or integrated in various combinations without departing from the spirit and teachings of the present disclosure. All these combinations and / or integrations fall within the scope of the present disclosure.

[0098] The above describes embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes, and are not intended to limit the scope of the present disclosure. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: providing, on a substrate, a lower field effect transistor and an upper field effect transistor stacked in a vertical direction, and a device isolation layer interposed between the lower field effect transistor and the upper field effect transistor, wherein each of the lower field effect transistor and the upper field effect transistor comprises: a plurality of channel layers stacked apart from each other in the vertical direction; a source / drain layer interfacing with the channel layers on both sides of the channel layers in a first direction; and a gate stack extending in a second direction intersecting the first direction and surrounding the channel layers; and an upper surface of the substrate interfaces with a lower surface of a lowermost gate stack and a lower surface of a source / drain layer in the lower field effect transistor; etching the substrate to expose the lower surface of the lowermost gate stack and the lower surface of the source / drain layer in the lower field effect transistor; forming a full silicide layer on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor; patterning the full silicide layer to remove the full silicide layer on the lower surface of the lowermost gate stack in the lower field effect transistor, thereby forming an opening exposing the lower surface of the lowermost gate stack in the lower field effect transistor, while forming a silicided layer pattern interfacing with the lower surface of the source / drain layer in the lower field effect transistor on both sides of the opening in the first direction; filling a dielectric material in the opening, so that the dielectric material filled in the opening is used as a lower isolation layer of the gate stack; providing a contact hole interfacing with the silicided layer pattern.

2. The method of claim 1, wherein, The forming a full silicide layer on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor comprises: inverting the lower field effect transistor and the upper field effect transistor so that the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor face upward; depositing a silicon layer on the exposed lower surface of the gate stack and the exposed lower surface of the source / drain layer in the lower field effect transistor facing upward; forming the full silicide layer by silicidizing the silicon layer with a metal.

3. The method of claim 2, wherein, The metal comprises at least one of Ti, Ni, Co, W, Pt, Al, Cu and Ru.

4. The method of claim 1, wherein, The patterning the full silicide layer comprises: etching the full silicide layer in the second direction according to a width of the gate stack surrounding the channel layers in the first direction, thereby forming the opening and the silicide pattern distributed on both sides of the opening.

5. The method of claim 1, wherein, The method further comprises: forming a dielectric layer surrounding the lower field effect transistor and the upper field effect transistor; etching the dielectric layer from above to form a source / drain layer opening exposing an upper surface of a source / drain layer of the upper field effect transistor, wherein a projection plane of the source / drain layer opening in the vertical direction protrudes beyond a projection plane of the source / drain layer of the upper field effect transistor in the vertical direction in the second direction; filling a conductive material in the source / drain layer opening, enclosing the filled source / drain layer opening with a dielectric material. etching the dielectric layer from below, so as to form an opening exposing the lower surface of the conductive material; filling the opening exposing the lower surface of the conductive material with conductive material, thereby forming a contact hole connected to the source / drain layer of the upper field effect transistor.

6. The method of claim 5, wherein, The contact hole is used to electrically connect the source / drain layer of the upper field effect transistor to a ground terminal; or the contact hole is used to electrically connect the source / drain layer of the upper field effect transistor to a bit line terminal.

7. The method of claim 1, wherein, The lower field effect transistor and the upper field effect transistor arranged in vertical direction on the substrate, and the device isolation layer between the lower field effect transistor and the upper field effect transistor, comprise: sequentially arranging a lower stack structure, an intermediate layer and an upper stack structure on the substrate, the upper stack structure and the lower stack structure each comprising the channel layer and the sacrificial layer arranged alternately; patterning the lower stack structure, the intermediate layer and the upper stack structure together with the upper part of the substrate to form a fin extending along the first direction; forming a sacrificial gate extending along a second direction intersecting the fin on the substrate; forming a gate sidewall on the sidewall of the sacrificial gate; patterning the lower stack structure, the intermediate layer and the upper stack structure with the sacrificial gate and the gate sidewall as a mask, so that the patterned lower stack structure, the intermediate layer and the upper stack structure have exposed side surfaces in the first direction; replacing the intermediate layer with a device isolation layer; forming the source / drain layer of the lower field effect transistor connected to the exposed side surface of the channel layer in the lower stack structure and the source / drain layer of the upper field effect transistor connected to the exposed side surface of the channel layer in the upper stack structure; and replacing the sacrificial gate and the sacrificial layer with a gate stack.

8. A vertical stacked semiconductor device, comprising: a lower field effect transistor and an upper field effect transistor stacked in vertical direction; a device isolation layer between the lower field effect transistor and the upper field effect transistor; and a full silicide layer and a lower isolation layer alternately arranged at the lower surface of the lower field effect transistor; wherein the lower field effect transistor and the upper field effect transistor each comprise: a plurality of channel layers stacked in vertical direction and spaced apart from each other; a source / drain layer connected to the channel layer on both sides of the plurality of channel layers in a first direction; a gate stack extending in a second direction intersecting the first direction and surrounding the channel layer; wherein the lowermost gate stack of the lower field effect transistor is covered by a lower isolation layer; the lower surface of the source / drain layer of the lower field effect transistor is covered by the upper surface of a silicide pattern, and the lower surface of the silicide pattern is connected to a contact hole.

9. The vertical stacked semiconductor device of claim 8, wherein, The contact hole connected to the lower surface of the silicide pattern is electrically connected to a power supply terminal. A contact hole which interfaces with an upper surface of the source / drain layer of the upper field effect transistor extends downward from one side of the upper field effect transistor to facilitate electrical connection with a bit line terminal or a ground terminal from the back side of the vertical stacked semiconductor device.

10. The vertical stacked semiconductor device of claim 8, wherein, The silicide pattern has a thickness in the range of 5-500 nm.

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