Semiconductor device

Abstract

A semiconductor device includes: a first substrate doped with an impurity of a first conductivity type; a first well region formed in the first substrate and doped with impurities of a second conductivity type different from the first conductivity type; a first protective tape extending in a first direction parallel to an upper surface of the substrate, located in the first well region, and doped with impurities of a second conductivity type; a second protective tape facing the first protective tape, in the substrate, and doped with impurities of the first conductivity type; a first electrode structure electrically connected to the first protective tape; a second electrode structure electrically connected to the second protective tape; and a first insulating layer on sidewalls of the first electrode structure and the second electrode structure, the first electrode structure, the insulating layer, and the second electrode structure providing a capacitor.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0099456 filed in the Korean Intellectual Property Office on July 31, 2023, the disclosure of which is incorporated herein in its entirety for all purposes by reference. Technical Field

[0003] The inventive concept relates to a semiconductor device. Background Art

[0004] A complementary metal oxide semiconductor (CMOS) transistor is a device in which a PMOS transistor and an NMOS transistor are insulated from each other and arranged on the same chip so that the two operate complementarily. Typically, a CMOS transistor includes a PNPN structured silicon controlled rectifier (SCR) composed of a parasitic PNP transistor and a parasitic NPN transistor.

[0005] Latch up refers to the unintended current flow caused by the parasitic bipolar transistors when the vertical PNP transistor (or NPN transistor), the parasitic bipolar component of the PNPN structure CMOS transistor, and the horizontal structure NPN transistor (or PNP transistor) operate simultaneously and enter a low impedance state, thereby damaging the characteristics of the CMOS.

[0006] A guard band is provided around the MOS transistor to prevent latch-up, prevent the parasitic transistor from operating by absorbing minority carriers, and prevent a potential difference from occurring. Summary of the invention

[0007] Example embodiments provide a semiconductor device in which power stability can be improved while preventing parasitic elements from operating by providing a guard band.

[0008] According to example embodiments, a semiconductor device includes: a substrate doped with impurities of a first conductivity type; a first well region located in the substrate, which is doped with impurities of a second conductivity type different from the first conductivity type; a first guard band extending in a first direction, parallel to an upper surface of the substrate, located in the first well region, and doped with impurities of the second conductivity type; a second guard band facing the first guard band in the substrate and doped with impurities of the first conductivity type; a plurality of first main wirings stacked on the first guard bands in a third direction perpendicular to an upper surface of the substrate, some of the plurality of first main wirings being electrically connected to each other through a plurality of first vias, and electrically connected to the first main wirings through one or more first contacts; a protection band; a plurality of second main wirings stacked on the second protection band along a third direction, some of the plurality of second main wirings being electrically connected to each other through a plurality of second vias and electrically connected to the second protection band through one or more second contacts; a plurality of first finger lines extending from the plurality of first main wirings along a second direction parallel to the upper surface of the substrate and intersecting the first direction; a plurality of second finger lines extending from the plurality of second main wirings along a fourth direction parallel to the upper surface of the substrate and opposite to the second direction; and an insulating layer located on the side walls of the plurality of first main wirings, on the side walls of the plurality of second main wirings, on the side walls of the plurality of first finger lines, and on the side walls of the plurality of second finger lines. The plurality of first finger lines and the plurality of second finger lines alternate at least in the first direction.

[0009] According to example embodiments, a semiconductor device includes: a substrate doped with impurities of a first conductivity type; a first well region located in the substrate and doped with impurities of a second conductivity type different from the first conductivity type; a first guard band extending in a first direction parallel to an upper surface of the substrate, located in the first well region, and doped with impurities of the second conductivity type; a second guard band facing the first guard band within the substrate and doped with impurities of the first conductivity type; a plurality of first main wirings stacked on the first guard band in a third direction perpendicular to the substrate, electrically connected to each other through a plurality of first vias, and electrically connected to the first guard band through one or more first contacts; a plurality of second main wirings stacked on the second guard band in the third direction, electrically connected to each other through a plurality of second vias, and electrically connected to the second guard band through one or more second contacts; and an insulating layer located on the plurality of first main wirings and on sidewalls of the plurality of second main wirings. The electrode structure is not between the plurality of first main wirings and the plurality of second main wirings.

[0010] According to example embodiments, a semiconductor device includes: a substrate doped with impurities of a first conductivity type; a first well region formed in the substrate and doped with impurities of a second conductivity type different from the first conductivity type; a first guard band extending in a first direction parallel to an upper surface of the substrate, located in the first well region, and doped with impurities of the second conductivity type; a second guard band facing the first guard band, located in the substrate, and doped with impurities of the first conductivity type; a first electrode structure electrically connected to the first guard band; a second electrode structure electrically connected to the second guard band; and an insulating layer located on sidewalls of the first electrode structure and sidewalls of the second electrode structure. The first electrode structure, the insulating layer, and the second electrode structure provide a capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a diagram illustrating a semiconductor device according to example embodiments;

[0013] Figure 2 is along Figure 1 A cross-sectional view taken along line II';

[0014] Figure 3 is a diagram illustrating a semiconductor device according to example embodiments;

[0015] Figure 4 is along Figure 3 A cross-sectional view taken along line I II I';

[0016] Figure 5 is along Figure 3 A cross-sectional view taken along line II II I I';

[0017] Figure 6 is a diagram illustrating a semiconductor device according to example embodiments;

[0018] Figure 7 is along Figure 6 A cross-sectional view taken along line IV-IV';

[0019] Figure 8 is along Figure 6 A cross-sectional view taken along line V-V';

[0020] Fig. 9 is a diagram illustrating a semiconductor device according to example embodiments;

[0021] Fig.10 is along Fig. 9 A cross-sectional view taken along line VI-VI';

[0022] Fig.11 is along Fig. 9 A cross-sectional view taken along line VI I-VI I';

[0023] Fig.12 is a diagram illustrating a semiconductor device according to example embodiments;

[0024] Fig.13 is a diagram illustrating a semiconductor device according to example embodiments;

[0025] Fig.14 is a diagram illustrating a semiconductor device according to example embodiments;

[0026] Fig.15 is a diagram illustrating a semiconductor device according to example embodiments; and

[0027] Fig.16 is a diagram illustrating a semiconductor layout design method according to example embodiments. DETAILED DESCRIPTION

[0028] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0029] Figure 1 is a diagram for explaining a semiconductor device according to example embodiments.

[0030] Reference Figure 1 , the semiconductor device 100 may include a substrate 101 and a first type well region (PW) and a second type well region (NW) formed in the substrate 101. For example, the substrate 101 and the first type well region (PW) may be doped with impurities of a first conductivity type, and the second type well region (NW) may be doped with impurities of a second conductivity type. The first conductivity type may be a P type, and the second conductivity type may be an N type. Hereinafter, the first conductivity type or type 1 well region is referred to as a P well region (PW), and the second conductivity type or type 2 well region is referred to as an N well region (NW).

[0031] A PMOS transistor (PMOS) may be formed in an N-well region (NW), and an NMOS transistor (NMOS) may be formed in a P-well region (PW). The PMOS transistor (PMOS) may include a first active region (PACT) and a gate structure (GS) doped with P-type impurities, and the NMOS transistor (NMOS) may include a second active region (NACT) and a gate structure (GS) doped with N-type impurities. A power supply voltage may be applied to the first active region (PACT) of the PMOS transistor (PMOS), and a ground voltage may be applied to the second active region (NACT) of the NMOS transistor (NMOS).

[0032] CMOS transistors may include PMOS transistors (PMOS) and NMOS transistors (NMOS). CMOS transistors may have a PNPN structure consisting of a first active region (PACT), an N-well region (NW), a P-well region (PW), and a second active region (NACT). If an undesired forward bias is formed in the PNPN structure due to reasons such as noise being applied to the CMOS transistor, the CMOS transistor may operate like a silicon controlled rectifier (SCR), which may cause overcurrent.

[0033] To prevent latch-up that may occur in a CMOS transistor, the semiconductor device 100 may include a guard band. For example, an N-well region (NW) may include an N-type guard band (NGB) surrounding a PMOS transistor (PMOS), the N-type guard band (NGB) being doped with a second conductivity type impurity having a higher concentration than the N-well region (NW), and a P-well region (PW) may include a P-type guard band (PGB) surrounding the NMOS transistor (NMOS), the P-type guard band (PGB) being doped with a first conductivity type impurity having a higher concentration than the P-well region (PW).

[0034] By applying a power supply voltage to the N-type guard band (NGB), the N-well region (NW) can be biased with the power supply voltage, and when a ground voltage is applied to the P-type guard band (PGB), the P-well region (PW) can be biased to the ground voltage. Electrons flowing into the N-well region (NW) can escape outward through the N-type guard band (NGB), and holes flowing into the P-well region (PW) can escape outward through the P-type guard band (PGB), thereby preventing latch-up of the CMOS transistor.

[0035] On the other hand, an electrical short circuit may occur between N-well regions (NW) that are spaced apart from each other and each biased by a power supply voltage. For example, between the first well region 102 and the second well region 103 in the N-well region (NW), a parasitic element consisting of the first well region 102, the substrate 101, and the second well region 103 is formed. Due to the operation of the configured parasitic element, an electrical short circuit may occur.

[0036] According to example embodiments, a P-type guard band may be formed on a substrate 101 of a semiconductor device 100, opposite to an N-type guard band (NGB) included in an N-well region (NW). For example, a second guard band 112 opposite to a first guard band 111 as an N-type guard band (NGB) included in a first well region 102 may be further formed on the substrate 101. Figure 1 In the example of , when the first guard band 111 extends in the first direction D1 parallel to the upper surface of the substrate 101, the second guard band 112 may also extend in the first direction D1. The second guard band 112 may be doped with impurities of the first conductivity type that is the same as the conductivity type of the substrate 101, and a ground voltage may be applied to the second guard band 112.

[0037] According to example embodiments, the second guard band 112 biases the substrate 101 to a ground voltage, thereby preventing the operation of a parasitic element consisting of the first well region 102, the substrate 101, and the second well region 103. As a result, an electrical short circuit may be prevented from occurring.

[0038] In addition, the semiconductor device 100 may further include a first electrode structure for connecting the first guard band 111 to the power supply voltage and a second electrode structure for connecting the second guard band 112 to the ground voltage. The first electrode structure and the second electrode structure may be arranged to face each other. Therefore, the first electrode structure and the second electrode structure may provide a power capacitor. As a result, the stability of the power supply voltage and the ground voltage may be improved.

[0039] Below, refer to Figure 2 The structures of the guard band and the power capacitor of the semiconductor device 100 according to example embodiments are described in more detail.

[0040] Figure 2 is along Figure 1 Schematic diagram taken along line II'.

[0041] Reference Figure 2 The first well region 102, the substrate 101, and the second well region 103 may have a parasitic NPN transistor (NPN). For example, the first well region 102, the substrate 101, and the second well region 103 may provide a collector, a base, and an emitter of the parasitic NPN transistor, respectively.

[0042] The first well region 102 includes a first guard band 111 doped with impurities of the second conductivity type, and the second well region 103 may include a third guard band 113 doped with impurities of the second conductivity type. The electrode structure 130 formed on the upper surface of the first guard band 111 is electrically connected to the first power pad (PWR1), and the first well region 102 can be biased using the first power supply. In addition, the electrode structure 150 formed on the upper surface of the third guard band 113 is electrically connected to the second power pad (PWR2) so that the second well region 103 can be biased using the second power supply. The first power supply and the second power supply may have the same potential or different potentials. On the other hand, the electrode structures 130 and 150 may be formed in the insulating layer 120.

[0043] On the other hand, a metal wiring (ML) may be provided on an upper portion of the substrate 101. The parasitic NPN transistor (NPN) may be turned on due to a voltage applied to the metal wiring (ML). In detail, when the semiconductor device 100 is a device using a high voltage of several tens of volts, such as a flash memory device, the potential of the substrate 101 may increase due to the high voltage applied to the metal wiring (ML), thereby turning on the parasitic NPN transistor (NPN).

[0044] When the parasitic NPN transistor (NPN) is turned on, a power short circuit may occur, wherein a low impedance current path is formed between the first power pad (PWR1) and the second power pad (PWR2). When a power short circuit occurs, a large amount of current flows between the first power pad (PWR1) and the second power pad (PWR2), and sufficient current may not flow through a device such as a PMOS transistor. Therefore, the power short circuit may cause a malfunction of the semiconductor device.

[0045] According to example embodiments, the substrate 101 may include P-type guard bands 112 and 114 surrounding each of the N-type guard bands 111 and 113. Figure 1 As described above, the first protection tape 111 and the second protection tape 112 may extend in directions parallel to each other, and the third protection tape 113 and the fourth protection tape 114 may extend in directions parallel to each other.

[0046] Electrode structure 140 may be formed on an upper surface of second guard tape 112, and electrode structure 160 may be formed on an upper surface of fourth guard tape 114. Substrate 101 may be biased with a ground voltage by connecting a ground pad (GND) to each of electrode structures 140 and 160.

[0047] According to example embodiments, the substrate 101 may be biased with a ground voltage. Therefore, even if a voltage is applied to the metal wiring ML, the voltage of the substrate 101 is fixed to the ground voltage, thereby preventing the operation of the parasitic NPN transistor. Therefore, a power short circuit between the first power source (PWR1) and the second power source (PWR2) may be prevented, and a malfunction of the semiconductor device 100 may be prevented.

[0048] On the other hand, the first electrode structure 130 formed on the upper surface of the first protective tape 111 and the second electrode structure 140 formed on the upper surface of the second protective tape 112 may face each other with the insulating layer 120 interposed therebetween. The first electrode structure 130 to which the first power is applied, the insulating layer 120, and the second electrode structure 140 to which the ground power is applied may provide a power capacitor. The insulating layer 120 between the first electrode structure 130 and the second electrode structure 140 may serve as a dielectric layer.

[0049] Similarly, the third electrode structure 150 to which the second power is applied, the insulating layer 120 , and the fourth electrode structure 160 to which the ground power is applied may also provide a power capacitor.

[0050] Depending on example embodiments, no electrode structure may be interposed between the first electrode structure 130 and the second electrode structure 140 , and no electrode structure may be interposed between the third electrode structure 150 and the fourth electrode structure 160 .

[0051] In addition, the opposing electrode structures may be spaced at a distance close enough to provide a power capacitor required by the semiconductor device 100. For example, the separation distance between the first electrode structure 130 and the second electrode structure 140 and the separation distance between the third electrode structure 150 and the fourth electrode structure 160 may be the same as the minimum distance defined in the layout design rules. However, the separation distance between the electrode structures may be greater than the minimum distance.

[0052] Depending on the example embodiment, the first electrode structure 130, the insulating layer 120, and the second electrode structure 140 may form a vertical capacitor. The insulating layer 120 may include a plurality of insulating layers 121 to 126. The first electrode structure 130 may be formed in the plurality of insulating layers 121 to 126, and may include first wirings 131a, 131b, and 131c stacked along a third direction D3 perpendicular to the upper surface of the substrate 101 starting from the upper surface of the first guard band 111, a first contact 132, and first vias 133a and 133b. The first contact 132 may be connected to the first wiring 131a of the lowest layer of the first wirings 131a, 131b, and 131c and the first guard band 111, and each of the first vias 133a and 133b may be electrically connected to the first wirings 131a, 131b, and 131c by being connected to adjacent first electrodes.

[0053] Similarly, the second electrode structure 140 may be formed in the plurality of insulating layers 121 to 126, and may include a plurality of second wirings 141a, 141b, and 141c, a second contact 142, and second vias 143a and 143b stacked along the third direction D3 from the upper surface of the second guard tape 112. The second contact 142 may be connected to the lowermost second wiring 141a of the second wirings 141a, 141b, and 141c and the second guard tape 112, and each of the second vias 143a and 143b may be electrically connected to the second wirings 141a, 141b, and 141c by being connected to an adjacent second electrode.

[0054] Depending on the example embodiment, the electrode structures 130, 140, 150, and 160 may extend to the upper surface of the insulating layer 120. For example, the upper surfaces of the electrode structures 130, 140, 150, and 160 may be exposed to the upper surface of the insulating layer 120 and may be connected to a power pad or a ground pad. However, the inventive concept is not limited to the structure that the electrode structures 130, 140, 150, and 160 must extend to the upper surface of the insulating layer 120.

[0055] According to an example embodiment, electrode structures 140 and 160 formed to apply a ground voltage (GND) to P-type guard bands 112 and 114 formed on substrate 101 may form power capacitors together with electrode structures 130 and 150, respectively. For example, semiconductor device 100 does not include an additional structure for providing a power capacitor, and by using a power capacitor as a structure for biasing substrate 101 to a ground voltage, noise in a first power supply voltage (PWR1), a second power supply voltage (PWR2), and a ground voltage (GND) may be effectively removed. As a result, the stability of power supply voltages PWR1 and PWR2 and a ground voltage (GND) may be improved while effectively using a circuit area of ​​semiconductor device 100.

[0056] According to example embodiments, the electrode structure disposed on the upper surface of the first guard band and the second guard band may have various shapes to provide a power capacitor. Figures 3 to 14 Semiconductor devices according to various example embodiments are described in detail.

[0057] Figure 3 is a diagram illustrating a semiconductor device according to example embodiments.

[0058] Reference Figure 3 , the semiconductor device 200 may include a substrate 201 doped with impurities of a first conductivity type, and a first well region 202 formed in the substrate 201 and doped with impurities of a second conductivity type.

[0059] With reference Figure 1 and Figure 2 Similar to the semiconductor device 100 described above, Figure 3 The semiconductor device 200 may include a first guard band 211 formed in the first well region 202 and a second guard band 212 formed in the substrate 201, wherein the first guard band 211 is doped with impurities of the second conductivity type and extends in the first direction D1, and the second guard band 212 is doped with impurities of the first conductivity type and extends in the first direction D1.

[0060] Furthermore, the semiconductor device 200 may include a first electrode structure 230 connected to the first guard tape 211 on an upper surface of the first guard tape 211 and a second electrode structure 240 connected to the second guard tape 212 on an upper surface of the second guard tape 212 .

[0061] When a power voltage is applied to the first electrode structure 230 , the first well region 202 is biased by the power voltage, and by applying a ground voltage to the second electrode structure 240 , the substrate 201 may be biased to a ground voltage.

[0062] According to example embodiments, the first electrode structure 230 may include at least one first main wiring 231 and a plurality of first finger lines 234 extending along a second direction D2 from the first main wiring 231. The first main wiring 231 may be electrically connected to the first guard tape 211 through a first contact 232. The second direction D2 may be parallel to an upper surface of the substrate 201 and intersect the first direction D1.

[0063] In addition, the second electrode structure 240 may include at least one second main wiring 241 and a plurality of second finger lines 244 extending from the second main wiring 241 in a direction opposite to the second direction D2. The second main wiring 241 may be electrically connected to the second guard tape 212 through a second contact 242.

[0064] According to example embodiments, the plurality of first finger lines 234 and the plurality of second finger lines 244 may be alternately disposed along the first direction D1. Figure 4 and Figure 5 Describe in more detail Figure 3 Structure of the semiconductor device 200.

[0065] Figure 4 is along Figure 3 Cross-sectional view taken along line III I I'.

[0066] Reference Figure 4 , the insulating layer 220 may be disposed on the upper surface of the substrate 201, and refer to Figure 3 The described first electrode structure 230 and second electrode structure 240 may be disposed in the insulating layer 220 .

[0067] The one or more first main wirings 231 may include a plurality of first main wirings 231a, 231b, and 231c. In addition, the one or more second main wirings 241 may include a plurality of second main wirings 241a, 241b, and 241c.

[0068] A plurality of first finger lines 234 may extend from each of the plurality of first main wirings 231 a , 231 b , and 231 c , and a plurality of second finger lines 244 may extend from each of the plurality of second main wirings 241 a , 241 b , and 241 c . Figure 4 Second finger lines 244a, 244b, and 244c extending from the plurality of second main wirings 241a, 241b, and 241c are shown.

[0069] The second main wiring 241a may be connected to the second guard tape 212 through the second contact 242, and the plurality of second main wirings 241a, 241b, and 241c may be electrically connected to each other through the second vias 243a and 243b. Figure 4Although not shown, the first main wiring 231a may be connected to the first guard tape 211 through the first contact 232, and the plurality of first main wirings 231a, 231b, and 231c may be electrically connected to each other through the first via.

[0070] Figure 5 is along Figure 3 Cross-sectional view taken along line II III I I'.

[0071] Reference Figure 5 , showing a plurality of first finger lines 234a and a plurality of second finger lines 244a formed in the second insulating layer 222, a plurality of first finger lines 234b and a plurality of second finger lines 244b formed in the fourth insulating layer 224, and a plurality of first finger lines 234c and a plurality of second finger lines 244c formed in the sixth insulating layer 226.

[0072] The first finger lines and the second finger lines formed in the same insulating layer may be alternately arranged along the first direction D1 to provide capacitance. On the other hand, the first finger lines 234a, 234b, and 234c formed in different insulating layers may be aligned along the third direction D3, and the second finger lines 244a, 244b, and 244c formed in different insulating layers may be aligned along the third direction D3.

[0073] According to example embodiments, the plurality of finger lines 234a and 244a, the plurality of finger lines 234b and 244b, and the plurality of finger lines 234c and 244c may be alternately disposed along the first direction D1. Thus, the area of ​​the power capacitor provided by the first electrode structure 230, the insulating layer 220, and the second electrode structure 240 increases, and the electrostatic capacity may be improved.

[0074] Figure 6 is a diagram illustrating a semiconductor device according to example embodiments.

[0075] Reference Figure 6 , the semiconductor device 300 may include a substrate 301 doped with impurities of a first conductivity type, and a first well region 302 formed in the substrate 301 and doped with impurities of a second conductivity type.

[0076] With reference Figure 1 and Figure 2 Similar to the semiconductor device 100 described above, Figure 6 The semiconductor device 300 may include a first guard band 311 formed in the first well region 302 and a second guard band 312 formed in the substrate 301, wherein the first guard band 311 is doped with impurities of the second conductivity type and extends in the first direction D1, and the second guard band 312 is doped with impurities of the first conductivity type and extends in the first direction D1.

[0077] The semiconductor device 300 may include a first electrode structure 330 connected to the first guard tape 311 on an upper surface of the first guard tape 311, and a second electrode structure 340 connected to the second guard tape 312 on an upper surface of the second guard tape 312. A power supply voltage may be applied to the first electrode structure 330, and a ground voltage may be applied to the second electrode structure 340.

[0078] The first electrode structure 330 may include a plurality of first main wirings 331a and 331b, and the second electrode structure 340 may include a plurality of second main wirings 341a and 341b. On the other hand, the plurality of first main wirings 331a and 331b and the plurality of second main wirings 341a and 341b may be respectively arranged at Figure 6 In the same position on the plane shown, but Figure 6 Slightly misaligned.

[0079] The first electrode structure 330 may include a plurality of first finger lines 334a and 334b ​​extending from each of the first main wirings 331a and 331b in the second direction D2. The second electrode structure 340 may include a plurality of second finger lines 344a and 344b extending from the second main wirings 341a and 341b in a direction opposite to the second direction D2.

[0080] According to example embodiments, the plurality of first finger lines 334a and 334b ​​and the plurality of second finger lines 344a and 344b may be alternately disposed along the first direction D1 and the third direction D3. Figure 7 and Figure 8 Describe in more detail Figure 6 FIG. 1 is a diagram showing a structure of a semiconductor device 300 .

[0081] Figure 7 is along Figure 6 A cross-sectional view taken along line IV-IV'.

[0082] Reference Figure 7 , an insulating layer 320 may be disposed on an upper surface of the substrate 301 , and a first electrode structure 330 and a second electrode structure 340 may be disposed in the insulating layer 320 .

[0083] The first electrode structure 330 may include a plurality of first main wirings 331a, 331b and 331c, a first contact 332, and a plurality of first vias 333a and 333b. The second electrode structure 340 may include a plurality of second main wirings 341a, 341b and 341c, a second contact 342, and a plurality of second vias 343a and 343b.

[0084] exist Figure 7In the example of FIG. 3 , a first finger line 334a extending from a first main wiring 331a, a second finger line 344b extending from a second main wiring 341b, and a first finger line 334c extending from a first main wiring 331c are shown.

[0085] According to example embodiments, the first finger line 334 a , the second finger line 344 b , and the first finger line 334 c overlap in the third direction D3 , thereby providing a power capacitor.

[0086] Figure 8 is along Figure 6 A cross-sectional view taken along line V-V'.

[0087] Reference Figure 8 , showing a plurality of first finger lines 334a and a plurality of second finger lines 344a formed in the second insulating layer 322, a plurality of first finger lines 334b ​​and a plurality of second finger lines 344b formed in the fourth insulating layer 324, and a plurality of first finger lines 334c and a plurality of second finger lines 344c formed in the sixth insulating layer 326.

[0088] According to example embodiments, first and second finger lines formed in the same insulating layer may be alternately disposed in a first direction D1 to provide capacitance. In addition, first and second finger lines formed in different insulating layers may be alternately disposed in a third direction D3 to provide capacitance.

[0089] The first finger lines 334a, 334b, 334c and the second finger lines 344a, 344b, 344c are alternately arranged along the first direction D1 and the third direction D3. The area of ​​the power capacitor provided by the first electrode structure 330, the insulating layer 320 and the second electrode structure 340 may be increased, and the electrostatic capacity may be increased.

[0090] Fig. 9 is a diagram illustrating a semiconductor device according to example embodiments.

[0091] Reference Fig. 9 , the semiconductor device 400 may include a substrate 401 doped with impurities of a first conductivity type, and a first well region 402 formed in the substrate 401 and doped with impurities of a second conductivity type.

[0092] With reference Figure 1 and Figure 2 Similar to the semiconductor device 100 described above, Fig. 9The semiconductor device 400 may include a first guard band 411 formed in a first well region 402 and a second guard band 412 formed in a substrate 401, wherein the first guard band 411 is doped with impurities of a second conductive type and extends in a first direction D1 parallel to an upper surface of the substrate, and the second guard band 412 is doped with impurities of a first conductive type and extends in the first direction D1.

[0093] The semiconductor device 400 may include a first electrode structure 430 connected to the first guard tape 411 on an upper surface of the first guard tape 411, and a second electrode structure 440 connected to the second guard tape 412 on an upper surface of the second guard tape 412. A power supply voltage may be applied to the first electrode structure 430, and a ground voltage may be applied to the second electrode structure 440.

[0094] According to example embodiments, the first electrode structure 430 may include at least one first main wiring 431, a first contact 432 connected to the first main wiring 431 and the first guard tape 411, and a first sub wiring 434 connected to an end portion of the first main wiring 431 in the first direction D1. The first sub wiring 434 may be connected to the first main wiring 431 in the second direction D2 from the first well region 402 toward the substrate 401.

[0095] In addition, the second electrode structure 440 may include at least one second main wiring 441, a second contact 442 connected to the second main wiring 441 and the second protection tape 412, and a second sub wiring 444 connected to an end portion of the second main wiring 441 in a direction opposite to the first direction D1. The second sub wiring 444 may be connected to the second main wiring 441 in the second direction D2.

[0096] Depending on example embodiments, the first and second sub wirings 434 and 444 may each have an L-shape, and the first and second electrode structures 430 and 440 may each have a U-shape.

[0097] According to example embodiments, the electrode structure may not be interposed between the first main wiring 431 and the second main wiring 441 .

[0098] According to example embodiments, the first electrode structure 430 and the second electrode structure 440 may be arranged in a Fig. 9 For example, the first electrode structure 430 and the second electrode structure 440 may have portions alternately arranged along the second direction D2. Fig.10 and Fig.11 Describe in more detail Fig. 9 Structure of a semiconductor device 400.

[0099] Fig.10 is along Fig. 9 A cross-sectional view taken along line VI-VI'. Fig.11 is along Fig. 9 A cross-sectional view taken along line VI I-VI I.

[0100] Refer to Fig.10 and Fig.11 , the insulating layer 420 may be disposed on the upper surface of the substrate 401, and refer to Fig. 9 The described first electrode structure 430 and second electrode structure 440 may be disposed in the insulating layer 420 .

[0101] The first electrode structure 430 may include a plurality of first main wirings 431a, 431b, 431c, a first contact 432, a plurality of first vias 433a, 433b, and a plurality of first sub wirings 434a, 434b, and 434c. The second electrode structure 440 may include a plurality of second main wirings 441a, 441b, and 441c, a second contact 442, a plurality of second vias 443a and 443b, and a plurality of second sub wirings 444a, 444b, and 444c.

[0102] A power voltage may be applied to the first electrode structure 430, and a ground voltage may be applied to the second electrode structure 440. Therefore, the first electrode structure 430 and the second electrode structure 440 may function as a power capacitor.

[0103] Reference Fig.11 , a first main wiring, a second main wiring, a first sub wiring, and a second sub wiring formed in the same insulating layer are alternately arranged to increase the area of ​​the power capacitor.

[0104] Reference Figures 9 to 11 , a case has been described in which the first electrode structure 430 and the second electrode structure 440 are interlocked and arranged so that the sub wiring has an L-shape. However, the line extending from the main wiring may have various shapes.

[0105] Fig.12 is a diagram illustrating a semiconductor device according to example embodiments.

[0106] Reference Fig.12 , the semiconductor device 500 may include a substrate 501 doped with impurities of a first conductivity type, and a first well region 502 formed in the substrate 501 and doped with impurities of a second conductivity type.

[0107] Fig.12 The semiconductor device 500 in the embodiment may include a substrate 501, a first well region 502, a first guard band 511 and a second guard band 512, and its structure is similar to that of the reference Figures 9 to 11 The structure of the semiconductor device 400 is described below. Fig.12The semiconductor device 500 focuses on the difference from the semiconductor device 400.

[0108] The semiconductor device 500 may include a first electrode structure 530 connected to the first guard tape 511 on an upper surface of the first guard tape 511, and a second electrode structure 540 connected to the second guard tape 512 on an upper surface of the second guard tape 512. A power supply voltage may be applied to the first electrode structure 530, and a ground voltage may be applied to the second electrode structure 540.

[0109] According to example embodiments, the first electrode structure 530 may include at least one first main wiring 531 extending in a first direction D1 parallel to the upper surface of the substrate 501, at least one first sub-wiring 534 extending from the first main wiring 531 in a second direction D2 intersecting the first direction D1, and a plurality of first finger lines 535 extending from the first sub-wiring 534 and parallel to the first main wiring 531.

[0110] In addition, the second electrode structure 540 may include at least one second main wiring 541 extending along the first direction D1, at least one second sub wiring 544 extending from the second main wiring 541 along the second direction D2, and a plurality of second finger lines 545 extending from the second sub wiring 544 and parallel to the second main wiring 541.

[0111] As an example, Fig.12 5. A first main wiring 531, a first sub-wiring 534, a plurality of first finger lines 535 extending from a first sub-wiring 534, a second main wiring 541, a second sub-wiring 544, and a plurality of second finger lines 545 extending from a second sub-wiring 544 are shown. Figures 9 to 11 Similar to the case of the described semiconductor device 400 , wirings may be stacked in a plurality of insulating layers.

[0112] According to example embodiments, the first main wiring 531 , the second main wiring 541 , the plurality of first finger lines 535 , and the plurality of second finger lines 545 are alternately arranged in the second direction D2 , thereby providing a power capacitor.

[0113] Fig.13 is a diagram illustrating a semiconductor device according to example embodiments.

[0114] Fig.13 The semiconductor device 600 in the embodiment may include a substrate 601, a first well region 602, a first guard band 611 and a second guard band 612, and its structure is similar to that of the reference Figures 9 to 11 The semiconductor device 400 described above will be described in detail below. Fig.13 The semiconductor device 600 is mainly based on the reference Figures 9 to 11The differences of the semiconductor device 400 are described.

[0115] The semiconductor device 600 may include a first electrode structure 630 connected to the first guard tape 611 on an upper surface of the first guard tape 611, and a second electrode structure 640 connected to the second guard tape 612 on an upper surface of the second guard tape 612. A power supply voltage may be applied to the first electrode structure 630, and a ground voltage may be applied to the second electrode structure 640.

[0116] According to example embodiments, the first electrode structure 630 may include at least one main wiring 631, a first contact 632 connected to the first main wiring 631 and the first guard tape 611, and a first sub wiring 634 connected to an end portion of the first main wiring 631 in the first direction D1. The first sub wiring 634 having an L shape may be connected to the first main wiring 631 in the second direction D2 from the first well region 602 toward the substrate 601.

[0117] The second electrode structure 640 may include at least one second main wiring 641, a second contact 642 connected to the second main wiring 641 and the second protection tape 612, and a second sub wiring 644 connected to an end of the second main wiring 641 in a direction opposite to the first direction D1. The second sub wiring 644 having an L shape may be connected to the second main wiring 641 in a direction opposite to the second direction D2.

[0118] According to example embodiments, the first electrode structure 630 and the second electrode structure 640 may be arranged in a Fig.13 The power capacitor is provided by structures joined to each other in a plane.

[0119] On the other hand, of course, the inventive concept can be applied even when the first well region doped with the second conductivity type impurities is a deep well region including one or more well regions.

[0120] Fig.14 is a diagram illustrating a semiconductor device according to example embodiments.

[0121] Fig.14 A substrate 101 , a first well region 102 , a first guard strip 111 , a second guard strip 112 , an insulating layer 120 , a first electrode structure 130 , and a second electrode structure 140 are provided.

[0122] According to example embodiments, the first well region 102 may be a deep well region including the third well region 104. Even in the case where the first well region 102 is a deep well region, in the substrate 101, the second guard band 112 may be formed around the first guard band 111 included in the first well region 102. In addition, the first electrode structure 130 connected to the first guard band 111 and the second electrode structure 140 connected to the second guard band 112 may provide a power capacitor. On the other hand, the third well region 104 in the deep well region may not be biased.

[0123] On the other hand, the semiconductor device may be formed in a structure in which a plurality of chips are stacked. According to example embodiments, a plurality of electrode structures for providing a power capacitor may be formed across two or more chips.

[0124] Fig.15 A semiconductor device 1000 according to example embodiments is shown.

[0125] Reference Fig.15 , the semiconductor device 1000 may include a first chip 700 and a second chip 800. The first chip 700 may include a first substrate 701 on which a semiconductor device is formed and a first insulating layer 720 on which a metal line is formed. Similar to the first chip 700, the second chip 800 may include a second substrate 801 and a second insulating layer 820. The semiconductor device 1000 may be formed by bonding the second chip 800 to the upper surface of the first chip 700 in an inverted state. The first chip 700 may be referred to as a lower chip, and the second chip 800 may be referred to as an upper chip.

[0126] According to example embodiments, first well region 702 is disposed on substrate 701, first guard band 711 is disposed in first well region 702, and second guard band 712 may be disposed in first substrate 701. Furthermore, first electrode structure 730 and second electrode structure 740 may be disposed in first insulating layer 720.

[0127] The first electrode structure 730 may include a plurality of first main wirings 731a, 731b and 731c, one or more first contacts 732, and a plurality of first vias 733a, 733b. In addition, the second electrode structure 740 may include a plurality of second main wirings 741a, 741b and 741c, one or more second contacts 742, and a plurality of second vias 743a, 743b.

[0128] The first electrode structure 730 may be connected to the upper surface of the first guard tape 711, may have a shape extending in a third direction D3 perpendicular to the upper surface of the first substrate 701, and may be exposed through the upper surface of the first insulating layer 720. Similarly, the second electrode structure 740 may be connected to the upper surface of the second guard tape 712, may extend in the third direction D3, and may be exposed through the upper surface of the first insulating layer 720.

[0129] According to example embodiments, the third electrode structure 830 and the fourth electrode structure 840 may be disposed in the second insulating layer 820. The third electrode structure 830 may include third main wirings 831a, 831b, and 831c, one or more third contacts 832, and a plurality of third vias 833a and 833b. In addition, the fourth electrode structure 840 may include fourth main wirings 841a, 841b, and 841c, one or more fourth contacts 842, and a plurality of fourth vias 843a, 843b.

[0130] The third main wiring 831c is exposed on the upper surface of the insulating layer 820, and the third contact 832 can be connected to the first contact plug 851 included in the second substrate 801. In addition, the fourth main wiring 841c is exposed on the upper surface of the insulating layer 820, and the fourth contact 842 can be connected to the second contact plug 852 included in the second substrate 801.

[0131] According to example embodiments, the first chip 700 and the second chip 800 are bonded so that the first main wiring 731 c and the third main wiring 831 c are electrically connected, and the second main wiring 741 c and the fourth main wiring 841 c may be electrically connected.

[0132] The second chip 800 may further include a power pad 861 and a ground pad 862. A power voltage may be applied to the first guard strip 711 through the first and third electrode structures 730 and 830. In addition, a ground voltage may be applied to the second guard strip 712 through the second and fourth electrode structures 740 and 840.

[0133] In addition, the first and third electrode structures 730 and 830 and the second and fourth electrode structures 740 and 840 may provide a power capacitor in a form in which they face each other.

[0134] According to an example embodiment, when a plurality of chips are stacked in the semiconductor device 1000, a power capacitor with increased capacitance may be provided by providing an electrode structure extending across the plurality of chips and facing each other, biasing the first well region 702 using a power supply voltage, and biasing the substrate 701 using a ground voltage.

[0135] For example, in the present invention, the memory cell area is implemented by the first chip and the peripheral circuit area is implemented by the second chip, and can be applied to flash memory devices such as COP (peripheral cell) NAND and bonded V-NAND (BVNAND), wherein the first chip and the second chip are vertically stacked.

[0136] On the other hand, in the semiconductor layout design device, the layout design of the second guard band formed around the first guard band and the second electrode structure formed on top of the second guard band can be automated. For example, a processor executing instructions loaded into a memory can determine the arrangement and shape of the second guard band and the second electrode structure in the main layout of the semiconductor device by executing the specified instructions.

[0137] Fig.16 is a diagram illustrating a semiconductor layout design method according to example embodiments.

[0138] In operation S11, a main layout of a semiconductor device may be obtained. The main layout of the semiconductor device may include an N-well region formed on a P-type substrate, a P-well region, a semiconductor element, a wiring pattern, and a first guard band formed for a well bias of the N-well region.

[0139] In operation S12, the arrangement and shape of the second guard band in the main layout may be determined. For example, the second guard band is in the P-type substrate, and the position and shape of the second guard band may be determined to have a shape extending in a direction parallel to the first guard band at a position at a predetermined distance from the first guard band.

[0140] In operation S13, the arrangement and shape of the second electrode structure in the main layout may be determined. For example, in the second electrode structure, the position and shape of the second electrode structure may be determined to have a shape facing or engaging the first electrode structure at a position opposite to the first electrode structure within the second guard band.

[0141] As described above, the semiconductor device according to the example embodiment includes a second guard band formed on a substrate doped with impurities of a first conductive type, thereby preventing the parasitic NPN transistor of the first well region and the substrate doped with impurities of a second conductive type and the second well region doped with impurities of the second conductive type from operating. Therefore, the leakage current of the semiconductor device can be reduced, and the reliability of the semiconductor device can be improved.

[0142] In a semiconductor device according to example embodiments, stability of power supply may be improved by using a first electrode structure electrically connected to a first guard band formed in a first well region and a second electrode structure electrically connected to a second guard band as a power capacitor.

[0143] While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device comprising: a substrate doped with impurities of a first conductivity type; a first well region, which is located in the substrate and is doped with impurities of a second conductivity type different from the first conductivity type; a first guard band extending in a first direction parallel to the upper surface of the substrate, located in the first well region, and doped with impurities of the second conductivity type; a second guard band facing the first guard band in the substrate and doped with impurities of the first conductivity type; a plurality of first main wirings stacked on the first guard band in a third direction perpendicular to the upper surface of the substrate, wherein some of the plurality of first main wirings are electrically connected to each other through a plurality of first vias and to the first guard band through one or more first contacts; a plurality of second main wirings, the plurality of second main wirings being stacked on the second protection tape along the third direction, wherein some of the plurality of second main wirings are electrically connected to each other through a plurality of second vias and are electrically connected to the second protection tape through one or more second contacts; a plurality of first finger lines, the plurality of first finger lines respectively extending from the plurality of first main wirings along a second direction, the second direction being parallel to the upper surface of the substrate and intersecting the first direction; a plurality of second finger lines extending from the plurality of second main wirings respectively along a fourth direction, the fourth direction being parallel to the upper surface of the substrate and opposite to the second direction; and an insulating layer located on side walls of the plurality of first main wirings, on side walls of the plurality of second main wirings, on side walls of the plurality of first finger lines, and on side walls of the plurality of second finger lines, The plurality of first finger lines and the plurality of second finger lines are alternated at least in the first direction.

2. The semiconductor device according to claim 1, wherein: The plurality of first finger lines are aligned in the first direction and the third direction, and Wherein, the plurality of second finger lines are aligned in the first direction and the third direction.

3. The semiconductor device according to claim 1, wherein: The plurality of first finger lines and the plurality of second finger lines alternate in the first direction and the third direction.

4. The semiconductor device according to claim 1, wherein: The plurality of first main wirings are electrically connected to the first power pad, and Wherein, the plurality of second main wirings are electrically connected to the ground pad.

5. The semiconductor device according to claim 1, further comprising: a third well region, which is located in the first well region, Wherein, the third well region is doped with impurities of the second conductivity type.

6. The semiconductor device according to claim 1, wherein: The first guard band is doped with a higher concentration of impurities than the first well region, and The second guard band is doped with impurities at a higher concentration than that of the substrate.

7. The semiconductor device according to claim 1, wherein: The first conductivity type is a P type, and the second conductivity type is an N type.

8. A semiconductor device comprising: a substrate doped with impurities of a first conductivity type; a first well region, which is located in the substrate and is doped with impurities of a second conductivity type different from the first conductivity type; a first guard band extending in a first direction parallel to the upper surface of the substrate, located in the first well region, and doped with impurities of the second conductivity type; a second guard band, which faces the first guard band, is located in the substrate and is doped with impurities of the first conductivity type; a plurality of first main wirings, the plurality of first main wirings being stacked on the first protection band along a third direction perpendicular to the substrate, wherein some of the plurality of first main wirings are electrically connected to each other through a plurality of first vias and are electrically connected to the first protection band through one or more first contacts; a plurality of second main wirings stacked on the second protection tape along the third direction, wherein some of the plurality of second main wirings are electrically connected to each other through a plurality of second vias and are electrically connected to the second protection tape through one or more second contacts; and an insulating layer located on side walls of the plurality of first main wirings and on side walls of the plurality of second main wirings, Wherein, the electrode structure is not between the plurality of first main wirings and the plurality of second main wirings.

9. The semiconductor device according to claim 8, wherein: The semiconductor device comprises: a first sub wiring extending in a second direction parallel to the upper surface, spanning the substrate and the first well region, and electrically connected to respective first ends of the plurality of first main wirings; and A second sub wiring extends in the second direction and is electrically connected to the respective second ends of the plurality of second main wirings.

10. The semiconductor device according to claim 9, wherein: The first main wiring, the second main wiring, the first sub wiring, and the second sub wiring have portions that are alternately disposed in the second direction.

11. The semiconductor device according to claim 9, wherein: Some of the first sub-routings and some of the second sub-routings have L-shapes, respectively.

12. The semiconductor device according to claim 8, further comprising: a plurality of first sub-routings, the plurality of first sub-routings respectively extending from the plurality of first main routings along a second direction parallel to the upper surface of the substrate and intersecting the first direction; a plurality of first finger lines extending from the plurality of first sub-routing lines along the first direction; a plurality of second sub-routings, the plurality of second sub-routings respectively extending from the plurality of second main routings along the second direction; as well as a plurality of second finger lines extending from the plurality of second sub-routing lines in a direction opposite to the first direction, The plurality of first finger lines and the plurality of second finger lines are alternated at least in the second direction.

13. The semiconductor device according to claim 8, wherein: In a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, a distance between the first guard band and the second guard band is a minimum distance defined by a layout design rule.

14. A semiconductor device comprising: a substrate doped with impurities of a first conductivity type; a first well region formed in the substrate and doped with impurities of a second conductivity type different from the first conductivity type; a first guard band extending in a first direction parallel to the upper surface of the substrate, located in the first well region, and doped with impurities of the second conductivity type; a second guard band, facing the first guard band, located in the substrate and doped with impurities of the first conductivity type; a first electrode structure electrically connected to the first guard strip; a second electrode structure electrically connected to the second guard tape; as well as an insulating layer, which is located on the sidewalls of the first electrode structure and the sidewalls of the second electrode structure, Wherein, the first electrode structure, the insulating layer and the second electrode structure provide a capacitor.

15. The semiconductor device according to claim 14, wherein: The first well region is configured to be biased to a first power supply voltage through the first electrode structure, and Wherein, the substrate is configured to be biased to a ground voltage through the second electrode structure.

16. The semiconductor device according to claim 15, wherein: The semiconductor device further comprises: a second well region, located in the substrate, doped with impurities of the second conductivity type, and spaced apart from the first well region; a third guard band doped with impurities of the second conductivity type and located in the second well region; and a fourth guard band, which faces the third guard band, is located in the substrate and is doped with impurities of the first conductivity type, The second well region is configured to be biased by a second power supply voltage, the second power supply voltage having a potential different from that of the first power supply voltage.

17. The semiconductor device according to claim 15, wherein: An upper surface of the first electrode structure and an upper surface of the second electrode structure are exposed to an upper surface of the insulating layer.

18. The semiconductor device according to claim 15, wherein: The substrate comprises a first substrate, wherein the insulating layer comprises a first insulating layer, and wherein the semiconductor device further comprises: a lower chip, comprising the first substrate, the first well region, the first guard band, the second guard band, the first electrode structure, the second electrode structure and the first insulating layer; and an upper chip, comprising a second substrate and a second insulating layer, wherein an upper surface of the second insulating layer is bonded to an upper surface of the first insulating layer, The upper chip further includes a third electrode structure electrically connected to the first electrode structure and a fourth electrode structure electrically connected to the second electrode structure in the second insulating layer.

19. The semiconductor device according to claim 18, wherein: The third electrode structure is electrically connected to a power pad, and the fourth electrode structure is electrically connected to a ground pad.

20. The semiconductor device according to claim 15, wherein The first electrode structure includes a plurality of first main wirings and a first sub-wiring, the plurality of first main wirings are stacked in a third direction perpendicular to the substrate and extend in the first direction, the first sub-wiring is electrically connected to corresponding ends of the plurality of first main wirings in a second direction from the first well region toward the substrate, and The second electrode structure includes a plurality of second main wirings and a second sub-wiring, the plurality of second main wirings are stacked along the third direction and extend along the first direction, and the second sub-wiring is electrically connected to corresponding ends of the plurality of second main wirings along a direction opposite to the second direction. The first electrode structure and the second electrode structure have parts alternately arranged in the second direction.

Images