Array substrate and manufacturing method thereof, display panel and display device

Abstract

The invention provides an array substrate. The array substrate comprises a substrate, a transistor and an insulating layer. The transistor comprises a grid electrode, an active layer, a source electrode, a drain electrode and a protection body, the insulating layer covers the grid electrode to one surface of the substrate, and the active layer is arranged on the surface, back to the substrate, of the insulating layer. The source electrode and the drain electrode are arranged on the surface, back to the substrate, of the insulating layer, the source electrode and the drain electrode are oppositely arranged in a spaced mode in the first direction, the source electrode and the drain electrode are connected with the active layer, the protection body is arranged on the surface, back to the insulating layer, of the active layer, and the protection body is spaced from the source electrode and the drain electrode. The protection body is used for slowing down flowing of liquid medicine needed by patterning of the source electrode and the drain electrode, the phenomenon that the active layer is corroded and damaged by the liquid medicine is reduced under the condition that sufficient etching of the source electrode and the drain electrode is guaranteed, and therefore vertical display Mura of the display panel caused by negative deviation of DR characteristics of the transistor is prevented. The invention further provides a manufacturing method of the array substrate, a display panel and a display device.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a method for manufacturing an array substrate, a display panel, and a display device. Background Art

[0002] With the development of display technology, display devices have been widely used in many fields and industries. The display device includes a display panel for displaying images, the display panel includes a plurality of sub-pixels, and each sub-pixel is provided with a transistor for controlling the potential.

[0003] A transistor usually includes a gate, a source, a drain and an active layer. In the manufacturing process of the transistor, when the source and drain are patterned through a mask, the chemical solution used will cause certain corrosion damage to the active layer, causing the dielectric relaxation (DR) characteristics of the transistor to shift negatively, and ultimately causing vertical display Mura on the display panel.

[0004] Therefore, how to solve the problem in the prior art that the DR characteristics of the transistor may be negatively shifted due to the corrosion damage of the active layer by the chemical solution is an urgent problem to be solved by those skilled in the art. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the purpose of the present application is to provide an array substrate, a method for manufacturing an array substrate, a display panel and a display device, which aims to solve the problem in the prior art that in the process of transistor manufacturing, the DR characteristics of the transistor may have a negative shift due to the corrosion damage of the active layer by the chemical solution.

[0006] In a first aspect, an embodiment of the present application provides an array substrate, the array substrate comprising a substrate, a transistor and an insulating layer, wherein the transistor and the insulating layer are arranged on the substrate. The transistor comprises a gate, an active layer, a source, a drain and at least one protective body, the insulating layer covers the gate to a surface of the substrate, the active layer is arranged on the surface of the insulating layer facing away from the substrate, and the orthographic projection of the active layer on the substrate and the orthographic projection of the gate on the substrate at least partially overlap. The source and the drain are both arranged on the surface of the insulating layer facing away from the substrate, and the source and the drain are arranged oppositely and spaced along a first direction. The source and the drain are respectively connected to the active layer, the protective body is arranged on the surface of the active layer facing away from the insulating layer, and the protective body is spaced from the source and the drain respectively. Wherein, the protective body is used to slow down the flow of the liquid required for patterning the source and the drain.

[0007] In summary, the array substrate provided in the embodiment of the present application slows down the flow of the solution required for patterning the source and drain through the protective body, and reduces the corrosion damage of the solution to the active layer while ensuring that the source and drain are fully etched, thereby preventing the display panel from having vertical display Mura caused by the negative shift of the DR characteristics of the transistor.

[0008] In an exemplary embodiment, a size of the active layer along a second direction is 4 um to 8 um, and a size of the protective body in the second direction is larger than a size of the active layer along the second direction, wherein the second direction is perpendicular to the first direction.

[0009] In an exemplary embodiment, a size of the protection body in the first direction is 0.5 um to 3 um.

[0010] In an exemplary embodiment, a plurality of the protection bodies are arranged at intervals along the first direction, and a distance between two adjacent protection bodies is 3 um to 8 um.

[0011] In an exemplary embodiment, the source electrode is spaced 3 um to 8 um from the nearest protection body.

[0012] In an exemplary embodiment, the drain electrode is spaced 3 um to 8 um from the nearest protection body.

[0013] In an exemplary embodiment, the source electrode, the drain electrode, and the protection body are made of the same material, and the source electrode, the drain electrode, and the protection body are formed in the same etching process.

[0014] In a second aspect, an embodiment of the present application further provides a method for manufacturing an array substrate, the method for manufacturing the array substrate comprising: providing a substrate, sequentially forming a gate, an insulating layer and an active layer on the substrate, the insulating layer covering the gate to the substrate, and the active layer being located on the surface of the insulating layer facing away from the gate. Forming a conductive layer on the surface of the insulating layer facing away from the substrate, the conductive layer covering the active layer. Forming a first mask body and a second mask body on the surface of the conductive layer facing away from the insulating layer, and forming at least one third mask body on the surface of the conductive layer facing away from the active layer. Wherein, at least one of the third mask bodies is located between the first mask body and the second mask body, and the first mask body, the second mask body and the third mask body are spaced apart from each other. The conductive layer and the staggered portions of the first mask body, the second mask body and the third mask body are removed to form a source electrode, a drain electrode and at least one protective body, wherein at least one protective body is located between the source electrode and the drain electrode, and the source electrode, the drain electrode and the protective body are spaced from each other, and the source electrode and the drain electrode are both connected to the active layer, and at least one protective body is located on the surface of the active layer facing away from the insulating layer. The first mask body, the second mask body and the third mask body are removed.

[0015] To sum up, the manufacturing method of the array substrate provided in the embodiment of the present application can slow down the flow of the solution required for patterning the source and drain by forming a protective body on the active layer, thereby reducing the corrosion damage of the solution to the active layer while ensuring that the source and drain are fully etched.

[0016] In a third aspect, an embodiment of the present application further provides a display panel, which includes a driver chip and the above-mentioned array substrate, wherein the driver chip is electrically connected to the array substrate, and the driver chip is used to provide an electrical signal for display to the array substrate.

[0017] In summary, the display panel provided in the embodiment of the present application includes a driving chip and an array substrate. The array substrate slows down the flow of the solution required for patterning the source and the drain through a protective body, thereby reducing the corrosion damage of the active layer by the solution while ensuring that the source and the drain are fully etched, thereby preventing the display panel from having vertical display Mura caused by the negative shift of the DR characteristics of the transistor.

[0018] In a fourth aspect, an embodiment of the present application further provides a display device, comprising a power board and the above-mentioned display panel, wherein the power board is electrically connected to the display panel, and the power board is used to supply power to the display panel.

[0019] In summary, the display device provided in the embodiment of the present application includes a power board and a display panel. The display panel includes an array substrate, and the array substrate slows down the flow of the liquid required for patterning the source and drain through a protective body, and reduces the corrosion damage of the liquid to the active layer while ensuring that the source and drain are fully etched, thereby preventing the display panel from having vertical display Mura caused by the negative shift of the DR characteristics of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A schematic diagram of the layer structure of a display device disclosed in the first embodiment of the present application;

[0022] Figure 2 A schematic diagram of the layer structure of a display panel disclosed in the second embodiment of the present application;

[0023] Figure 3 This is a schematic diagram of a first layer structure of an array substrate disclosed in the third embodiment of the present application;

[0024] Figure 4 This is a schematic diagram of a second layer structure of an array substrate disclosed in the third embodiment of the present application;

[0025] Figure 5 A schematic flow chart of a method for manufacturing an array substrate disclosed in a fourth embodiment of the present application;

[0026] Figure 6 for Figure 5 The schematic diagram of the structure formed corresponding to step S10 shown;

[0027] Figure 7 for Figure 5 The schematic diagram of the structure formed corresponding to step S20 shown;

[0028] Figure 8 for Figure 5 The schematic diagram of the structure formed corresponding to step S30 shown;

[0029] Fig. 9 for Figure 5 The schematic diagram of the structure formed corresponding to step S40 shown;

[0030] Fig.10 A schematic diagram of the structure of an active layer formed by an existing process;

[0031] Fig.11 A schematic diagram of the structure of an active layer formed by the method for manufacturing an array substrate disclosed in this application;

[0032] Fig.12 It is a schematic diagram comparing the DR characteristic curve of the transistor of the present application with the DR characteristic curve of the transistor of the prior art.

[0033] Description of reference numerals:

[0034] 1-display device; 10-display panel; 11-array substrate; 12-liquid crystal layer; 13-color filter substrate;

[0035] 30-backlight module; 111-substrate; 112-transistor; 113-insulating layer; 110-conductive layer; 120-first mask body; 130-second mask body; 140-third mask body; 1121-gate; 1122-active layer; 1123-source; 1124-drain; 1125-protective body; Step S10-Step S50-steps of the method for manufacturing the array substrate. DETAILED DESCRIPTION

[0036] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0037] The following descriptions of the embodiments are with reference to the attached diagrams to illustrate specific embodiments that the present application can be used to implement. The serial numbers for the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in the present application, unless otherwise specified, include direct and indirect connections (couplings). The directional terms mentioned in the present application, such as "upper", "lower", "front", "back", "left", "right", "inside", "outside", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the present application, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application.

[0038] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be fixedly connected, detachably connected, or integrally connected; it can be mechanically connected; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including", "may include", "include", or "may include" used in this application indicate the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit one or more other functions, operations, elements, etc. In addition, the terms "including" or "include" indicate the existence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and do not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusions. It should also be understood that "at least one" described herein means one or more, such as one, two or three, etc., and "plurality" means at least two, such as two or three, etc., unless otherwise clearly defined.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0040] See also Figure 1 , Figure 1 Schematic diagram of the layer structure of the display device disclosed in the first embodiment of the present application. The display device 1 can be used for electronic devices including but not limited to televisions, tablet computers, laptop computers, desktop computers, mobile phones, car displays, etc. According to the embodiments of the present application, the specific type of the display device 1 is not particularly limited, and those skilled in the art can design it accordingly according to the specific use requirements of the display device 1, which will not be repeated here.

[0041] The display device 1 includes a stacked display panel 10 and a backlight module 30 . The display panel 10 is arranged on the light-emitting side of the backlight module 30 . The backlight module 30 is used to provide backlight. The display panel 10 is used to display images under the backlight provided by the backlight module 30 .

[0042] In the embodiment of the present application, Figure 1The backlight module 30 shown can be an edge-lit backlight module, or a direct-lit backlight module. The display panel 10 can be a twisted nematic (TN) display panel, a vertical alignment (VA) display panel, an in-plane switching (IPS) display panel, or a fringe field switching (FFS) display panel, and the present application does not impose any specific restrictions on this.

[0043] In an exemplary embodiment, the display device 1 may also include other necessary components and parts such as a driving board, a power board, a high-voltage board, and a key control board, which may be supplemented accordingly by those skilled in the art according to the specific type and actual function of the display device 1, and will not be described in detail here. The power board is electrically connected to the display panel, and the power board is used to supply power to the display panel.

[0044] In some embodiments, the display device 1 may further include a processor and a memory, wherein the processor is electrically connected to the display panel 10 and is used to control the display panel 10 to display. The memory is electrically connected to the processor and is used to store program codes required for the processor to run, control the display content of the display panel 10, etc.

[0045] In an exemplary embodiment, the memory may include a volatile memory (Volatile Memory), such as a random access memory (Random Access Memory, RAM); the memory may also include a non-volatile memory (NVM), such as a read-only memory (Read-Only Memory, ROM), a flash memory (Flash Memory, FM), a hard disk drive (Hard Disk Drive, HDD) or a solid-state drive (SSD). The memory may also include a combination of the above-mentioned types of memory.

[0046] In an exemplary embodiment, the processor includes one or more general-purpose processors, wherein a general-purpose processor can be any type of device capable of processing electronic instructions, including a central processing unit (CPU), a microprocessor, a microcontroller, a main processor, a controller, etc. The processor is used to execute various types of digital storage instructions, such as software or firmware programs stored in a memory, which enables the computing device to provide a wide variety of services.

[0047] See also Figure 2 , Figure 2 Schematic diagram of the layer structure of the display panel disclosed in the second embodiment of the present application. The display panel 10 includes an array substrate 11, a liquid crystal layer 12 and a color filter substrate 13. The array substrate 11 and the color filter substrate 13 are arranged opposite to each other and spaced apart, and the liquid crystal layer 12 is arranged between the array substrate 11 and the color filter substrate 13. The array substrate 11 and the color filter substrate 13 are used to form a preset electric field, and the preset electric field is used to drive the liquid crystal molecules of the liquid crystal layer 12 to deflect, so as to change the transmittance of the liquid crystal layer 12.

[0048] It should be noted that the array substrate 11 of the present application can also be applied to an organic light-emitting diode (OLED) display panel, a mini light-emitting diode (Mini LED) display panel, and a micron light-emitting diode (Micro LED) display panel, and the present application does not impose specific restrictions on this. The display panel 10 may also include a driver chip, which is electrically connected to the array substrate, and the driver chip is used to provide an electrical signal for display to the array substrate.

[0049] See also Figure 3 , Figure 3 This is a schematic diagram of the first layer structure of the array substrate disclosed in the third embodiment of the present application. For the convenience of description, it is defined as Figure 3 The length direction of the array substrate 11 is the X-axis direction, the width direction of the array substrate 11 is the Y-axis direction, the thickness direction of the array substrate 11 is the Z-axis direction, and the X-axis direction, the Y-axis direction and the Z-axis direction are perpendicular to each other. The X-axis direction can also be defined as a first direction, and the Y-axis direction can also be defined as a second direction.

[0050] The directional terms such as "upper", "lower", "top", and "bottom" mentioned in the description of the embodiments of the present application are based on the Figure 3 The description of the orientation shown uses the positive direction of the Z axis as “up” and “top”, and the negative direction of the Z axis as “down” and “bottom”, which does not constitute a limitation on the array substrate 11 in actual application scenarios.

[0051] Specifically, the array substrate 11 includes a substrate 111, a plurality of transistors 112 and an insulating layer 113. Each of the transistors 112 includes a gate 1121, an active layer 1122, a source 1123, a drain 1124 and a protective body 1125. The gate 1121 and the insulating layer 113 are arranged on a surface of the substrate 111, and the insulating layer 113 also covers the peripheral side of the gate 1121 and the surface of the gate 1121 facing away from the substrate 111, that is, the insulating layer 113 covers the gate 1121 to a surface of the substrate 111. The active layer 1122 is arranged on the surface of the insulating layer 113 facing away from the substrate 111, and the orthographic projection of the active layer 1122 in the Z-axis direction at least partially overlaps with the orthographic projection of the gate 1121 in the Z-axis direction, that is, the orthographic projection of the active layer 1122 on the substrate 111 at least partially overlaps with the orthographic projection of the gate 1121 on the substrate 111. The source electrode 1123 and the drain electrode 1124 are both arranged on the surface of the insulating layer 113 facing away from the substrate 111. The source electrode 1123 and the drain electrode 1124 are arranged opposite to each other and spaced apart along the X-axis direction. The source electrode 1123 and the drain electrode 1124 are respectively connected to opposite sides of the active layer 1122. The orthographic projection of part of the source electrode 1123 in the Z-axis direction partially overlaps with the orthographic projection of the gate electrode 1121 in the Z-axis direction, and the orthographic projection of part of the drain electrode 1124 in the Z-axis direction partially overlaps with the orthographic projection of the gate electrode 1121 in the Z-axis direction, that is, the orthographic projections of part of the source electrode 1123 and part of the drain electrode 1124 on the substrate 111 both overlap with the orthographic projection of the gate electrode 1121 on the substrate 111. The protection body 1125 is disposed on the surface of the active layer 1122 facing away from the insulating layer 113 , and is located between two opposite ends of the source electrode 1123 and the drain electrode 1124 , and is spaced apart from the source electrode 1123 and the drain electrode 1124 , respectively.

[0052] The insulating layer 113 is used to insulate the gate 1121 from the active layer 1122, the gate 1121 from the source 1123, and the gate 1121 from the drain 1124. The source 1123 is electrically connected to the active layer 1122, and the drain 1124 is electrically connected to the active layer 1122. The gate 1121 is used to form a control electric field, and the control electric field is used to turn on the active layer 1122, and then the source 1123 and the drain 1124 are turned on. The protective body 1125 is used to slow down the flow of the liquid required for patterning the source 1123 and the drain 1124, and weaken the corrosion damage of the liquid to the active layer 1122, so as to prevent the display panel 10 from having vertical display Mura caused by the negative shift of the DR characteristics of the transistor 112. The patterning refers to the process of etching the conductive layer to form the source 1123 and the drain 1124.

[0053] In an exemplary embodiment, the number of the protection body 1125 is one.

[0054] In an exemplary embodiment, the source electrode 1123, the drain electrode 1124 and the protection body 1125 are made of the same material. The source electrode 1123, the drain electrode 1124 and the protection body 1125 are formed in the same etching process.

[0055] See also Figure 4 , Figure 4 The second layer structure diagram of the array substrate disclosed in the third embodiment of the present application is shown in FIG. The difference between the array substrate 11 with the second layer structure and the array substrate 11 with the first layer structure is that the number of the protective bodies 1125 of the array substrate 11 with the second layer structure is two.

[0056] It should be noted that for the convenience of illustration, Figure 3 The number of the protection body 1125 in is 1, Figure 4 The number of the protection bodies 1125 is 2. In fact, the number of the protection bodies 1125 may be at least one, that is, the number of the protection bodies 1125 may be 1, 2, or more than 2, and the present application does not impose any specific limitation on this.

[0057] The plurality of protection bodies 1125 are sequentially spaced apart along the X-axis direction.

[0058] In an exemplary embodiment, the size of the active layer 1122 along the X-axis direction is 20um to 100um, for example, 20um, 30um, 37um, 45um, 50um, 61um, 76um, 80um, 90um, 100um, or other values, which is not specifically limited in the present application.

[0059] In an exemplary embodiment, the size of the active layer 1122 along the Y-axis direction is 4um to 8um, for example, 4um, 5um, 5.5um, 5.8um, 6um, 6.3um, 7um, 7.6um, 8um, or other values, which are not specifically limited in the present application. The size of the protective body 1125 in the Y-axis direction is greater than the size of the active layer 1122 along the Y-axis direction.

[0060] It can be understood that by setting the size of the protective body 1125 in the Y-axis direction to be larger than the size of the active layer 1122 along the Y-axis direction, the protective body 1125 can better slow down the flow of the drug solution, and can also reduce the contact area between the active layer 1122 and the drug solution, thereby reducing the corrosion damage of the drug solution to the active layer 1122.

[0061] In an exemplary embodiment, the size of the protective body 1125 in the X-axis direction is 0.5um to 3um, for example, 0.5um, 0.8um, 1um, 1.4um, 1.9um, 2um, 2.5um, 3um, or other values, which is not specifically limited in the present application.

[0062] It can be understood that if the size of the protective body 1125 in the X-axis direction is less than 0.5um, it is easy to cause the protective body 1125 to fall off from the active layer 1122 and increase the contact area between the active layer 1122 and the liquid medicine. If the size of the protective body 1125 in the X-axis direction is greater than 3um, it is easy to cause the protective body 1125 to couple with the source electrode 1123 and thus affect the potential of the source electrode 1123, and it is easy to cause the protective body 1125 to couple with the drain electrode 1124 and thus affect the potential of the drain electrode 1124. Therefore, by setting the size of the protective body 1125 in the X-axis direction to 0.5um to 3um, it is possible to prevent the protective body 1125 from falling off from the active layer 1122, reduce the contact area between the active layer 1122 and the liquid medicine, and prevent the protective body 1125 from affecting the potential of the source electrode 1123 and the drain electrode 1124.

[0063] In an exemplary embodiment, the interval between two adjacent protective bodies 1125 is 3um to 8um, for example, 3um, 3.4um, 4um, 4.8um, 5um, 5.5um, 6um, 7um, 7.2um, 8um, or other values, and the present application does not impose any specific limitation on this.

[0064] It can be understood that if the interval between two adjacent protective bodies 1125 is less than 3um, the two adjacent protective bodies 1125 are easily coupled to each other, thereby affecting the resistance and potential of the active layer 1122. If the interval between two adjacent protective bodies 1125 is greater than 8um, the contact area between the active layer 1122 and the liquid medicine will be increased. Therefore, setting the interval between two adjacent protective bodies 1125 to 3um to 8um can avoid the mutual coupling of the two protective bodies 1125 and reduce the contact area between the active layer 1122 and the liquid medicine.

[0065] In an exemplary embodiment, the source electrode 1123 is spaced 3um to 8um from the nearest protective body 1125, for example, 3um, 3.4um, 4um, 4.8um, 5um, 5.5um, 6um, 7um, 7.2um, 8um, or other values, and the present application does not impose any specific limitation on this.

[0066] It can be understood that by spacing the source electrode 1123 and the nearest protection body 1125 by 3 um to 8 um, it is possible to avoid mutual coupling between the source electrode 1123 and the protection body 1125 and reduce the contact area between the active layer 1122 and the drug solution.

[0067] In an exemplary embodiment, the drain 1124 is spaced 3um to 8um from the nearest protective body 1125, for example, 3um, 3.4um, 4um, 4.8um, 5um, 5.5um, 6um, 7um, 7.2um, 8um, or other values, and the present application does not impose any specific limitation on this.

[0068] It can be understood that by spacing the drain electrode 1124 and the nearest protective body 1125 by 3 um to 8 um, mutual coupling between the drain electrode 1124 and the protective body 1125 can be avoided and the contact area between the active layer 1122 and the drug solution can be reduced.

[0069] It should be noted that for the convenience of presentation, Figure 3 and Figure 4 Only one transistor is shown in each of the figures. The number of transistors in the array substrate 11 is determined by the number of sub-pixels, and one transistor is disposed in each sub-pixel.

[0070] In an exemplary embodiment, the array substrate 11 may further include a planar layer and a plurality of pixel electrodes, wherein the planar layer covers the source electrode 1123, the drain electrode 1124, the active layer 1122 and the protective body 1125. The plurality of pixel electrodes are disposed on a surface of the planar layer facing away from the active layer 1122, and one pixel electrode is electrically connected to one drain electrode 1124.

[0071] The color filter substrate 13 may further include a common electrode, and the common electrode and the pixel electrode form the preset electric field.

[0072] In summary, the array substrate 11 provided in the embodiment of the present application includes a substrate 111, a transistor 112 and an insulating layer 113, wherein the transistor 112 includes a gate 1121, an active layer 1122, a source 1123, a drain 1124 and a protective body 1125. The insulating layer 113 covers the gate 1121 to a surface of the substrate 111. The active layer 1122 is arranged on the surface of the insulating layer 113 facing away from the substrate 111, and the orthographic projection of the active layer 1122 in the Z-axis direction coincides with the orthographic projection of the gate 1121 in the Z-axis direction. The source 1123 and the drain 1124 are both arranged on the surface of the insulating layer 113 facing away from the substrate 111, and the source 1123 and the drain 1124 are opposite and spaced apart along the X-axis direction, and the source 1123 and the drain 1124 are respectively connected to the active layer 1122. The protective body 1125 is disposed on the surface of the active layer 1122 facing away from the insulating layer 113, and the protective body 1125 is spaced apart from the source electrode 1123 and the drain electrode 1124. The protective body 1125 is used to slow down the flow of the liquid required for patterning the source electrode 1123 and the drain electrode 1124, and reduces the corrosion damage of the active layer 1122 by the liquid while ensuring that the source electrode 1123 and the drain electrode 1124 are fully etched, thereby preventing the display panel 10 from having vertical display Mura caused by the negative shift of the DR characteristic of the transistor 112.

[0073] See also Figure 5 , Figure 5 This is a flow chart of a method for manufacturing an array substrate disclosed in the fourth embodiment of the present application. The method for manufacturing an array substrate is used to form the array substrate 11 of the third embodiment. For the description of the similarities between the structure involved in the method for manufacturing an array substrate and the structure of the array substrate 11, please refer to the description of the array substrate 11 in the above embodiment, which will not be repeated here. Figure 3 , Figure 4 and Figure 5 The manufacturing method of the array substrate 11 specifically includes the following steps.

[0074] It should be noted that, for the sake of convenience, the description of the manufacturing method of the array substrate 11 and its diagrams all show one transistor, but in fact, multiple transistors are formed together.

[0075] Step S10 , providing a substrate 111 , sequentially forming a gate 1121 , an insulating layer 113 and an active layer 1122 on the substrate 111 , wherein the insulating layer 113 covers the gate 1121 to the substrate 111 , and the active layer 1122 is located on a surface of the insulating layer 113 facing away from the gate 1121 .

[0076] Specifically, see Figure 6 , Figure 6 for Figure 5The schematic diagram of the structure formed in step S10 is shown in FIG. The orthographic projection of the gate 1121 on the substrate 111 at least partially overlaps with the orthographic projection of the active layer 1122 on the substrate 111 .

[0077] Step S20 , forming a conductive layer 110 on a surface of the insulating layer 113 facing away from the substrate 111 , wherein the conductive layer 110 covers the active layer 1122 .

[0078] Specifically, see Figure 7 , Figure 7 for Figure 5 The schematic diagram of the structure formed in step S20 is shown. A conductive layer 110 is formed on the surface of the insulating layer 113 facing away from the substrate 111 by a deposition process, and the conductive layer 110 covers the peripheral side of the active layer 1122 and the surface of the active layer 1122 facing away from the insulating layer 113. The material of the conductive layer 110 includes metal.

[0079] Step S30, forming a first mask body 120 and a second mask body 130 on a surface of the conductive layer 110 facing away from the insulating layer 113, and forming at least one third mask body 140 on a surface of the conductive layer 110 facing away from the active layer 1122, wherein the at least one third mask body 140 is located between the first mask body 120 and the second mask body 130, and the first mask body 120, the second mask body 130 and the third mask body 140 are spaced apart from each other.

[0080] Specifically, see Figure 8 , Figure 8 for Figure 5 The schematic diagram of the structure formed corresponding to step S30 is shown. The first mask body 120, the second mask body 130 and at least one third mask body 140 are formed by coating, exposure, development and other processes, wherein at least one third mask body 140 is located between the first mask body 120 and the second mask body 130, and the first mask body 120, the second mask body 130 and the third mask body 140 are spaced from each other. The orthographic projection of part of the first mask body 120 on the substrate 111 overlaps with the orthographic projection of the active layer 1122 on the substrate 111, the orthographic projection of part of the second mask body 130 on the substrate 111 overlaps with the orthographic projection of the active layer 1122 on the substrate 111, and the orthographic projection of the third mask body 140 on the substrate 111 is located within the orthographic projection of the active layer 1122 on the substrate 111. The first mask body 120, the second mask body 130 and the third mask body 140 can all be photoresists.

[0081] It should be noted that Figure 8 Only one third mask body 140 is shown in FIG. 1 , and the number of the third mask bodies 140 may be two or more than two.

[0082] Step S40, removing the staggered portions of the conductive layer 110 and the first mask body 120, the second mask body 130 and the third mask body 140 to form a source 1123, a drain 1124 and a protective body 1125, wherein the protective body 1125 is located between the source 1123 and the drain 1124, and the source 1123, the drain 1124 and the protective body 1125 are spaced apart from each other, and the source 1123 and the drain 1124 are both connected to the active layer 1122, and the protective body 1125 is located on the surface of the active layer 1122 facing away from the insulating layer 113.

[0083] Specifically, see Fig. 9 , Fig. 9 for Figure 5 The schematic diagram of the structure formed corresponding to step S40 is shown. The staggered portions of the conductive layer 110 and the first mask body 120, the second mask body 130 and the third mask body 140 are removed by a wet process to form a source 1123, a drain 1124 and a protective body 1125, wherein the protective body 1125 is located between the source 1123 and the drain 1124, and the source 1123, the drain 1124 and the protective body 1125 are spaced from each other. Specifically, the orthographic projection of the source 1123 on the substrate 111 coincides with the orthographic projection of the first mask body 120 on the substrate 111, the orthographic projection of the drain 1124 on the substrate 111 coincides with the orthographic projection of the second mask body 130 on the substrate 111, and the orthographic projection of the protective body 1125 on the substrate 111 coincides with the orthographic projection of the third mask body 140 on the substrate 111. Moreover, the source electrode 1123 and the drain electrode 1124 are both connected to the active layer 1122 , and the protection body 1125 is located on the surface of the active layer 1122 facing away from the insulating layer 113 .

[0084] The gate 1121 , the active layer 1122 , the source 1123 , the drain 1124 and the protection body 1125 constitute the transistor 112 .

[0085] S50 , removing the first mask body 120 , the second mask body 130 and the third mask body 140 .

[0086] See also Fig.10 and Fig.11 , Fig.10 The schematic diagram of the structure of the active layer formed by the existing process is as follows: Fig.11The schematic diagram of the structure of the active layer formed by the method for manufacturing the array substrate disclosed in the present application. The thickness of the active layer formed by the existing process is 73.69nm, and the thickness of the active layer 1122 formed by the method for manufacturing the array substrate of the present application is 75.92nm. That is, the thickness of the active layer formed by the method for manufacturing the array substrate of the present application is increased by 2.23nm compared with the thickness of the active layer formed by the existing process. Therefore, the method for manufacturing the array substrate of the present application can slow down the flow of the liquid required for patterning the source 1123 and the drain 1124 by forming a protective body 1125 on the active layer 1122, thereby reducing the corrosion damage of the liquid to the active layer 1122 while ensuring that the source 1123 and the drain 1124 are fully etched.

[0087] See also Fig.12 , Fig.12 Schematic diagram comparing the DR characteristic curve of the transistor of the present application with the DR characteristic curve of the transistor of the prior art. Fig.12 The first curve shown in is the DR characteristic curve of the transistor of the present application, and the second curve is the DR characteristic curve of the transistor of the prior art. Fig.10 and Fig.11 , the thickness of the active layer of the transistor of the present application is greater than that of the transistor of the prior art, so that the DR characteristic curve of the transistor of the present application is positively offset by about 3V compared with the DR characteristic curve of the transistor of the prior art. Moreover, the first curve is relatively close to the normal curve, wherein the normal curve is the DR characteristic curve of the transistor under the standard thickness of the active layer. Therefore, the transistor 112 formed by the manufacturing method of the array substrate disclosed in the present application can prevent the vertical display Mura of the display panel 10 caused by the negative offset of the DR characteristic of the transistor 112.

[0088] Furthermore, the process of forming the protection body 1125 of the present application does not increase the number of masks or the number of processes, and does not increase the cost by simply changing the position and number of the mask bodies.

[0089] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0090] It should be understood that the application of this application is not limited to the above examples. For ordinary technicians in this field, they can make improvements or changes based on the above description, and all these improvements and changes should fall within the scope of protection of the claims attached to this application. Ordinary technicians in this field can understand that all or part of the processes of the above embodiments are implemented, and equivalent changes made according to the claims of this application still fall within the scope covered by this application.

Claims

1. An array substrate, comprising a substrate, a transistor and an insulating layer, wherein the transistor and the insulating layer are arranged on the substrate, characterized in that: The transistor includes a gate, an active layer, a source, a drain and at least one protective body, the insulating layer covers the gate to a surface of the substrate, the active layer is arranged on the surface of the insulating layer facing away from the substrate, and the orthographic projection of the active layer on the substrate and the orthographic projection of the gate on the substrate at least partially overlap, the source and the drain are both arranged on the surface of the insulating layer facing away from the substrate, and the source and the drain are opposite and spaced apart along a first direction, the source and the drain are respectively connected to the active layer, the protective body is arranged on the surface of the active layer facing away from the insulating layer, and the protective body is spaced apart from the source and the drain respectively; wherein the protective body is used to slow down the flow of the solution required for patterning the source and the drain.

2. The array substrate according to claim 1, characterized in that: The size of the active layer along the second direction is 4um to 8um, and the size of the protection body in the second direction is larger than the size of the active layer along the second direction, wherein the second direction is perpendicular to the first direction.

3. The array substrate according to claim 1, characterized in that: The size of the protection body in the first direction is 0.5um to 3um.

4. The array substrate according to claim 1, wherein: The plurality of protection bodies are arranged at intervals along the first direction, and the interval between two adjacent protection bodies is 3um to 8um.

5. The array substrate according to claim 1, wherein: The source electrode is spaced 3 um to 8 um from the nearest protection body.

6. The array substrate according to claim 1, characterized in that: The drain electrode is spaced 3 um to 8 um from the nearest protection body.

7. The array substrate according to claim 1, wherein: The source electrode, the drain electrode and the protection body are made of the same material, and the source electrode, the drain electrode and the protection body are formed in the same etching process.

8. A method for manufacturing an array substrate, characterized in that: Used to form the array substrate according to any one of claims 1 to 7, the manufacturing method of the array substrate comprising: Providing a substrate, and sequentially forming a gate, an insulating layer and an active layer on the substrate, wherein the insulating layer covers the gate to the substrate, and the active layer is located on a surface of the insulating layer facing away from the gate; forming a conductive layer on a surface of the insulating layer facing away from the substrate, wherein the conductive layer covers the active layer; A first mask body and a second mask body are formed on a surface of the conductive layer facing away from the insulating layer, and at least one third mask body is formed on a surface of the conductive layer facing away from the active layer, wherein the at least one third mask body is located between the first mask body and the second mask body, and the first mask body, the second mask body and the third mask body are spaced apart from each other; Removing the staggered portions of the conductive layer and the first mask body, the second mask body and the third mask body to form a source electrode, a drain electrode and at least one protective body, wherein at least one of the protective bodies is located between the source electrode and the drain electrode, and the source electrode, the drain electrode and the protective bodies are spaced from each other, and the source electrode and the drain electrode are both connected to the active layer, and at least one of the protective bodies is located on the surface of the active layer facing away from the insulating layer; The first mask body, the second mask body and the third mask body are removed.

9. A display panel, characterized in that: The invention comprises a driving chip and an array substrate as claimed in any one of claims 1 to 7, wherein the driving chip is electrically connected to the array substrate, and the driving chip is used to provide an electrical signal for display to the array substrate.

10. A display device, characterized in that: It comprises a power board and the display panel as claimed in claim 9, wherein the power board is electrically connected to the display panel and is used to supply power to the display panel.

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