Semiconductor device

Abstract

The present application provides a semiconductor device, comprising: a substrate having a first conductivity type; the epitaxial layer is arranged on the substrate, and the epitaxial layer has a second conduction type different from the first conduction type; the buried layer is arranged in the substrate; the first well region is arranged in the epitaxial layer and has the second conduction type; and a second well region disposed in the epitaxial layer and having the first conductivity type. The first well region directly contacts the buried layer. The second well region directly contacts the first well region in the horizontal direction and directly contacts the buried layer in the vertical direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and more particularly to semiconductor devices that use buried layers to improve electrostatic discharge (ESD) efficiency. Background Art

[0002] Integrated circuits can be severely damaged by various electrostatic discharge events. One major electrostatic discharge mechanism comes from the human body, called the human-body model (HBM). The human body can generate a sharp current of several amperes to the integrated circuit in about 100 nanoseconds and burn it. The second electrostatic discharge mechanism comes from metal objects, called the machine model (MM), which has a higher rise time and current level than the human body model. The third electrostatic discharge mechanism comes from the integrated circuit itself, called the charged-device model (CDM), where the accumulated charge is discharged to the ground in a rise time of less than 0.5 nanoseconds. Therefore, effective electrostatic protection devices are needed to protect integrated circuits from the hazards of electrostatic discharge. Summary of the invention

[0003] A semiconductor device includes: a substrate having a first conductivity type; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a second conductivity type different from the first conductivity type; a buried layer disposed in the substrate; a first well region disposed in the epitaxial layer and having the second conductivity type; and a second well region disposed in the epitaxial layer and having the first conductivity type. The first well region directly contacts the buried layer. The second well region directly contacts the first well region in a horizontal direction and directly contacts the buried layer in a vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The following will be described in detail with reference to the accompanying drawings. It should be noted that, according to standard practice in the industry, various features are not drawn to scale. In fact, the size of various devices can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present application.

[0005] Figure 1 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present application.

[0006] Figure 2 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present application.

[0007] Figure 3 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present application.

[0008] Figure 4 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present application.

[0009] Figure 5 is a schematic cross-sectional view of a semiconductor device according to some embodiments of the present application.

[0010] [Explanation of symbols]

[0011] 10: Semiconductor devices

[0012] 20: Semiconductor devices

[0013] 30: Semiconductor devices

[0014] 40: Semiconductor device

[0015] 50:Semiconductor device

[0016] 100: substrate

[0017] 200: buried layer

[0018] 220: buried layer

[0019] 300: epitaxial layer

[0020] 320: first well region

[0021] 322: Base region

[0022] 324: Emitter region

[0023] 340: Second well region

[0024] 342: Collector region

[0025] 360: Third well region

[0026] 362: Base region

[0027] 380: Doping area

[0028] 400a: first isolation structure

[0029] 400b: second isolation structure

[0030] 400c: third isolation structure

[0031] 400d: fourth isolation structure

[0032] 400e: Fifth isolation structure

[0033] 400f: Sixth isolation structure

[0034] 400g: Seventh isolation structure

[0035] 500: Conductive structure

[0036] 600: interlayer dielectric layer

[0037] 620: Lead hole

[0038] 700: First metal layer

[0039] 800: Intermetallic dielectric layer

[0040] 820: first lead hole

[0041] 840: Second lead hole

[0042] 860: Third lead hole

[0043] 880: Fourth lead hole

[0044] 900: second metal layer. DETAILED DESCRIPTION

[0045] The following content provides many different embodiments or examples for implementing different components of the embodiments of the present application. Specific examples of components and configurations are described below to simplify the embodiments of the present application. Of course, these are merely examples and are not intended to limit the embodiments of the present application. For example, the description mentions that the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. In addition, the present application may repeat device symbols and / or letters in various examples. Such repetition is for the purpose of simplification and clarity, and does not itself dominate the relationship between the various embodiments and / or configurations discussed.

[0046] In addition, in some embodiments of the present application, terms related to bonding and connection, such as "connection", "interconnection", etc., unless otherwise defined, may refer to two structures being in direct contact, or may refer to two structures not being in direct contact, with other structures disposed between the two structures.

[0047] Furthermore, spatially relative terms such as "below," "beneath," "below," "above," "above," and the like may be used herein to describe the relationship between one device or component and other devices or components as shown in the figures. These spatial terms are intended to encompass different orientations of the device in use or operation, as well as the orientations depicted in the figures. When the device is otherwise oriented (rotated 90 degrees or at other orientations), the spatially relative descriptors used herein may be interpreted in accordance with that rotated orientation.

[0048] The terms "about", "approximately", and "generally" used herein generally mean within ±20% of a given value, preferably within ±10%, and more preferably within ±5%, or within ±3%, or within ±2%, or within ±1%, or within 0.5%. The numerical values ​​given herein are approximate values, that is, in the absence of specific description of "about", "approximately", and "generally", the given numerical values ​​may still imply the meaning of "about", "approximately", and "generally".

[0049] Some embodiments of the present application are described below. Additional steps may be provided before, during, and / or after the various stages described in these embodiments. Additional components may be added to the semiconductor device structure. Some of the components may be replaced or omitted in different embodiments. Although some embodiments discussed are performed in a specific order of steps, these steps may still be performed in another logical order.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art. It is understood that these terms, such as those defined in general dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present application, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present application.

[0051] As devices are miniaturized to improve operating efficiency, the tolerance of electrostatic breakdown of semiconductor devices is also reduced. In existing technologies, metal-oxide semiconductor (MOS) transistors are usually used with parasitic dual-carrier junctions as electrostatic discharge (ESD) devices. In industry practice, a transmission line pulse (TLP) machine can be used for electrostatic discharge measurement and set to human body discharge mode. When the applied voltage increases, junction breakdown will occur. After the breakdown, the metal oxide semiconductor transistor can be triggered to turn on, so that a large amount of current will instantly cause a snap back, resulting in junction breakdown, that is, the voltage drops linearly to a value, which is called the holding voltage, and then slowly rises.

[0052] When electrostatic discharge occurs, the discharge path of the current can be achieved through the parasitic two-carrier junction. However, in order for the metal oxide semiconductor transistor to operate at high voltage (for example, higher than 5V), the doping concentration of the well region in the epitaxial layer will be very low to withstand the high voltage. This will make the electrostatic discharge of the two-carrier junction transistor only able to withstand 1A and cannot exceed 2kV, making the snapback too large and resulting in the holding voltage being too low. It should be understood that the snapback of high-voltage devices is relatively large, while the snapback of low-voltage devices is relatively small. When the holding voltage is lower than the operating voltage of the device, a latch-up effect will occur, causing the device to fail to operate normally or even burn out.

[0053] The semiconductor device of the present application only has an embodiment of a parasitic bipolar junction transistor (BJT), and omits a metal oxide semiconductor transistor. The base terminal and the emitter terminal can be connected to a higher potential together, and the collector terminal can be connected to a lower potential as an electrical ground. Electrostatic discharge can flow along the high potential to the low potential, thereby causing the parasitic bipolar junction transistor to turn on. When the voltage applied to the transistor is greater than the turn-on voltage (for example, greater than 0.7V), discharge can occur. More specifically, a buried layer can be added to the substrate to directly contact the well region in the epitaxial layer. The doping concentration of the buried layer is higher than the doping concentration of the well region, thereby providing another electrostatic discharge path based on the original electrostatic discharge path to reduce the incidence of snapback. In other words, the latch effect can be reduced and the holding voltage can be increased, thereby preventing the device from failing to operate normally or being burned. In addition, the innovative parasitic bipolar junction transistor of the present application can also be integrated into other circuits (such as a printed circuit board (PCB) or other components) to enhance the electrostatic discharge protection of the overall circuit.

[0054] Figure 11 is a schematic cross-sectional view of a semiconductor device 10 according to some embodiments of the present application. In some embodiments, the semiconductor device may generally include any number of active components and passive components. Active components include metal-oxide semiconductor (MOS) transistors, complementary metal-oxide semiconductor (CMOS) transistors, laterally diffused metal-oxide semiconductor (LDMOS) transistors, bipolar complementary metal oxide semiconductor-double diffused metal oxide semiconductor (BCD) transistors, bipolar junction transistors, planar transistors, fin field-effect transistors (FinFET), gate-all-around field-effect transistors (GAA FET), other similar devices, or combinations thereof. Passive components include metal traces, capacitors, inductors, resistors, diodes, bonding pads, or other similar structures. For simplicity, Figure 1 Only illustrative two-carrier junction transistors are shown.

[0055] Reference Figure 1 , the semiconductor device 10 may include a substrate 100, a buried layer 200, an epitaxial layer 300, a first isolation structure 400a, a second isolation structure 400b, a third isolation structure 400c, a fourth isolation structure 400d, a fifth isolation structure 400e, an interlayer dielectric (ILD) layer 600, a lead hole 620, a first metal layer 700, an inter-metal dielectric (IMD) layer 800, a first lead hole 820, a second lead hole 840, a third lead hole 860, and a second metal layer 900. In some embodiments, the epitaxial layer 300 may include a first well region 320, a second well region 340, and a third well region 360. The first well region 320 may include a base region 322 and an emitter region 324. The second well region 340 may include a collector region 342. The third well region 360 may include a base region 362.

[0056] Reference Figure 1The substrate 100 may be, for example, a wafer or a die, but the present application is not limited thereto. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon (Si) substrate. In addition, in some embodiments, the semiconductor substrate may also be: an elemental semiconductor, including germanium (Ge); a compound semiconductor, including gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, including silicon germanium (SiGe) alloy, gallium arsenide phosphide (GaAsP) alloy, aluminum indium arsenide (AlInAs) alloy, aluminum gallium arsenide (AlGaAs) alloy, gallium indium arsenide (GaAs) alloy, and / or indium antimonide (InSb) alloy. arsenide (GaInAs) alloy, gallium indium phosphide (GaInP) alloy, and / or gallium indium arsenide phosphide (GaInAsP) alloy, or a combination thereof.

[0057] In other embodiments, the substrate 100 may also be a semiconductor on insulator (SOI) substrate. The semiconductor on insulator substrate may include a base plate, a buried oxide (BOX) layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer. In addition, the substrate 100 may be a first conductivity type or a second conductivity type different from the first conductivity type. In the following embodiments, the first conductivity type and the second conductivity type may represent P-type and N-type, respectively. The first conductivity type (P-type) and the second conductivity type (N-type) may be doped with appropriate dopants (or impurities) respectively. P-type dopants may include boron (B), indium (In), aluminum (Al), and gallium (Ga), while N-type dopants may include phosphorus (P) and arsenic (As). In a specific embodiment of the present application, the substrate 100 may be a first conductivity type (P-type) with a doping concentration between 1×1016cm-3 and 3×1019cm-3.

[0058] In other embodiments, the substrate 100 may include an isolation structure (not shown) to define an active region and electrically isolate active region components in or on the substrate 100, but the embodiments of the present application are not limited thereto. The isolation structure may include a deep trench isolation (DTI) structure, a shallow trench isolation (STI) structure, or a local oxidation of silicon (LOCOS) structure. In some embodiments, forming the isolation structure may include, for example, forming an insulating layer on the substrate 100, selectively etching the insulating layer and the substrate 100 to form a trench extending from the top surface of the substrate 100 to a position in the substrate 100, wherein the trench is located between adjacent active regions. Next, forming the isolation structure may include growing a liner rich in nitrogen (such as silicon oxynitride (SiON) or other similar materials) along the trench, and then filling the trench with an insulating material (such as silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride, or other similar materials) by a deposition process. Afterwards, an annealing process is performed on the insulating material in the trench, and a planarization process (such as chemical mechanical polishing (CMP)) is performed on the substrate 100 to remove excess insulating material so that the insulating material in the trench is flush with the top surface of the substrate 100 .

[0059] Continue to refer to Figure 1, an epitaxial layer 300 is formed on the substrate 100. According to some embodiments of the present application, the epitaxial layer 300 may have a second conductivity type (N type), and its doping concentration is between 1.13×1015cm-3 and 2.30×1015cm-3. In a specific embodiment of the present application, the substrate 100 and the epitaxial layer 300 may have different conductivity types, and the doping concentration of the substrate 100 is greater than the doping concentration of the epitaxial layer 300. The material of the epitaxial layer 300 may include silicon, silicon germanium, silicon carbide, other similar materials, or a combination thereof. The thickness of the epitaxial layer 300 may be between 3μm and 7μm. The epitaxial layer 300 may be formed by an epitaxial process, and its epitaxial process may include metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods, or a combination thereof.

[0060] Reference Figure 1 , the semiconductor device 10 includes a buried layer 200 disposed in the substrate 100. According to some embodiments of the present application, the buried layer 200 may directly contact the well region (e.g., the first well region 320, the second well region 340, and the third well region 360) in the epitaxial layer 300, thereby providing an additional electrostatic discharge path to improve the electrostatic discharge efficiency. More specifically, the buried layer 200, the first well region 320, and the second well region 340 may be configured to simultaneously constitute a first path and a second path of electrostatic discharge. The first path passes through the first well region 320 and the second well region 340, while the second path passes through the first well region 320, the buried layer 200, and the second well region 340. It should be understood that the buried layer 200 needs to be in direct contact with the first well region 320 and the second well region 340 to form the second path of electrostatic discharge. Since the doping concentration of the buried layer 200 is higher than the doping concentration of the well region, the resistance of the buried layer 200 is lower than the resistance of the well region. The buried layer 200 with a relatively low resistance can cause the current to discharge along the second path. In other words, the presence of the buried layer 200 can provide a second path based on the original first path to improve the efficiency of electrostatic discharge, thereby preventing the device from not functioning properly or being burned.

[0061] It is worth noting that, since the buried layer is often used in the epitaxial process, the number of masks required for the semiconductor device 10 as a whole will not increase, so the manufacturing cost or cycle will not increase significantly. In the present embodiment, the buried layer 200 has a second conductivity type (N type). The doping concentration of the buried layer 200 may be between 5×1016cm-3 and 5×1018cm-3. The vertical dimension of the buried layer 200 may be between 2μm and 4μm. The lateral dimension of the buried layer 200 may cross the first well region 320, the second well region 340, and the third well region 360 in the epitaxial layer 300. The method for forming the buried layer 200 may include, before forming the epitaxial layer 300, ion implanting N-type dopants (such as phosphorus or arsenic) in the substrate 100, performing heat treatment to drive the implanted ions into the substrate 100, and then forming the epitaxial layer 300 on the substrate 100. In some embodiments, since the epitaxial layer 300 is formed under high temperature conditions, the implanted ions will diffuse into the epitaxial layer 300. Figure 1 As shown, the buried layer 200 is located near the interface between the substrate 100 and the epitaxial layer 300, and has a portion in the substrate 100 and another portion in the epitaxial layer 300. In other words, the buried layer 200 may extend upward from the interface between the substrate 100 and the epitaxial layer 300.

[0062] Continue to refer to Figure 1 , a first well region 320, a second well region 340, and a third well region 360 may be formed in the epitaxial layer 300. The first well region 320, the second well region 340, and the third well region 360 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300, or extend to the interface between the epitaxial layer 300 and the buried layer 200. As mentioned previously, the first well region 320, the second well region 340, and the third well region 360 need to directly contact the buried layer 200 to form an additional electrostatic discharge path. According to some embodiments of the present application, the first well region 320 and the third well region 360 may be of the second conductivity type (N type), and the second well region 340 may be of the first conductivity type (P type). Since the semiconductor regions with the first conductivity type and the semiconductor regions with the second conductivity type are alternately arranged in the horizontal direction, a parasitic bipolar (NPN) junction is formed, which can provide an electrostatic discharge path to prevent the device from not functioning properly or being burned.

[0063] According to some embodiments of the present application, the first well region 320, the second well region 340, and the third well region 360 may be formed by, for example, ion implantation and / or diffusion processes. In other embodiments, instead of using ion implantation and / or diffusion processes, the first well region 320, the second well region 340, and the third well region 360 may be doped in situ during the growth of the epitaxial layer 300. Alternatively, in situ and implantation doping may be used together.

[0064] In some embodiments, the first well region 320 may be located above a portion of the buried layer 200. More specifically, the first well region 320 may be in direct contact with the buried layer 200 in the vertical direction. The doping concentration of the first well region 320 may be between 1×1017cm-3 and 5×1018cm-3. As previously mentioned, the first well region 320 may include a base region 322 and an emitter region 324. The base region 322 and the emitter region 324 may be connected together to the second metal layer 900 of a higher potential, which serves as an end point for voltage supply during device operation. Therefore, a large electric field may be generated in the first well region 320, and a large amount of charge easily accumulated in the first well region 320 needs to be released.

[0065] In some embodiments, the second well region 340 may be laterally adjacent to the first well region 320 and may be located above the buried layer 200. More specifically, the second well region 340 may be in direct contact with the first well region 320 in the horizontal direction and in direct contact with the buried layer 200 in the vertical direction. Figure 1 As shown, the second well region 340 may be laterally located between the first well region 320 and the third well region 360. The doping concentration of the second well region 340 may be between 5×1016cm-3 and 5×1017cm-3. As mentioned previously, the second well region 340 may include a collector region 342. The collector region 342 may be connected to the first metal layer 700 of a lower potential, which serves as an electrically grounded terminal during device operation. According to some embodiments of the present application, a large amount of charge accumulated in the first well region 320 may flow to the second well region 340 via the first path and / or the second path for release.

[0066] In some embodiments, the third well region 360 may be laterally adjacent to the second well region 340 and may be located above a portion of the buried layer 200. More specifically, the third well region 360 may be in direct contact with the second well region 340 in the horizontal direction and in direct contact with the buried layer 200 in the vertical direction. The doping concentration of the third well region 360 may be between 1×1017cm-3 and 5×1018cm-3. As mentioned previously, the third well region 360 may include a base region 362. The base region 362 may be connected to the second metal layer 900 at a higher potential, and thus share the same potential with the base region 322 and the emitter region 324. According to some embodiments of the present application, the function of the third well region 360 is to utilize different doping concentrations to further generate an additional third path for electrostatic discharge.

[0067] Reference Figure 1 , a base region 322 and an emitter region 324 may be provided in the first well region 320. The base region 322 and the emitter region 324 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. In the present embodiment, the base region 322 and the emitter region 324 are laterally separated from each other. According to some embodiments of the present application, the base region 322 may be of the second conductivity type (N type), and the emitter region 324 may be of the first conductivity type (P type). The formation method of the base region 322 and the emitter region 324 may be similar to the formation method of the first well region 320, the second well region 340, and the third well region 360, and the details thereof will not be repeated here.

[0068] In some embodiments, the base region 322 may partially overlap with the buried layer 200. According to some embodiments of the present application, the base region 322 may serve as the base terminal of the semiconductor device 10. The doping concentration of the base region 322 may be between 1×1019cm-3 and 5×1020cm-3. It should be understood that the doping concentration of the base region 322 may be greater than the doping concentration of the buried layer 200, the doping concentration of the buried layer 200 may be greater than the doping concentration of the first well region 320, and the doping concentration of the first well region 320 may be greater than the doping concentration of the epitaxial layer 300. The thickness of the base region 322 may be between 0 μm and 1 μm. In addition, since the base region 322, the first well region 320, and the buried layer 200 and / or the epitaxial layer 300 all have the second conductivity type (N type), such a configuration allows the base region 322 to be electrically grounded to the substrate 100.

[0069] In some embodiments, the emitter region 324 may overlap with the buried layer 200. According to some embodiments of the present application, the emitter region 324 may serve as the emitter end of the semiconductor device 10. The doping concentration of the emitter region 324 may be between 1×1018cm-3 and 1×1020cm-3. It should be understood that the doping concentration of the emitter region 324 may be greater than the doping concentration of the buried layer 200, the doping concentration of the buried layer 200 may be greater than the doping concentration of the first well region 320, and the doping concentration of the first well region 320 may be greater than the doping concentration of the epitaxial layer 300. The thickness of the emitter region 324 may be between 0 μm and 1 μm. According to some embodiments of the present application, the first path and the second path of electrostatic discharge further pass through the emitter region 324. It should be understood that the emitter region 324, the first well region 320, and the second well region 340 may constitute a parasitic bipolar (PNP) junction, thereby providing a first path for electrostatic discharge. As mentioned previously, since the doping concentration of the buried layer 200 is higher than that of the well region, the resistance of the buried layer 200 is lower than that of the well region, which can promote the flow of charges through the buried layer 200. Therefore, the emitter region 324, the first well region 320, the buried layer 200, and the second well region 340 provide a second path for electrostatic discharge. Both the first path and the second path have the properties of a bipolar junction. The coexistence of the first path and the second path can improve the efficiency of electrostatic discharge, thereby preventing the device from not being able to operate normally or being burned.

[0070] Continue to refer to Figure 1 , a collector region 342 may be provided in the second well region 340. The collector region 342 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300 and may overlap with the buried layer 200. According to some embodiments of the present application, the collector region 342 may be of the first conductivity type (P-type) and may serve as the collector end of the semiconductor device 10. The doping concentration of the collector region 342 may be between 1×1018cm-3 and 1×1020cm-3. It should be understood that the doping concentration of the collector region 342 may be greater than the doping concentration of the buried layer 200, the doping concentration of the buried layer 200 may be greater than the doping concentration of the second well region 340, and the doping concentration of the second well region 340 may be greater than the doping concentration of the epitaxial layer 300. In addition, since both the collector region 342 and the second well region 340 have the first conductivity type (P-type), such a configuration may serve as an electrical grounding of a parasitic double-carrier junction transistor on the surface of the epitaxial layer 300. The thickness of the collector region 342 may be between 0 μm and 1 μm. The formation method of the collector region 342 may be similar to the formation method of the first well region 320 , the second well region 340 , and the third well region 360 , and the details thereof will not be repeated here.

[0071] Reference Figure 1, a base region 362 may be provided in the third well region 360. The base region 362 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300, and may partially overlap with the buried layer 200. According to some embodiments of the present application, the base region 362 may be of the second conductivity type (N-type) and may serve as another base terminal of the semiconductor device 10. The function of the base region 362 may be similar to that of the base region 322, and the details thereof will not be repeated here. The doping concentration of the base region 362 may be between 1×1019cm-3 and 5×1020cm-3. It should be understood that the doping concentration of the base region 362 may be greater than the doping concentration of the buried layer 200, the doping concentration of the buried layer 200 may be greater than the doping concentration of the third well region 360, and the doping concentration of the third well region 360 may be greater than the doping concentration of the epitaxial layer 300. The thickness of the base region 362 may be between 0 μm and 1 μm. The method for forming the base region 362 may be similar to the method for forming the first well region 320 , the second well region 340 , and the third well region 360 , and the details thereof will not be repeated herein.

[0072] Reference Figure 1 , a first isolation structure 400a, a second isolation structure 400b, a third isolation structure 400c, a fourth isolation structure 400d, and a fifth isolation structure 400e may be formed on the epitaxial layer 300. Specifically, since the manufacturing process thereof involves high temperature processing, the first isolation structure 400a, the second isolation structure 400b, the third isolation structure 400c, the fourth isolation structure 400d, and the fifth isolation structure 400e are partially embedded in the epitaxial layer 300. According to some embodiments of the present application, the first isolation structure 400a, the second isolation structure 400b, the third isolation structure 400c, the fourth isolation structure 400d, and the fifth isolation structure 400e may be drift oxide (DOX), which is used to isolate various conductive components to prevent electrical short circuits from occurring during operation of the semiconductor device 10.

[0073] like Figure 1 As shown, the base region 322 in the first well region 320 may be laterally located between the first isolation structure 400a and the second isolation structure 400b. The second isolation structure 400b may laterally isolate the base region 322 from the emitter region 324. The base region 362 in the third well region 360 may be laterally located between the third isolation structure 400c and the fourth isolation structure 400d. The emitter region 324 in the first well region 320 may be laterally located between the second isolation structure 400b and the fifth isolation structure 400e. The collector region 342 in the second well region 340 may be laterally located between the fourth isolation structure 400d and the fifth isolation structure 400e.

[0074] In some embodiments, the first isolation structure 400a, the second isolation structure 400b, the third isolation structure 400c, the fourth isolation structure 400d, and the fifth isolation structure 400e may be formed by silicon oxide (SiO), which may be silicon local oxidation isolation structures formed by thermal oxidation. In other embodiments, the first isolation structure 400a, the second isolation structure 400b, the third isolation structure 400c, the fourth isolation structure 400d, and the fifth isolation structure 400e may be shallow trench isolation structures formed by etching, oxidation, and deposition processes.

[0075] Continue to refer to Figure 1 After forming the first isolation structure 400a, the second isolation structure 400b, the third isolation structure 400c, the fourth isolation structure 400d, and the fifth isolation structure 400e, an interlayer dielectric layer 600 may be formed on the epitaxial layer 300. In some embodiments, the interlayer dielectric layer 600 may cover the epitaxial layer 300, the first isolation structure 400a, the second isolation structure 400b, the third isolation structure 400c, the fourth isolation structure 400d, and the fifth isolation structure 400e. In addition to providing mechanical protection and insulation for the components below, the interlayer dielectric layer 600 may also isolate different levels of conductive materials. The material of the interlayer dielectric layer 600 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxynitrocarbide (SiOxNyC1-xy, where x and y are in the range of 0 to 1), tetraethoxysilane (tetra ethyl ortho silicate, TEOS), undoped silicate glass, doped silicon oxide (such as boron-doped phospho-silicate glass (BPSG), fused silica glass (FSG), phospho-silicate glass (PSG), boron-doped silicate glass (BSG), or other similar materials), low dielectric constant (low-k) dielectric material, or other suitable dielectric materials.

[0076] The thickness of the interlayer dielectric layer 600 may be between and The interlayer dielectric layer 600 may be formed by spin-on coating, chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), other similar methods, or a combination thereof. Then, the interlayer dielectric layer 600 may be planarized (e.g., by chemical mechanical polishing) to allow the interlayer dielectric layer 600 to have a flat top surface.

[0077] Reference Figure 1 , a lead hole 620 may be formed to pass through the interlayer dielectric layer 600. The lead hole 620 may physically contact the collector region 342. In addition, a first metal layer 700 may be formed on the interlayer dielectric layer 600. In some embodiments, the first metal layer 700 is electrically coupled to the collector region 342 through the lead hole 620. According to some embodiments of the present application, the first metal layer 700 may serve as an electrical ground for the semiconductor device 10. The lead hole 620 and the first metal layer 700 may be integrally formed, and thus include the same material.

[0078] In some embodiments, the material of the lead hole 620 and the first metal layer 700 may include amorphous silicon, polysilicon, polycrystalline silicon germanium (poly-SiGe), metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), or other similar materials), metal silicides (such as nickel silicide (NiSi), cobalt silicide (CoSi), tantalum silicon nitride (TaSiN), or other similar materials), metal carbides (such as tantalum carbide (TaC), tantalum carbonitride (TaCN), or other similar materials), metal oxides, and metals. The metal may include cobalt (Co), ruthenium (Ru), aluminum (Al), palladium (Pd), platinum (Pt), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), nickel (Ni), manganese (Mn), zirconium (Zr), other similar materials, combinations thereof, or multiple layers thereof. The lead hole 620 and the first metal layer 700 may be formed by physical vapor deposition (PVD), atomic layer deposition (ALD), plating, other suitable processes, or combinations thereof.

[0079] First, an opening may be formed in the interlayer dielectric layer 600 to correspond to the collector region 342. Then, the above-mentioned materials may be blanket deposited on the interlayer dielectric layer 600 by a suitable deposition process. In addition to being formed on the surface of the interlayer dielectric layer 600, the above-mentioned materials are also filled into the openings to form lead holes 620. The first metal layer 700 may be formed by patterning the deposited film layer through a photolithography process followed by an etching process. The photolithography process may include coating photoresist, soft baking, exposure, post-exposure baking, development, other similar methods, or a combination thereof. The etching process may include dry etching, wet etching, other similar methods, or a combination thereof. The thickness of the first metal layer 700 may be between and between.

[0080] Continue to refer to Figure 1 , an intermetallic dielectric layer 800 may be formed on the interlayer dielectric layer 600. In some embodiments, the intermetallic dielectric layer 800 may cover the interlayer dielectric layer 600 and the first metal layer 700. According to some embodiments of the present application, the intermetallic dielectric layer 800 may not only provide mechanical protection and electrical insulation for the underlying structure, but also separate different levels of conductive materials. The thickness of the intermetallic dielectric layer 800 may be between 100 and 200. and The material and formation method of the intermetal dielectric layer 800 may be similar to the material and formation method of the interlayer dielectric layer 600, and the details thereof will not be repeated herein.

[0081] Reference Figure 1 , a first lead hole 820, a second lead hole 840, and a third lead hole 860 may be formed to pass through the intermetallic dielectric layer 800. It is noteworthy that the first lead hole 820, the second lead hole 840, and the third lead hole 860 further pass through the interlayer dielectric layer 600 to physically contact the base region 322, the emitter region 324, and the base region 362, respectively. In addition, a second metal layer 900 may be formed on the intermetallic dielectric layer 800. In some embodiments, the second metal layer 900 connects the first lead hole 820, the second lead hole 840, and the third lead hole 860 together, and is electrically coupled to the base region 322, the emitter region 324, and the base region 362 through the first lead hole 820, the second lead hole 840, and the third lead hole 860, respectively. According to some embodiments of the present application, the second metal layer 900 may serve as an end point for the voltage supply of the semiconductor device 10. The thickness of the second metal layer 900 may be between 100 and 200 Å. and The materials and forming methods of the first lead hole 820, the second lead hole 840, the third lead hole 860, and the second metal layer 900 may be similar to those of the lead hole 620 and the first metal layer 700, and the details thereof will not be repeated herein.

[0082] Figure 2 is a cross-sectional schematic diagram of a semiconductor device 20 according to some embodiments of the present application. Figure 1, the semiconductor device 20 may include a conductive structure 500 on the surface of the epitaxial layer 300. The substrate 100, the buried layer 200, the epitaxial layer 300, the first well region 320, the base region 322, the emitter region 324, the second well region 340, the collector region 342, the third well region 360, the base region 362, the first isolation structure 400a, the second isolation structure 400b, the third isolation structure 400c, the fourth isolation structure 400d, the interlayer dielectric layer 600, the lead hole 620, the first metal layer 700, the intermetallic dielectric layer 800, the first lead hole 820, the second lead hole 840, the third lead hole 860, and the second metal layer 900 have the same characteristics as those of the substrate 100, the buried layer 200, the epitaxial layer 300, the first well region 320, the base region 322, the emitter region 324, the second well region 340, the collector region 342, the third well region 360, the base region 362, the first isolation structure 400a, the second isolation structure 400b, the third isolation structure 400c, the fourth isolation structure 400d, the interlayer dielectric layer 600, the lead hole 620, the first metal layer 700, the intermetallic dielectric layer 800, the first lead hole 820, the second lead hole 840, the third lead hole 860, and the second metal layer 900. Figure 1 The details are similar to those shown, and will not be repeated here.

[0083] Reference Figure 2 , a conductive structure 500 may be formed on the epitaxial layer 300 before forming the interlayer dielectric layer 600. According to some embodiments of the present application, the conductive structure 500 may exhibit a field plate effect to change the electric field distribution in the epitaxial layer 300. Since electrostatic discharge usually requires a large area to improve the efficiency of protection, the fifth isolation structure 400e of the semiconductor device 10 has a larger size to create the required space. However, the conductive structure 500 can improve the electric field distribution at a smaller size. Therefore, the use of the conductive structure 500 can improve the design flexibility of the overall circuit of the semiconductor device 20. The conductive structure 500 may cross the upper surfaces of the first well region 320 and the second well region 340 in the horizontal direction, and be located laterally between the emitter region 324 and the collector region 342. The thickness of the conductive structure 500 may be between and The material and the forming method of the conductive structure 500 may be similar to the material and the forming method of the first metal layer 700, and the details thereof will not be repeated here.

[0084] Continue to refer to Figure 2 , the semiconductor device 20 further includes a sixth isolation structure 400f and a seventh isolation structure 400g. It is worth noting that the conductive structure 500 replaces the location of the fifth isolation structure 400e of the semiconductor device 10. In addition, the semiconductor device 20 may further include a very thin insulating layer (not shown) vertically disposed between the epitaxial layer 300 and the conductive structure 500.

[0085] The conductive structure 500 may be laterally located between the sixth isolation structure 400f and the seventh isolation structure 400g, and may be disposed on an insulating layer (not shown). The sixth isolation structure 400f may laterally isolate the conductive structure 500 from the emitter region 324, and the seventh isolation structure 400g may laterally isolate the conductive structure 500 from the collector region 342. In other words, the conductive structure 500 does not overlap with the emitter region 324 or the collector region 342. However, the conductive structure 500 may extend over a portion of the surface of the sixth isolation structure 400f and / or the seventh isolation structure 400g. The materials and formation methods of the sixth isolation structure 400f and the seventh isolation structure 400g may be similar to the materials and formation methods of the first isolation structure 400a, the second isolation structure 400b, the third isolation structure 400c, the fourth isolation structure 400d, and the fifth isolation structure 400e, and the details thereof will not be repeated herein.

[0086] Reference Figure 2 , a fourth lead hole 880 may be formed to pass through the intermetallic dielectric layer 800. It is noteworthy that the fourth lead hole 880 further passes through the interlayer dielectric layer 600 to physically contact the conductive structure 500. In some embodiments, the second metal layer 900 is electrically coupled to the conductive structure 500 through the fourth lead hole 880. According to some embodiments of the present application, since the conductive structure 500 is connected to the second metal layer 900, the conductive structure 500 shares the same potential with the base region 322, the emitter region 324, and the base region 362, serving as the end point of the voltage supply of the semiconductor device 20. The material and formation method of the fourth lead hole 880 may be similar to the material and formation method of the lead hole 620, and the details thereof will not be repeated here.

[0087] Figure 3 is a cross-sectional schematic diagram of a semiconductor device 30 according to some embodiments of the present application. Figure 1 , the base region 322 and the emitter region 324 of the semiconductor device 30 are laterally adjacent to each other. The features of the substrate 100, the buried layer 200, the epitaxial layer 300, the first well region 320, the base region 322, the emitter region 324, the second well region 340, the collector region 342, the third well region 360, the base region 362, the first isolation structure 400a, the third isolation structure 400c, the fourth isolation structure 400d, the fifth isolation structure 400e, the interlayer dielectric layer 600, the lead hole 620, the first metal layer 700, the intermetallic dielectric layer 800, the first lead hole 820, the second lead hole 840, the third lead hole 860, and the second metal layer 900 are the same as those of the semiconductor device 30. Figure 1 The details are similar to those shown, and will not be repeated here.

[0088] Reference Figure 3, the second isolation structure 400b of the semiconductor device 10 can be omitted, so that the base region 322 is in direct contact with the emitter region 324. When the base region 322 and the emitter region 324 are laterally adjacent to each other, the base resistance can be reduced. Since both the base region 322 and the emitter region 324 are connected to the second metal layer 900, the mutual abutment of the base region 322 and the emitter region 324 will not cause an electrical short circuit. However, when the base resistance is reduced, the time required for conduction may be extended. Therefore, how to configure the base region 322 and the emitter region 324 can be selected, depending on the application and design requirements.

[0089] Figure 4 is a cross-sectional view of a semiconductor device 40 according to some embodiments of the present application. Figure 1 , the semiconductor device 40 may include a doped region 380 in the epitaxial layer 300. The substrate 100, the buried layer 200, the epitaxial layer 300, the first well region 320, the base region 322, the emitter region 324, the second well region 340, the collector region 342, the base region 362, the first isolation structure 400a, the second isolation structure 400b, the third isolation structure 400c, the fourth isolation structure 400d, the fifth isolation structure 400e, the interlayer dielectric layer 600, the lead hole 620, the first metal layer 700, the intermetallic dielectric layer 800, the first lead hole 820, the second lead hole 840, the third lead hole 860, and the second metal layer 900 have the same characteristics as those of the substrate 100, the buried layer 200, the epitaxial layer 300, the first well region 320, the base region 322, the emitter region 324, the second well region 340, the collector region 342, the base region 362, the first isolation structure 400a, the second isolation structure 400b, the third isolation structure 400c, the fourth isolation structure 400d, the fifth isolation structure 400e, the interlayer dielectric layer 600, the lead hole 620, the first metal layer 700, the intermetallic dielectric layer 800, the first lead hole 820, the second lead hole 840, the third lead hole 860, and the second metal layer 900. Figure 1 The details are similar to those shown, and will not be repeated here.

[0090] Reference Figure 4 , a doping region 380 may be formed in the epitaxial layer 300. The doping region 380 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. According to some embodiments of the present application, the doping region 380 may be of the second conductivity type (N type). The doping region 380 replaces the location of the third well region 360 of the semiconductor device 10. It should be understood that the provision of the third well region 360 or the doping region 380 is optional. The doping region 380 may be adjacent to the second well region 340 laterally and may be partially located above the buried layer 200. More specifically, the doping region 380 may be in direct contact with the second well region 340 in the horizontal direction and in direct contact with the buried layer 200 in the vertical direction. The doping concentration of the doping region 380 may be between 1×1017cm-3 and 9×1018cm-3. The base region 362 may be disposed in the doping region 380 and may be connected to the second metal layer 900. The method for forming the doped region 380 may be similar to the method for forming the first well region 320 , the second well region 340 , and the third well region 360 , and the details thereof will not be repeated herein.

[0091] Continue to refer to Figure 4, the doping concentration of the doping region 380 may be higher than the doping concentration of the second well region 340 or the first well region 320, and may be at the same level as the doping concentration of the buried layer 200. According to some embodiments of the present application, in addition to the first path and the second path, the emitter region 324, the first well region 320, the buried layer 200, and the doping region 380 may additionally provide a third path for electrostatic discharge. In addition, the third path will eventually flow to the second well region 340 to release the charge. The simultaneous existence of the first path, the second path, and the third path can improve the efficiency of electrostatic discharge, thereby preventing the device from not functioning properly or being burned.

[0092] Figure 5 is a cross-sectional view of a semiconductor device 50 according to some embodiments of the present application. Figure 1 , the semiconductor device 50 may include a buried layer 220 in the substrate 100. The features of the substrate 100, the epitaxial layer 300, the first well region 320, the base region 322, the emitter region 324, the second well region 340, the collector region 342, the third well region 360, the base region 362, the first isolation structure 400a, the second isolation structure 400b, the third isolation structure 400c, the fourth isolation structure 400d, the fifth isolation structure 400e, the interlayer dielectric layer 600, the lead hole 620, the first metal layer 700, the intermetallic dielectric layer 800, the first lead hole 820, the second lead hole 840, the third lead hole 860, and the second metal layer 900 are the same as those of the semiconductor device 50. Figure 1 The details are similar to those shown, and will not be repeated here.

[0093] Reference Figure 5 , a buried layer 220 may be formed in the substrate 100. Different from the buried layer 200 of the semiconductor device 10 (which has the second conductivity type), the buried layer 220 of the semiconductor device 50 has the first conductivity type (P type), which is formed by ion implanting P type dopants (such as boron, indium, aluminum, or gallium) into the substrate 100. Therefore, the semiconductor device 10 and the semiconductor device 50 may be different types of devices. The doping concentration of the buried layer 220 may be between 5×1015cm-3 and 9×1016cm-3. Since the doping concentration of the buried layer 220 is higher than the doping concentration of the first well region 320, the second well region 340, and the third well region 360, the resistance of the buried layer 220 is lower than the resistance of the well region. The buried layer 220 with a relatively low resistance may cause the current to discharge along the second path. In other words, the presence of the buried layer 220 may provide a second path on the basis of the original first path to improve the efficiency of electrostatic discharge, thereby preventing the device from failing to operate normally or being burned. The size and formation method of the buried layer 220 may be similar to the size and formation method of the buried layer 200 , and the details thereof will not be repeated herein.

[0094] Continue to refer to Figure 5, the buried layer 220 can directly contact the first well region 320, the second well region 340, and the third well region 360 in the epitaxial layer 300, thereby providing an additional electrostatic discharge path to improve the electrostatic discharge efficiency. More specifically, the buried layer 220, the first well region 320, and the second well region 340 can be configured to simultaneously constitute the first path and the second path of electrostatic discharge. The first path passes through the first well region 320 and the second well region 340, and the second path passes through the first well region 320, the buried layer 220, and the second well region 340. It should be understood that the buried layer 220 needs to be in direct contact with the first well region 320 and the second well region 340 to form the second path of electrostatic discharge.

[0095] The parasitic double-carrier junction transistor of the present application can add a buried layer in the substrate to directly contact the well region in the epitaxial layer. Since the doping concentration of the buried layer is higher than the doping concentration of the well region, the resistance of the buried layer is lower than the resistance of the well region. The buried layer with relatively low resistance can promote the flow of charge through the buried layer. Therefore, on the basis of the original electrostatic discharge path, another electrostatic discharge path can be provided to improve the efficiency of electrostatic discharge, reduce the latch effect and increase the holding voltage, thereby preventing the device from not being able to operate normally or being burned.

[0096] The features of several embodiments are summarized above so that those skilled in the art can better understand the viewpoints of the embodiments of the present application. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present application to achieve the same purpose and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the present application, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present application.

Claims

1. A semiconductor device, characterized in that: include: a substrate having a first conductivity type; an epitaxial layer disposed on the substrate, wherein the epitaxial layer has a second conductivity type different from the first conductivity type; a buried layer disposed in the substrate; a first well region disposed in the epitaxial layer and having the second conductivity type, wherein the first well region directly contacts the buried layer; as well as A second well region is disposed in the epitaxial layer and has the first conductivity type, wherein the second well region directly contacts the first well region in a horizontal direction and directly contacts the buried layer in a vertical direction.

2. The semiconductor device according to claim 1, wherein: The buried layer, the first well region, and the second well region are configured to simultaneously form a first path and a second path for electrostatic discharge.

3. The semiconductor device according to claim 2, wherein: The first path passes through the first well region and the second well region, and the second path passes through the first well region, the buried layer, and the second well region.

4. The semiconductor device according to claim 3, wherein: The first path and the second path further pass through an emitter region, and the emitter region is disposed in the first well region and has the first conductivity type.

5. The semiconductor device according to claim 4, wherein: The device also includes a base region, which is disposed in the first well region and has the second conductivity type.

6. The semiconductor device according to claim 5, wherein: The base region and the emitter region are laterally spaced apart from each other.

7. The semiconductor device according to claim 5, wherein: The base region and the emitter region laterally adjoin each other.

8. The semiconductor device according to claim 5, wherein: The device also includes a collector region, which is disposed in the second well region and has the first conductivity type.

9. The semiconductor device according to claim 8, wherein: Also includes: an interlayer dielectric layer disposed on the epitaxial layer; a first metal layer disposed on the interlayer dielectric layer; an intermetallic dielectric layer, covering the interlayer dielectric layer and the first metal layer; and A second metal layer is disposed on the intermetallic dielectric layer.

10. The semiconductor device according to claim 9, wherein: The first metal layer is electrically coupled to the collector region through a lead hole.

11. The semiconductor device according to claim 9, wherein: The second metal layer is electrically coupled to the base region and the emitter region through a first lead hole and a second lead hole, respectively.

12. The semiconductor device according to claim 9, wherein: The invention also comprises a conductive structure which is arranged on the epitaxial layer and is laterally located between the emitter region and the collector region.

13. The semiconductor device according to claim 12, wherein: The second metal layer is electrically coupled to the conductive structure through a third lead hole.

14. The semiconductor device according to claim 1, wherein: The first well region and the second well region extend downward from the upper surface of the epitaxial layer, and the buried layer extends upward from the interface between the substrate and the epitaxial layer.

15. The semiconductor device according to claim 1, wherein: The buried layer has the first conductivity type.

16. The semiconductor device according to claim 1, wherein: The buried layer has the second conductivity type.

17. The semiconductor device according to claim 1, wherein: The invention also includes a third well region, which is disposed in the epitaxial layer and has the second conductivity type, wherein the third well region is adjacent to the second well region.

18. The semiconductor device according to claim 17, wherein: The device also includes a base region, which is disposed in the third well region and has the second conductivity type.

19. The semiconductor device according to claim 1, wherein: It also includes a doped region, which is arranged in the epitaxial layer and has the second conductivity type, wherein the doped region directly contacts the second well region in the horizontal direction and directly contacts the buried layer in the vertical direction, wherein the doping concentration of the doped region is higher than the doping concentration of the second well region or the first well region.

20. The semiconductor device according to claim 19, wherein: The buried layer, the first well region, and the doped region are configured to form a third path for electrostatic discharge.

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