Display panel and display device

Abstract

The invention discloses a display panel and a display device, and belongs to the technical field of display. The display panel comprises a substrate, a plurality of pixel circuits, a plurality of light emitting devices, a plurality of data signal lines and a plurality of redundant signal lines. One of the redundant signal lines may include a first lead portion connected with one of the data signal lines. Here, the first lead portion may be a part of a fan-out lead electrically connected to the data signal line. Due to the fact that the redundant signal lines are distributed in the display area, parts of the fan-out leads used for being electrically connected with the data signal lines can be distributed in the display area, and when the parts, except for the first lead parts, in the fan-out leads are distributed in the non-display area, the occupied space in the non-display area is reduced. Therefore, the width of the area where the fan-out lead is arranged in the non-display area can be effectively reduced. Therefore, the screen-to-body ratio of the display device integrated with the display panel can be effectively improved, and the display effect of the display device is good.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] At present, in order to provide users with a better visual experience, display screens (also called display panels) in display devices are developing in the direction of large-screen and full-screen.

[0003] The display device may generally include a display panel and a driver chip. The display panel has a display area and a non-display area, and the display panel may include: a plurality of sub-pixels and a plurality of data signal lines located in the display area, and a plurality of fan-out leads located in the non-display area; each data signal line may be electrically connected to a column of sub-pixels, and each data signal line may be electrically connected to the driver chip through a fan-out lead. In this way, the driver chip may send a drive signal to the data signal line through the fan-out lead so that the display panel can display the picture.

[0004] However, in the above-mentioned display panel, the space occupied by the fan-out leads is relatively large, resulting in a larger width of the area where the fan-out leads are set in the non-display area, which in turn results in a lower screen-to-body ratio of the display device, affecting the display effect of the display device. Summary of the invention

[0005] The embodiments of the present application provide a display panel and a display device, which can solve the problem of low screen-to-body ratio of display devices in the prior art. The technical solution is as follows:

[0006] In one aspect, a display panel is provided, wherein the display panel has a display area, and the display panel includes:

[0007] substrate;

[0008] A plurality of pixel circuits arranged in an array on one side of the substrate, the plurality of pixel circuits comprising: a plurality of first pixel circuits and a plurality of virtual pixel circuits;

[0009] a plurality of light-emitting devices located on a side of the plurality of pixel circuits away from the substrate, the plurality of light-emitting devices being electrically connected to the plurality of first pixel circuits in a one-to-one correspondence;

[0010] and, a plurality of data signal lines and a plurality of redundant signal lines located in the display area, wherein an extension direction of the data signal lines is the same as an extension direction of the redundant signal lines;

[0011] Among them, one of the data signal lines is connected to a column of the first pixel circuits; one of the redundant signal lines is located in the area where a column of the virtual pixel circuits is located; at least some of the multiple redundant signal lines are first redundant signal lines, and one of the first redundant signal lines includes a first lead portion connected to one of the data signal lines.

[0012] Optionally, the display panel further comprises: a plurality of auxiliary signal lines located in the display area, wherein an extension direction of the auxiliary signal lines intersects with an extension direction of the redundant signal lines;

[0013] Among them, one of the auxiliary signal lines is located in the area where a row of pixel circuits is located; at least some of the multiple auxiliary signal lines are first auxiliary signal lines, and one of the first auxiliary signal lines includes: a second lead portion, one end of the second lead portion is electrically connected to one of the data signal lines, and the other end is electrically connected to one end of the first lead portion.

[0014] Optionally, one of the first redundant signal lines further includes: a redundant line body disconnected from the first lead portion, and one of the first auxiliary signal lines further includes: an auxiliary line body disconnected from the second lead portion;

[0015] Wherein, the redundant line body and the auxiliary line body are electrically connected at the intersection.

[0016] Optionally, a portion of the plurality of redundant signal lines is the first redundant signal line, another portion of the redundant signal lines is a second redundant signal line, the first lead portion is not provided in the second redundant signal line, and the second redundant signal line is electrically connected to the auxiliary line body at the intersection;

[0017] And / or, a part of the multiple auxiliary signal lines are the first auxiliary signal lines, and another part of the auxiliary signal lines are second auxiliary signal lines, the second lead part is not set in the second auxiliary signal line, and the second auxiliary signal line is electrically connected to the redundant line body at the intersection.

[0018] Optionally, when the display panel includes both the second redundant signal line and the second auxiliary signal line, the second redundant signal line is electrically connected to the second auxiliary signal line at an intersection.

[0019] Optionally, the display panel further includes: a first power signal line; the second redundant signal line is electrically connected to the first power signal line, and / or the second auxiliary signal line is electrically connected to the first power signal line.

[0020] Optionally, the light emitting device comprises: an anode, a light emitting layer and a cathode layer which are stacked, and the anode is closer to the substrate than the cathode layer;

[0021] The first pixel circuit is electrically connected to the anode of the corresponding light-emitting device, and the cathode layer is electrically connected to the first power signal line.

[0022] Optionally, the display panel further has a non-display area located outside the display area;

[0023] The display panel further comprises: a plurality of connection leads located in the non-display area and electrically connected to the plurality of data signal lines in a one-to-one correspondence, a portion of the plurality of connection leads being electrically connected to the corresponding data signal lines through the first lead portion and the second lead portion, and another portion of the plurality of connection leads being electrically connected directly to the corresponding data signal lines;

[0024] Wherein, the plurality of connecting leads are used for binding and connecting with the driving component.

[0025] Optionally, the redundant signal line and the data signal line are arranged in the same layer and made of the same material, and the redundant signal line and the auxiliary signal line are arranged in different layers.

[0026] Optionally, the display panel further comprises: a gate driving circuit; the light emitting device comprises: an anode, a light emitting layer and a cathode layer which are stacked, and the anode is closer to the substrate than the cathode layer;

[0027] There is an overlapping area between the orthographic projection of the gate driving circuit on the substrate and the orthographic projection of the anode on the substrate.

[0028] Optionally, the display area includes: a first display partition, a second display partition and a third display partition, and the second display partition is located between the first display partition and the third display partition;

[0029] The plurality of pixel circuits are all located in the first display subarea and the second display area, and are all located outside the third display subarea; at least part of the GOA circuit is located in the third display subarea;

[0030] Among them, the pixel circuits located in the first display partition include the first pixel circuit and the virtual pixel circuit; the pixel circuits located in the second display partition among the multiple pixel circuits are all the first pixel circuits, and a part of the first pixel circuits located in the second display area is electrically connected to the light-emitting device located in the second display area, and another part of the first pixel circuits located in the second display area is electrically connected to the light-emitting device located in the third display area.

[0031] Optionally, within the first display partition, a plurality of columns of the first pixel circuits and a plurality of columns of the virtual pixel circuits are distributed alternately.

[0032] Optionally, N columns of the first pixel circuits are distributed between two adjacent columns of the virtual pixel circuits, where N is an integer greater than or equal to 2 and less than or equal to 6.

[0033] Optionally, a distribution density of the light-emitting devices distributed in the first display partition is equal to a distribution density of the light-emitting devices distributed in the second display partition.

[0034] Optionally, a plurality of columns of the first pixel circuits located in the second display subarea are electrically connected to anodes of a plurality of columns of the light-emitting devices located in the second display subarea and the third display subarea, respectively.

[0035] Optionally, the display panel further includes: a plurality of transparent connection lines located in the second display area and the third display area;

[0036] Wherein, the anodes of at least some of the light-emitting devices located in the second display subarea and the third display subarea are electrically connected to the corresponding first pixel circuits through the transparent connecting lines.

[0037] Optionally, the display panel further includes: a plurality of auxiliary signal lines, and some of the auxiliary signal lines are located in the second display partition and the third display partition;

[0038] The transparent connecting line comprises: a first transparent wiring portion and a second transparent wiring portion connected to each other, wherein the extension direction of the first transparent wiring portion is the same as the extension direction of the auxiliary signal line, and the extension direction of the second transparent wiring portion intersects with the extension direction of the auxiliary signal line;

[0039] Among them, the orthographic projection of the first transparent wiring portion on the substrate does not overlap with the orthographic projection of the auxiliary signal line on the substrate, and the orthographic projection of the second transparent wiring portion in at least part of the transparent connecting line on the substrate overlaps with the orthographic projection of the auxiliary signal line on the substrate.

[0040] Optionally, the area where the orthographic projection of at least one of the transparent connecting lines on the substrate overlaps with the orthographic projection of at least one of the auxiliary signal lines on the substrate accounts for less than or equal to 30% of the total area of ​​the orthographic projection of at least one of the transparent connecting lines on the substrate.

[0041] Optionally, the orthographic projections of anodes of at least some of the light-emitting devices located in the second display subarea and the third display subarea on the substrate overlap with the orthographic projections of at least two of the transparent signal lines on the substrate.

[0042] On the other hand, a display device is provided, characterized in that it includes: a power supply component, and a display panel electrically connected to the power supply component, and the display panel is the above-mentioned display panel.

[0043] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least:

[0044] A display panel includes: a substrate, a plurality of pixel circuits, a plurality of light-emitting devices, a plurality of data signal lines and a plurality of redundant signal lines. A redundant signal line may include: a first lead portion connected to a data signal line. Here, the first lead portion may be used as a part of a fan-out lead electrically connected to the data signal line. Since the redundant signal line is distributed in the display area, the part of the fan-out lead (that is, the first lead portion) used to be electrically connected to the data signal line may be distributed in the display area, so that when the part of the fan-out lead other than the first lead portion is distributed in the non-display area, the occupied space in the non-display area is reduced, thereby effectively reducing the width of the area where the fan-out lead is set in the non-display area. In this way, the screen-to-body ratio of a display device integrating such a display panel can be effectively improved, so that the display effect of the display device is better. In addition, a plurality of data signal lines and a plurality of redundant signal lines may be located in the same conductive pattern, and the conductive pattern containing the data signal lines and the redundant signal lines may be evenly distributed in the display area. To this end, when a part of the first redundant signal line in the area where a column of virtual pixel circuits is located is used as the part of the fan-out lead located in the display area, it can be ensured that the various conductive layer patterns in the display panel are evenly distributed in the display area under the premise of ensuring that the part of the fan-out lead can be distributed in the display area, which can effectively reduce the probability of color deviation of the display panel and make the display effect of the display panel better. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 is a top view of a display panel provided in an embodiment of the present application;

[0047] Figure 2 yes Figure 1 A partial enlarged view of the display panel at position A1 is shown;

[0048] Figure 3 yes Figure 2A schematic diagram of the film layer structure of the display panel at BB' is shown;

[0049] Figure 4 An embodiment of the present application provides a schematic diagram of connecting a plurality of light-emitting devices with a plurality of first pixel circuits;

[0050] Figure 5 is a partial top view of another display panel provided in an embodiment of the present application;

[0051] Figure 6 yes Figure 5 The schematic diagram of the film layer structure of the display panel at CC' is shown;

[0052] Figure 7 is a top view of another display panel provided in an embodiment of the present application;

[0053] Figure 8 is a schematic diagram of the distribution of redundant signal lines and auxiliary signal lines provided in an embodiment of the present application;

[0054] Fig. 9 yes Figure 8 The schematic diagram of the film layer structure of the display panel at D-D' is shown;

[0055] Fig.10 is a schematic diagram of a film layer structure in a display area of ​​a display panel provided in an embodiment of the present application;

[0056] Fig.11 is a partial top view of a display panel provided in an embodiment of the present application;

[0057] Fig.12 is a top view of a display panel provided in another embodiment of the present application;

[0058] Fig.13 is a top view of another display panel provided by another embodiment of the present application;

[0059] Fig.14 yes Fig.12 A partial enlarged view of the display panel at position A2 is shown;

[0060] Fig.15 Another schematic diagram of connecting a plurality of light-emitting devices and a plurality of first pixel circuits is provided in an embodiment of the present application;

[0061] Fig.16 yes Fig.12 A schematic diagram showing electrical connection between the light emitting device and the first pixel circuit at A3 of the display panel;

[0062] Fig.17 This is a schematic diagram of the connection between an anode of a light-emitting device and a first pixel circuit provided in an embodiment of the present application;

[0063] Fig.18 This is a schematic diagram of the distribution of a transparent connecting line and auxiliary signal routing provided in an embodiment of the present application;

[0064] Fig.19 This is a schematic diagram of the relative position relationship between an anode and a transparent signal line of a light-emitting device provided in an embodiment of the present application;

[0065] Fig. 20 yes Fig.19 A schematic diagram of the film layer structure of the display panel at EE' is shown. DETAILED DESCRIPTION

[0066] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0067] Please refer to Figure 1 , Figure 2 and Figure 3 , Figure 1 is a top view of a display panel provided in an embodiment of the present application, Figure 2 yes Figure 1 The partial enlarged view of the display panel at position A1 is shown. Figure 3 yes Figure 2 The schematic diagram of the film structure of the display panel at BB' is shown. The display panel 000 may have a display area 00a and a non-display area 00b located outside the display area 00a. The display panel 000 may include: a substrate 100, a plurality of pixel circuits 200, a plurality of light-emitting devices 300, a plurality of data signal lines D10, and a plurality of redundant signal lines D20.

[0068] The multiple pixel circuits 200 in the display panel 000 can be arranged in an array on one side of the substrate 100, and the multiple pixel circuits 200 can all be located in the display area 00a. Among them, the multiple pixel circuits 200 may include: multiple first pixel circuits 201 and multiple virtual pixel circuits 202. Here, the multiple first pixel circuits 201 can be arranged in multiple columns, and the multiple virtual pixel circuits 202 can also be arranged in multiple columns, and the multiple columns of virtual pixel circuits 202 can be interspersed in the multiple columns of first pixel circuits 201. And the number of columns of first pixel circuits 201 is more than the number of columns of virtual pixel circuits 202. To this end, at least two columns of first pixel circuits 201 can be distributed between two adjacent columns of virtual pixel circuits 202. It should be noted that, Figure 2 This is to facilitate the identification of the distribution relationship of the plurality of pixel circuits 200 in the display panel 000. Figure 2 The light emitting device 300 in the display panel 000 is not shown. Figure 2In the figure, each box P1 represents a first pixel circuit 201 , and each box P2 represents a virtual pixel circuit 202 .

[0069] The plurality of light emitting devices 300 in the display panel 000 may be located on a side of the plurality of pixel circuits 200 away from the substrate 100, and the plurality of light emitting devices 300 may all be located in the display area 00a. Here, in order to more clearly see the connection relationship between the plurality of light emitting devices 300 and the plurality of first pixel circuits 201, please refer to Figure 4 , Figure 4 The embodiment of the present application provides a schematic diagram of connecting multiple light-emitting devices with multiple first pixel circuits. Multiple light-emitting devices 300 can be electrically connected to multiple first pixel circuits 201 in a one-to-one correspondence. Each first pixel circuit 201 is used to drive the corresponding light-emitting device 300 to emit light, so that the display surface 00a of the display panel 000 can present a corresponding display screen. It should be noted that the virtual pixel circuit 202 needs to be insulated from the light-emitting device 300, that is, there is no electrical connection relationship between the virtual pixel circuit 202 and the light-emitting device 300.

[0070] The plurality of data signal lines D10 and the plurality of redundant signal lines D20 in the display panel 000 may be both located in the display area 00a. Here, the extending direction of the data signal lines D10 may be the same as the extending direction of the redundant signal lines D20.

[0071] The plurality of data signal lines D1 may correspond one-to-one to the plurality of columns of first pixel circuits 201, each data signal line D10 may be located in a region where a corresponding column of first pixel circuits 201 is located, and each data signal line D10 may be electrically connected to each first pixel circuit 201 in a corresponding column of first pixel circuits 201. Furthermore, the data signal line D10 may be insulated from the virtual pixel circuit 202, that is, there is no electrical connection relationship between the data signal line D10 and the virtual pixel circuit 202.

[0072] The plurality of redundant signal lines D20 may correspond one-to-one to the plurality of columns of virtual pixel circuits 202, each redundant signal line D20 may be located in the region where the corresponding column of virtual pixel circuits 202 is located, and each redundant signal line D20 needs to be insulated from each virtual pixel circuit in the corresponding column of virtual pixel circuits 202. That is, there is no electrical connection relationship between the redundant signal line D20 and the virtual pixel circuit 202.

[0073] It should be noted that the multiple first pixel circuits 201 and the multiple virtual pixel circuits 202 in the display panel 000 are formed simultaneously using the same process, and in the process of forming the multiple first pixel circuits 201, a data signal line D10 electrically connected to a column of first pixel circuits 201 is also formed synchronously. Therefore, in the process of forming the multiple virtual pixel circuits 202, a redundant signal line D20 is also formed in the area where a column of virtual pixel circuits 202 is located, but it is necessary to ensure that the redundant signal line D20 is insulated from each virtual pixel circuit in the column of virtual pixel circuits 202.

[0074] In the present application, at least part of the redundant signal lines D20 in the display panel 000 may be first redundant signal lines D201. Here, a first redundant signal line D201 may include: a first lead portion D21 connected to a data signal line D10. Here, the first lead portion D21 may be used as a part of a fan-out lead electrically connected to the data signal line D10. Since the redundant signal line D20 is distributed in the display area 00a, the part of the fan-out lead (that is, the first lead portion D21) used to be electrically connected to the data signal line D10 may be distributed in the display area 00a, so that when the part of the fan-out lead other than the first lead portion D21 is distributed in the non-display area 00b, the occupied space in the non-display 00b is reduced, and the width of the area where the fan-out lead is set in the non-display area 00b can be effectively reduced. In this way, the screen-to-body ratio of the display device integrated with such a display panel 000 can be effectively improved, so that the display effect of the display device is better.

[0075] It should be noted that in the related art, a signal lead electrically connected to the data signal line can be additionally inserted between two adjacent columns of sub-pixels, and the signal lead can be used as the part of the fan-out lead located in the display area. However, in such a display panel, some areas need to be provided with signal leads, while some areas do not need to be provided with signal leads, resulting in that the conductive patterns used to form these signal leads in the display panel are not evenly distributed in the display area, which in turn causes the display panel to be prone to display problems such as color deviation.

[0076] In the embodiment of the present application, the data signal line D10 and the redundant signal line D20 in the display panel 000 are arranged in the same layer and made of the same material. That is, the data signal line D10 and the redundant signal line D20 are formed by the same patterning process. In other words, the data signal line D10 and the redundant signal line D20 in the display panel 000 can be located in the same conductive pattern. Since the multiple columns of virtual pixel circuits 202 are interspersed in the multiple columns of first pixel circuits 201, the multiple redundant signal lines D20 in the display panel 000 are also interspersed in the multiple data signal lines D10. To this end, the conductive pattern including the data signal line D10 and the redundant signal line D20 can be evenly distributed in the display area 00a. When a portion of the first redundant signal line D201 in the area where a column of virtual pixel circuits 202 is located is used as the portion of the fan-out lead located in the display area 00a, it can be ensured that the various conductive layer patterns in the display panel 000 are evenly distributed in the display area 00a, under the premise of ensuring that the portion of the fan-out lead can be distributed in the display area 00a. In this way, the probability of color deviation in the display panel 000 can be effectively reduced, so that the display effect of the display panel 000 is better.

[0077] In summary, the display panel provided by the embodiment of the present application includes: a substrate, a plurality of pixel circuits, a plurality of light-emitting devices, a plurality of data signal lines and a plurality of redundant signal lines. A redundant signal line may include: a first lead portion connected to a data signal line. Here, the first lead portion may be used as a part of a fan-out lead electrically connected to the data signal line. Since the redundant signal line is distributed in the display area, the part of the fan-out lead (that is, the first lead portion) used to be electrically connected to the data signal line can be distributed in the display area, so that when the part of the fan-out lead other than the first lead portion is distributed in the non-display area, the occupied space in the non-display is reduced, and the width of the area where the fan-out lead is set in the non-display area can be effectively reduced. In this way, the screen-to-body ratio of the display device integrating such a display panel can be effectively improved, so that the display effect of the display device is better. In addition, multiple data signal lines and multiple redundant signal lines can be located in the same conductive pattern, and this conductive pattern containing data signal lines and redundant signal lines can be evenly distributed in the display area. To this end, when a part of the first redundant signal line in the area where a column of virtual pixel circuits is located is used as the part of the fan-out lead located in the display area, it can be ensured that the various conductive layer patterns in the display panel are evenly distributed in the display area under the premise of ensuring that the part of the fan-out lead can be distributed in the display area, which can effectively reduce the probability of color deviation of the display panel and make the display effect of the display panel better.

[0078] In the embodiments of the present application, Figure 5 As shown, Figure 5000 is a partial top view of another display panel provided by an embodiment of the present application. The display panel 000 may further include: a plurality of gate lines G10. Here, the extension direction of the gate line G10 may intersect with the extension direction of the data signal line D10, for example, the extension direction of the gate line G10 may be perpendicular to the extension direction of the data signal line D10.

[0079] Among them, the multiple pixel circuits 200 in the display panel 000 can also be arranged in an array into multiple rows, and the multiple rows of pixel circuits 200 can correspond to the multiple gate lines G10 one by one, each gate line G10 can be located in the area where the corresponding row of pixel circuits 200 are located, and each gate line G10 can be electrically connected to each first pixel circuit 201 in the corresponding row of pixel circuits 200. In addition, the gate line G10 can be insulated from the virtual pixel circuit 202, that is, there is no electrical connection relationship between the gate line G10 and the virtual pixel circuit 202.

[0080] Optional, such as Figure 5 As shown, the display panel 000 may further include: a plurality of auxiliary signal lines G20 located in the display area 00a. Here, the extension direction of the auxiliary signal line G20 may intersect with the extension direction of the redundant signal line D20. For example, the extension direction of the auxiliary signal line G20 may be perpendicular to the extension direction of the redundant signal line D20.

[0081] In the present application, the extension direction of the auxiliary signal line G20 may be the same as the extension direction of the gate line G10. It should be noted that, since the distribution density of the gate line G10 in the display panel 000 is relatively large, even if the extension direction of the auxiliary signal line G20 is the same as the extension direction of the gate line G10, it is necessary to ensure that the auxiliary signal line G20 and the gate line G10 are distributed in different layers, that is, the conductive pattern where the auxiliary signal line G20 is located is not the same as the conductive pattern where the gate line G10 is located, and an insulating layer is distributed between the conductive pattern where the auxiliary signal line G20 is located and the conductive pattern where the gate line G10 is located.

[0082] Here, the auxiliary signal line G20 and the redundant signal line D20 are also distributed in different layers, that is, the conductive pattern where the auxiliary signal line G20 is located is not the same as the conductive pattern where the redundant signal line D20 is located, and an insulating layer is distributed between the conductive pattern where the auxiliary signal line G20 is located and the conductive pattern where the redundant signal line D20 is located. In this way, it can be ensured that there will be no short circuit between the auxiliary signal line G20 and the data signal line D10, and it can also be ensured that there will be no short circuit between the gate line G10 and the data signal line D10.

[0083] Among them, multiple auxiliary signal lines G20 in the display panel 000 can correspond one-to-one to multiple rows of pixel circuits 200, each auxiliary signal line G20 can be located in the area where a corresponding row of pixel circuits 200 is located, and each auxiliary signal line G20 can be insulated from each pixel circuit in the corresponding row of pixel circuits 200, that is, there is no electrical connection between the auxiliary signal line G20 and the pixel circuit 200.

[0084] In the present application, at least part of the auxiliary signal lines G20 among the multiple auxiliary signal lines G20 are first auxiliary signal lines G201. Here, an auxiliary signal line G20 may include: a second lead portion G21, and one end of the second lead portion G21 may be electrically connected to the data signal line D10, and the other end may be electrically connected to one end of the first lead portion D21. In this case, the portion of the fan-out lead connected to the data signal line D10 located in the display area 00a may include: a second lead portion G21 and a first lead portion D21. After the multiple fan-out leads in the display panel are bound and connected to the driving chip, the driving signal can transmit the data signal to the data signal line D10 in sequence through the portion of the fan-out lead located in the non-display area 00b, the first lead portion D21, and the second lead portion G21.

[0085] Here, since an auxiliary signal line G20 is distributed in each row of pixel circuits 200, the conductive pattern including multiple auxiliary signal lines G20 can be evenly distributed in the display area 00a. And the conductive pattern including multiple redundant signal lines D20 is also evenly distributed in the display area 00a. Therefore, when a part of the auxiliary signal line G20 and a part of the redundant signal line D20 are used as the part of the fan-out lead located in the display area 00a, it can be ensured that the various conductive layer patterns in the display panel 000 are evenly distributed in the display area 00a under the premise of ensuring that the part of the fan-out lead can be distributed in the display area 00a, thereby further reducing the probability of color deviation of the display panel 000.

[0086] In the embodiments of the present application, Figure 6 As shown, Figure 6 yes Figure 5 The schematic diagram of the film layer structure of the display panel at CC' is shown. Since there is an insulating layer 001 between the conductive pattern where the data signal line D10 is located and the conductive pattern where the auxiliary signal line G20 is located, it is necessary to set a first via hole V1 and a second via hole V2 for penetrating the insulating layer 001 in the display panel 000, so that one end of the second lead part G21 in the first auxiliary signal line G201 can be overlapped with the data signal line D10 through the first via hole V1, and the other end of the second lead part G21 in the first auxiliary signal line G201 can be overlapped with one end of the first lead part G21 in the first redundant signal line D201 through the second via hole V2.

[0087] It should be noted that the portion of the redundant signal lines D20 other than the first lead portion D21 will not be loaded with a driving signal, causing it to be in a suspended state. When the portion of the redundant signal line D20 other than the first lead portion D21 is in a suspended state, the portion of the redundant signal line D20 other than the first lead portion D21 may interfere with the gate scanning signal loaded on the gate line G10 intersecting with it. Similarly, the portion of the auxiliary signal lines G20 other than the second lead portion G21 will not be loaded with a driving signal, causing it to be in a suspended state. When the portion of the auxiliary signal line G20 other than the second lead portion G21 is in a suspended state, the portion of the auxiliary signal line G20 other than the second lead portion G21 may interfere with the data signal recorded on the data signal line D10 intersecting with it.

[0088] To this end, the embodiment of the present application requires further processing of the portions of the multiple redundant signal lines D20 except the first lead portion D21, and the portions of the multiple auxiliary signal lines G20 except the second lead portion G21, to ensure that these signal lines do not interfere with the signals loaded on other signal lines.

[0089] For example, Figure 7 As shown, Figure 7 000 is a top view of another display panel provided by an embodiment of the present application. The display panel 000 may further include: a first power signal line 400 located in the non-display area 00b. Here, the first power signal line 400 may be a low-level power signal line (ie, a VSS power signal line), and the first power signal line 400 may be a ring-shaped power signal line.

[0090] Here, the portion of the plurality of redundant signal lines D20 other than the first lead portion D21 may be electrically connected to the first power signal line 400, and / or the portion of the plurality of auxiliary signal lines G20 other than the second lead portion G21 may be electrically connected to the first power signal line 400. It should be noted that, Figure 7 The following is a schematic illustration of an example in which portions of the plurality of redundant signal lines D20 excluding the first lead portion D21 and portions of the plurality of auxiliary signal lines G20 excluding the second lead portion G21 are electrically connected to the first power signal line 400 .

[0091] In this way, since the first power signal line 400 records a VSS signal of a fixed potential, when the parts of the redundant signal lines D20 other than the first lead part D21 are electrically connected to the first power signal line 400, the parts of the redundant signal lines D20 other than the first lead part D21 can also be loaded with a VSS signal of a fixed potential; when the parts of the auxiliary signal lines G20 other than the second lead part G21 are electrically connected to the first power signal line 400, the parts of the auxiliary signal lines G20 other than the second lead part G21 can also be loaded with a VSS signal of a fixed potential. In this way, it can be ensured that the parts of the redundant signal lines D20 other than the first lead part D21 and the parts of the auxiliary signal lines G20 other than the second lead part G21 are no longer in a suspended state, so that the parts of the redundant signal lines D20 other than the first lead part D21 will not interfere with the gate line G10, and the parts of the auxiliary signal lines G20 other than the second lead part G21 will not interfere with the data line D1.

[0092] Optionally, the portion of the plurality of redundant signal lines D20 in the display panel 000 other than the first lead portion D21 may be electrically connected to the portion of the plurality of auxiliary signal lines G20 other than the second lead portion G21. In this way, as long as it is ensured that the portion of the plurality of redundant signal lines D20 other than the first lead portion D21 and one of the portions of the plurality of auxiliary signal lines G20 other than the second lead portion G21 are connected to the first power signal line 400, it can be ensured that the first power signal line 400 can provide a VSS signal to the portion of the plurality of redundant signal lines D20 other than the first lead portion D21, and it can also be ensured that the first power signal line 400 provides a VSS signal to the portion of the plurality of auxiliary signal lines G20 other than the second lead portion G21.

[0093] For example, Figure 8 As shown, Figure 8 It is a distribution diagram of a redundant signal line and an auxiliary signal line provided in an embodiment of the present application. In addition to including a first lead portion D21, a first redundant signal line D201 may also include: a redundant line body D22 disconnected from the first lead portion D21. For example, a first partition U1 is provided between the first lead portion D21 and the redundant line body D22 in the first redundant signal line D201, and the first lead portion D21 and the redundant line body D22 may be insulated by the first partition U1. In addition to including a second lead portion G21, a first auxiliary signal line G201 may also include: an auxiliary line body G22 disconnected from the second lead portion G21. For example, a second partition U2 is provided between the second lead portion G21 and the auxiliary line body G22 in the first auxiliary signal line G201, and the second lead portion G21 and the auxiliary line body G22 may be insulated by the second partition U2.

[0094] Among them, the redundant line body D22 in the first redundant signal line D201 can be electrically connected to the auxiliary line body G22 in the first auxiliary signal line G201 at the intersection, so that the part of the first redundant signal line D201 except the first lead part D21 can be electrically connected to the part of the first auxiliary signal line G201 except the second lead part G21.

[0095] It should be noted that, in the display panel 000 , not every redundant signal line D20 needs to be provided with the first lead portion D21 , and not every auxiliary signal line G1 needs to be provided with the second lead portion G21 .

[0096] To this end, a portion of the redundant signal lines D20 in the display panel 000 may be the first redundant signal line D201, and another portion of the redundant signal lines D20 may be the second redundant signal line D202. Here, the first redundant signal line D201 may include both the first lead portion D21 and the redundant line body D22, while the second redundant signal line D201 is not provided with the first lead portion D21, and the second redundant signal line D201 is a whole signal line without a partition therein. The second redundant signal line D202 may be electrically connected to the auxiliary line body G22 in the first auxiliary signal line G201 at the intersection.

[0097] And / or, a part of the auxiliary signal lines G20 in the display panel 000 may be the first auxiliary signal line G201, and another part of the auxiliary signal lines G20 may be the second auxiliary signal line G202. Here, the first auxiliary signal line G201 may include both the second lead portion G21 and the auxiliary line body G22, and the second auxiliary signal line G202 is not provided with the second lead portion G21. The second auxiliary signal line G202 is a whole signal line, and no partition is provided therein. The second auxiliary signal line G202 may be electrically connected to the redundant line body D22 in the first redundant signal line D201 at the intersection.

[0098] In the embodiment of the present application, when the display panel 000 includes both the second redundant signal line D202 and the second auxiliary signal line G202, the second redundant signal line D202 and the second auxiliary signal line G202 may be electrically connected at the intersection.

[0099] In this case, it can be ensured that the parts of the plurality of redundant signal lines D20 except the first lead part D21 and the parts of the plurality of auxiliary signal lines G20 except the second lead part G21 are electrically connected at the intersections in the display panel 000. In addition, the parts of the plurality of redundant signal lines D20 except the first lead part D21 and the parts of the plurality of auxiliary signal lines G20 except the second lead part G21 can form a grid-shaped conductive layer in the display panel 000.

[0100] For example, see Fig. 9 , Fig. 9 yes Figure 8 A schematic diagram of the film layer structure of the display panel at D-D' is shown. Since there is an insulating layer 001 between the conductive pattern where the redundant signal line D20 is located and the conductive pattern where the auxiliary signal line G20 is located, it is necessary to set a third via hole V3 for penetrating the insulating layer 001 in the display panel 000, so that the portion of the multiple redundant signal lines D20 except the first lead portion D21 and the portion of the multiple auxiliary signal lines G20 except the second lead portion G21 can be overlapped at the intersection through the third via hole V3.

[0101] In the present application, the end of the second redundant signal line D202 in the display panel 000 can be electrically connected to the first power signal line 400, and / or the end of the second auxiliary signal line G202 can be electrically connected to the first power signal line 400. Of course, the end of the redundant line body D22 in the first redundant signal line D201 can also be electrically connected to the first power signal line 400, and / or the end of the auxiliary line body G22 in the first auxiliary signal line G201 can also be electrically connected to the first power signal line 400. In this way, the grid-shaped conductive layer composed of the parts of the multiple redundant signal lines D20 except the first lead part D21 and the parts of the multiple auxiliary signal lines G20 except the second lead part G21 in the display panel 000 can be connected to the first power signal line 400.

[0102] In the embodiments of the present application, Fig.10 As shown, Fig.10 Schematic diagram of a film structure of a display panel in a display area provided by an embodiment of the present application. The light emitting device 300 in the display panel 000 may include: an anode 301, a light emitting layer 302 and a cathode layer 303 arranged in a stacked manner, wherein the anode 301 of the light emitting device 300 is closer to the substrate 100 than the cathode layer 303.

[0103] Optionally, the display panel 000 may further include: a pixel definition layer 500. The conductive pattern where the anode 301 is located is closer to the substrate 100 than the pixel definition layer 500, the cathode layer 303 may be located on the side of the pixel definition layer 500 away from the substrate 100, and the light-emitting layer 302 may be located between the anode 301 and the cathode layer 303. Here, the pixel definition layer 500 may have pixel openings 501 corresponding to a plurality of light-emitting devices 300, and the orthographic projection of each pixel opening 501 on the substrate 100 may be located within the orthographic projection of the anode 301 in the corresponding light-emitting device 300 on the substrate 100. It should be noted that the light-emitting layer 302 and the cathode layer 303 are both film layer structures arranged in an entire layer. Therefore, in the display panel 000, the portion of the anode 301 located in the corresponding pixel opening 501, the portion of the light-emitting layer 302 located in the pixel opening 501, and the portion of the cathode layer 303 located in the pixel opening 501 are used to form a light-emitting device 300. For example, the light emitting device 300 may be an organic light emitting diode (OLED) device.

[0104] In the present application, each first pixel circuit 201 in the display panel 000 may be electrically connected to the anode 301 in the corresponding light emitting device 300 , and the cathode layer 303 in the light emitting device 300 may be electrically connected to the first power signal 400 .

[0105] Here, since the cathode layer 303 in the display panel 000 is a film layer structure arranged in an entire layer, when the cathode layer 303 is electrically connected to the first power signal line 400, the first power signal line 400 can provide a VSS signal to each light-emitting device 300. In addition, since the thickness of the cathode layer 303 is usually thin, its resistance is usually large, and when a grid-shaped conductive layer is formed by the parts of the plurality of redundant signal lines D20 except the first lead part D21 and the plurality of auxiliary signal lines G20 except the second lead part G21, and is electrically connected to the cathode layer 303, the grid-shaped conductive layer can be used as an auxiliary electrode of the cathode layer 303. Therefore, the resistance of the cathode layer 303 can be reduced by the grid-shaped conductive layer, so that the VSS signal at each position of the cathode layer 303 is consistent, and thus the uniformity when the VSS signal is applied to the cathode layer 303 can be ensured to be good.

[0106] Optionally, the display panel 000 may further include: a second power signal line (not shown in the figure), at least part of which may be located in the display area 00a, and the second power signal line may be electrically connected to each effective driving circuit 201 in the display area 00a. Here, the second power signal line may be a high-level signal line (that is, a VDD power signal line), and a VDD signal may be applied to each effective driving circuit 201 through the second power signal line, so that the effective driving circuit 201 may drive the corresponding light-emitting device 300 to emit light.

[0107] In the embodiments of the present application, Fig.11 As stated, Fig.11 It is a partial top view of a display panel provided by an embodiment of the present application. The display panel 000 may also include: a plurality of connecting leads F corresponding to the plurality of data signal lines D10 one by one. Among them, the plurality of connecting leads F may be located in the non-display area 00b of the display panel 000. A portion of the connecting leads F among the plurality of connecting leads F may be electrically connected to the corresponding data signal line D10 through the first lead portion D21 and the second lead portion G21. Among them, when the connecting lead F needs to be electrically connected to the corresponding data signal line D10 through the first lead portion D21 and the second lead portion G21, the connecting lead F, the first lead portion D21 and the second lead portion D22 may constitute a fan-out lead corresponding to the data signal line D10, so that a portion of the fan-out leads may be ensured to be arranged in the display area 00a, and the space occupied by the fan-out leads in the non-display area 00b may be effectively reduced. Another portion of the connecting leads F among the plurality of connecting leads F may be directly electrically connected to the corresponding data signal line D10. When the connecting lead F is directly electrically connected to the data signal line D10 , the connecting lead F is a fan-out lead corresponding to the data signal line D10 .

[0108] In the present application, a plurality of connecting leads F located in the non-display area 00b are used to bind and connect with the driving component. For example, the driving component can be bound at position B1 in the non-display area 00b, so that the driving component can provide data signals to the corresponding data signal line D10 through these connecting leads F.

[0109] For example, in order to connect multiple data signal lines D10 in the display panel 000 to the driver chip, it is usually necessary to connect multiple data signal lines D1 to the driver chip by converging from both sides to the center. Since the data signal lines D10 on both sides of the binding position B1 of the driver chip are far away from the driver chip, the data signal lines D10 in the center are closer to the driver chip. Therefore, the data signal lines D10 on both sides need to be connected to the corresponding connecting leads F through the second lead part G21 and the first lead part D21, while the data signal lines D10 in the center can be directly connected to the corresponding connecting leads F.

[0110] Here, for the data signal lines D10 located at both sides, the driving component can sequentially apply data signals to these data signal lines D10 through the corresponding connecting leads F, the first lead portion D21 and the second lead portion G21. For the data signal lines D10 located in the center, the driving component can directly apply data signals to these data signal lines D10 through the corresponding connecting leads F.

[0111] In the embodiments of the present application, Fig.12 As shown, Fig.12 It is a top view of a display panel provided by another embodiment of the present application. The display panel 000 may also include: a gate driver (English: Gate Driver On Array, referred to as: GOA) circuit 600, at least part of the GOA circuit 600 may be located in the display area 00a of the display panel 000. Here, the number of GOA circuits 600 is usually two, and two GOA circuits 600 may be usually distributed on both sides of the display panel 000, and both ends of each gate line G10 in the display panel 000 may be electrically connected to the two GOA circuits 600, and a gate scan signal may be provided to each gate line G10 through the GOA circuit 600. In the present application, since at least part of the GOA circuit 600 in the display panel 000 is located in the display 00a, therefore, the width of the non-display area 00b of the display panel 000 may be further reduced. In this way, the screen ratio of the display device integrating such a display panel may be further improved.

[0112] For examples, please refer to Fig.13 , Fig.13 It is a top view of another display panel provided by another embodiment of the present application. The orthographic projection of the gate drive circuit 600 in the display panel 000 on the substrate 100 may overlap with the orthographic projection of the anode 301 in the light-emitting device 300 on the substrate 100. To this end, some of the light-emitting devices 300 in the display panel 000 may be distributed on the side of the gate drive circuit 600 away from the substrate 100, so that the area in the display panel 600 where the gate drive circuit 600 is set can also display the picture normally.

[0113] In the present application, the display area 00a of the display panel 000 may include: a first display partition 00a1, a second display partition 00a2 and a third display partition 00a3. Among them, the second display partition 00a2 may be located between the first display partition 00a1 and the third display partition 00a3, and the first display partition 00a1, the second display partition 00a2 and the third display partition 00a3 may be distributed with light-emitting devices 300. Therefore, through the light emission of the light-emitting devices 300 in the three display partitions, it can be ensured that the three display partitions can display corresponding pictures.

[0114] Here, a plurality of pixel circuits 200 in the display panel 000 may be located in the first display partition 00a1 and the second display partition 00a2, and these pixel circuits 200 are all located outside the third display partition 00a3. At least part of the GOA circuit 600 in the display panel 000 may be located in the third display partition 00a3. It should be noted that, since the pixel circuit 200 and the GOA circuit 600 may generally include transistors, and the transistors in the pixel circuit 200 and the crystals in the GOA circuit 600 are generally formed at the same time. Therefore, in the present application, the pixel circuit 200 is arranged outside the third display partition 00a3, and at least part of the GOA circuit 600 is arranged in the third display partition 00a3, it can be ensured that there is no mutual interference between the setting position of the GOA circuit 600 and the setting position of the pixel circuit 200 under the premise of ensuring that the GOA circuit 600 is arranged in the display area 00a.

[0115] In the present application, the pixel circuits of the plurality of pixel circuits 200 located in the first display partition 00a1 may include: a first pixel circuit 201 and a virtual pixel circuit 202. The pixel circuits of the plurality of pixel circuits 200 located in the second display partition 00a2 may all be first pixel circuits 201. Among them, a portion of the first pixel circuits 201 located in the second display partition 00a2 may be electrically connected to the light emitting device 300 located in the second display partition 00a2, and another portion of the first pixel circuits 201 located in the second display partition 00a2 may be electrically connected to the light emitting device 300 located in the third display partition 00a3.

[0116] It should be noted that, in the first display partition 00a, multiple columns of first pixel circuits 201 and multiple columns of virtual pixel circuits 202 are staggered. The number of columns of the first pixel circuit 201 is greater than the number of columns of the virtual pixel circuit 202. For this reason, at least two columns of the first pixel circuit 201 can be distributed between two adjacent columns of virtual pixel circuits 202. In this case, compared with the display panel in the related art in which multiple pixel circuits are electrically connected to multiple light-emitting devices in a one-to-one correspondence, the multiple pixel circuits 200 in the display panel 000 in the embodiment of the present application are equivalent to compressing the multiple pixel circuits in the display panel in the related art in the row direction. For this reason, the pixel circuits 200 in the embodiment of the present application will be greater than the number of light-emitting devices 300, and in the display panel 000 in the embodiment of the present application, the width of the pixel circuit 200 in the row direction is much smaller than the width of the light-emitting device 300.

[0117] For example, Fig.14 As shown, Fig.14 yes Fig.12The enlarged view of the part of the display panel at A2 is shown. In the first display subarea 00a of the display panel 000, the ratio of the number of columns of the first pixel circuits 201 to the number of columns of the virtual pixel circuits 202 is N:1. That is, N columns of virtual pixel circuits 202 can be distributed between two adjacent columns of virtual pixel circuits 202. Here, N can be an integer greater than or equal to 2 and less than or equal to 6. In this way, please refer to Fig.15 , Fig.15 The embodiment of the present application provides another schematic diagram of connecting multiple light-emitting devices with multiple first pixel circuits. When N is equal to 4, in the first display subarea 00a, in the area where four adjacent columns of light-emitting devices 300 are located, four columns of first pixel circuits 201 and one column of virtual pixel circuits 202 can be distributed, and these four columns of first pixel circuits 201 are electrically connected to the four adjacent columns of light-emitting devices 300 in a one-to-one correspondence. It should be noted that the four adjacent columns of light-emitting devices 300 can be: one column of light-emitting devices for emitting red light, one column of light-emitting devices for emitting blue light, and two columns of light-emitting devices for emitting green light. In this way, each light-emitting device in the display panel 000 is arranged in RGBB. In the row direction of multiple light-emitting devices 300, a light-emitting device R for emitting red light, a light-emitting device B for emitting blue light, and two light-emitting devices G for emitting green light arranged adjacent to each other can form a group of pixels.

[0118] In the embodiment of the present application, the distribution density of the light emitting devices 300 distributed in the first display partition 00a1, the light emitting devices 300 distributed in the second display partition 00a2, and the light emitting devices 300 distributed in the third display partition 00a3 is equal. In this way, it can be ensured that the display effect of the first display partition 00a1 is basically consistent with the display effect of the second display partition 00a2, and is basically consistent with the display effect of the third display partition 00a3, thereby effectively improving the overall display effect of the display panel.

[0119] It should be noted that, since the number of GOA circuits 600 in the display panel 000 is two, the number of the third display partitions 00a3 in the display area 00a also needs to be two, so that the two GOA circuits are respectively arranged between the two third display partitions 00a3. Since the second display partition 00a2 needs to be arranged between the third display partition 00a3 and the first display partition 00a1, the number of the second display partitions 00a2 in the display area 00a also needs to be two. In this case, the first display partition 00a1 in the display area 00a needs to be located between the two second display partitions 00a2, and the third display partition 00a3 needs to be located on the side of the second display partition 00a2 away from the first display partition 00a1.

[0120] In the embodiment of the present application, the distribution density of the pixel circuits 200 distributed in the first display partition 00a1 is equal to the distribution density of the pixel circuits 200 distributed in the second display partition 00a2.

[0121] In this case, please refer to Fig.16 , Fig.16 yes Fig.12 The schematic diagram of the light emitting device and the first pixel circuit electrically connected in A3 of the display panel is shown. Since the pixel circuits 200 in the second display subarea 00a2 are all first pixel circuits 201, and the width of the pixel circuits 200 in the row direction is much smaller than the width of the light emitting device 300. Therefore, in the second display subarea 00a2, the number of columns of the first pixel circuits 201 will be more than the number of columns of the light emitting device 300. In this way, a part of the first pixel circuits 201 in the second display subarea 00a2 can be electrically connected to the multiple light emitting devices 300 in the second display subarea 00a2 in a one-to-one correspondence, and there are another part of the redundant first pixel circuits 201 in the second display subarea 00a2, and these first pixel circuits 201 do not need to be electrically connected to the multiple light emitting devices 300 in the second display subarea 00a2, and these first pixel circuits 201 can be electrically connected to the multiple light emitting devices 300 in the third display subarea 00a3 in a one-to-one correspondence.

[0122] For example, the number of columns of the first pixel circuit 201 in the second display partition 00a2 is the same as the number of columns of the light emitting devices 300 in the second display partition 00a2 and the third display partition 00a3. That is, the sum of the number of columns of the light emitting devices 300 in the second display partition 00a2 and the light emitting devices 300 in the third display partition 00a3 is equal to the number of columns of the first pixel circuit 201 in the second display partition 00a2. In this way, the multiple columns of the first pixel circuit 201 in the second display partition 00a2 can be electrically connected to the multiple columns of the light emitting devices 300 in the second display partition 00a2 and the third display partition 00a3 in a one-to-one correspondence. That is, the multiple columns of the first pixel circuit 201 located in the second display partition 00a2 can be electrically connected to the anodes 301 of the multiple columns of the light emitting devices 300 located in the second display partition 00a2 and the third display partition 00a3, respectively. In this way, the anode 301 in the light emitting device 300 in the third display subarea 00a3 can be connected to the first pixel circuit 201 in the second display subarea 00a, so that the GOA circuit 600 can be set in the third display subarea 00a3. In this way, the GOA circuit 600 can be hidden in the third display subarea 00a3 in the display area 00a.

[0123] In the embodiments of the present application, Fig.17 As shown, Fig.17Schematic diagram of the connection between the anode of a light emitting device and the first pixel circuit provided by an embodiment of the present application. The display panel 000 may further include: a plurality of transparent connecting lines L located in the second display partition 00a2 and the third display partition 00a3. Here, the anodes 301 of at least some of the light emitting devices 300 located in the second display partition 00a2 and the third display partition 00a3 may be electrically connected to the corresponding first pixel circuit 201 through the transparent connecting lines L. In this way, since the transparent connecting line L has a high transmittance to light and a low reflectivity to light, when the anode 301 of the light-emitting device 300 distributed in the second display partition 00a2 and the third display partition 00a3 is connected to the corresponding first pixel circuit 201 through the transparent connecting line L, it can be ensured that the light-emitting devices 300 distributed in the second display partition 00a2 and the third display partition 00a3 can be normally connected to the corresponding first pixel circuit 201, and the reflectivity of the second display partition 00a2 and the third display partition 00a3 to ambient light is basically consistent with the reflectivity of the first display partition 00a1 to ambient light, so that the reliability of the display panel 000 is higher.

[0124] In the embodiments of the present application, Fig.18 As shown, Fig.18 1 is a schematic diagram of the distribution of a transparent connecting line and an auxiliary signal routing line provided in an embodiment of the present application. The transparent connecting line L may include: a first transparent routing portion L1 and a second transparent routing portion L2 connected to each other. The extension direction of the first transparent routing portion L1 in the transparent connecting line L is the same as the extension direction of the auxiliary signal line G20, and the extension direction of the second transparent routing portion L2 intersects with the extension direction of the auxiliary signal line G20.

[0125] In the present application, the orthographic projection of the first transparent wiring portion L1 in each transparent connection line L in the display panel 000 on the substrate 100 may not overlap with the orthographic projection of the auxiliary signal line G20 on the substrate 100, and the orthographic projection of the second transparent wiring L2 in at least part of the transparent connection lines L in the display panel 000 on the substrate 100 overlaps. In this case, it can be ensured that the area of ​​the orthographic projection of the transparent connection line L in the display panel 000 on the substrate 100 overlaps with the orthographic projection of the auxiliary signal line G20 on the substrate 100 is small, so that the parasitic capacitance generated between the transparent connection line L and the auxiliary signal line G20 is small. For example, the area of ​​the orthographic projection of at least one transparent connection line L on the substrate 100 overlaps with the orthographic projection of at least one auxiliary signal line G20 on the substrate 100, which accounts for less than or equal to 30% of the total area of ​​the orthographic projection of at least one transparent connection line L on the substrate 100. In this way, it can be ensured that when the first pixel circuit 201 transmits a signal to the anode 301 of the corresponding light-emitting device 300 through the transparent connecting line L, the transparent connecting line L is less interfered by the auxiliary signal line G20, thereby ensuring that the light emitted by the light-emitting devices 300 in the second display partition 00a2 and the third display partition 00a3 has a better effect.

[0126] Optional, please refer to Fig.19 , Fig.19 Schematic diagram of the relative position relationship between the anode and the transparent signal line of a light-emitting device provided in an embodiment of the present application, wherein the orthographic projections of the anodes 301 of at least some of the light-emitting devices 300 located in the second display partition 00a2 and the third display partition 00a3 on the substrate 100 overlap with the orthographic projections of at least two of the transparent signal lines on the substrate. Here, there may be no electrical connection relationship between the anode 301 and the transparent signal line L whose orthographic projections on the substrate 100 overlap, that is, the transparent signal line L needs to pass through other light-emitting devices 300 before being electrically connected to the anode 301 in the corresponding light-emitting device 300.

[0127] In this case, please refer to Fig. 20 , Fig. 20 yes Fig.19 The schematic diagram of the film structure of the display panel at EE' shows that there are at least two transparent signal lines L below the anode 301 in the light-emitting device 300 (i.e., on the side close to the substrate 100). In this way, the flatness of the anode 301 can be ensured to be high, so that the light emitted by the light-emitting device 300 has a better effect.

[0128] In the embodiments of the present application, Fig. 20As shown, there is a first flat layer 701 between the conductive layer where the transparent signal line L in the display panel 000 is located and the conductive layer where the anode 301 is located. The conductive layer where the data signal line D10 in the display panel 000 is located can be located on the side of the first flat layer 701 facing the substrate 100, and the data signal line D10 in the display panel 000 can be arranged in the same layer and made of the same material as the VDD power supply signal line. Here, there is a second flat layer 702 between the conductive layer where the data signal line D10 is located and the conductive layer where the transparent signal line L is located. The auxiliary signal line G20 in the display panel 000 can be located on the side of the second flat layer 702 facing the substrate 100, and there is a third flat layer 703 between the conductive layer where the second auxiliary signal line G20 is located and the conductive layer where the data signal line D10 is located.

[0129] It should be noted that each pixel circuit 200 and GOA circuit 600 in the present application can be distributed on the side of the third flat layer 703 facing the substrate 100. To this end, it is necessary to open a connection through hole in the first flat layer 701, the second flat layer 702 and the third flat layer 703, so that the first pixel circuit 201 can be electrically connected to the anode 301 in the corresponding light-emitting device 300 through the connection through hole. In addition, the flat layer between the virtual pixel circuit 202 and the light-emitting device 300 in the display panel 000 is not provided with a connection through hole, so that the virtual pixel circuit 202 and the light-emitting device 300 can be insulated by the flat layer. Similarly, the flat layer between the GOA circuit 600 and the light-emitting device 300 in the display panel 000 is not provided with a connection via, so that the GOA circuit 600 and the light-emitting device 300 can be insulated by the flat layer.

[0130] In the embodiment of the present application, the display panel 000 may further include: an encapsulation layer. The encapsulation layer may be located on the side of the plurality of light-emitting devices 300 away from the substrate 100. The encapsulation layer may isolate water and oxygen in the external environment, so that water and oxygen in the external environment will not corrode the light-emitting layer 302 in the light-emitting device 300, thereby ensuring a longer service life of the light-emitting device 300.

[0131] In summary, the display panel provided by the embodiment of the present application includes: a substrate, a plurality of pixel circuits, a plurality of light-emitting devices, a plurality of data signal lines and a plurality of redundant signal lines. A redundant signal line may include: a first lead portion connected to a data signal line. Here, the first lead portion may be used as a part of a fan-out lead electrically connected to the data signal line. Since the redundant signal line is distributed in the display area, the part of the fan-out lead (that is, the first lead portion) used to be electrically connected to the data signal line can be distributed in the display area, so that when the part of the fan-out lead other than the first lead portion is distributed in the non-display area, the occupied space in the non-display is reduced, and the width of the area where the fan-out lead is set in the non-display area can be effectively reduced. In this way, the screen-to-body ratio of the display device integrating such a display panel can be effectively improved, so that the display effect of the display device is better. In addition, multiple data signal lines and multiple redundant signal lines can be located in the same conductive pattern, and this conductive pattern containing data signal lines and redundant signal lines can be evenly distributed in the display area. To this end, when a part of the first redundant signal line in the area where a column of virtual pixel circuits is located is used as the part of the fan-out lead located in the display area, it can be ensured that the various conductive layer patterns in the display panel are evenly distributed in the display area under the premise of ensuring that the part of the fan-out lead can be distributed in the display area, which can effectively reduce the probability of color deviation of the display panel and make the display effect of the display panel better.

[0132] The embodiment of the present application also provides a display device. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. The display device can include a power supply component and a display panel. The display panel can be the display panel in the above embodiment.

[0133] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It is also understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it is understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it is also understood that when a layer or element is referred to as being "between" two layers or two elements, it may be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0134] In the present application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "plurality" refers to two or more than two, unless otherwise clearly defined.

[0135] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: The display panel has a display area, and the display panel includes: substrate; A plurality of pixel circuits arranged in an array on one side of the substrate, the plurality of pixel circuits comprising: a plurality of first pixel circuits and a plurality of virtual pixel circuits; a plurality of light-emitting devices located on a side of the plurality of pixel circuits away from the substrate, the plurality of light-emitting devices being electrically connected to the plurality of first pixel circuits in a one-to-one correspondence; and, a plurality of data signal lines and a plurality of redundant signal lines located in the display area, wherein an extension direction of the data signal lines is the same as an extension direction of the redundant signal lines; Among them, one of the data signal lines is connected to a column of the first pixel circuits; one of the redundant signal lines is located in the area where a column of the virtual pixel circuits is located; at least some of the multiple redundant signal lines are first redundant signal lines, and one of the first redundant signal lines includes a first lead portion connected to one of the data signal lines.

2. The display panel according to claim 1, characterized in that: The display panel further comprises: a plurality of auxiliary signal lines located in the display area, wherein an extension direction of the auxiliary signal lines intersects an extension direction of the redundant signal lines; Among them, one of the auxiliary signal lines is located in the area where a row of pixel circuits is located; at least some of the multiple auxiliary signal lines are first auxiliary signal lines, and one of the first auxiliary signal lines includes: a second lead portion, one end of the second lead portion is electrically connected to one of the data signal lines, and the other end is electrically connected to one end of the first lead portion.

3. The display panel according to claim 2, characterized in that: One of the first redundant signal lines further includes: a redundant line body disconnected from the first lead portion; one of the first auxiliary signal lines further includes: an auxiliary line body disconnected from the second lead portion; Wherein, the redundant line body and the auxiliary line body are electrically connected at the intersection.

4. The display panel according to claim 3, characterized in that: A portion of the plurality of redundant signal lines is the first redundant signal line, another portion of the redundant signal lines is a second redundant signal line, the first lead portion is not provided in the second redundant signal line, and the second redundant signal line is electrically connected to the auxiliary line body at a crossing; And / or, a part of the multiple auxiliary signal lines are the first auxiliary signal lines, and another part of the auxiliary signal lines are second auxiliary signal lines, the second lead part is not set in the second auxiliary signal line, and the second auxiliary signal line is electrically connected to the redundant line body at the intersection.

5. The display panel according to claim 4, characterized in that: In a case where the display panel includes both the second redundant signal line and the second auxiliary signal line, the second redundant signal line is electrically connected to the second auxiliary signal line at a crossing point.

6. The display panel according to claim 4, characterized in that: The display panel further includes: a first power signal line; the second redundant signal line is electrically connected to the first power signal line, and / or the second auxiliary signal line is electrically connected to the first power signal line.

7. The display panel according to claim 6, characterized in that: The light emitting device comprises: an anode, a light emitting layer and a cathode layer which are stacked, wherein the anode is closer to the substrate than the cathode layer; The first pixel circuit is electrically connected to the anode of the corresponding light-emitting device, and the cathode layer is electrically connected to the first power signal line.

8. The display panel according to any one of claims 2 to 7, characterized in that: The display panel also has a non-display area located outside the display area; The display panel further comprises: a plurality of connection leads located in the non-display area and electrically connected to the plurality of data signal lines in a one-to-one correspondence, a portion of the plurality of connection leads being electrically connected to the corresponding data signal lines through the first lead portion and the second lead portion, and another portion of the plurality of connection leads being electrically connected directly to the corresponding data signal lines; Wherein, the plurality of connecting leads are used for binding and connecting with the driving component.

9. The display panel according to any one of claims 2 to 7, characterized in that: The redundant signal line and the data signal line are arranged in the same layer and made of the same material, and the redundant signal line and the auxiliary signal line are arranged in different layers.

10. The display panel according to any one of claims 1 to 7, characterized in that: The display panel further comprises: a gate driving circuit; the light emitting device comprises: an anode, a light emitting layer and a cathode layer which are stacked, the anode being closer to the substrate than the cathode layer; There is an overlapping area between the orthographic projection of the gate driving circuit on the substrate and the orthographic projection of the anode on the substrate.

11. The display panel according to claim 10, characterized in that: The display area includes: a first display partition, a second display partition and a third display partition, wherein the second display partition is located between the first display partition and the third display partition; The plurality of pixel circuits are all located in the first display subarea and the second display area, and are all located outside the third display subarea; at least part of the GOA circuit is located in the third display subarea; Among them, the pixel circuits located in the first display partition include the first pixel circuit and the virtual pixel circuit; the pixel circuits located in the second display partition among the multiple pixel circuits are all the first pixel circuits, and a part of the first pixel circuits located in the second display area is electrically connected to the light-emitting device located in the second display area, and another part of the first pixel circuits located in the second display area is electrically connected to the light-emitting device located in the third display area.

12. The display panel according to claim 11, characterized in that: In the first display partition, a plurality of columns of the first pixel circuits and a plurality of columns of the virtual pixel circuits are arranged alternately.

13. The display panel according to claim 12, characterized in that: N columns of the first pixel circuits are distributed between two adjacent columns of the virtual pixel circuits, where N is an integer greater than or equal to 2 and less than or equal to 6.

14. The display panel according to claim 11, characterized in that: The distribution density of the light emitting devices distributed in the first display partition is equal to the distribution density of the light emitting devices distributed in the second display partition.

15. The display panel according to claim 11, characterized in that: The plurality of columns of the first pixel circuits in the second display subarea are electrically connected to the anodes of the plurality of columns of the light emitting devices in the second display subarea and the third display subarea respectively.

16. The display panel according to claim 15, characterized in that: The display panel further includes: a plurality of transparent connection lines located in the second display area and the third display area; Wherein, the anodes of at least some of the light-emitting devices located in the second display subarea and the third display subarea are electrically connected to the corresponding first pixel circuits through the transparent connecting lines.

17. The display panel according to claim 16, characterized in that: The display panel further comprises: a plurality of auxiliary signal lines, some of the auxiliary signal lines being located in the second display subarea and the third display subarea; The transparent connecting line comprises: a first transparent wiring portion and a second transparent wiring portion connected to each other, wherein the extension direction of the first transparent wiring portion is the same as the extension direction of the auxiliary signal line, and the extension direction of the second transparent wiring portion intersects with the extension direction of the auxiliary signal line; Among them, the orthographic projection of the first transparent wiring portion on the substrate does not overlap with the orthographic projection of the auxiliary signal line on the substrate, and the orthographic projection of the second transparent wiring portion in at least part of the transparent connecting line on the substrate overlaps with the orthographic projection of the auxiliary signal line on the substrate.

18. The display panel according to claim 17, characterized in that: The area where the orthographic projection of at least one of the transparent connecting lines on the substrate overlaps with the orthographic projection of at least one of the auxiliary signal lines on the substrate accounts for less than or equal to 30% of the total area of ​​the orthographic projection of at least one of the transparent connecting lines on the substrate.

19. The display panel according to claim 16, characterized in that: The orthographic projections of anodes of at least some of the light-emitting devices located in the second display subarea and the third display subarea on the substrate overlap with the orthographic projections of at least two of the transparent signal lines on the substrate.

20. A display device, characterized in that: include: A power supply component, and a display panel electrically connected to the power supply component, wherein the display panel is the display panel according to any one of claims 1 to 19.

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