Automatic mirroring ROM

Abstract

A method is disclosed that may include detecting, by a control circuit coupled to a first read only memory (ROM) device and a second ROM device, a failure of a first output signal from the first ROM device to a common output. The first ROM device is connected to the common output, and the second ROM device is disconnected from the common output. The method also includes switching, by the control circuit, the common output from the first ROM device to the second ROM device in response to detecting the fault. Various other methods, systems, and computer readable media are also disclosed.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. non-provisional application No. 17 / 855,628, filed on June 30, 2022, and entitled “AUTOMATIC MIRRORED ROM,” which claims the benefit of Chinese provisional application No. 202210575524.8, filed on May 25, 2022, and entitled “MIRRORED SPIROM DESIGN TO INCREASE SYSTEM STABILITY,” the entire contents of which are incorporated herein by reference. Background Art

[0003] Computing devices may use read-only memory (ROM) for storing application-specific data and / or software, such as firmware. The ROM chip may typically be soldered to a printed circuit board (PCB) of the computing device, or may be otherwise incorporated into the computing device in a manner that makes the ROM chip difficult to replace in the event of any failure of the ROM chip. Therefore, many computing devices may incorporate a second ROM chip to act as a backup ROM.

[0004] However, using a backup ROM chip may require a manual process. Detecting a failure in the first ROM chip itself may require manual intervention. Even if a failure can be detected automatically, switching to the second ROM chip may require manual reconfiguration of the device. For example, a user may need to reconfigure the device to use different chip select pins, update the device's BIOS, and / or other operations that would typically require restarting the device. Therefore, using a backup ROM chip may disrupt normal operation of the device. Summary of the invention

[0005] As will be described in more detail below, the present disclosure describes various systems and methods for automatically decoupling a first ROM device from a common output and connecting a second ROM device to the common output in response to detecting a failure of the first ROM device. The second ROM device may mirror the first ROM device to serve as a backup ROM device.

[0006] In one example, a method for automatic ROM switching may include detecting, by a control circuit coupled to a first read-only memory (ROM) device and a second ROM device, a fault of a first output signal from the first ROM device to a common output. The first ROM device may be connected to the common output, and the second ROM device may be disconnected from the common output. The method may also include switching, by the control circuit, the common output from the first ROM device to the second ROM device in response to detecting the fault.

[0007] In some examples, switching the common output from the first ROM device to the second ROM device may be responsive to detecting, by the control circuit, a second output signal from the second ROM device. In some examples, detecting the failure of the first output signal may further include comparing, by the control circuit, the first output signal with the second output signal from the second ROM device. In some examples, detecting the failure may further include detecting a logic low signal on the first output signal and a logic high signal on the second output signal. In some examples, detecting the failure of the first output signal may further include evaluating the delayed first output signal with the first output signal.

[0008] In some examples, the first ROM device and the second ROM device may operate simultaneously. In some examples, the first ROM device and the second ROM device may both be connected to a common input. In some examples, the second ROM device may mirror the first ROM device.

[0009] In one embodiment, a system for automatically mirroring a ROM may include a first read-only memory (ROM) device coupled to a common output, a second ROM device disconnected from the common output, and control circuitry coupled to the first ROM device and the second ROM device, the control circuitry configured to detect a failure of the first ROM device on the common output and, in response, switch the second ROM device to the common output.

[0010] In some examples, switching the second ROM device to the common output may be further responsive to detecting, by the control circuit, a second output signal from the second ROM device. In some examples, detecting the failure of the first ROM device may further include comparing, by the control circuit, the first output signal of the first ROM device with the second output signal of the second ROM device. In some examples, detecting the failure of the first ROM device may further include detecting at least one of: a logic low signal on the first output signal and a logic high signal on the second output signal, a continuous logic signal on the first output signal that is inconsistent with the second output signal, and a change in the first output signal from the logic high signal to the logic low signal that is inconsistent with the second output signal.

[0011] In one embodiment, a system for automatically mirroring ROM may include at least one physical processor, physical memory, a first read-only memory (ROM) device coupled to a common output, a second ROM device disconnected from the common output, and control circuitry coupled to the first ROM device and the second ROM device, the control circuitry configured to automatically couple the second ROM device to the common output in response to detecting a failure of the first ROM device.

[0012] Features from any of the above-described embodiments may be used in combination with each other according to the general principles described herein. These and other embodiments, features and advantages will be more fully understood when the following detailed description is read in conjunction with the accompanying drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings illustrate several exemplary embodiments and are a part of the specification. Together with the following description, these drawings demonstrate and explain various principles of the present disclosure.

[0014] Figure 1 is a block diagram of an exemplary system for automatically mirroring a ROM.

[0015] Figure 2A is a basic circuit diagram of an exemplary automatic mirroring ROM.

[0016] Figure 2B is corresponding to Figure 2A Signal diagram of the circuit.

[0017] Figure 3A is a basic circuit diagram of an exemplary automatic mirroring ROM.

[0018] Figure 3B is corresponding to Figure 3A Signal diagram of the circuit.

[0019] Figure 4 is a flow chart of an exemplary method for automatic switching of a mirrored ROM design.

[0020] In all drawings, the same reference numerals and descriptions represent similar but not necessarily identical elements. Although the exemplary embodiments described herein may have various modifications and alternative forms, specific embodiments are shown by way of example in the drawings and described in detail herein. However, the exemplary embodiments described herein are not intended to be limited to the specific forms disclosed. On the contrary, the present disclosure covers all modifications, equivalents, and alternatives that fall within the scope of the appended claims. DETAILED DESCRIPTION

[0021] The present disclosure as a whole relates to a dual ROM design that can automatically switch from one ROM chip to another ROM chip. As will be explained in more detail below, embodiments of the present disclosure can detect a failure of a first output signal from a first ROM, and switch to a second ROM in response. The present disclosure provides a device with a mirrored ROM design that can automatically switch from a first ROM to a second ROM when a first ROM fails. Advantageously, the switch can occur seamlessly without requiring reconfiguration or restarting of the device.

[0022] The features of any of the embodiments described herein may be used in combination with each other according to the general principles described herein. These and other embodiments, features and advantages will be more fully understood when the following detailed description is read in conjunction with the accompanying drawings and claims.

[0023] refer to Figures 1 to 4 , a detailed description of the automatic mirroring ROM is provided below. Figure 1 A detailed description of an example system with an automatic mirroring ROM is provided. FIG. 2A to FIG. 2B A detailed description of an example circuit and its signals for an automatic mirroring ROM is provided. FIG. 3A to FIG. 3B A detailed description of another example circuit and its signals for an automatic mirroring ROM is provided. Figure 4 A detailed description of the corresponding computer-implemented method is provided.

[0024] Figure 1 1 is a block diagram of an example system 100 of a dual ROM design capable of automatic switching. System 100 may correspond to a computing device such as a desktop computer, a laptop computer, a server, a tablet device, a mobile device, a smart phone, a wearable device, an augmented reality device, a virtual reality device, a network device, and / or an electronic device. Figure 1 As shown, system 100 may include one or more memory devices, such as memory 120. Memory 120 generally represents any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. Examples of memory 120 include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical drive, cache, one or more variations or combinations of the above, and / or any other suitable storage memory.

[0025] like Figure 1 As shown, the example system 100 may include one or more physical processors, such as processor 110. Processor 110 generally represents a hardware-implemented processing unit of any type or form capable of interpreting and / or executing computer-readable instructions. In some examples, processor 110 may access and / or modify data and / or instructions stored in memory 120. Examples of processor 110 include, but are not limited to, a microprocessor, a microcontroller, a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA) implementing a soft-core processor, an application-specific integrated circuit (ASIC), a system on a chip (SoC), a digital signal processor (DSP), a neural network engine (NNE), an accelerator, a graphics processing unit (GPU), one or more of the above, one or more variations or combinations of the above, and / or any other suitable physical processor.

[0026] like Figure 1 As further shown, system 100 may include control circuit 112, ROM 114, ROM 116, and common output 160. ROM 114 may be a ROM device, and in some examples, ROM 116 may be a mirror image of ROM 116 (e.g., having the same speed, size, data, etc.). Control circuit 112 may be coupled to both ROM 114 and ROM 116, and more specifically, in some examples, to an output of ROM 114 and an output of ROM 116. Control circuit 112 may include switching circuits and / or elements for switching between the outputs of ROM 114 and ROM 116, such that one of the outputs of ROM 114 and ROM 116 (e.g., common output 160) may be coupled to processor 110 and / or memory 120 (e.g., coupled to a bus connected to processor 110 and / or memory 120). In other words, control circuit 150 may control which output of ROM 130 and ROM 140 is connected to common output 160. Furthermore, in some examples, a common input (eg, a signal sent from processor 110 and / or memory 120) may be coupled to ROM 130 and ROM 140. For example, any updates to ROM 130 may also be mirrored to ROM 140.

[0027] Figure 2A An example circuit 200 is shown, and Figure 2B 2 shows a signal diagram 201 of the circuit 200. The circuit 200 may include a ROM 230 (e.g., ROM #1) that may correspond to the ROM 130, a ROM 240 (e.g., ROM #2) that may correspond to the ROM 140, and a control circuit 250 that may correspond to the control circuit 150. The control circuit 250 may include a logic block 251, which may include, for example, Figure 2A The inverter shown is used to evaluate the output of ROM 230. In other examples, logic block 251 may include other components and / or circuits (see, for example, Figure 3A ). Further reference Figure 2B , various signals are shown, including clock 270, switching signal 252, output 260, and select signal 254. In some examples, one or more components of circuit 200 can communicate via a serial peripheral interface (SPI), although other interfaces can be used in other examples. Circuit 200 shows one example of a circuit for automatically mirroring a ROM.

[0028] like Figure 2BAs shown, clock 270 may provide a clock signal for coordinating various circuit components, such as by using rising edges for synchronization. At time t0, the output signal of ROM 240 may have a logic high, while ROM 230 has a logic low. As described herein, ROM 240 may mirror ROM 230 so that the same logic signal (e.g., high or low) should be expected at any given time. However, at time t0, because ROM 230 outputs a logic low when a logic high is expected (as indicated by ROM 240), ROM 230 may have experienced a fault that prevents ROM 230 from outputting the expected logic high.

[0029] The control circuit 250 can detect a fault in the ROM 230 and replace the output of the ROM 230 with the output of the ROM 240 to output 260, such as Figure 2B More specifically, Figure 2A In the example shown, the control circuit 250 may use a switching signal 252. The switching signal 252 may be derived from the outputs of the ROM 230 and the ROM 240. At time t0, the logic low output from the ROM 230 may be inverted to a logic high by an inverter (or NOT gate). The XOR gate may combine the logic low output from the ROM 230 and the logic high output from the ROM 240 to output a logic high (e.g., because the exclusive OR—XOR—may produce a logic high when only one of its two inputs is a logic high). The inverted signal (e.g., a logic high at time t0) and the XOR signal (e.g., a logic high at time t0) may be combined with an AND gate—to output a switching signal 252 that is a logic high at time t0—the AND gate produces a logic high when both of its inputs are logic high.

[0030] like Figure 2A As further indicated, control circuit 250 may include active-low tri-state buffers—allowing data to pass when a logic low is applied to their control lines—that are each coupled to the outputs of ROM 230 and ROM 240, respectively, and controlled by switching signal 252. More specifically, switching signal 252 may control the buffer coupled to ROM 230, and switching signal 252 inverted by an inverter may control the buffer coupled to ROM 240. Thus, at time t0, a logic high of switching signal 252 controlling the buffer of ROM 230 may disable the output from ROM 230. Furthermore, at time t0, the logic high of switching signal 252 is inverted to a logic low for controlling the buffer of ROM 240, enabling output from ROM 240 to output 260. Thus, when ROM 230 fails, control circuit 250 may automatically switch output 260 from ROM 230 to ROM 240.

[0031] When the switching signal 252 is logic high, the switching signal 252 may only switch the output 260 from the ROM 230 to the ROM 240. When the switching signal 252 is logic low, the buffer of the ROM 230 may be enabled, and the buffer of the ROM 240 may be disabled (e.g., because the switching signal 252 is inverted to logic high). In the case where the ROM 230 outputs a logic high and the ROM 240 outputs a logic low (which may indicate a failure of the ROM 240), the first inverter coupled to the ROM 230 generates a logic low signal input to the AND gate, so that the switching signal 252 is logic low. In the case where the ROM 230 and the ROM 240 output the same signal (e.g., both are logic high or both are logic low), the XOR gate generates a logic low signal input to the AND gate, so that the switching signal 252 is logic low.

[0032] In some examples, control circuit 250 may also use select signal 254 for selecting between ROM 230 and ROM 240. In some examples, select signal 254 may correspond to a chip select signal of the SPI, which may indicate which component (e.g., between ROM 230 and ROM 240) should send data and which component should be disconnected from the SPI bus. In some examples, chip select may be active low logic, such that when select signal 254 is logic high, ROM 230 may be connected (and ROM 240 disconnected), and when select signal 254 is logic low, ROM 230 may be disconnected (and ROM 240 connected).

[0033] Figure 3A An example circuit 300 is shown, and Figure 3B 3 shows a signal diagram 301 of circuit 300. Circuit 300 may include ROM 330 (e.g., ROM #1) that may correspond to ROM 130, ROM 340 (e.g., ROM #2) that may correspond to ROM 140, and control circuit 350 that may correspond to control circuit 150. Control circuit 350 may include logic block 351 for evaluating the output of ROM 330. Figure 3A As shown, logic block 351 may include a NAND gate and 2N+1 inverters, where N is an integer corresponding to a desired signal delay amount (eg, clock cycle or other delay amount). Figure 3B , various signals are shown, including clock 370, XOR output 356, delayed ROM 332, NAND output 358, switch signal 352, select signal 354, and output 360. In some examples, one or more components of circuit 300 can communicate via SPI, although other interfaces can be used in other examples.

[0034] Circuit 300 illustrates another example of a circuit for automatically mirroring a ROM, which may be a variation of circuit 200 and operates similarly to that circuit, but adds a delayed output signal for ROM 330 (e.g., delayed ROM 332) for determining a failure of ROM 330 and / or preventing a failure of ROM 340 from triggering a switch. The outputs of ROM 330 and delayed ROM 332 may be the outputs of ROM 330 delayed by a single clock cycle and inverted, which may be input to a NAND gate—which produces a NAND output 358—which produces a logic low only when both of its inputs are logic high. The fact that both ROM 330 and delayed ROM 332 are logic high indicates that the output of ROM 330 has changed from a logic low at the previous cycle to a logic high at the current cycle (e.g., at Figure 3B ), which does not indicate a fault, so that the logic low of NAND output 358 does not indicate a fault.

[0035] Switching signal 352 is output from the AND combination of NAND output 358 and XOR output 356. Similar to switching signal 252, switching signal 352 may only switch output 360 from ROM 330 to ROM 340 when switching signal 352 is high. Thus, a logic low from NAND output 358 may not trigger switching.

[0036] When both ROM 330 and delayed ROM 332 are logic low, or when ROM 330 and delayed ROM 332 are different, NAND output 358 may be logic high. Both ROM 330 and delayed ROM 332 being logic low indicates that the output of ROM 330 has changed from a logic high at the previous cycle to a logic low at the current cycle, which may indicate a failure of ROM 330 (e.g., a failure after the previous cycle), so that the logic high of NAND output 358 may indicate a failure of ROM 330. However, ROM 330 and delayed ROM 332 being different does not necessarily indicate a failure, because the difference may be due to a valid continuous logic low or logic high in the output. XOR output 356 may indicate whether a continuous logic low or logic high is valid.

[0037] like Figure 3AAs shown, XOR output 356 may be an XOR combination of ROM 330 and ROM 340. XOR output 356 may only be a logic high when ROM 330 and ROM 340 output different signals, which may indicate that one of ROM 330 and ROM 340 has failed. Therefore, if XOR output 356 is a logic low (indicating that ROM 330 and ROM 340 output the same signal) and NAND output 358 is a logic high (e.g., a continuous logic low or logic high of ROM 330 is verified by XOR output 356), then switching signal 352 will be a logic low so that switching will not occur. However, if XOR output 356 is a logic high (indicating a failure of one of ROM 330 and ROM 340) and NAND output 358 is a logic high (e.g., a continuous logic low or logic high of ROM 330 is not verified by XOR output 356), switching signal 352 will be a logic high so that switching will automatically occur. In other words, if ROM 330 maintains a logic signal or changes from a logic high to a logic low that is inconsistent with ROM 340 , control circuit 350 may automatically switch output 360 from ROM 330 to ROM 340 .

[0038] Figure 3A and Figure 3B It is further shown how a failure of ROM 340 may also prevent control circuit 350 from switching output 360 from ROM 330 to ROM 340. Figure 3B As shown, a failure of ROM 340 may manifest as a continuous logic low output from ROM 340. While XOR output 356 may indicate a difference between the outputs of ROM 330 and ROM 340 (such as at time t0), NAND output 358 may indicate valid activity from ROM 330. For example, if ROM 340 fails and only produces a logic low, then ROM 330 going from a logic low to a logic high (producing a logic low NAND output 358, which further produces a logic low switching signal 352, as shown at time t0) may prevent switching.

[0039] In some examples, control circuit 350 may also use select signal 354 for selecting between ROM 330 and ROM 340. In some examples, select signal 354 may correspond to a chip select signal of the SPI, which may indicate which component (e.g., between ROM 330 and ROM 340) should send data and which component should be disconnected from the SPI bus. In some examples, chip select may be active low logic, such that when select signal 354 is logic high, ROM 330 may be connected (and ROM 340 disconnected), and when select signal 354 is logic low, ROM 330 may be disconnected (and ROM 340 connected).

[0040] Figure 4 is a flow chart of an exemplary computer-implemented method 400 for automatic switching of ROM devices. Figure 4 The steps shown in may be performed by any suitable computer executable code and / or computing system, including Figure 1 , Figure 2A and / or Figure 3A In one example, Figure 4 Each of the steps shown in may represent an algorithm whose structure includes and / or is represented by a plurality of sub-steps, examples of which are provided in more detail below.

[0041] like Figure 4 As shown, at step 402, one or more of the systems described herein may detect a fault of a first output signal from a first read-only memory (ROM) device to a common output by a control circuit coupled to a first ROM device and a second ROM device. The first ROM device may be connected to the common output, and the second ROM device may be disconnected from the common output. For example, the output of ROM 130 may be connected to the common output 160, and the output of ROM 140 may be disconnected from the common output 160. The control circuit 150 may detect a fault of the output signal from ROM 130.

[0042] The systems described herein can perform step 402 in various ways. In one example, the first ROM device and the second ROM device can operate simultaneously. In addition, the first ROM device and the second ROM device can both be connected to a common input so that any data input to the first ROM device can be input to the second ROM device. More specifically, the second ROM device can mirror the first ROM device. For example, ROM 140 can share the same size, speed, data, etc. as ROM 130 so as to be used as a backup ROM for ROM 130. In addition, therefore, ROM 130 and ROM 140 can operate and / or behave the same, even though only one ROM can output to the common output 160.

[0043] In some examples, detecting a fault in the first output signal from the first ROM device may further include comparing, by the control circuit, the first output signal with a second output signal from the second ROM device. For example, detecting a fault in the first output signal from the first ROM device may include detecting a logic low signal on the first output signal and a logic high signal on the second output signal.

[0044] Because ROM 130 and ROM 140 may be designed to behave identically, any difference between the outputs may indicate a failure of either ROM 130 or ROM 140. For example, if ROM 140 outputs a logic high signal (indicating output data) and ROM 130 outputs a logic low signal (as indicated by ROM 140) when a logic high signal is expected, such a difference in the outputs may indicate that ROM 130 exhibits a failure.

[0045] In some examples, detecting a failure of the first ROM may include detecting at least one of a persistent logic signal on the first output signal that is inconsistent with the second output signal, and the first output signal changing from a logic high signal to a logic low signal that is inconsistent with the second output signal. As described above (see, e.g., Figure 3A and Figure 3B ), if ROM 130 outputs the same logic signal in the previous clock cycle and the current clock cycle that is inconsistent with the output of ROM 140 in the current clock cycle, the control circuit 150 may switch the common output 160 from ROM 130 to ROM 140. In addition, if ROM 130 outputs a logic high in the previous clock cycle and a logic low in the current clock cycle, and ROM 140 outputs a logic high in the current clock cycle, the control circuit 150 may switch the common output 160.

[0046] In yet other examples, control circuit 150 may detect faults in ROM 130 in other ways, such as detecting weak (e.g., not reaching a logic high) and / or corrupted signals, unexpected delays in signals, detecting faults via one or more sensors, etc.

[0047] At step 404, one or more of the systems described herein may switch the common output from the first ROM device to the second ROM device by the control circuit in response to detecting the fault. For example, the control circuit 150 may automatically disconnect the ROM 130 from the common output 160 and connect the ROM 140 to the common output 160 in response to detecting the fault.

[0048] The systems described herein can perform step 404 in various ways. In one example, switching the common output from the first ROM device to the second ROM device can be further responsive to detecting, by the control circuit, a second output signal from the second ROM device. For example, as described above, the control circuit 150 can detect a logic high signal from the ROM 140 while the ROM 130 outputs a logic low or no signal.

[0049] In other examples, control circuit 150 may further determine that ROM 140 has not failed, or prevent switching if ROM 140 has failed. For example, detecting a logic low output from ROM 130 in a previous clock cycle and a logic high output from ROM 130 in a current clock cycle may prevent control circuit 150 from switching common output 160 even though ROM 140 outputs a logic low signal (inconsistent with ROM 130) in the current clock cycle.

[0050] As described above, many server / workstation designs may have a dual SPI ROM design to increase system stability. A dual ROM design may provide a backup ROM when the primary ROM fails. However, the two ROMs may reside on different chip select pins, so when one ROM is damaged or otherwise fails, the user may need to restart the system, and the firmware may need to be updated to extract code from the other ROM by using different chip select pins. The present disclosure allows the ROM to be switched transparently to the end user. If one ROM becomes damaged, the system described herein may automatically switch to the backup ROM without the need to power down or restart or change the BIOS code.

[0051] The present disclosure provides a mirrored SPI ROM design, where the second ROM is a backup chip. When the main ROM becomes damaged or otherwise fails, the system described herein can detect the failure (e.g., by detecting that the main ROM has no output) and automatically switch to the backup ROM, so that the system can still extract code from the backup ROM without the need to power down or restart to replace the ROM. This can advantageously help increase system stability.

[0052] This design allows the dual ROMs to act as mirror ROMs, sharing the same SPI bus signals and the same chip select pins. However, only one ROM can provide data output at a time, allowing the second ROM to be used as a backup and connected as needed. When the primary ROM fails, the system can automatically switch to the second (backup) ROM. To further improve on the current dual SPI ROM design, the system can remain powered on while switching from the bad ROM to the good ROM. This type of design may be advantageous for systems that require long runtimes and may not otherwise be easily restarted or powered down. In addition, if the second ROM fails, the switch can be prevented.

[0053] As mentioned above, the computing devices and systems described and / or illustrated herein broadly represent any type or form of computing devices or systems capable of executing computer-readable instructions. In its most basic configuration, these computing devices may each include at least one memory device and at least one physical processor.

[0054] In some examples, the term "memory device" generally refers to any type or form of volatile or non-volatile storage device or medium capable of storing data and / or computer-readable instructions. In one example, a memory device can store, load, and / or maintain one or more of the modules described herein. Examples of memory devices include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), optical drive, cache, one or more variations or combinations of the foregoing, or any other suitable storage memory.

[0055] In some examples, the term "physical processor" generally refers to any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In one example, the physical processor can access and / or modify one or more modules stored in the above-mentioned memory device. Examples of physical processors include, but are not limited to, microprocessors, microcontrollers, central processing units (CPUs), field programmable gate arrays (FPGAs) implementing soft-core processors, application-specific integrated circuits (ASICs), systems on chips (SOCs), digital signal processors (DSPs), neural network engines (NNEs), accelerators, graphics processing units (GPUs), one or more of the above, one or more variations or combinations of the above, or any other suitable physical processors.

[0056] In some embodiments, the term "computer-readable medium" generally refers to any form of device, carrier, or medium capable of storing or carrying computer-readable instructions. Examples of computer-readable media include, but are not limited to, transmission-type media such as carrier waves, and non-transitory media such as magnetic storage media (e.g., hard drives, tape drives, and floppy disks), optical storage media (e.g., compact disks (CDs), digital video disks (DVDs), and Blu-ray disks), electronic storage media (e.g., solid-state drives and flash memory media), and other distribution systems.

[0057] The process parameters and order of steps described and / or illustrated herein are given by way of example only and may be changed as desired. For example, although the steps illustrated and / or described herein may be shown or discussed in a particular order, the steps do not necessarily need to be performed in the order illustrated or discussed. The various exemplary methods described and / or illustrated herein may also omit one or more of the steps described or illustrated herein, or include additional steps in addition to those disclosed.

[0058] The foregoing description has been provided to enable others skilled in the art to best utilize the various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed by the invention. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. In determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0059] Unless otherwise indicated, the terms "connected to" and "coupled to" (and their derivatives) as used in the specification and claims should be interpreted as allowing both direct and indirect (i.e., via other elements or components) connections. In addition, the terms "a" or "an" as used in the specification and claims should be interpreted to mean "at least one of the following". Finally, for ease of use, the terms "including" and "having" (and their derivatives) as used in the specification and claims are interchangeable with the word "comprising" and have the same meaning as the word "including".

Claims

1. A method, comprising: detecting, by a control circuit coupled to a first read-only memory (ROM) device and a second ROM device, a failure of a first output signal from the first ROM device to a common output, wherein the first ROM device is connected to the common output and the second ROM device is disconnected from the common output; as well as In response to detecting the fault, the common output is switched by the control circuit from the first ROM device to the second ROM device.

2. The method of claim 1 , wherein switching the common output from the first ROM device to the second ROM device is further responsive to: detecting, by the control circuit, a second output signal from the second ROM device; and The first output signal is compared by the control circuit with the second output signal from the second ROM device.

3. The method of claim 2, wherein detecting the failure of the first output signal from the first ROM device further comprises detecting a logic low signal on the first output signal and a logic high signal on the second output signal.

4. The method of claim 2, wherein detecting the failure of the first output signal from the first ROM further comprises evaluating a delayed first output signal with the first output signal.

5. The method of claim 1, wherein the first ROM device and the second ROM device operate simultaneously.

6. The method of claim 1, wherein the first ROM device and the second ROM device are both connected to a common input.

7. The method of claim 1, wherein the second ROM device mirrors the first ROM device.

8. A system, comprising: a first read-only memory (ROM) device coupled to the common output; a second ROM device disconnected from the common output; and A control circuit is coupled to the first ROM device and the second ROM device, the control circuit being configured to detect a failure of the first ROM device on the common output and, in response, switch the second ROM device to the common output.

9. The system of claim 8, wherein switching the second ROM device to the common output is further responsive to detecting, by the control circuit, a second output signal from the second ROM device.

10. The system of claim 9, wherein detecting the failure of the first ROM device further comprises comparing, by the control circuit, a first output signal of the first ROM device with a second output signal of the second ROM device.

11. The system of claim 10, wherein detecting the failure of the first ROM device further comprises detecting at least one of: a logic low signal on the first output signal and a logic high signal on the second output signal, a continued logic signal on said first output signal that is inconsistent with said second output signal, and The first output signal changes from the logic high signal to the logic low signal inconsistent with the second output signal.

12. The system of claim 8, wherein the first ROM device and the second ROM device operate simultaneously.

13. The system of claim 8, wherein the second ROM device mirrors the first ROM device.

14. The system of claim 8, wherein the first ROM device and the second ROM device are both connected to a common input.

15. A system, comprising: at least one physical processor; Physical storage; a first read-only memory (ROM) device coupled to the common output; a second ROM device disconnected from the common output; and A control circuit is coupled to the first ROM device and the second ROM device, the control circuit being configured to automatically couple the second ROM device to the common output in response to detecting a failure of the first ROM device.

16. The system of claim 15, wherein detecting the failure of the first ROM device further comprises comparing, by the control circuit, a first output signal of the first ROM device with a second output signal of the second ROM device.

17. The system of claim 16, wherein detecting the failure of the first ROM device further comprises detecting at least one of: a logic low signal on the first output signal and a logic high signal on the second output signal, a continued logic signal on said first output signal that is inconsistent with said second output signal, and The first output signal changes from the logic high signal to the logic low signal inconsistent with the second output signal.

18. The system of claim 15, wherein the first ROM device and the second ROM device operate simultaneously.

19. The system of claim 15, wherein the first ROM device and the second ROM device are both connected to a common input.

20. The system of claim 15, wherein the second ROM device mirrors the first ROM device.

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