Channel and sub-channel throttling for memory controller

Abstract

The arbiter is operable to select a command from the command queue to dispatch to the memory. The arbiter includes a flow throttling circuit for cooperating with one or more additional arbiters to mitigate an increase in excess power usage. The flow throttling circuit comprises a monitoring circuit and a throttling circuit. Monitoring circuitry is used to measure the number of read and write commands selected by the arbiter and one or more additional arbiters for a first predetermined period of time. A throttling circuit limits the number of read and write commands issued by the arbiter during a second predetermined time period in response to the low activity state.

Description

Background Art

[0001] Computer systems typically use cheap and high-density dynamic random access memory (DRAM) chips as main memory. Most DRAM chips sold today are compatible with various double data rate (DDR) DRAM standards issued by the Joint Electron Device Engineering Council (JEDEC). DDR DRAM uses a conventional DRAM memory cell array with a high-speed access circuit to achieve high transfer rates and improve the utilization of the memory bus. A DDR memory controller can interface with multiple DDR channels to accommodate more DRAM modules and exchange data with the memory faster than using a single channel. In addition, modern server systems typically include multiple memory controllers in a single data processor. For example, some modern server processors include eight or twelve memory controllers, each of which is connected to a corresponding DDR channel.

[0002] Traffic on a memory channel is sometimes throttled or slowed down to save power. Such throttling occurs over a relatively long period of time relative to the memory clock speed, and is achieved, for example, by adjusting the memory clock and / or the memory controller clock. Traffic on a memory channel is often "bursty," that is, it may have idle periods or periods of low traffic followed by periods of high traffic. The memory controller may also be placed into a low power mode in which it does not issue commands to the memory, and then begins issuing commands when the low power mode ends. Especially when multiple memory controllers are involved, such sudden increases in traffic can cause unwanted spikes in the current consumed by the memory controller and memory channel circuitry. These peaks may occur over relatively short periods of time compared to the memory clock speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 A data processing system 100 according to the prior art is shown in block diagram form;

[0004] Figure 2 The block diagram shows a Figure 1 An APU is used in data processing system 100.

[0005] Figure 3 illustrates in block diagram form a memory system including multiple memory controllers according to some embodiments;

[0006] Figure 4 The block diagram shows a device suitable for use with Figure 2 The dual-channel memory controller used in the APU is similar to the data processing system of the APU.

[0007] Figure 5is a flow chart of another process for throttling traffic at a memory controller according to some embodiments;

[0008] Figure 6 shows in block diagram form a flow throttling circuit according to some embodiments; and

[0009] Figure 7 is a flow diagram of another process for throttling flow according to some embodiments.

[0010] In the following description, the same reference numerals are used in different drawings to indicate similar or identical items. Unless otherwise specified, the word "couple" and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise specified, any description of direct connection also means an alternative embodiment using an appropriate form of indirect electrical connection. DETAILED DESCRIPTION

[0011] The memory controller is operable to select commands from the command queue to dispatch to the memory. The memory controller includes an arbitrator and a flow throttling circuit, the flow throttling circuit being used to cooperate with one or more additional arbitrators to mitigate excess power usage increases. The flow throttling circuit includes a monitoring circuit and a throttling circuit. The monitoring circuit is used to measure the number of read and write commands selected by the arbitrator and the one or more additional arbitrators within a first predetermined time period. The throttling circuit is responsive to a low activity state associated with the read and write commands, and limits the number of read and write commands issued by the arbitrator during a second predetermined time period.

[0012] A method cooperates with one or more additional arbitrators to mitigate excessive power usage increases at an arbitrator. The method includes measuring a number of read and write commands picked up by the arbitrator and the one or more additional arbitrators during a first predetermined time period. The method includes limiting the number of read and write commands issued by the arbitrator during a second predetermined time period in response to a low activity state associated with the read and write commands.

[0013] A processing system includes a data processor and a plurality of memory channels connecting the data processor to a memory. A memory controller is operable to select commands from a command queue to be dispatched to a memory for one of the memory channels. The memory controller includes an arbitrator and a flow throttling circuit, the flow throttling circuit being used to cooperate with one or more additional arbitrators to mitigate excess power usage increases, the one or more additional arbitrators being used for corresponding memory channels in the memory channels. The flow throttling circuit includes a monitoring circuit and a throttling circuit. The monitoring circuit measures the number of read and write commands selected by the arbitrator and the one or more additional arbitrators within a first predetermined time period. The throttling circuit is connected to the monitoring circuit and the arbitrator, and the throttling circuit is responsive to a low activity state associated with the read and write commands, and limits the number of read and write commands issued by the arbitrator during a second predetermined time period.

[0014] Figure 1 A data processing system 100 according to the prior art is shown in block diagram form. The data processing system 100 typically includes a data processor 110 in the form of an accelerated processing unit (APU), a memory system 120, a peripheral component interconnect express (PCIe) system 150, a universal serial bus (USB) system 160, and a disk drive 170. The data processor 110 operates as a central processing unit (CPU) of the data processing system 100 and provides various buses and interfaces available in modern computer systems. These interfaces include two double data rate (DDRx) memory channels, a PCIe root complex for connecting to a PCIe link, a USB controller for connecting to a USB network, and an interface to a serial advanced technology attachment (SATA) mass storage device.

[0015] Memory system 120 includes memory channel 130 and memory channel 140. Memory channel 130 includes a set of dual inline memory modules (DIMMs) connected to DDRx bus 132, including representative DIMMs 134, 136, and 138, which correspond to separate memory ranks in this example. Similarly, memory channel 140 includes a set of DIMMs connected to DDRx bus 142, including representative DIMMs 144, 146, and 148.

[0016] The PCIe system 150 includes a PCIe switch 152 (which is connected to a PCIe root complex in the data processor 110), a PCIe device 154, a PCIe device 156, and a PCIe device 158. The PCIe device 156 is in turn connected to a system basic input / output system (BIOS) memory 157. The system BIOS memory 157 may be any of a variety of non-volatile memory types, such as a read-only memory (ROM), a flash electrically erasable programmable ROM (EEPROM), etc.

[0017] USB system 160 includes a USB hub 162 connected to a USB host in data processor 110, and representative USB devices 164, 166, and 168 each connected to USB hub 162. USB devices 164, 166, and 168 may be devices such as keyboards, mice, flash EEPROM ports, and the like.

[0018] The disk drive 170 is connected to the data processor 110 via a SATA bus and provides mass storage for an operating system, application programs, application files, and the like.

[0019] By providing memory channel 130 and memory channel 140, data processing system 100 is suitable for use in modern computing applications. Each of memory channels 130 and 140 can be connected to the most advanced DDR memory (such as DDR version four (DDR4), low power DDR4 (LPDDR4), graphics DDR version five (GDDR5)) and high bandwidth memory (HBM), and can be adapted to future memory technologies. These memories provide high bus bandwidth and high-speed operation. At the same time, they also provide low power modes to save power for battery-powered applications such as laptops, and also provide built-in thermal monitoring.

[0020] Figure 2 The block diagram shows a suitable Figure 1 The APU 200 is used in a data processing system similar to the system 100 of the present invention. The APU 200 generally includes a central processing unit (CPU) core complex 210, a graphics core 220, a set of display engines 230, a memory management hub 240, a data fabric 250, a set of peripheral controllers 260, a set of peripheral bus controllers 270, a system management unit (SMU) 280, and a set of memory controllers 290.

[0021] The CPU core complex 210 includes a CPU core 212 and a CPU core 214. In this example, the CPU core complex 210 includes two CPU cores, but in other embodiments, the CPU core complex 210 may include any number of CPU cores. Each of the CPU cores 212 and 214 is bidirectionally connected to a system management network (SMN) (which forms a control structure) and a data structure 250, and can provide memory access requests to the data structure 250. Each of the CPU cores 212 and 214 can be a unitary core, or can also be a core complex with two or more unitary cores that share certain resources such as cache.

[0022] The graphics core 220 is a high-performance graphics processing unit (GPU) that can perform graphics operations such as vertex processing, fragment processing, shading, texture blending, etc. in a highly integrated and parallel manner. The graphics core 220 is bidirectionally connected to the SMN and the data fabric 250, and can provide memory access requests to the data fabric 250. In this regard, the APU 200 may support a unified memory architecture in which the CPU core complex 210 and the graphics core 220 share the same memory space, or a memory architecture in which the CPU core complex 210 and the graphics core 220 share a portion of the memory space while the graphics core 220 also uses a private graphics memory that the CPU core complex 210 cannot access.

[0023] The display engine 230 renders and rasterizes objects generated by the graphics core 220 for display on the monitor. The graphics core 220 and the display engine 230 are bidirectionally connected to a common memory management hub 240 for unified translation to the appropriate addresses in the memory system 120, and the memory management hub 240 is bidirectionally connected to the data fabric 250 for generating such memory accesses and receiving read data returned from the memory system.

[0024] The data fabric 250 includes a crossbar switch for routing memory access requests and memory responses between any memory accessing agents and the memory controller 290. The data fabric also includes a system memory map defined by the BIOS for determining the destination of memory accesses based on the system configuration, and buffers for each virtual connection.

[0025] Peripheral controller 260 includes USB controller 262 and SATA interface controller 264, each of which is bidirectionally connected to system hub 266 and SMN bus. These two controllers are merely examples of peripheral controllers that may be used for APU 200.

[0026] The peripheral bus controller 270 includes a system controller or "South Bridge" (SB) 272 and a PCIe controller 274, each of which is bidirectionally connected to an input / output (I / O) hub 276 and the SMN bus. The I / O hub 276 is also bidirectionally connected to the system hub 266 and the data fabric 250. Thus, for example, the CPU core can program registers in the USB controller 262, the SATA interface controller 264, the SB 272, or the PCIe controller 274 through accesses routed through the I / O hub 276 through the data fabric 250.

[0027] SMU 280 is a local controller that controls the operation of resources on APU 200 and synchronizes communications between these resources. SMU 280 manages the power-up sequencing of the various processors on APU 200 and controls a number of off-chip devices via reset, enable, and other signals. SMU 280 includes one or more clock sources ( Figure 2 2), such as a phase-locked loop (PLL) to provide clock signals to each component of APU 200. SMU 280 also manages power to the various processors and other functional blocks, and may receive measured power consumption values ​​from CPU cores 212 and 214 and graphics core 220 to determine appropriate power states.

[0028] In this implementation, a set of memory controllers 290 includes memory controllers 292, 294, 296, and 298. Each memory controller has an upstream bidirectional connection to the data fabric 250 and a downstream connection to a memory channel for accessing memory such as DDR memory, as described further below.

[0029] Figure 3 A memory system 300 including multiple memory controllers according to some embodiments is shown in block diagram form. The memory system 300 is typically embodied on an integrated circuit, such as an APU, a GPU, or the like. Figure 2 A CPU system on chip. The memory system 300 includes memory controllers 310, 320, and 330, and DDR PHY interfaces 340, 342, and 344 for interfacing with one or more external memory modules. The memory system 300 also typically includes a power distribution network (PDN) including a first power domain 302 labeled "VDD domain" (wherein the circuit is powered by voltage VDD), and a second power domain 304 labeled "VDDP domain" (wherein the circuit is powered by voltage VDDP). Although three memory controllers are shown, in most implementations of modern server systems, the system on chip may have more DDR channels with more memory controllers, such as twelve, sixteen, or more. In some implementations, such memory controllers are arranged in "quadrants", where a group of memory controllers coordinate throttling in the group. In this implementation, memory controllers 310, 320, and 330 constitute such a group.

[0030] The memory channel controllers 310, 320, and 330 are typically provided in a first power domain 302 and may include lower level domains specific to each memory controller under the first power domain 302 in the PDN. Similarly, the DDR PHY interfaces 340, 342, and 344 are typically provided in a second power domain 304 and may include lower level domains specific to each DDR PHY interface under the second power domain 304 in the PDN. Typically, in operation, the memory channel controllers 310, 320, and 330 handle various traffic loads that exhibit "bursty" behavior, where the memory channel controllers are idle and then quickly become busy satisfying memory access requests. Such behavior tends to cause voltage drops in one or both of the VDDP domain 304 and the VDD domain 302. Specifically, when all memory controllers in a quadrant send read (RD) and write (WR) commands at their full bandwidth capacity from idle at approximately the same time, voltage drops of nanoseconds (10 nanoseconds to 20 nanoseconds) tend to result.

[0031] Each memory channel controller includes a corresponding one or more arbiters 312, 322 and 332 and a corresponding flow throttling circuit 314, 324 and 334. Each flow throttling circuit is bidirectionally connected to other flow throttling circuits for cooperating with arbiters of other memory controllers to mitigate excessive power usage increases. In this specific implementation, each flow throttling circuit 314, 324 and 334 includes: a monitoring circuit for measuring the number of read and write commands selected by its corresponding arbitrator and other arbitrators within a first predetermined time period; and a throttling circuit coupled to the monitoring circuit and the corresponding arbitrator. In response to a low activity state associated with the read and write commands, each throttling circuit is used to limit the number of read and write commands issued by the arbitrator during a second predetermined time period, which can be repeated as further described below.

[0032] Figure 4 The block diagram shows a device suitable for use with Figure 2250 and APU 200. The dual-channel memory controller 410 is connected to the data texture 250, to which the dual-channel memory controller can communicate with multiple memory agents present in the data processing system 400. The dual-channel memory controller 410 can control two sub-channels defined in the DDR5 specification, for example, for use with DDR5 DRAMS, or control those sub-channels defined in the high bandwidth memory 2 (HBM2) and HBM3 standards. In some specific implementations, instead of two sub-channels, the dual-channel memory controller 410 can replace two independent memory channel controllers and control two DDRx channels together in a transparent manner to the data texture 250 and various memory address agents in the APU 200, so that a single memory controller interface 412 can be used to send memory access commands and receive results. The dual-channel memory controller 410 generally includes an interface 412, an address decoder 422, and two instances of memory channel control circuits 423A and 423B, each assigned to a different memory channel. Each instance of the memory channel control circuit 423A, 423B includes a memory interface queue 414A, 414B, a command queue 420A, 420B, a content addressable memory (CAM) 424A, 424B, a timing block 434A, 434B, a page table 436A, 436B, an arbiter 438A, 438B, an ECC generation block 444A, 444B, a data buffer 446A, 446B and a flow throttling circuit 432A, 432B, which includes a window monitoring circuit 448A, 448B.

[0033] In other specific implementations, for each memory channel or sub-channel used, only the command queues 430A, 430B, arbiters 438A, 438B, flow throttling circuits 432A, 432B, and memory interface queues 414A, 414B are copied, and the remaining circuits shown are suitable for use with two channels. In addition, although the depicted dual-channel memory controller 410 includes two instances of arbiters 438A, 438B, command queues 420A, 420B, and memory interface queues 414A, 414B for controlling two memory channels or sub-channels, other embodiments may include more instances, such as three or four or more instances, which are used to communicate with DRAM on three or four channels or sub-channels according to the credit management techniques of this article. In addition, although a dual-channel memory controller is used in this specific implementation, other specific implementations can use the throttling techniques of this article for a single-channel memory controller.

[0034] The interface 412 has a first bidirectional connection to the data fabric 250 through the communication bus, and a second bidirectional connection to the credit control circuit 421. In this embodiment, the interface 412 uses a scalable data port (SDP) link to establish several channels to communicate with the data fabric 250, but other interface link standards are also applicable. For example, in another embodiment, the communication bus is compatible with the Advanced Extensible Interface version four (referred to as AXI4) specified by ARM Holdings, PLC of Cambridge, England, but can be other types of interfaces in other embodiments. The interface 412 converts memory access requests from a first clock domain called the "FCLK" (or "MEMCLK") domain to a second clock domain called the "UCLK" domain inside the dual channel memory controller 410. Similarly, the memory interface queue 414 provides memory access from the UCLK domain to the "DFICLK" domain associated with the DFI interface.

[0035] The address decoder 422 has a bidirectional link to the interface 412, a first output connected to the first command queue 420A (labeled "command queue 0"), and a second output connected to the second command queue 420B (labeled "command queue 1"). The address decoder 422 decodes the address of the memory access request received on the data texture 250 through the interface 412. The memory access request includes an access address in a physical address space represented in a normalized format. Based on the access address, the address decoder 422 selects one of the memory channels and an associated one of the command queues 420A and 420B to process the request. The selected channel for each request is identified to the credit control circuit 421 so that a credit issuance decision can be made. The address decoder 422 converts the normalized address into a format that can be used to address the actual memory device in the memory system 130 and efficiently schedule the related accesses. The format includes a region identification that associates the memory access request with a specific storage column, row address, column address, storage bank address, and storage bank group. At startup, the system BIOS queries the memory devices in the memory system 130 to determine their size and configuration, and programs a set of configuration registers associated with the address decoder 422. The address decoder 422 uses the configuration stored in the configuration registers to convert the normalized address into the appropriate format. Each memory access request is loaded into the command queue 420A or 420B for the memory channel selected by the address decoder 422.

[0036] Each command queue 420A, 420B is a queue of memory access requests received from various memory access engines in the APU 200, such as the CPU cores 212 and 214 and the graphics core 220. Each command queue 420A, 420B is bidirectionally connected to a corresponding arbiter 438A, 438B for selecting memory access requests to be issued through the associated memory channel from the command queue 420A, 420B. Each command queue 420A, 420B stores the address field decoded by the address decoder 422 and other address information that allows the corresponding arbiter 438A, 438B to efficiently select memory access, including access type and quality of service (QoS) identification. Each CAM 424A, 424B includes information that implements ordering rules such as write-after-write (WAW) and read-after-write (RAW) ordering rules.

[0037] The arbiters 438A, 438B are each bidirectionally connected to the corresponding command queues 420A, 420B for selecting memory access requests to be completed with appropriate commands, and are bidirectionally connected to the corresponding traffic throttling circuits 432A, 432B for receiving throttling signals. The arbiters 438A, 438B generally improve the use of the memory bus of the memory channel through intelligent access scheduling to improve the efficiency of its corresponding memory channel. Each arbiter 438A, 438B uses a corresponding timing block 434A, 434B to implement the correct timing relationship by determining whether certain accesses in the corresponding command queues 420A, 420B are eligible for issuance based on DRAM timing parameters. Each page table 436A, 436B maintains state information about active pages in each memory bank and column of the corresponding memory channel for its corresponding arbiter 438A, 438B, and is bidirectionally connected to its corresponding replay queue 430A, 430B. Each arbiter 438A, 438B uses the decoded address information, the timing eligibility information indicated by the timing blocks 434A, 434B, and the active page information indicated by the page tables 436A, 436B to efficiently schedule memory accesses while adhering to other criteria such as quality of service (QoS) requirements. In some embodiments, the arbiter 438A, 438B determines whether to allow the selected command to be released based on a signal from the traffic throttling circuit 432A, 432B.

[0038] Each flow throttle circuit 432A, 432B is bidirectionally connected to a corresponding arbiter 438A, 438B and bidirectionally connected to one or more other flow throttle circuits that may be in other memory controllers. As shown, the flow throttle circuits 432A, 432B are bidirectionally connected to each other to provide a signal labeled CASSENT to indicate to each other when a column address strobe (CAS) command has been sent to the memory channel. As shown below with reference to Figures 5 to 7As further described, the CASSENT signal is used in the throttling process. Each flow throttling circuit includes a window monitoring circuit 448A, 448B, which is used to measure the number of read and write commands selected by its corresponding arbiter 438A, 438B and one or more additional arbiters within a first predetermined time period. Typically, as further described below, each flow throttling circuit 432A, 432B limits the number of read and write commands issued by the arbiter 438A, 438B during a second predetermined time period in response to a low activity state associated with the read and write commands. Each flow throttling circuit 432A, 432B can also send an "idle" signal to indicate that an idle condition has been reached at the arbiter sending the flow throttling circuit, i.e., a period of a specified length in which no CAS signal is dispatched. In response to the idle signal, the flow throttling circuit 432A, 432B currently in throttling mode adjusts its own throttling rate to allow more CAS commands to be sent.

[0039] Each error correction code (ECC) generation block 444A, 444B determines the ECC of the write data to be sent to the memory. In response to receiving a write memory access request from the interface 412, the ECC generation block 444A, 444B calculates the ECC based on the write data. The data buffer 446A, 446B stores the write data and ECC of the received memory access request. When the corresponding arbiter 438A, 438B selects the corresponding write access to be assigned to the memory channel, the data buffer 446A, 446B outputs the combined write data / ECC to the corresponding memory interface queue 414A, 414B.

[0040] Figure 5 is a flowchart 500 of a process for throttling traffic at a memory controller according to some embodiments. The process is suitable for use with Figure 3 Memory systems, Figure 4 memory controller or use multiple memory channels or sub-channels and include such as Figure 3 , Figure 4 or Figure 6 The flow throttling circuit shown may be used in conjunction with other suitable systems.

[0041] The process begins at block 502 where the traffic throttling circuitry monitors a plurality of arbiters or subchannel arbiters for a plurality of memory access commands (specifically reads and writes) selected for dispatch to the memory. During such monitoring, at block 504, the traffic throttling circuitry detects a low activity state for a data command over a specified prior time window. The time window is measured as a configurable number of clock cycles of the memory clock, such as 64 cycles. For example, monitoring may be performed for two subchannels of a single memory controller, or may be performed across multiple subchannels having, for example, a plurality of memory controllers. Figure 3The plurality of memory controllers of the linked flow throttling circuits are monitored. Detecting the low activity state may include detecting that no read or write commands are issued to the memory during a first time period, or that a number of commands issued during the first time period is below a specified threshold.

[0042] The process at block 506 limits the number of read and write commands issued by the arbitrator during a second predetermined time period in response to detecting a low activity state. The second time period may also be configured as a number of memory clock cycles, such as 32. It should be noted that read and write commands may be assigned different weights when monitoring. In this specific implementation, limiting the number of commands is achieved by setting a ramp-up limit that is implemented by preventing read and write commands (specifically, CAS commands) from being issued at the arbitrator or the memory interface queue of the arbitrator during the time window.

[0043] At block 508, the memory controller then leaves the low activity state and begins dispatching memory commands. This may be because, for example, the memory controller leaves an idle state, or simply because there has been no command traffic to the memory controller for a period of time and then traffic begins. As shown in block 510, the throttling circuitry at each arbitrator implements a ramp-up limit to ensure that the arbitrator does not immediately increase traffic to 100% of the available bandwidth. The ramp-up limit is implemented during a second window or specified time period and at each arbitrator involved in the process. When the window monitoring circuit (e.g., Figure 4 448A and 448B, Figure 6 When the ramp-up limit is determined to have been reached for the current window or time period, the flow throttling circuit at each arbitrator throttles the flow of the corresponding arbitrator. Figure 4 When used with the memory controller 410 of FIG. 1 , the two subchannel arbiters have a common ramp-up limit. As another example, when the Figure 3 When this process is used with quadrant level throttling enabled for the memory controller group, all three memory controllers 310, 320, and 330 have a ramp-up limit in common.

[0044] At block 512, after the second specified period of time, the throttling circuit increases the ramp-up limit at each arbitrator. Blocks 510 and 512 are then repeated until the limit reaches 100% of the available bandwidth.

[0045] For subchannel throttling, the process can be configured using configuration settings set in memory controller registers. Register settings are provided to enable subchannel throttling. Register settings are provided to specify the number of clock cycles during which the process does not allow both subchannels to send CAS simultaneously when the throttling condition is met, thereby specifying the size of the monitored time window. Another register setting is provided to specify the maximum number of clocks that both channels can be idle before throttling between the subchannels is initiated. Another register setting provides bandwidth increase limits for each time window being monitored, setting a "ramp rate" for each time window during throttling, for example as a percentage of the total bandwidth.

[0046] Typically, the ramp-up limit sets the allowable increase in read and write commands within a second predetermined time period and is based on a first value stored in a programmable control register. The lengths of the first and second time periods are preferably based on a second value stored in a programmable control register indicating a number of clock cycles.

[0047] Figure 6 FIG. 6 is a block diagram of a flow throttling circuit 600 according to some embodiments. The flow throttling circuit 600 is suitable for use in Figure 3 Memory systems, Figure 4 The present invention is used in a memory controller of the present invention or in other suitable systems using multiple memory channels or sub-channels.

[0048] In this example, the flow throttling circuit 600 is implemented in a memory controller designated as "UMC0", which is in a group of memory controllers including two other memory controllers "UMC1" and "UMC2". The flow throttling circuit 600 has a first input labeled "CASSENT UMC1", a second input labeled "CASSENT UMC2", and an output labeled "CASSENT UMC0", and includes a window monitoring circuit 602, a synchronous counter 604, and a ramp counter 606, as well as throttling logic for implementing the throttling process. The flow throttling circuit 600 may also include a synchronization input terminal (not shown) that is used to coordinate the synchronous counter 604 with the synchronous counters of the other memory controllers.

[0049] For example, Figure 3As shown, the CASSENT UMC0 output is used to indicate that a column address strobe (CAS) has been dispatched by UMC0 and is fed to the flow throttling circuits of UMC1 and UMC2. CASSENT UMC1 and CASSENT UMC2 receive similar signals from UMC1 and UMC2. Window monitoring circuit 602 measures the number of read and write commands picked by the arbiter of UMC0 and the additional arbiters UMC1 and UMC2 during a first predetermined time period. In this specific implementation, the measurement is performed by counting the CAS commands dispatched at UMC0 during the first time period and the CASSENT indicators received from UMC1 and UMC2.

[0050] The synchronization counter 604 generally acts as a "toggle" circuit to implement ramp-up limits by coordinating between multiple memory controllers. In this specific implementation, the synchronization counter 604 counts 0, 1, and 2 in each command cycle of the memory controller (8 clock cycles per command cycle) and directly indicates which of the memory controllers UMC0, UMC1, and UMC2 is authorized to send read and write commands in each command cycle under certain conditions, as further described below. The synchronization counter can receive a synchronization signal to ensure that it is synchronized with the synchronization counters at UMC1 and UMC2.

[0051] In this implementation, a ramp counter 606 is used to track the ramp up limit. When one of UMC1 or UMC2 sends a CAS command, the ramp counter 606 is started, as indicated by the rising edge of the CASSENT signal received from UMC1 or UMC2. In this implementation, the ramp counter 606 counts down from a specified value and is employed in two different modes to delay the sending of a CAS command at UMC0, as shown in FIG. Figure 7 Further described.

[0052] While this arrangement of counters and signaling is employed in some embodiments, other embodiments may of course use various arrangements of counters and timers to achieve similar functionality.

[0053] Figure 7 is a flow chart 700 of another process for throttling flow according to some embodiments. The process is suitable for use with Figure 3 The memory system and Figure 6 The invention is used together with a flow throttling circuit of the present invention and generally provides an exemplary method of implementing a ramp-up limit after leaving a low activity state at a memory controller (e.g., Figure 5The process is performed at each memory controller in a memory controller group or quadrant. Although the process steps are depicted in sequence, the sequence is not limiting and the steps are typically performed in parallel by the digital logic in the flow throttling circuit 600.

[0054] The process begins at block 702 where it determines whether quadrant level throttling is enabled, which in this implementation is determined by a bit in a configuration register. Figure 3 A method for coordinating ramp-up from an idle state between multiple memory controllers 310, 320 and 330.

[0055] If quadrant level throttling is used, if the CASSENT signals of both memory controllers (UMC) are asserted and the ramp counter is non-zero, process block 704 blocks the CAS command selected by the arbitrator. As described above, the ramp counter 606 in this implementation counts down to zero, providing a delay period for throttling commands.

[0056] At block 706, if only one CASSENT signal from another memory controller is asserted, the process allows a CAS to be sent from the current memory controller if the synchronization counter 604 indicates the current memory controller.

[0057] If quadrant level throttling is not enabled, the process at blocks 708-712 is used. At block 708, the process blocks CAS commands from being sent from the current memory controller if any other memory controller in the group has asserted the CASSENT signal and the ramp counter 606 is non-zero. At block 710, once the ramp counter 606 reaches zero, CAS is allowed to be sent from the current memory controller if the synchronization counter 604 indicates the current memory controller. At block 712, if both CASSENT signals from the other memory controllers are asserted simultaneously, the process ends throttling and resumes normal operation of the current memory controller.

[0058] While this process uses synchronous counters and ramp counters, other processes may certainly use other schemes to limit the number of read and write commands issued by the arbitrator.

[0059] Register settings are provided to configure quadrant level throttling. Register settings are provided to enable quadrant level throttling. Register settings are provided to configure the detection of an idle condition requiring throttling, which includes the number of clock cycles of inactivity to consider the idle condition activated. During quadrant level throttling, the ramp rate setting provides a maximum increase for each monitored window period. When the ramp rate is reached during the time window, the throttling length setting provides the number of clock cycles to delay the next CAS.

[0060] Figure 3 Memory systems, Figure 2 Dual-channel memory controller and Figure 6 The flow throttling circuit or any portion thereof may be described or represented by a computer accessible data structure in the form of a database or other data structure that can be read by a program and used directly or indirectly to manufacture the integrated circuit. For example, the data structure may be a behavioral level description or a register transfer level (RTL) description of the hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool, which may synthesize the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware comprising the integrated circuit. The netlist may then be placed and routed to produce a data set describing the geometry to be applied to the mask. The mask may then be used in various semiconductor manufacturing steps to produce the integrated circuit. Alternatively, the database on the computer accessible storage medium may be a netlist (with or without a synthesis library) or a data set (as desired) or a Graphic Data System (GDS) II data.

[0061] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, although a dual-channel memory controller is used as an example, the technology herein may also be applied to more than two memory channels to combine their capacity in a transparent manner to data texture and host data processing system. For example, by providing independent command queues and memory channel control circuits for each channel, while providing a single interface, address decoder, and credit control circuits that request credits to data textures that are independent of each memory channel, the technology herein may be used to control three or four memory channels. In addition, the internal architecture of the dual-channel memory controller 210 may be changed in different embodiments. The dual-channel memory controller 210 may be interfaced to other types of memory other than DDRx, such as high bandwidth memory (HBM), RAMbus DRAM (RDRAM), etc. Although the illustrated embodiments show each memory storage rank corresponding to a separate DIMM or SIMM, in other embodiments, each module may support multiple storage ranks. Still other embodiments may include other types of DRAM modules or DRAMs not included in a particular module, such as DRAMs mounted to a host motherboard. Therefore, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. A memory controller operable to select commands to dispatch to a memory, the memory controller comprising: Arbitrator; A flow throttling circuit, connected to the arbitrator, for cooperating with one or more additional arbitrators to mitigate excess power usage increases, the flow throttling circuit comprising: monitoring circuitry for measuring a number of read and write commands selected by the arbitrator and the one or more additional arbitrators within a first predetermined time period; and A throttling circuit limits the number of read and write commands issued during a second predetermined time period in response to the low activity state.

2. The memory controller of claim 1 , wherein: The throttling circuit further includes a programmable control register that stores a limit value indicating an allowable increase in read and write commands within the second predetermined period of time.

3. The memory controller of claim 2, wherein: The programmable control register further holds a value indicating the first predetermined period of time and the second predetermined period of time as a number of clock cycles.

4. The memory controller of claim 1 , wherein: The monitoring circuit includes one or more first inputs that receive signals from the one or more additional arbitrators, respectively, to indicate that the corresponding additional arbitrator has sent a column address strobe command associated with a read or write command to the memory.

5. The memory controller of claim 4, wherein: The monitoring circuit includes one or more second inputs that receive second signals from the one or more additional arbitrators, respectively, to indicate that the respective additional arbitrator has selected a read or write command to be sent to the memory.

6. The memory controller of claim 1, wherein: At least one of the one or more additional arbiters is a sub-channel arbiter for dispatching commands to a sub-channel of a memory channel at least partially shared with the arbitrator.

7. The memory controller of claim 1, wherein: At least one of the one or more additional arbiters is a channel arbiter for dispatching commands to a channel different from a channel used by the arbitrator.

8. The memory controller of claim 1, wherein: The throttling circuit includes a toggle circuit operable to indicate to the arbitrator after the low activity state whether the arbitrator is authorized to send read and write commands, the toggle circuit being synchronized with similar toggle circuits in the one or more additional arbitrators.

9. A method of mitigating excess power usage increases at an arbitrator in cooperation with one or more additional arbitrators, the method comprising: measuring a number of read and write commands selected by the arbitrator and the one or more additional arbitrators within a first predetermined time period; as well as Responsive to a low activity state associated with the read and write commands, a number of read and write commands issued by the arbitrator for transmission to the memory during a second predetermined time period is limited.

10. The method according to claim 9, further comprising: An allowable increase in read and write commands within the second predetermined period of time is determined based on a first value stored in a programmable control register.

11. The method according to claim 10, further comprising: The first time period and the second time period are determined based on a second value indicating a number of clock cycles stored in the programmable control register.

12. The method according to claim 9, further comprising: Signals are received from the one or more additional arbitrators, respectively, to indicate that the corresponding additional arbitrator has sent a column address strobe command associated with a read or write command to the memory.

13. The method according to claim 12, further comprising: A second signal is received from each of the one or more additional arbitrators to indicate that the corresponding additional arbitrator has selected a read or write command to be sent to the memory.

14. The method of claim 9, wherein: At least one of the one or more additional arbiters is a sub-channel arbiter for dispatching commands to sub-channels on a memory channel at least partially shared with the arbitrator.

15. The method of claim 9, wherein: At least one of the one or more additional arbiters is a channel arbiter for dispatching commands to a channel different from a channel used by the arbitrator.

16. The method according to claim 9, further comprising: indicating to the arbitrator after the low activity state whether the arbitrator is authorized to send read and write commands based on the value of the toggle circuit; as well as The toggle circuit is synchronized with similar toggle circuits in the one or more additional arbitrators.

17. A processing system, the processing system comprising: Data processors; a plurality of memory channels coupling the data processor to memory; and a memory controller operable to select commands to dispatch to the memory for one of the memory channels, the memory controller comprising an arbitrator and a flow throttling circuit for cooperating with one or more additional arbitrators for a corresponding one of the memory channels to mitigate excess power usage increases, the one or more additional arbitrators for a corresponding one of the memory channels, the flow throttling circuit comprising: monitoring circuitry for measuring a number of read and write commands selected by the arbitrator and the one or more additional arbitrators within a first predetermined time period; and A throttling circuit limits the number of read and write commands issued during a second predetermined time period in response to the low activity state.

18. The processing system of claim 17, wherein: The throttling circuit further includes a programmable control register that stores a limit value indicating an allowable increase in read and write commands within the second predetermined period of time.

19. The processing system of claim 18, wherein: The programmable control register further holds a value indicating the first predetermined period of time and the second predetermined period of time as a number of clock cycles.

20. The processing system of claim 17, wherein: The monitoring circuit includes one or more first inputs that respectively receive signals from the one or more additional arbitrators to indicate that the corresponding additional arbitrator has sent a column address strobe command associated with a read or write command to the memory.

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