Through-silicon via macros with dense layouts for placement in integrated circuit layout

Abstract

A system and method for efficiently designing a through silicon via (TSV) macroblock is described. In various implementations, circuitry of a processor executes instructions of a layout and routing tool that provides automatic placement of macroblocks and standard cells on an integrated circuit die based on a copy of a netlist of the integrated circuit being designed and a copy of a standard cell library including various standard cells and macroblocks. The processor places two functional macros in a planar layout with a channel therebetween. In the channel, the processor places a TSV macro including at least one boundary cell inside the TSV macro. The processor prevents boundary cells from being placed near at least one side of the TSV macros despite the presence of white space due to the absence of standard cells or macros around the at least one side.

Description

Background Art

[0001] Description of Related Technology

[0002] The floor plan of a semiconductor die (or die) is a graphical representation of the die partitioning. The partitioning uses shapes such as rectangles to represent the arrangement of multiple components, such as one or more processing units, one or more memory blocks, one or more interface units, etc. These components are generally referred to as macroblocks or macros. The shape used for the floor plan has the size of the macroblock it represents. The size of the shape has restrictions so that all of these components are placed on the same die. These restrictions are set by various factors, such as the arrangement of standard cells from a standard library, such as boundary cells. The boundary cell does not include active devices such as transistors, but includes multiple base layers and one or more metal layers that are not connected to a power supply. The boundary cell improves the manufacturability of the semiconductor and increases the yield. Other examples of factors that limit the size of the floor plan are areas for bonding pads, input / output (I / O) line drivers for signals corresponding to bonding pads, timing constraints for macroblocks, predefined rectangles for at least one processing unit and other intellectual property blocks (IP blocks), and reserved areas. Some examples of reserved areas are areas for routing and buffering clock signals and data and control signals across the die.

[0003] An additional example of a reserved area is an area for a combination of a through silicon via (TSV) and its corresponding forbidden area. TSVs are used as interconnectors between dies of three-dimensional integrated circuits (3D ICs), which include two or more layers of active electronic components integrated vertically and horizontally into a single circuit. Each of a first die such as a main die or a base die and at least one other die is used in a 3D package for a computing system. This type of packaging is referred to as a system-in-package (SiP). Typically, the size of the TSV and the corresponding forbidden area is significantly smaller than the minimum TSV spacing. Therefore, the resulting TSV macro consumes a large amount of empty space on the die and the corresponding floor plan.

[0004] There is a channel between two macroblocks, such as two memory macroblocks, which includes a column of TSVs for transmitting power signals. The first macroblock has a boundary cell placed at one side of the channel. The TSV macroblock is placed in a channel for transmitting a power supply voltage or a ground reference voltage. The TSV macroblock has a boundary cell placed on each of its four sides. The second macroblock also has a boundary cell placed at one side of the channel. Therefore, along the channel size, there needs to be enough minimum width to allow the placement of two boundary cells of the macroblock, the placement of two boundary cells of the TSV macroblock, and the placement of the TSV macroblock. If the minimum width does not exist in the floor plan, the necessary components are not suitable for assembly on the same tube core. Therefore, significant redesign is required, as well as possible movement or displacement of the macroblocks in the floor plan. Such redesign consumes a considerable amount of design time, thereby delaying product release.

[0005] In view of the foregoing, there is a need for efficient methods and systems for effectively designing TSV macros. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A schematic drawing that is part of a floor plan.

[0007] Figure 2 is a schematic diagram of a through silicon via (TSV) macro.

[0008] Figure 3 A schematic drawing that is part of a floor plan.

[0009] Figure 4 It is a schematic diagram of a computing system.

[0010] Figure 5 is an overview of a method for efficiently creating a floorplan layout using efficient TSV macroblocks.

[0011] Figure 6 is an overview of a method for efficiently creating a floorplan layout using efficient TSV macroblocks.

[0012] Figure 7 is a schematic diagram of a method for efficiently designing a TSV macroblock.

[0013] Figure 8 This is a schematic diagram of a system-in-package (SiP).

[0014] Although the present invention is susceptible to various modifications and alternative forms, specific implementations are shown by way of example in the drawings and described in detail herein. However, it should be understood that the drawings and detailed description thereof are not intended to limit the invention to the specific forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents and alternatives within the scope of the invention defined by the appended claims. DETAILED DESCRIPTION

[0015] In the following description, many specific details are set forth to provide a thorough understanding of the present invention. However, it will be appreciated by those of ordinary skill in the art that the present invention may be practiced without these specific details. In some cases, well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the present invention. In addition, it should be understood that for simplicity and clarity of illustration, the elements shown in the figures are not necessarily drawn to scale. For example, the size of some elements is enlarged relative to other elements.

[0016] A system and method for efficiently designing silicon through-hole macroblocks is contemplated. As disclosed herein, a computing device used by a user includes hardware, such as a circuit of a processor, to execute instructions (e.g., a placement and routing tool or other tool) that provide automatic placement of macroblocks and standard cells on a die. These instructions use a copy of the netlist of an integrated circuit and a standard cell library including various standard cells and macroblocks. As used herein, the term "automatic generation" or "automatic generation" refers to the ability to perform generation or perform generation steps without user intervention. Similarly, as used herein, the term "automatic placement" or "automatic placement" refers to the ability to perform placement or perform placement steps without user intervention. For example, when a processor of a computing device executes the instructions of a tool, the processor automatically selects the placement location of a component and the signal routing between components. In other words, based on the netlist of the integrated circuit being designed and access to the standard cell library, when the instructions of the placement and routing tool are executed, the processor generates data indicating the placement of components in the floor plan of the die of the integrated circuit being designed. Similarly, when the processor of the computing device executes the instructions of the placement and routing tool, the processor prevents the automatic placement of specific components, such as boundary cells, in the floor plan of the die that can be automatically placed. In other words, the processor generates data indicating the locations of these specific components in the floor plan of the die that are not allowed. These data prevent the die area from placing these specific components.

[0017] When the processor of the computing device executes the instructions of the placement and routing tool, the processor places (or automatically places) two functional macro blocks, such as two memory macro blocks, in the floor plan of the integrated circuit. In other words, the processor generates data indicating the placement of two memory macro blocks in the floor plan of the die of the integrated circuit being designed. There is a channel between the two functional macro blocks. The processor places a column of through silicon vias (TSV) macro blocks (or macros) in the channel for transmitting a power supply voltage or a ground reference voltage to one or more of the two functional macros. Typically, based on a predetermined power grid design of the floor plan, the TSV macro is placed at a specific distance from the two macros. When the column of TSV macros is created in the channel, the processor places a first type of TSV macro. In various specific implementations, the first type of TSV macro includes at least one boundary cell inside the TSV macro. In a specific implementation, the first type of TSV macro includes a first boundary cell on a first side and a second boundary cell on a second side different from the first side, wherein each of the first side and the second side is located within a TSV macro along a given dimension of the floor plan. An example of a given dimension is the horizontal or x-dimension of a floor plan.

[0018] The processor also places at least one boundary cell near the first functional macro of the two functional macros. For example, the processor places the boundary cell on one side of the first functional macro in the trench along a given dimension of the floor plan, such as the x dimension of the floor plan. Typically, the boundary cell is placed around one or more sides of the macro to fill the blank space between a pair of macros on the die, between a pair of macros and a standard cell, or between the macro and the edge of the die. The boundary cell improves the manufacturability of the semiconductor and increases the yield. However, the processor prevents the placement of a boundary cell adjacent to at least one side of the first type of TSV macro in the floor plan. In other words, the processor generates data indicating a position in the floor plan, wherein a boundary cell adjacent to at least one side of the first type of TSV macro is not allowed. In a specific implementation, the data includes a first type of TSV macro and an identification of one side. In another specific implementation, the data includes a boundary, which includes a region on one side of the first type of TSV macro. When the instructions of the placement and routing tool are executed, and the processor reaches the step of automatically placing a boundary cell around the macro, the processor uses the data indicating the prevention of the placement of the boundary cell to prevent the placement of the boundary cell adjacent to at least one side of the first type of TSV macro. In some implementations, the processor prevents placement of boundary cells adjacent to a first side and a second side of a first type of TSV macro in a floorplan. In such implementations, the first type of TSV macro includes boundary cells therein on the first side and the second side. Use of the first type of TSV macro reduces the required distance between two functional macros.

[0019] In a specific implementation, the standard cell library includes a second type of TSV macro, which has the same size as the first type of TSV macro. However, there is no boundary cell in the second type of TSV macro. Therefore, when selecting and placing the second type of TSV, the processor also places the boundary cell around the side of the second type of TSV macro. In some specific implementations, when the distance between two functional macros is less than a threshold distance, the processor selects the first type of TSV macro and places it between the two functional macros. When the distance between the two functional macros is greater than or equal to the threshold distance, the processor selects the second type of TSV macro and places it between the two functional macros.

[0020] Now turn to Figure 1 , a schematic diagram of a portion 100 of an integrated circuit floor plan is shown. The portion 100 of the integrated circuit floor plan includes function macros 110, 112, 130, and 132 and through silicon via (TSV) macros 120 and 140. The function macros 110, 112, 130, and 132 and the TSV macro 120 have various types of boundary cells 150, 160, and 170 placed near and around them. However, in a specific implementation, the TSV macro 140 includes boundary cells 150 within the macro and does not have boundary cells 150 placed adjacent to it. In addition to the boundary cells 170 placed adjacent to the corners of the TSV macro 140, the TSV macro 140 also has boundary cells 160 placed adjacent to the top and bottom sides of the y dimension. However, in the x dimension of the TSV macro 140, there are no boundary cells 150 placed adjacent to the left and right sides. In addition to the TSV block 144, the TSV 140 also includes a boundary cell 150 within the macro, which includes a silicon through-hole, a corresponding forbidden area, a guard ring, and a filling layer. The portion 100 of the floor plan relies on standard cells and individual Boolean gate cells. The standard cell library includes individual Boolean gate cells with multiple versions of different available transistor sizes. The cells in the standard cell library use active devices. Examples of active devices are one or more of n-type and p-type planar transistors and n-type and p-type non-planar transistors.

[0021] As used herein, "standard cell" is the smallest building block of a standard cell library above the cells of each Boolean gate. Standard cells and each Boolean gate cell are used to provide the function of a larger design block by instantiating copies of standard cells and Boolean gates in a larger design block, followed by a wiring step to provide interconnection. In addition to indicating the Boolean function and other functions of the components used in the standard cell, the standard cell also includes mask layout data. The mask layout data of a specific standard cell includes one or more mask layers associated with one or more layers of a specific standard cell. One or more layers of a specific standard cell include a base layer and multiple metal layers for signal interconnection. The mask layout data includes mask patterns used in lithography performed during semiconductor manufacturing of integrated circuits. These patterns indicate the placement of components in a specific standard cell relative to a reference point (such as a certain corner of a specific standard cell). Examples of components are active devices and passive components (e.g., resistors, capacitors, inductors) placed in the standard cell. The mask layout data also includes parasitic information of the component, such as the resistance of the leads and nodes, the coupling capacitance of the leads and transistor terminals, and the load capacitance.

[0022] As described above, by making copies of standard cells and Boolean gates instantiated within a larger design block, followed by a routing step to provide interconnection, standard cells and individual Boolean gate cells are used to provide the functionality of a larger design block. Copies of a specific larger design block that can be instantiated multiple times in a floor plan are referred to as "macro blocks," or simply "macros." Most macros include active devices for providing functionality. As used herein, these types of macros are also referred to as "functional macros." However, TSV macros 120 and 140 are examples of macros that do not include active devices. In some specific implementations, each of the functional macros 110, 112, 130, and 132 is an instance of the same functional macro. Therefore, each of the functional macros 110, 112, 130, and 132 provides the same functionality. In a specific implementation, each of the functional macros 110, 112, 130, and 132 is a memory macro that includes static random access memory cells arranged in rows and columns. In other implementations, one or more of the function macros 110, 112, 130, and 132 provide different functionality than other macros of the function macros 110, 112, 130, and 132. Similar to standard cells, macros such as the function macros 110, 112, 130, and 132 and the TSV macros 120 and 140 include mask layout data.

[0023] Some macros do not include any active devices, such as TSV macros 120 and 140. TSV is used as an interconnector between the dies of a three-dimensional integrated circuit (3D IC), which includes two or more layers of active devices vertically and horizontally integrated into a single circuit. In 3D IC, each of a first semiconductor die (or die) such as a main die or a base die and at least one other die is used in a three-dimensional (3D) package for a computing system. This type of packaging is referred to as a system-in-package (SiP). TSV is used as an interconnector between a base die at the bottom of a vertical die stack in SiP and one or more other dies stacked on top of the base die. When horizontal on-chip signal transmission is used in a 3D IC, the main die has another die horizontally placed next to the main die, and chip communication uses the TSV in the main die and another die, with an integrated connection based on an interposer between these TSVs. The printed circuit board is located below the interposer.

[0024] Each of the TSV macro 120 and the TSV block 144 includes at least a TSV, a guard ring indicating a corresponding keep-out area, and a fill layer. Figure 2 ) provides more details of these components in the upcoming description of the TSV macro 200 of the embodiment of the present invention. In a specific implementation, the TSV macro 140 includes boundary cells 150 placed adjacent to the left and right sides along the x dimension of the TSV block 144. Similar to other macros, the TSV macro 120 does not include any boundary cells 150, 160 and 170. There is a channel between the function macros 110 and 112 in which the TSV macro 120 is placed. In a specific implementation, the TSV macro 120 provides a power supply voltage or a ground reference voltage to one or more of the function macros 110 and 112. Similarly, there is a channel between the function macros 130 and 132 in which the TSV macro 140 is placed. In a specific implementation, the TSV macro 140 provides a power supply voltage or a ground reference voltage to one or more of the function macros 130 and 132.

[0025] TSV macros 120 and 140 are placed in a manner aligned with each other in the y dimension. In the specific implementation shown, the y dimension is aligned with the vertical direction. For example, in the orientation shown, the function macro 130 is placed above the function macro 110 in the vertical direction (or in the y dimension). Similarly, in the orientation shown, the function macro 112 is placed on the right side of the function macro 110 in the horizontal direction (or in the x dimension). According to the power grid specifications, TSV macros 120 and 140 are placed in a manner aligned vertically in the y dimension. Therefore, each of the TSV macros 120 and 140 has the same distance from the center of the corresponding TSV to the extreme left edge of the die in the x dimension. In addition to having an aligned arrangement, in some specific implementations, each of the TSV macros 120 and 140 has the same macro width. In other words, the macro width 122 of the TSV macro 120 is equal to the macro width 142 of the TSV 140. When macro width 122 is equal to macro width 142, placing boundary cells, such as at least boundary cell 150, in TSV macro 140 provides a dense layout for TSV macro 140. The dense layout of TSV macro 140 maximizes channel width usage between functional macros 130 and 132.

[0026] Each of the function macros 110, 112, 130 and 132 has a boundary cell placed around it. For example, on the side aligned with the x dimension, a boundary cell 150 is placed. On the side aligned with the y dimension, a boundary cell 160 is placed. On the corner, a boundary cell 170 is placed. Therefore, in various specific implementations, the boundary cells 150, 160 and 170 form a ring around each of the function macros 110, 112, 130 and 132. Each of the boundary cells 150, 160 and 170 does not provide a function, does not receive a signal connection, and does not contain an active device. Therefore, although the boundary cells 150, 160 and 170 are in the standard cell library for design, the boundary cells 150, 160 and 170 are not part of the netlist of the design of the part 100 including the floor plan. The boundary cells 150, 160 and 170 are used to improve semiconductor manufacturability and increase the yield of the manufactured die.

[0027] Each of the boundary cells 150, 160, and 170 includes one or more manufacturing structures, such as one or more base layers and one or more metal layers. Examples of base layers are n-type or p-type diffusion well layers, dummy metal gate layers such as polysilicon or other metal layers, and implant layers. The metal layer includes a specific pattern of a metal layer of one or more of the metal layers. In some specific implementations, the boundary cells 150, 160, and 170 include a pattern of each of the available signal metal layers. The pattern of the metal layer in the boundary cells 150, 160, and 170 fills the blank areas of the floor plan to provide a regular flattening of the resulting manufactured wafer.

[0028] In some implementations, the standard cell library includes multiple variations of each of the boundary cells 150, 160, and 170, wherein each of the multiple variations has a different number of one or more layers than another variation. For example, the number of dummy metal gates may vary between different standard cells because the specific number depends on the location in the floor plan where the boundary cell is instantiated. In some implementations, the boundary cell 150 placed adjacent to the function macros 110, 112, 130, and 132 has a different width than the boundary cell 150 placed adjacent to the TSV macro 120. In some implementations, one or more of the boundary cells 150, 160, and 170 includes a tap cell for connecting the n-type well to a power supply voltage and connecting the silicon substrate to a ground reference voltage. In a specific implementation, one or more of the boundary cells 150, 160, and 170 includes an end cap cell that improves the alignment of the well and the row and helps the later semiconductor manufacturing process use the correct laser wavelength.

[0029] Similar to the functional macros 110, 112, 130, and 132, the TSV macro 120 is surrounded by boundary cells 150, 160, and 170. The trench between the functional macros 110 and 112 includes a distance 124, which is measured from the edge of the boundary cell 150 placed adjacent to the functional macro 110 to the center of the TSV in the TSV macro 120. There is enough distance for placing the TSV macro 120 and the additional surrounding boundary cells 150. In other words, the distance 124 is equal to or greater than the threshold distance. However, in the trench between the functional macros 130 and 132, the distance 144 is less than the distance 124 and less than the threshold distance. The distance 144 is measured from the edge of the boundary cell 150 placed adjacent to the functional macro 130 to the center of the TSV in the TSV macro 140. The TSV macro 120 and the surrounding boundary cells 150 will not be placed in the trench. Shifting along the x dimension is not possible because the TSV macros placed in the trench are aligned with a specific dimension, such as the requirements of the power grid.

[0030] Compared to the functional macros 110, 112, 130, and 132 and the TSV macro 120, the TSV macro 140 includes one or more boundary cells 150, 160, and 170 in its interior. In the illustrated implementation, the TSV macro 140 includes a boundary cell 150 on each of the first side and the second side of the TSV block 144 along the x dimension. Despite including the boundary cell 150, the TSV macro 140 has a macro width 142 that is equal to the macro width 122 of the TSV macro 120. The placement and routing tool determines that the TSV macro 140 is to be placed in the trench between the functional macros 130 and 132, rather than in the TSV macro 120. In some implementations, the placement and routing tool measures the distance 144, and determines that the distance 144 is less than a threshold distance, and therefore selects the TSV macro 140. The placement and routing tool also prevents the boundary cell 150 from being placed adjacent to the TSV macro 140. In other words, the processor generates data indicating a location in the floorplan where a boundary cell 150 adjacent to at least one side of the TSV macro 140 is not allowed. However, the place and route tool performs placement of boundary cells 160 and 170 adjacent to the TSV macro 140, as is done for the function macros 110, 112, 130, and 132 and the TSV macro 120. The use of the TSV macro 140 allows the necessary boundary cells 150, 160, and 170 to be placed, supports the grid specification, and prevents any redesign to move the function macro 130 in the floorplan.

[0031] refer to Figure 2 , a schematic diagram of a through silicon via (TSV) macro 200 is shown. TSV macro 200 includes TSV 210 and guard ring 220. Boundary cells 240 are placed on each of the first side and the second side along the horizontal dimension or x dimension. Between boundary cell 240 and guard ring 220 is a fill layer 230. Boundary cell 240 includes the same boundary cells 150, 160 and 170 ( Figure 1 ) the same component. Boundary cell 240 includes multiple instances of boundary cells in a standard cell library. TSV 210 indicates a location where a TSV is formed using one of a plurality of conductive metals or metal alloys based on design requirements. TSVs transmit data signals and control signals or power signals between dies of a 3D IC. Guard ring 220 indicates a forbidden area of ​​TSV 210. The empty space between TSV 210 and guard ring 220 is a forbidden area or region.

[0032] Similar to the boundary cell 240, each of the guard ring 220 and the filling layer 230 includes one or more manufacturing structures, such as one or more base layers and one or more metal layers. The selection of which base layers and metal layers are included in the guard ring 220 and the filling layer 230 is based on design selection. The boundary cell 240 and the filling layer 230 are used to provide a uniform distribution of the metal layer across the tube core by including shapes in the metal layer of the open area. These shapes are not used to transmit signals. The uniform distribution provides uniformity that helps the semiconductor manufacturing process. For example, adding one or more metal layers that do not transmit signals in the boundary cell 240 and the filling layer 230 reduces the thickness variation during the chemical mechanical polishing (CMP) manufacturing step, and improves the electrochemical deposition (ECD), etching and lithography steps, and reduces the stress effect across the tube core. The standard cell library includes one or more standard cells referred to as "filling cells" or "filler cells". These standard cells or filler cells in the library are used to generate the filling layer 230. These filler cells are used to provide both front end of line (FEOL) fill and back end of line (BEOL) fill in the filling of fill layer 230. In other words, fill layer 230 shown in TSV macro 200 includes one or more of these standard cells or filler cells from a standard cell library.

[0033] In addition to using the boundary cell 240 and the filling layer 230, the guard ring 220 also defines the forbidden area of ​​the TSV 210. In some specific implementations, the generation of the TSV macro 200 includes the use of one or more barriers. These barriers are not shown because they are not retained in the TSV macro 200. These barriers include shapes that do not transmit signals in the metal layer, which are also used in the filler cells of the filling layer 230. The purpose of the barrier is to ensure that there is enough empty space between the filling layer 230 and the guard ring 220 when the filling layer 230 is formed in the TSV macro 200. In a specific implementation, the placement and routing tool automatically places the filling layer 230 between the boundary cell 240 and the guard ring 220. However, the placement of the boundary cell 240 reduces the area of ​​the filling layer 230.

[0034] The filling layer 230 has a requirement for having a specific number of components, such as at least a plurality of dummy metal gates. In order to meet the design rule check (DRC) requirements, the placement and routing tool places the filling layer 230 at an edge other than the extreme left edge of the TSV macro 200 or the extreme right edge of the TSV macro 200. In contrast to the TSV macro without a boundary cell, each of the extreme left edge and the extreme right edge of the TSV macro 200 is occupied by the boundary cell 240. In some specific implementations, the guard ring 220 does not have enough metal layer shapes located at the outer edge to instruct the placement and routing tool to complete the formation of the filling layer 230 at a specific distance away from the guard ring 220. In this case, the barrier is placed adjacent to a specific side of the guard ring 220 to instruct the placement and routing tool to complete the formation of the filling layer 230 at a specific distance away from the specific side of the guard ring 220. One or more of the width and length of the barrier are adjusted until the placement (or formation) of the filling layer 230 provides the filling layer 230 with a threshold distance from the guard ring 220. After the fill layer 230 is placed in the TSV macro 200 and meets the DRC requirements, the barrier is removed from the TSV macro 200. If necessary, these steps of placing the barrier, adjusting the width and length of the barrier, forming the fill layer 230, and removing the barrier are repeated for one or more other sides of the guard ring 220.

[0035] Although the boundary cells 240 are shown on each of the extreme left and right sides along the x-dimension in the TSV macro 200, in other implementations, the TSV macro 200 includes boundary cells 240 on one or more of the top and bottom sides along the y-dimension. In a specific implementation, the TSV macro 200 also includes boundary cells 240 on each of the four sides in addition to each of the four corners. Any combination of placement of the boundary cells 240 in the TSV macro 200 is possible and contemplated. For each combination, the placement of the fill layer 230 and the use and subsequent removal of any barriers during the placement of the fill layer 230 are adjusted accordingly.

[0036] Once formed in the mask layout editor, and after verification by the design rule check (DRC), the TSV macro 200 is placed in the standard cell library. The TSV macro 200 is used to provide interconnections, such as interconnections between the power supply voltage between the functional macro on the die and the bonding pads of the die. The TSV macro 200 is an example of a macro that does not include active devices, and therefore does not provide Boolean functions. The TSV macro 200 of the standard cell library includes mask layout data. As previously described, the mask layout data of a specific standard cell includes one or more mask layers associated with one or more layers of a specific standard cell. One or more layers of a specific standard cell include a base layer and multiple metal layers for signal interconnection. The mask layout data includes mask patterns used in lithography performed during semiconductor manufacturing of integrated circuits. These patterns indicate the placement of components within a specific standard cell relative to a reference point, such as a certain corner of a specific standard cell. Examples of components are active devices and passive elements (e.g., resistors, capacitors, inductors) placed in a standard cell. The mask layout data also includes parasitic information of components, such as resistance of leads and nodes, coupling capacitance of leads and transistor terminals, and load capacitance.

[0037] Now turn to Figure 3 , a schematic diagram of a portion 300 of an integrated circuit floor plan is shown. The portion 300 of the integrated circuit floor plan (or floor plan) includes function macros 310 and 320 that are instantiated multiple times across the die. The portion 300 of the floor plan also includes a TSV macro 340. Although not shown, boundary cells are placed around the function macros 310 and 320. In a specific implementation, the TSV macro 340 provides a supply voltage or a ground reference voltage to one or more of the function macros 310 and 320 and any surrounding logic gates (not shown).

[0038] In various implementations, one or more of the TSVs 340 include a TSV macro 140 ( Figure 1 ) and TSV Macro 200( Figure 2 ) components. In some implementations, the use of these types of TSV macros supports smaller channel widths between function macros 310 than if other types of TSV macros were used. Additionally, in implementations, the use of these types of TSV macros allows Boolean logic gates, data buffers, and other types of standard cells to be placed between TSV macros 340 and nearby function macros 310. TSV macros 340 are aligned with each other in the y dimension within channels between function macros 310 and channels between function macros 320. In some implementations, the alignment is based on a predetermined power grid.

[0039] In some implementations, each of the function macros 310 is an instance of the same function macro. Therefore, each of the function macros 310 provides the same functionality. In an implementation, each of the function macros 310 is a memory macro that includes static random access memory cells arranged in rows and columns. In such implementations, the function macro 320 includes access circuits such as one or more of a read word line driver, a write word line driver, a read storage latch or register, a write data storage latch or register, etc. In other implementations, the function macros 310 and 320 provide other functionality.

[0040] refer to Figure 4 , a schematic block diagram of a computing system 400 is shown. In the illustrated implementation, the computing system 400 includes a client computing device 450, servers 420A to 420D including hardware for executing software and supporting an organizing center 410, a network 440, and a data storage device 430 including one or more data repositories supported and used by the organizing center 410. Although a single client computing device 450 is shown, any number of client computing devices utilize the organizing center 410 via the network 440. The client computing device 450 (which is also referred to as the client device 450) includes hardware, such as circuitry of a processor, for executing instructions of an automated place and route (PNR) generator 460. The automated PNR generator 460 (or PNR generator 460) uses copies of data stored in the data storage device 430. Examples of copies of data are integrated circuit (IC) mask layout data 432 and IC netlist 434.

[0041] IC mask layout data 432 can be available in a standard cell library, which includes various cells that use devices of different sizes to provide specific functions. IC mask layout data 432 also includes mask layout data of macros. As previously mentioned, the IC mask layout data 432 of a specific standard cell includes one or more mask layers associated with one or more layers of a specific standard cell. One or more layers of a specific standard cell include a base layer and multiple metal layers for signal interconnection. Mask layout data includes mask patterns used in lithography performed during semiconductor manufacturing of integrated circuits. These patterns indicate the placement position of components in a specific standard cell relative to a reference point, such as a certain corner of a specific standard cell. Examples of components are active devices and passive components (e.g., resistors, capacitors, inductors) placed in a standard cell. IC mask layout data 432 also includes parasitic information of components, such as the resistance of leads and nodes, the coupling capacitance of leads and transistor terminals, and load capacitance.

[0042] In a specific implementation, a user initiates the use of PNR generator 460 using a graphical user interface (GUI) 462, a script, a command line, or a combination of these elements. PNR generator 460 generates a representation of the hardware layout from the schematic diagram of the integrated circuit being designed. To this end, PNR generator 460 additionally uses a copy of mask layout data 432 and RDL netlist 434 and the dimension specifications of the floor plan of the IC to identify the placement of standard cells and macros in the floor plan of the IC die being designed.

[0043] The PNR generator 460 also uses DRC 436 to verify that the arrangement of standard cells, macros, boundary cells, and fill layers does not violate the design rules of the layout. The output of the PNR generator 460 is later sent to the semiconductor wafer manufacturer. The output indicates the arrangement and connectivity of the components across the die of the IC being designed. The output uses one or more TSV macros including one or more boundary cells. Examples of these TSV macros are TSV macro 140 ( Figure 1 ) and TSV Macro 200( Figure 2 ). If the arrangement of standard cells, macros, boundary cells, and fill layers passes the DRC and LVS checks, one or more copies of the updated version of the mask layout data 432 are stored in the client device 450 and the data storage device 430. Subsequently, a semiconductor chip tape-out process is performed on the integrated circuit being developed, and the semiconductor manufacturing process provides hardware of the integrated circuit for testing.

[0044] The client device 450 includes a desktop computer or a mobile computing device such as a laptop, a tablet computer, etc. The client device 450 includes hardware circuits for processing instructions of a computer program, such as a processing unit 470. In some implementations, the processing unit 470 includes one or more homogeneous cores of a processor. In other implementations, the processing unit includes heterogeneous cores, such as parallel processing architecture cores and general purpose cores as used in a central processing unit (CPU). The parallel architecture core can be a graphics processing unit (GPU), a digital signal processing unit (DSP), or others.

[0045] The client device 450 includes a network interface (not shown) that supports one or more communication protocols for data and message transmission over the network 440. The network 440 includes a plurality of switches, routers, cables, wireless transmitters, and the Internet for transmitting messages and data. Thus, the network interfaces of the organization center 410 and the client device 450 support at least the Hypertext Transfer Protocol (HTTP) for communication across the World Wide Web. In addition to communicating with the client device 450 over the network 440, the organization center 410 also communicates with the data storage device 430 to store and retrieve data.

[0046] In various specific implementations, the organization center 410 is the infrastructure of a supplier that produces one or more hardware products. The organization center 410 includes an intranet network that provides a private network that can only be accessed by the staff of the organization. The intranet portal is used to provide access to resources using user-friendly interfaces such as graphical user interfaces (GUIs) and panels. The information and services provided by the organization center 410 cannot be provided to the general public through direct access. Through user authentication, employees can access resources through the organization center 410 to communicate with other employees, collaborate on projects and monitor product development, update products, documents and tools stored in centralized repositories, etc.

[0047] The servers 420A to 420D used to support the organization center 410 and the resources accessed through the organization center 410 include a variety of server types, such as database servers, computing servers, application servers, file servers, mail servers, etc. In various specific implementations, the servers 420A to 420D and the client device 450 operate in a client-server architecture model. The client device 450 includes a copy of a specific version of a given software product or tool such as a PNR generator 460. In some specific implementations, the version of the PNR generator 460 is based at least on the operating system and processor used by the client device 450. The PNR generator 460 includes an engine 464 that, when executed by a processor of the processing unit 470, causes the processing unit 470 to automatically generate a layout mask for components across an IC die designed according to a specific floor plan.

[0048] refer to Figure 5 , shows an overview of a method 500 for efficiently creating a floor plan layout using efficient TSV macroblocks. For discussion purposes, this specific implementation (and Figure 6 to Figure 7 However, in other implementations, some steps occur in a different order than shown, some steps are performed simultaneously, some steps are combined with other steps, and some steps are not present.

[0049] The hardware of the processor of the corresponding computing device executes an automatic placement and routing (PNR) tool or generator. The PNR tool (based on the execution of the hardware of the processor) selects the netlist of the IC being designed, accesses the size specifications of the IC's floor plan, and accesses the standard cell library. The PNR generator places the first function macro in the floor plan of the integrated circuit (box 502). The PNR generator places the through silicon via (TSV) macro in the floor plan (box 504). The PNR generator places at least one boundary cell near the function macro (box 506). The PNR generator prevents the placement of boundary cells adjacent to at least one side of the TSV macro in the floor plan (box 508). In other words, the PNR generator generates data indicating a position in the floor plan, wherein boundary cells adjacent to at least one side of the TSV macro are not allowed. The PNR generator performs design rule checking (DRC) verification and layout to schematic (LVS) verification (box 510). Any errors are corrected by the designer. Once the verification is performed without error, the IC design is taped out and manufactured (box 512).

[0050] If a potential is not applied to the first node of the integrated circuit in the semiconductor package (the "No" branch of conditional block 514), the semiconductor package waits for power-up (block 516). However, if a potential is applied to the first node, which creates a potential difference (the "Yes" branch of conditional block 514), the input node transfers current from the motherboard to the function macro (block 518).

[0051] Now turn to Figure 6 , a schematic diagram of a method 600 for efficiently creating a floor plan layout using efficient silicon through-via macroblocks is shown. The hardware of the processor of the corresponding computing device executes an automatic placement and routing (PNR) tool or generator. The PNR tool (based on the execution of the hardware of the processor) selects the netlist of the IC being designed, accesses the size specifications of the floor plan of the IC, and accesses the standard cell library. The PNR tool places the function macro in the floor plan of the integrated circuit (box 602). The PNR tool determines the distance between the edge of the function macro and the power grid layout (box 604). The PNR tool compares the measured distance with a distance threshold. The distance threshold includes a minimum distance that supports the placement of boundary cells adjacent to the side of the function macro facing the power grid, the placement of boundary cells adjacent to the side of the TSV macro facing the function macro, and the distance from the side of the TSV macro facing the function macro to the center of the TSV macro.

[0052] If the PNR tool determines that the measured distance is less than the distance threshold (the "yes" branch of conditional block 606), the PNR tool places a first type of through silicon via (TSV) macro on the power grid including at least one boundary cell (block 608). An example of such a first type of TSV macro is ( Figure 1 TSV macro 140 and ( Figure 2The PNR tool prevents placement of a boundary cell adjacent to at least one side of a first type of TSV macro (block 610). If the PNR tool determines that the measured distance is equal to or greater than a distance threshold (the "no" branch of conditional block 606), the PNR tool places a second type of TSV macro on the power grid in a trench where no boundary cell exists in the second type of TSV macro (block 612). Subsequently, the PNR tool places the boundary cell near the side of the second type of TSV macro (block 614). Regardless of the comparison between the measured distance and the threshold distance, the PNR tool places the boundary cell near the side of the functional macro (block 616).

[0053] refer to Figure 7 , a schematic diagram of a method 700 for efficiently designing a through silicon via macroblock is shown. Hardware of a processor of a corresponding computing device executes a mask layout editor tool (or editor tool). The editor tool forms a through silicon via (TSV) in a TSV macro (block 702). The editor tool forms a guard ring around the TSV (block 704). The editor tool places a boundary cell on at least one side of the TSV macro (block 706). Between any boundary cell and the guard ring, the editor tool forms a fill layer (block 708). Between any side without a boundary cell and the guard ring, the editor tool forms a fill layer (block 710).

[0054] The editor tool runs DRC verification on the TSV macro. If the TSV macro does not pass DRC verification (the "No" branch of conditional box 712), the editor tool places one or more barriers in the TSV macro to control the formation of the fill layer (box 714). As previously described, these barriers include shapes that do not transmit signals in metal layers that are also used in filler cells of the fill layer. The purpose of the barrier is to ensure that there is enough empty space between the fill layer and the guard ring when the fill layer is formed in the TSV macro. Afterwards, the control flow of method 700 returns to box 708, where the editor tool forms the fill layer. In some specific implementations, the editor tool removes part or all of the previously formed fill layer. If the TSV macro passes DRC verification (the "Yes" branch of conditional box 712), the barrier is removed from the TSV macro (box 716). The TSV macro is ready for use in an integrated circuit floor plan. In some specific implementations, the TSV macro is placed in a standard cell library.

[0055] Now turn to Figure 8, showing a schematic diagram of a system-level package (SiP) 800. In various specific implementations, a three-dimensional (3D) package is used in a computing system to create a SiP 800. SiP 800 includes a semiconductor base die 820 (or die 820) and semiconductor die 830A-830C (or die 830A-830C). Here, SiP 800 also uses active electronic component layers that are integrated horizontally and vertically into a single circuit. Die stacking technology is a manufacturing process that enables multiple independent silicon chips (integrated chips) to be physically stacked together in the same package with high bandwidth and low latency interconnection. SiP 800 includes additional components that are not shown for ease of illustration, such as one or more interposers, packaging substrates, redistribution layers (RDLs), bonding pads, etc. Although four die 820 and 830A to 830C are shown, any number of dies, any number of types of dies, and vertical stacking in any order can be used in other specific implementations.

[0056] As shown, in one specific implementation, SiP 800 includes a die 830C stacked on top of a die 830B. In other words, die 830C is placed on a side of die 820B away from a printed circuit board (not shown), such as a motherboard located below a package external connector 860. In this configuration, die 830C and die 830B use a through silicon via (TSV) 842 between them for transmitting data signals, control signals, and power signals. A printed circuit board (not shown) is located below SiP 800 and communicates with base die 820 through a package external connector 860. In various specific implementations, package external connector 860 is a SMD pin in a variety of surface mount device (SMD) pins, which allows SiP 800 to be placed directly on the surface of a printed circuit board, or if RDL is used, directly on a redistribution layer (RDL). Examples of SMD pins include ball grid arrays (BGAs), bumps or micro-bumps, flat contacts or bonding pads, etc.

[0057] It is envisioned that the base die 820 and the die 830A-830C include one or more of various processing units, cache memory subsystems, data storage arrays, one or more of various application-specific integrated circuits (ASICs), display controllers, communication interconnects or structures, etc. For example, the base die 820 and one or more of the die 830A to 830C are systems on a chip (SoC). Multiple routes use vertical jumps between the base die 820 and the die 830A to 830C. These routes include signal routes, such as commands and messages and packets, address information, response data, write data, data snooping requests, etc. These routes also include power connection routes, such as one or more power lines for transmitting power supply voltage levels and ground reference voltage levels. In addition to using TSV 842, SiP 800 also uses a horizontal, low-latency integrated interconnect 846 (or interconnect 846) within the package, which provides a shortened interconnect signal length compared to a long off-chip interconnect. Interconnect 846 uses specific signals and protocols as if the chips (such as base die 820 and dies 830A to 830C) were mounted in separate packages on a circuit board.

[0058] The active device layers of each of the base die 820 and the die 830A to 830C have direct vertical interconnects such as TSVs 842 that tunnel or otherwise traverse through them. TSVs 842 are alternative interconnects for wire bonding and flip chips. The corresponding forbidden areas of each TSV of TSV 842 define an area around the TSV that provides a predicted stress above a threshold to the active device. The stress is caused by the arrangement of the TSVs. The area outside the forbidden area provides a predicted stress below a threshold to the active device. The size and density of the TSVs that can tunnel between different device layers vary based on the underlying technology used to manufacture 3D ICs.

[0059] In some implementations, the base die 820 and die 830A to 830C do not include every TSV that tunnels completely through each of them to transmit signals between them and other die. Instead, one or more TSVs tunnel through the silicon substrate and oxide layers and terminate at a specific metal layer within the base die 820 and die 830A to 830C. The metal layer can be any metal layer from the lowest metal zero (M0) layer to the highest metal layer used by the particular die. In some implementations, a particular TSV reaches the upper metal layer and goes no further. Therefore, no active devices (transistors) are formed where the particular TSV is formed. In various implementations, the placement of TSVs 842 on the floor plan of the base die 820 and die 830A to 830C uses the previously described ( Figure 1 TSV macro 140 and ( Figure 2 )TSV macro 200 describes the technology.

[0060] It should be noted that one or more of the above-mentioned specific implementations include software. In such specific implementations, the program instructions of the implementation method and / or mechanism are transmitted or stored on a computer-readable medium. Many types of media configured to store program instructions are available and include hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROMs (PROMs), random access memories (RAMs) and various other forms of volatile or non-volatile storage devices. Generally speaking, a computer-accessible storage medium includes any storage medium that can be accessed by a computer during use to provide instructions and / or data to a computer. For example, a computer-accessible storage medium includes such as magnetic or optical media, such as storage media such as disks (fixed or removable), tapes, CD-ROMs or DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs or blue-rays. The storage medium also includes volatile or non-volatile storage media, such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (RDRAM), static RAM (SRAM), etc.), ROM accessible via a peripheral device interface (such as a universal serial bus (USB) interface, etc.), flash memory, non-volatile memory (e.g., flash memory). The storage medium includes micro-electromechanical systems (MEMS), and storage media accessible via communication media such as a network and / or a wireless link.

[0061] In addition, in various specific implementations, the program instructions include a behavioral level description or a register transfer level (RTL) description of the hardware functionality in a high-level programming language such as C or a design language (HDL) such as Verilog, VHDL, or a database format such as GDS II stream format (GDSII). In some cases, the description is read by a synthesis tool, which synthesizes the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates, which also represents the functionality of the hardware comprising the system. The netlist is then placed and threaded to produce a data set describing the geometry to be applied to the mask. The mask is then used in various semiconductor manufacturing steps to produce a semiconductor circuit or circuit corresponding to the system. Alternatively, the instructions on the computer-accessible storage medium are a netlist (with or without a synthesis library) or a data set as desired. In addition, the instructions are used by the computer-accessible storage medium such as and Mentor Such vendors' hardware-based types of emulators are used for emulation purposes.

[0062] Although the above embodiments have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to encompass all such variations and modifications.

Claims

1. A processor, comprising: A circuit configured to generate data indicating the following based at least in part on a netlist corresponding to the integrated circuit and the standard cell library: The layout of the integrated circuit in the floor plan is: Type 1 through silicon via (TSV) macro; A functional macro including a plurality of active devices; and at least one boundary cell adjacent to the function macro; and A location in the floorplan of the integrated circuit wherein boundary cells adjacent to at least a first side of a TSV macro of the first type are not permitted. 2 . The processor of claim 1 , wherein the first type of TSV macro comprises at least one boundary cell.

3. The processor of claim 2 , wherein the circuit is further configured to generate data indicating locations in the floorplan of the integrated circuit based at least in part on the netlist and the standard cell library where boundary cells adjacent to a second side different from the first side of the TSV macro of the first type are not allowed. 4 . The processor of claim 3 , wherein the first type of TSV macro comprises a first boundary cell on the first side and a second boundary cell on the second side. 5 . The processor of claim 1 , wherein the first type of TSV macro comprises a threshold distance between a fill layer and a guard ring.

6. The processor of claim 1 , wherein the circuit is further configured to: determining a distance between an edge of the function macro and a grid arrangement; Based at least in part on the netlist and the standard cell library, generating data indicative of a placement in the floorplan of the integrated circuit of: In response to determining that the distance is less than a threshold distance, a TSV macro of the first type on the power grid.

7. The processor of claim 1 , wherein the circuit is further configured to generate data indicating a placement in the floorplan of the integrated circuit of: In response to determining that the distance is equal to or greater than the threshold distance, a second type of TSV macro on the power grid that is different from the first type of TSV macro, wherein no boundary cells exist in the second type of TSV macro; and At least one boundary cell adjacent to the second type TSV macro.

8. A method comprising: receiving, by the circuitry of the processor, a netlist of the integrated circuit; accessing, by the circuit, a standard cell library comprising a plurality of standard cells and a plurality of macros; as well as Generating, by the circuit, data indicating the following based at least in part on the netlist and the standard cell library: The layout of the integrated circuit in the floor plan is: Type 1 through silicon via (TSV) macro; A functional macro including a plurality of active devices; and at least one boundary cell adjacent to the function macro; and A location in the floorplan of the integrated circuit wherein boundary cells adjacent to at least a first side of a TSV macro of the first type are not permitted. 9 . The method of claim 8 , wherein the first type of TSV macro includes at least one boundary cell.

10. The method of claim 9, further comprising generating, by the circuit, data indicating locations in the floor plan of the integrated circuit based at least in part on the netlist and the standard cell library, wherein boundary cells adjacent to a second side different from the first side of the TSV macro of the first type are not allowed. 11 . The method of claim 10 , wherein the first type of TSV macro comprises a first boundary cell on the first side and a second boundary cell on the second side. 12 . The method of claim 8 , wherein the first type of TSV macro comprises a threshold distance between a fill layer and a guard ring.

13. The method according to claim 8, further comprising: determining, by the circuit, a distance between an edge of the function macro and a grid arrangement; generating, by the circuitry based at least in part on the netlist and the standard cell library, data indicative of a placement in the floorplan of the integrated circuit of: In response to determining that the distance is less than a threshold distance, a TSV macro of the first type on the power grid.

14. The method of claim 8, further comprising generating, by the circuit, based at least in part on the netlist and the standard cell library, data indicating placement in the floorplan of the integrated circuit of: In response to determining that the distance is equal to or greater than a threshold distance, a second type of TSV macro on the power grid that is different from the first type of TSV macro, wherein no boundary cells exist in the second type of TSV macro; and At least one boundary cell adjacent to the second type TSV macro.

15. A computing system, comprising: Processing unit; A memory coupled to the processing unit, wherein the memory is configured to store the following: Netlist of the integrated circuit; and a standard cell library including a plurality of standard cells and a plurality of macros; and The circuit of the processing unit is configured as follows: receiving the netlist; accessing the standard cell library; and Based at least in part on the netlist and the standard cell library, generating data indicative of: The layout of the integrated circuit in the floor plan is: Type 1 through silicon via (TSV) macro; A functional macro including a plurality of active devices; and at least one boundary cell adjacent to the function macro; and A location in the floorplan of the integrated circuit wherein boundary cells adjacent to at least a first side of a TSV macro of the first type are not permitted. 16 . The computing system of claim 15 , wherein the first type of TSV macro comprises at least one boundary cell.

17. The computing system of claim 16, wherein the circuit is further configured to generate data indicating locations in the floorplan of the integrated circuit based at least in part on the netlist and the standard cell library where boundary cells adjacent to a second side different from the first side of the TSV macro of the first type are not allowed. 18 . The computing system of claim 17 , wherein the first type of TSV macro comprises a first boundary cell on the first side and a second boundary cell on the second side. 19 . The computing system of claim 15 , wherein the first type of TSV macro comprises a threshold distance between a fill layer and a guard ring.

20. The computing system of claim 15, wherein the circuit is further configured to: determining a distance between an edge of the function macro and a grid arrangement; Based at least in part on the netlist and the standard cell library, generating data indicative of a placement in the floorplan of the integrated circuit of: In response to determining that the distance is less than a threshold distance, a TSV macro of the first type on the power grid.

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