Method of fabricating structure including barrier layer preventing atomic species diffusion

Abstract

The invention relates to a structure (1) comprising a support (2) made of a charge trapping layer (2b) arranged on a surface of a base substrate (2a) and comprising a thin film (4) made of a lithium-based material and transferred onto the support (2). The structure (1) comprises an interlayer dielectric layer (3) arranged between and in contact with the support (2) and the membrane (4). The interlayer dielectric layer (3) comprises a first dielectric layer (31) arranged on the trap layer (2b) and in contact with the trap layer (2b), a silicon nitride barrier layer (5) arranged on the first dielectric layer (31) and in contact with the first dielectric layer (31), and a second dielectric layer (32) arranged on the barrier layer (5) and in contact with the barrier layer (5).

Description

Technical Field

[0001] The invention relates to a method for producing a structure comprising a thin layer transferred to a support provided with a charge-trapping layer. The invention is particularly useful in the fields of microelectronics, microsystems, photonics, etc. Background Art

[0002] Document WO2021008742 points out that it is often advantageous to provide a charge trapping layer (more concisely referred to as a "trapping layer" in the rest of this specification) in a structure formed by a thin layer transferred to the support via a dielectric layer. For example, the manufacture of this type of structure is disclosed in documents FR2860341, FR2933233, FR2953640, US2015115480, US7268060 and US6544656. Specifically, it can be used to shape electronic or electroacoustic components in the field of radio frequency (RF) signals. US20180114720A1 and US20180158721A1 also propose a "semiconductor on insulator" structure including a trapping layer.

[0003] The thin films, which are typically single crystals, can be semiconducting (e.g., silicon, to form an SOI or "silicon-on-insulator" structure) or insulating (e.g., piezoelectric materials such as lithium tantalate or lithium niobate, to form a POI or "piezoelectric-on-insulator" structure).

[0004] The aforementioned document also discloses the fact that this type of structure is particularly sensitive to hydrogen, since this atomic species can diffuse and condense in the trapping layer, which tends to passivate the electrical defects comprised by this layer and thus degrade the RF performance of the structure. As described in the publication "White paper - RF SOI Characterisation" published by SOITEC in January 2015, the RF performance of the substrate can be characterized by second harmonic distortion measurements.

[0005] It has also been observed that when the film includes lithium, this atomic species may also diffuse into the structure during the manufacturing phase, thereby solidifying in the trapping layer and doping it therein. As with hydrogen, the presence of lithium in the trapping layer tends to degrade the RF performance of the structure.

[0006] In order to prevent RF performance degradation caused by the diffusion of atomic species (especially hydrogen) in the structure containing the trapping layer, documents WO2021008742 and WO2022023630 propose using a dielectric interlayer to provide a blocking effect.

[0007] The nature and dimensions of the various layers making up the structure are not freely chosen. They are generally determined by the intended application and the characteristics of the part to be formed using the structure.

[0008] For example, and by way of example only, the nature and thickness of the dielectric layer of the POI structure is determined by the desired performance of the surface elastic wave filter formed on the thin piezoelectric layer. The thickness of the trapping layer may also affect the propagation of elastic waves on the surface of the thin layer, and its thickness may also be imposed to ensure compliant operation of the component.

[0009] However, in certain structural configurations, the blocking effect of the dielectric layer proposed in documents WO2021008742 and WO2022023630 may not be sufficient. This is the case, for example, when the structure has a relatively thin trapping layer (e.g., less than 0.5 micrometer thick). In this case, the RF performance of the structure is very sensitive to the migration of species in the trapping layer. There are relatively few electrical traps in this layer, and a large part of them can be passivated by a small number of trapped species.

[0010] When the dielectric interlayer is relatively thin (eg, less than 200 nm), the diffusion barrier effect of this layer is naturally much lower, especially for lithium diffusion in the structure.

[0011] In other configurations, the barrier effect of the dielectric layer can impose manufacturing constraints. Thus, when the dielectric interlayer is relatively thick (e.g., greater than 20 nm), the layer can introduce stress into the structure that tends to deform the structure. Excessively deformed structures can no longer be manipulated and processed by conventional microelectronic devices, making their manufacture extremely complex, if not impossible.

[0012] Therefore, the solutions proposed by documents WO2021008742 and WO2022023630 for preventing the diffusion of atomic species cannot be easily applied to a wide range of sizes and types of the various layers that make up the structure.

[0013] Purpose of the Invention

[0014] It is an object of the present invention to improve this state of the art by providing a structure comprising a diffusion barrier to certain atomic species, in particular hydrogen and / or lithium, in a structure comprising a charge trapping layer. In particular, it is an object of the present invention to provide an interlayer dielectric layer having a diffusion barrier effect which can be used for a wide range of sizes of the various elements constituting the structure. Summary of the invention

[0015] To achieve this objective, the object of the present invention is to propose a method for manufacturing a structure comprising a thin layer formed of a lithium-based material and transferred to a support via an interlayer dielectric layer comprising a first dielectric layer, a silicon nitride barrier layer and a second dielectric layer, the support comprising a charge trapping layer arranged superficially on one side of the thin layer on a base substrate. According to the present invention, the method comprises the following steps:

[0016] - forming the first dielectric layer on the capture layer arranged on the main face of the support;

[0017] - forming a silicon nitride barrier layer on and in contact with the first dielectric layer, and the silicon nitride barrier layer has a thickness of at least 20 nm between 20% and 30% of the thickness of the dielectric interlayer;

[0018] - forming the second dielectric layer on and in contact with the barrier layer;

[0019] - assembling the main face of the support and the main face of the donor substrate to form an intermediate structure;

[0020] - removing a portion of the donor substrate from the intermediate structure so as to define the thin layer (4) on the support.

[0021] Other advantageous non-limiting features according to the invention (alone or in any technically feasible combination):

[0022] The donor substrate comprises a single crystal piezoelectric material;

[0023] the donor substrate being provided with a surface dielectric layer on its main face and before the donor substrate is assembled to the support;

[0024] The first dielectric layer and the second dielectric layer are composed of silicon oxide or silicon oxynitride;

[0025] The first dielectric layer and the second dielectric layer are composed of silicon oxynitride into which nitrogen is introduced at a nitrogen / oxygen ratio of less than 0.5;

[0026] The capture layer is made of polysilicon;

[0027] The formation of the first dielectric layer includes oxidation of the trapping layer;

[0028] the first dielectric layer and the second dielectric layer are made of silicon oxynitride into which nitrogen has been introduced with a variable nitrogen / oxygen ratio increasing in the direction of the barrier layer;

[0029] • The stack formed by the first dielectric layer, the barrier layer and the second dielectric layer is deposited on the support by deposition “in situ” in a chamber using LPCVD technology.

[0030] According to another aspect, the present invention provides a structure comprising a support formed by a charge trapping layer superficially disposed on a base substrate, and comprising a thin layer formed by a lithium-based material and transferred to the support, the structure comprising an interlayer dielectric layer disposed between the support and the thin layer and in contact with the support and the thin layer.

[0031] According to the present invention, the structure is characterized in that the interlayer dielectric layer comprises:

[0032] a. a first dielectric layer disposed on the capture layer and in contact with the capture layer;

[0033] b. a silicon nitride barrier layer on and in contact with the first dielectric layer, wherein the silicon nitride barrier layer has a thickness of at least 20 nm that is between 20% and 30% of the thickness of the dielectric interlayer;

[0034] c. A second dielectric layer located on and in contact with the barrier layer.

[0035] Other advantageous non-limiting features according to the invention (alone or in any technically feasible combination):

[0036] The base substrate is a single crystal silicon substrate;

[0037] The capture layer is made of polysilicon;

[0038] The capture layer has a thickness of less than 0.5 micrometers;

[0039] The thin layer is composed of a single crystal piezoelectric material;

[0040] The first dielectric layer and the second dielectric layer are composed of silicon oxide or silicon oxynitride;

[0041] the first dielectric layer and the second dielectric layer are made of silicon oxynitride into which nitrogen has been introduced with a variable nitrogen / oxygen ratio increasing in the direction of the barrier layer;

[0042] The structure is in the form of a circular wafer having a diameter less than or equal to 200 mm and a curvature less than 100 microns;

[0043] The thickness of the dielectric layer may be less than 200 nm;

[0044] The barrier layer consists of non-stoichiometric silicon nitride. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Other features and advantages of the present invention will become apparent from the following detailed description of the invention with reference to the accompanying drawings, in which:

[0046] [ Figure 1 ] Figure 1 shows a structure according to the present invention;

[0047] [ Figure 2 ] Figure 2 Another structure according to the present invention is shown;

[0048] [ Figure 3 ] Figure 3 A method of manufacturing a structure according to the invention is shown; DETAILED DESCRIPTION

[0049] Very generally and with reference to Figure 1 and Figure 2 , the present disclosure relates to a structure 1 and a method for manufacturing the structure 1. The structure 1 comprises in sequence a single-crystalline thin film 4, an interlayer dielectric layer 3 and a support 2. The support 2 itself comprises a base substrate 2a provided with a charge trapping layer 2b. In the embodiment shown in the figures, the interlayer dielectric layer 3 is in contact with the trapping layer 2b and the thin layer 4. As explained in the introduction of the present application, such a structure 1 is particularly suitable for accommodating radio frequency (RF) components on or in the thin film 4.

[0050] Typically, the structure 1 may be in the form of a circular wafer, which may be 100 mm, 150 mm, 200 mm, 300 mm or even 450 mm in diameter.

[0051] The base substrate 2a of the support 2 on which the capture layer 2b is located typically has a thickness of several hundred micrometers. Preferably, the base substrate 2a has a high resistivity of greater than 1000 ohm-cm, even more preferably greater than 2000 ohm-cm. Thus, the density of charges, holes or electrons that may move in the base substrate is limited. However, the present invention is not limited to base substrates 2a having such resistivities, and the present invention also provides RF performance advantages when the base substrate has a more compliant resistivity of the order of several hundred ohm-cm (e.g., less than 1000 ohm.cm, or less than 500 ohm.cm, or even less than 10 ohm.cm).

[0052] For reasons of availability and cost, the base substrate 2a is preferably composed of single crystal silicon. For example, the base substrate 2a can be a CZ silicon substrate with a low interstitial oxygen content between 6ppm and 10ppm, or a FZ silicon substrate with a naturally very low interstitial oxygen content (below the detection limit usually set at 10^16cm^-3). It can also be a CZ silicon substrate with a large amount of interstitial oxygen exceeding 26ppm (indicated by the expression "high Oi"). The base substrate 2a can alternatively be formed of another material: for example, it can be sapphire, glass, quartz, silicon carbide, etc. In some cases, and in particular when the capture layer 2b is thick enough (for example, a thickness greater than 30 microns), the base substrate 2a can have a standard resistivity of less than 1kohm.cm.

[0053] As documented in the documents constituting the prior art, the trapping layer 2b can be very different in nature. Typically, the trapping layer 2b is a non-single-crystalline layer with structural defects such as dislocations, grain boundaries, amorphous regions, interstices, inclusions, holes, etc. These structural defects form traps for charges that tend to circulate in the material, for example, at incomplete or pending chemical bonds. This prevents conduction in the trapping layer, which therefore has a high resistivity.

[0054] In particular when it is formed on a resistive base substrate 2a, its thickness may be between 0.1 μm and 3 μm. However, other thicknesses below or above this range are fully conceivable depending on the RF performance level expected from the structure 1 .

[0055] Advantageously, and for simplicity of implementation, the capture layer 2b is formed of a polysilicon layer. It may also include a silicon-carbon alloy layer or be formed entirely of a silicon-carbon alloy. The capture layer comprising polysilicon may be formed by deposition on the base substrate 2a.

[0056] In order to preserve the polycrystalline quality of this layer during the thermal treatments that may be applied to the structure 1 , an amorphous layer, for example consisting of silicon dioxide, may advantageously be provided on the base substrate 2a before depositing the capture layer 2b.

[0057] Alternatively, the trapping layer 2b may be formed by implanting relatively heavy species (such as argon) in the surface thickness of the base substrate 2a so as to form structural defects therein that constitute electrical traps. The layer 2b may also be formed by making the surface thickness of the base substrate 2a porous or by any other method capable of forming structural defects in the surface thickness of the base substrate 2a that are capable of trapping charges.

[0058] The thin film 4 of the structure 1 can be of any suitable type, in particular a single-crystal material. When the structure 1 is intended to accommodate an integrated semiconductor component, the thin layer 4 can therefore consist of single-crystal silicon, or of any other single-crystal semiconductor material (such as germanium, silicon germanium, silicon carbide). When the structure 1 is intended to accommodate a surface elastic wave filter, the thin layer 4 can consist of a single-crystal piezoelectric and / or ferroelectric material (such as lithium tantalate or lithium niobate). The thin layer 4 can also include a finished or semi-finished integrated component, which is initially formed on a donor substrate and transferred to the support 2 during the step of manufacturing the structure 1. In general, depending on the intended application of the structure 1 and the intended performance of the component, the thin film can have a thickness between 10 nm and 10 microns.

[0059] The interlayer dielectric layer 3 may have a thickness between 50 nm and several micrometers (eg, 5 micrometers or more).

[0060] In order to prevent certain atomic species from diffusing toward the trapping layer 2b, the structure 1 includes a silicon nitride barrier layer 5 in the interlayer dielectric layer 3. "Silicon nitride" refers to a silicon nitride having a general formula of Si x N y The form is thus a nitride composed of nitrogen and silicon in proportions that may or may not be stoichiometric (Si3N4).

[0061] More specifically, the interlayer dielectric layer 3 includes:

[0062] - a first dielectric layer 31 disposed on and in contact with the capture layer 2b;

[0063] - a silicon nitride barrier layer 5 located on and in contact with the first dielectric layer;

[0064] A second dielectric layer 32 situated on and in contact with the barrier layer 5 .

[0065] For reasons that will become apparent from the remainder of this disclosure, and as will be apparent from [ Figure 2 ] Obviously, the interlayer dielectric layer 3 may also include a dielectric surface layer 41 disposed between the second dielectric layer 32 and the thin layer 4. The surface dielectric layer 41 is advantageously in contact with the thin layer 4 and the second dielectric layer 32, but this feature is not necessary, and it is conceivable that the interlayer dielectric layer 3 includes a layer arranged between the second dielectric layer 32 and the thin layer 4 in addition to the surface dielectric layer 41.

[0066] Atomic species that tend to diffuse towards the trapping layer 2 b may in particular come from the thin layer 4. This may be lithium, for example, when the thin layer 4 is made of lithium tantalate or lithium niobate (or more generally, any lithium-based material). By providing a silicon nitride barrier layer 5 that is able to block the diffusion of in particular lithium between the thin layer 4 and the trapping layer 2 b, a degradation of the RF performance of the structure 1 is avoided. In order for the blocking effect to be effective, in particular against light species (such as lithium), it is preferred that the silicon nitride barrier layer 5 has a thickness of at least 20 nm. Generally, it is not necessary to provide a thickness greater than 70 nm to make the blocking effect sufficient (for the diffusion of light species such as lithium or hydrogen), but the barrier layer 5 may still be formed to have a thickness greater than this 70 nm value if other benefits are expected or if the structure 1 is particularly sensitive to the migration of these species, as will be disclosed in the following parts of the present disclosure.

[0067] The second dielectric layer 32 and the surface dielectric layer 41 (if present) are provided to facilitate the assembly of the structure. These layers are advantageously based on silicon oxide, since the adhesion properties of these materials are well known and they can be prepared for assembly (cleaning, activation treatments, etc.). These layers 32, 41 do not need to be thick to achieve their adhesion function during the manufacture of the structure, and advantageously, their thickness is respectively between 5 nm and 30 nm.

[0068] Finally, the first dielectric layer 31 provides a dielectric thickness complementary to the second dielectric layer 32, the barrier layer 5 arranged on the second dielectric layer 32 and any other dielectric layer to obtain an interlayer dielectric layer 3 with a selected thickness. Remember that the dielectric interlayer 3 can have a thickness between 50nm and several microns, so the first dielectric layer 31 can have a thickness between 20nm and several microns. For ease of use, the first dielectric layer 31 is preferably based on silicon oxide.

[0069] Atomic species that may migrate to the trapping layer 2 b may also come from the interlayer dielectric layer 3 itself, or from the assembly interface present at the second dielectric layer 32. This is particularly the case when the interlayer dielectric layer 3 is at least partially produced by deposition techniques involving mild thermal treatments below 650° C. These treatments do not allow certain species, such as hydrogen, to diffuse out of the deposited layers, and these species may therefore diffuse towards the trapping layer 2 b during other stages in the manufacture of the structure 1.

[0070] In order to prevent these species desorbed from the interlayer dielectric layer 3 and in particular from the first dielectric layer 31 below the barrier layer 5 from diffusing as close to the trapping layer 2b as possible, it may be advantageous to select the materials and techniques used to form the first dielectric layer 31 and the second dielectric layer 32 (and to a lesser extent any layers present between the second dielectric layer 32 and the thin layer 4) so ​​that they contain little hydrogen or limit the diffusion rate of this hydrogen. This is particularly the case when the interlayer dielectric layer 3 is relatively thick (thickness greater than or equal to 200nm) resulting in a thickness of the first dielectric layer 31 typically greater than 100nm. This is also the case when the trapping layer 2b is relatively thin (less than 500nm). In both cases, the RF performance of the structure 1 is particularly sensitive to hydrogen diffusion towards the trapping layer 2b, as explained in the introduction of this application.

[0071] The low hydrogen dielectric layer can be formed by LPCVD (Low Pressure Chemical Vapor Deposition) in a temperature range of 650° C. to 850° C. and preferably 700° C. to 800° C. In the case where the first dielectric layer 31 is provided directly on the trapping layer 2 b, when this layer consists of silicon, it can be formed by thermal oxidation of the trapping layer. In order to form a dielectric layer that limits the diffusion rate of the hydrogen, nitrogen can be introduced (to form a SiON layer). In order to characterize the proportion of nitrogen in this layer, we can rely on the measurement of its refractive index, which varies (at a wavelength of 633 nm) between 1.45 for SiO 2 and 2.02 for Si 3 N 4 (that is, stoichiometric silicon nitride).

[0072] The proportion of nitrogen in the SiON layer can be freely chosen to limit the expected diffusion rate, provided that the higher the proportion, the lower the diffusion rate. If we do not want to modify the acoustic properties of these layers excessively compared to layers formed from silicon oxide (which could affect the performance of certain components formed on the structure 1 (such as elastic wave components)), it is preferred to limit the proportion of nitrogen, for example so that the nitrogen / oxygen ratio remains between 0.01 and 0.5 or between 0.05 and 0.1.

[0073] The ratio of nitrogen in the first dielectric layer 31 and the second dielectric layer 32 can be the same or different. The ratio can be constant or variable within the layer. In one embodiment, the nitrogen / oxygen ratio is variable in the first dielectric layer 31 and in the second dielectric layer 32, increasing towards the barrier layer 5.

[0074] It should be noted that some dielectrics can impart compressive mechanical stresses to the substrate on which they are formed. This is the case with silicon oxide. Other dielectrics, such as silicon nitride, can provide voltage stresses. These stresses can cause the substrate to deform ("bend").

[0075] Therefore, when the first and second layers 31, 32 are made of a dielectric material providing a compressive mechanical stress, such as silicon oxide, the thickness of the silicon nitride barrier layer 5 can be adjusted to compensate for this stress. Of course, we stay above a threshold thickness of 20 nm, which gives this layer its barrier effect.

[0076] The thickness of the silicon nitride barrier layer 5 is chosen to be between 20% and 30% of the thickness of the interlayer dielectric layer. This is particularly true when the rest of the interlayer consists of silicon oxide or silicon oxynitride with a nitrogen / oxygen ratio of less than 0.5 and / or when the interlayer 3 has a thickness greater than 100 nm. With this choice, we can limit the deformation of the structure 1 in the form of a circular wafer with a diameter greater than or equal to 150 mm to less than 60 microns. For a structure 1 in the form of a circular wafer with a diameter of 200 mm, the deformation can be limited to less than 100 microns.

[0077] Note that this method of adjusting the thickness of the barrier layer 5 to limit the deformation of the structure 1 is particularly useful when the interlayer dielectric layer 3 is relatively thick (more than 200 nm). In this case, the stresses induced in the structure 1 may be relatively high, and it becomes interesting to compensate for them to avoid excessive deformation of the structure. It should also be noted that the larger the size of the structure (for example, the diameter of the wafer when the structure takes the form of a circular wafer), the greater this deformation.

[0078] In other cases, particularly when the interlayer dielectric layer 3 is relatively thin (e.g., less than 200 nm), it may be desirable to limit the stress applied by the tensile silicon nitride barrier layer 5. This can be achieved by forming the barrier layer 5 from a non-stoichiometric nitride that is rich in Si compared to stoichiometric silicon nitride in order to reduce its voltage. The refractive index of this type of nitride exceeds 2.02 at 633 nm, tending towards 2.1, 2.2 or even 2.3.

[0079] Very generally, and with reference to [ Figure 3 ], the structure 1 can be made by a manufacturing method comprising the following steps:

[0080] - providing a support 2 comprising a surface-arranged charge-trapping layer 2b;

[0081] - forming a first dielectric layer 31 on the "main" face of the support 2;

[0082] - forming a silicon nitride barrier layer 5 on and in contact with the first dielectric layer 31;

[0083] - forming a second dielectric layer 32 on and in contact with the barrier layer 5;

[0084] - assembling the main face of the support and the main face of the donor substrate to form an intermediate structure;

[0085] A portion of the donor substrate is removed from the intermediate structure so as to define a thin layer 4 on the support 2 .

[0086] In this way, the first dielectric layer 31, the barrier layer 5 and the second dielectric layer 32 are applied successively to the support 2. As previously mentioned, the thickness and / or stoichiometry of the barrier layer 5 can be adjusted to limit the deformation of the support 2 after it is received in the stack. In this way, the assembly phase is facilitated since the main faces of the donor substrate and the support are flat (which facilitates their close contact).

[0087] "Donor substrate" refers to a substrate made of the material of thin film 4, or including a surface thickness of such material. For example, the donor substrate can be a single crystal silicon bulk substrate, a lithium tantalate or lithium niobate bulk substrate, or a composite substrate consisting of a first substrate to which a layer of lithium tantalate or lithium niobate or other lithium-based material (at least equal to the layer of thin film 4) is applied.

[0088] The dielectric layer constituting the interlayer dielectric layer 3 can be made by deposition, for example using LPCVD ("low pressure chemical vapor deposition") or PECVD ("plasma enhanced chemical vapor deposition") techniques. As already mentioned, the LPCVD technique may be preferred because it tends to introduce less hydrogen into the formed layer than the PECVD technique.

[0089] The first dielectric layer 31 and / or the second dielectric layer 32 may be made of silicon oxide or silicon oxynitride.

[0090] When deposited in silicon oxide or silicon oxynitride, such a stack of layers can be produced in situ in the same deposition apparatus and without the need to remove the support from the apparatus, which is an interesting possibility from the point of view of production speed.

[0091] The use of this "in situ" method is particularly interesting when the first dielectric layer 31 and the second dielectric layer 32 are made of silicon oxynitride into which the nitrogen is introduced with a variable nitrogen / oxygen ratio increasing in the direction of the silicon nitride barrier layer 5. The introduction of nitrogen into the device can be controlled by varying the nitrogen concentration when building the different layers of the stack.

[0092] Alternatively, when the capture layer 2b is made of silicon, the first dielectric layer 31 made of silicon oxide can be obtained by oxidizing the capture layer 2b. This treatment can be achieved by exposing the support 2 provided with the capture layer 2b to a temperature strictly included between 700°C and 1000°C and in an oxygen-rich atmosphere in an oxidation furnace. This can be a dry or wet atmosphere. As is well known, the duration of this exposure is chosen according to the desired thickness of the first dielectric layer. It is generally preferred to limit the oxidation temperature to 900°C to avoid any risk of recrystallization of the capture layer 2b. In this method, the oxidation is preferably followed by a polishing step on the oxidized surface to facilitate the subsequent assembly of the donor substrate and the support substrate 2.

[0093] Before being assembled to the support 2, the donor substrate may be provided at its main face with a surface dielectric layer 41. As already stated, the presence of this surface dielectric layer facilitates subsequent assembly steps between the donor substrate and the second dielectric layer 32 present on the support 2.

[0094] The assembly step is advantageously carried out by molecular adhesion. As is well known, during the molecular adhesion method, the exposed surfaces of the fully clean, flat and smooth support 2 (second dielectric layer) and the donor substrate (possibly formed by the surface dielectric layer) are brought into close contact with each other to promote the formation of molecular bonds of the van der Waals or covalent type, for example. The two bodies are then assembled without the use of an adhesive. These bonds can be strengthened by applying a heat treatment to the intermediate structure.

[0095] The step of removing a portion of the donor substrate may be performed by chemical mechanical thinning of the substrate. Preferably, by applying Smart Cut TMThe structure 1 is manufactured using a technique according to which the layer intended to form the thin layer 4 is defined by means of an embrittlement plane formed by implanting light species (generally hydrogen and / or helium) into a donor substrate. After the assembly step, the layer is removed from the donor substrate by fracture at the embrittlement plane and is thus transferred to the support 2.

[0096] Whether the removal of a portion of the donor substrate thickness is achieved by thinning or fracturing, any type of finishing treatment may be applied to the structure 1 thus formed so that the thin layer 4 meets specifications for thickness, thickness uniformity, roughness or any other type of specification.

[0097] Of course, the invention is not limited to the embodiments described and variant embodiments may be added thereto without departing from the scope of the invention as defined by the claims.

Claims

1. A method for manufacturing a structure (1), the structure comprising a thin layer (4) formed of a lithium-based material and transferred to a support (2) via an interlayer dielectric layer (3) comprising a first dielectric layer (31), a silicon nitride barrier layer (5) and a second dielectric layer (32), the support comprising a charge trapping layer (2b) arranged on a base substrate (2a) on one side of the thin layer (4), the method comprising the following steps: - forming the first dielectric layer (31) on the capture layer (2b) arranged on the main surface of the support; - forming a silicon nitride barrier layer (5) on and in contact with the first dielectric layer (31), and the silicon nitride barrier layer has a thickness of at least 20 nm between 20% and 30% of the thickness of the dielectric interlayer (3); - forming the second dielectric layer (32) on and in contact with the barrier layer (5); - assembling the main face of the support (2) and the main face of the donor substrate to form an intermediate structure; - removing a portion of the donor substrate from the intermediate structure in order to define the thin layer (4) on the support (2).

2. The manufacturing method according to claim 1, wherein: The donor substrate includes a single crystal piezoelectric material.

3. The manufacturing method according to claim 1 or 2, wherein: The capture layer (2b) is made of polysilicon.

4. The manufacturing method according to any one of claims 1 to 3, wherein: The donor substrate is provided with a surface dielectric layer (41) on its main surface and before the donor substrate is assembled to the support (2).

5. The manufacturing method according to any one of claims 1 to 4, wherein: The first dielectric layer (31) and the second dielectric layer (32) are composed of silicon oxide or silicon oxynitride.

6. The manufacturing method according to claim 5, wherein: The first dielectric layer (31) and the second dielectric layer (32) are made of silicon oxynitride into which nitrogen has been introduced with a variable nitrogen / oxygen ratio increasing in the direction of the barrier layer (5).

7. The manufacturing method according to claim 5 or 6, wherein: The stack formed by the first dielectric layer (31), the barrier layer (5) and the second dielectric layer (32) is deposited on the support (2) by "in-situ" deposition in a chamber using LPCVD technology.

8. The manufacturing method according to any one of claims 1 to 6, wherein: The formation of the first dielectric layer (31) includes oxidation of the trapping layer (2b).

9. A structure (1), comprising a support (2) formed by a charge trapping layer (2b) disposed superficially on a base substrate (2a), and comprising a thin layer (4) formed by a lithium-based material and transferred to the support (2), the structure (1) comprising an interlayer dielectric layer (3) disposed between the support (2) and the thin layer (4) and in contact with the support (2) and the thin layer (4), the structure being characterized in that the interlayer dielectric layer comprises: a. a first dielectric layer (31) disposed on the capture layer (2b) and in contact with the capture layer (2b); b. a silicon nitride barrier layer (5) located on and in contact with the first dielectric layer (31), and the silicon nitride barrier layer (5) has a thickness of at least 20 nm between 20% and 30% of the thickness of the dielectric interlayer (3); c. A second dielectric layer (32) located on and in contact with the barrier layer (5).

10. The structure (1) according to claim 9, wherein: The capture layer (2b) is made of polysilicon.

11. The structure (1) according to claim 9 or 10, wherein: The capture layer (2b) has a thickness of less than 0.5 micrometers.

12. The structure (1) according to any one of claims 9 to 11, wherein: The film (4) is composed of a single crystal piezoelectric material.

13. The structure (1) according to any one of claims 9 to 12, wherein: The first dielectric layer (31) and the second dielectric layer (32) are composed of silicon oxide or silicon oxynitride.

14. The structure (1) according to any one of claims 9 to 13, wherein: The first dielectric layer (31) and the second dielectric layer (32) are made of silicon oxynitride into which nitrogen has been introduced with a variable nitrogen / oxygen ratio increasing in the direction of the barrier layer (5).

15. Structure (1) according to any one of claims 9 to 14, assumed to be in the form of a circular wafer with a diameter less than or equal to 200 mm and a curvature less than 100 microns.

16. The structure (1) according to any one of claims 9 to 15, wherein: The interlayer dielectric layer (3) has a thickness greater than 200 nm.

17. The structure (1) according to any one of claims 9 to 16, wherein: The barrier layer (5) consists of non-stoichiometric silicon nitride.

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