LTH and SVLC hybrid core architecture for low cost component embedding in package substrates

Abstract

An apparatus and method for efficiently transmitting information as a signal through a silicon package substrate. A semiconductor manufacturing process (or process) begins from a relatively thin package substrate core layer and uses a laser to create an opening in the package substrate at the location of a signal path. The use of each of the relatively thin core layer and the laser allows for a reduction in the spacing of the signal paths. The process creates a signal path in the opening using stacked vias from one side of the package substrate to an opposite side of the package substrate. In addition, the process forms the package substrate having a plurality of embedded passive components, the plurality of embedded passive components having different thicknesses in different layers of the package substrate. The embedded passive component is used to improve the signal integrity of the signal path.

Description

Background Art

[0001] Description of Related Technology

[0002] There is a growing demand for semiconductor packages that provide communication between one or more integrated circuits in a chip package and external components on a motherboard located outside the chip package. Electronic products associated with mobile computing, wearable electronics, and the Internet of Things (IoT) are driving the demand for small packages that utilize vertical signal interconnects. Examples of chip packages used in these products include ball grid arrays (BGAs), chip scale packages (CSPs), and system-in-package (SiPs).

[0003] The need for SiPs and more signal interconnects between integrated circuits and printed circuit boards (PCBs) has also increased the need for semiconductor packaging substrates (or packaging substrates). The packaging substrate is the part of the chip package that provides mechanical base support and is used to provide an electrical interface for signal interconnects. Vertical through silicon vias (TSVs) are formed in the silicon packaging substrate, which is connected to the printed circuit board using bump pads. The TSV groups formed through the silicon bus serve as interconnects between the base die, one or more additional integrated circuits, and the wiring on a printed circuit board (PCB) such as a motherboard or card.

[0004] When transmitting information between a transmitter and a receiver, electrical signals are typically transmitted over multiple parallel metal traces. The transmitter transmits electrical signals across parallel metal traces. The receiver receives the electrical signals. Metal traces have transmission line effects, such as distributed inductance, capacitance, and resistance throughout their length. For modern integrated circuits, interconnect capacitance degrades signal integrity and signal transmission rate more than the gate capacitance of semiconductor devices. Interconnect capacitance per unit length includes both sidewall edge capacitance and cross-coupling capacitance. For example, the electromagnetic field used to conduct signals on metal traces and the return current on the ground plane generate electrical interference to adjacent metal traces and adjacent devices.

[0005] Designers provide multiple signal integrity components in or near the metal signal path to reduce distortion caused by many noise sources (transmission line effects). These components typically include passive components arranged in a specific manner to prevent the noise source from affecting the shape and amplitude of the electrical signal transmitted across the metal signal path. Examples of passive components are resistors, inductors, and capacitors. Placing these passive components on the side of the silicon package substrate where the integrated circuit is located does not allow the passive components to be fully used for noise reduction. In addition, passive components consume area on the silicon package substrate, which reduces the density of the signal path.

[0006] In view of the foregoing, there is a need for efficient methods and systems for transmitting information as signals through a silicon packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a generalized block diagram of a package substrate including a plurality of embedded passive components having different thicknesses in different layers of the package substrate.

[0008] Figure 2 is a generalized block diagram of a cross-sectional view of a package substrate formed with signal paths and embedded passive components.

[0009] Figure 3 is another generalized block diagram of a cross-sectional view of a package substrate formed with signal paths and embedded passive components.

[0010] Figure 4 is another generalized block diagram of a cross-sectional view of a package substrate formed with signal paths and embedded passive components.

[0011] Figure 5 is another generalized block diagram of a cross-sectional view of a package substrate formed with signal paths and embedded passive components.

[0012] Figure 6 is another generalized block diagram of a cross-sectional view of a package substrate formed with signal paths and embedded passive components.

[0013] Figure 7 is another generalized block diagram of a cross-sectional view of a package substrate formed with signal paths and embedded passive components.

[0014] Figure 8 is another generalized block diagram of a cross-sectional view of a package substrate formed with signal paths and embedded passive components.

[0015] Fig. 9 It is a generalized block diagram of a semiconductor chip package.

[0016] Fig.10 is a generalized block diagram of a method for forming a packaging substrate including a plurality of embedded passive components having different thicknesses in different layers of the packaging substrate.

[0017] Fig.11 is a generalized block diagram of a method for forming a semiconductor chip package having a packaging substrate including a plurality of embedded passive components.

[0018] Fig.12 is a generalized block diagram of a semiconductor chip package having a packaging substrate including a plurality of embedded passive components.

[0019] Although the present invention is susceptible to various modifications and alternative forms, specific implementations are shown by way of example in the drawings and described in detail herein. However, it should be understood that the drawings and detailed description thereof are not intended to limit the invention to the specific forms disclosed, but on the contrary, the invention is to cover all modifications, equivalents and alternatives within the scope of the invention defined by the appended claims. DETAILED DESCRIPTION

[0020] In the following description, many specific details are set forth to provide a thorough understanding of the present invention. However, it will be appreciated by those of ordinary skill in the art that the present invention may be practiced without these specific details. In some cases, well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the present invention. In addition, it should be understood that for simplicity and clear illustration, the elements shown in the figures are not necessarily drawn to scale. For example, the size of some elements is enlarged relative to other elements.

[0021] An apparatus and method for effectively transmitting information as a signal through a silicon package substrate is envisioned. A semiconductor manufacturing process (or process) forms a package substrate having one or more signal paths, which use stacked vias from one side of the package substrate to the opposite side of the package substrate. Therefore, these one or more signal paths abandon the use of plated through holes (PTH). The spacing of these signal paths is smaller than the spacing of signal paths that do use plated through holes. The process forms a package substrate with multiple embedded passive components, which have different thicknesses in different layers of the package substrate. To this end, the process starts with a relatively thin package substrate core layer, and uses a laser to create an opening in the package substrate at the location of the signal path. The use of each of the relatively thin core layer and the laser allows the reduction of the spacing of the signal path. In contrast, the use of a relatively thick package substrate core and mechanical drilling increases the spacing of the signal path. The relatively large opening created by mechanical drilling reduces the reliability of forming multiple embedded passive components with different thicknesses in different layers of the package substrate later.

[0022] Examples of embedded passive components include resistors, inductors, and capacitors. Embedded passive components are used to improve signal integrity on signal paths that transmit data within a package substrate. For example, embedded passive components are placed in layers of a package substrate in a manner that performs impedance matching to minimize signal reflections, reduces signal skew by closely matching the length of signal paths, reduces crosstalk, minimizes overshoot and undershoot of electrical signals, and reduces electromigration interference.

[0023] The process places a first side of a package substrate on a plurality of interconnects of a motherboard. The process places an integrated circuit on a second side different from the first side of the package substrate. The process completes the connection of a chip package, which may be one of a ball grid array (BGA) surface mount package, a chip scale package (CSP), or a system-in-package (SiP). In addition to the components on the motherboard, a potential, such as at least one power supply voltage, is applied to one or more nodes of the chip package. When the package substrate receives data to be transmitted, the package substrate communicates the data from the first side of the package substrate receiving the data to the second side opposite to the first side of the package substrate. Multiple embedded passive components having different thicknesses in different layers of the package substrate improve the signal integrity of the transmitted electrical signals.

[0024] In the following description, Figure 1 A plurality of packaging substrates are shown that include a plurality of embedded passive components having different thicknesses in different layers of the packaging substrate. Figure 2 A package substrate with large pitches that relies on mechanical drilling to create openings for plated through holes is illustrated. The relatively large and widely spaced plated through holes limit the number and types of embedded passive components that can be placed in the package substrate. Figure 3 A semiconductor chip package is illustrated. Figures 4 to 10 Fabrication steps for creating a package substrate having multiple embedded passive components with different thicknesses in different layers of the package substrate are illustrated. Figure 11 to Figure 12 Method steps for performing a method for creating a package substrate having multiple embedded passive components with different thicknesses in different layers of the package substrate are provided. FIG. 13 shows an example of a fabricated chip package including a package substrate having multiple embedded passive components placed in a computing system.

[0025] refer to Figure 1 , shows a generalized block diagram of a package substrate 100 having multiple embedded passive components located in multiple layers. As shown, the package substrate 100 includes a core layer 102 having a relatively small thickness 120. The thickness 120 of the core layer 102 is measured along a dimension of the package substrate 100 that is aligned with the direction of the signal path that transmits data as electrical signals through the package substrate 100. The signal path uses metal layers 106 and stacked vias instead of plated through holes (PTHs). Although not shown for ease of illustration, it is possible and conceivable that one side of the package substrate 100 (such as Figure 1 The other side of the package substrate 100 has a plurality of interconnects placed on the other side of the package substrate 100 (such as Figure 1The core layer 102 includes a passive component, such as an inductor 110, having a thickness less than a thickness 120 of the core layer 102. The packaging substrate 100 also includes another passive component, such as a capacitor 112, in a different layer from the inductor 110. Thus, the packaging substrate 100 includes a plurality of embedded passive components (passive components 110 and 112) located in a plurality of layers of the packaging substrate 100.

[0026] The packaging substrate 100 also includes a plurality of dielectric layers 104, wherein one or more of the layers have a different thickness and composition than other dielectric layers 104 of the packaging substrate 100. It should be noted that in various implementations, the thickness of the capacitor 112 is different than the thickness of the inductor 110. Thus, the packaging substrate 100 includes a plurality of embedded passive components having different thicknesses.

[0027] In various specific implementations, metal layer 106 includes an alloy of copper or other metals (such as aluminum) mixed with copper. Similar to motherboards and other printed circuit boards, such as expansion cards, network cards, and video cards, core layer 102 uses glass-reinforced epoxy laminates. The material provides relatively high mechanical strength while also providing electrical insulation between interconnects and semiconductor chips. An example of a glass-reinforced epoxy laminate is FR-4 (or FR4) glass epoxy. Core layer 102 includes one or more signal paths embedded in and running through the FR-4 material. Another example is glass bismaleimide triazine (BT) epoxy.

[0028] In various specific implementations, dielectric layer 104 includes various types of encapsulated dielectric layers. For example, various types of prepreg resin materials are used. Prepreg is a reinforcing fabric that has been pre-impregnated with resin, such as epoxy resin that already contains a curing agent. Therefore, the prepreg is ready to be placed in a corresponding mold and more resin is added. A combination of heat and pressure is used to cure the laminate. Heat softens, flows and surrounds the metal layer 106 with the prepreg material, bonding multiple different layers together, and then fully curing. Dielectric layer 104 protects metal layer 106 and passive components (such as inductor 110 and capacitor 112) from physical, chemical and electrical damage by insulating them.

[0029] It should be noted that the core layer 102 is not mechanically drilled after the dielectric layer 104 is formed. Instead, in order to increase the pitch density of the stacked vias used to create the signal path, the core layer 102 has openings created by a laser before the dielectric layer 104 is formed. In a specific implementation, the thickness 120 of the core layer 102 is 250 microns. The thickness of each of the inductor 110 and the capacitor 112 is less than the thickness of the core layer 102. In order to create the openings in the core layer 102, a laser is used due to the relatively thin core layer 102. In contrast, mechanical drilling is used to create openings in the core layer having a relatively high thickness of 1,000 microns (or 1 mm). Using a relatively thin core layer 102 and using a laser to create openings for the signal path allows the spacing of the signal path to be reduced (increasing the pitch density).

[0030] It is possible and conceivable that data can be transmitted through a stack of vias created in the package substrate 100 using the metal layer 106. The process creates a signal path in the opening created by the laser using the stacked vias including the metal layer 106. The stacked vias using the metal layer 106 create a signal path from one side of the package substrate 100 to the opposite side of the package substrate 100. Therefore, in various implementations, the package substrate 100 abandons the use of plated through holes (PTHs) as signal paths.

[0031] Examples of embedded passive components placed in the packaging substrate 100 are resistors, inductors, and capacitors. Although a single inductor 110 and a single capacitor 112 are shown, in other implementations, the packaging substrate 100 includes other numbers of passive components placed in different layers of the packaging substrate 100. The embedded passive components are used to improve signal integrity on signal paths that transmit data within the packaging substrate 100. For example, embedded passive components such as the inductor 110 and the capacitor 112 are placed in layers of the packaging substrate 100 in a specific manner that performs impedance matching to minimize signal reflections, reduces signal skew by closely matching the length of the signal path, reduces crosstalk, minimizes overshoot and undershoot of electrical signals, and reduces electromigration interference.

[0032] When the package substrate 100 receives data to be transmitted, the package substrate 100 communicates the data from a first side of the package substrate 100 receiving the data (such as the top of the package substrate 100) to a second side opposite to the first side of the package substrate 100. A plurality of embedded passive components, such as at least the inductor 110 and the capacitor 112, having different thicknesses in different layers of the package substrate 100 improves the signal integrity of the transmitted electrical signal.

[0033] Now go to Figure 2, a generalized block diagram of a cross-sectional view of a package substrate 200 being formed is shown. The materials, layers, and components previously described are numbered identically. It should be noted that the core layer 102 is not mechanically drilled after the dielectric layer 104 is formed. Instead, in order to increase the pitch density of the stacked vias used to create signal paths, the core layer 102 has openings created by a laser before the dielectric layer 104 is formed. The core layer 102 has a relatively thin thickness 120, and a laser is used to form vias in the locations of the stacked vias made by the metal layer 106. The laser-formed vias are electrically filled with copper or another metal mixture and patterned using existing standard processes.

[0034] A cavity 210 is formed for later embedding of a passive component such as the inductor 110. A laminated temporary tape 220 is formed for component embedding. Thereafter, a passive component such as the inductor 110 is placed in the cavity 210. Although the inductor 110 is shown as being placed in the cavity 210, in other specific implementations, other types of passive components are placed in the cavity 210. It should be noted that the width of the cavity 210 measured in a direction aligned with the spacing of the signal path is relatively small. The relatively small width of the cavity 210 makes subsequent cavity filling more manageable and improves yield. It should also be noted that the thickness of the passive component such as the inductor 110 is less than the thickness 120 of the core layer 102. After the passive component is placed in the cavity 210, a copper (Cu) attachment promotion (AP) processing step is performed.

[0035] Figures 3 to 8 Subsequent processing steps for forming a package substrate having multiple embedded passive components located in multiple layers are illustrated. Figures 3 to 9 , previously described materials, layers and components are numbered identically. Figure 3 A generalized block diagram of a package substrate 300 is illustrated after a dielectric lamination step for filling the cavity 210 and with the tape 220 removed. Another dielectric lamination step is performed, followed by a curing step, and openings are created by laser in locations for stacked vias. Afterwards, a burr removal (deburring) step is performed. Figure 4 A generalized block diagram of a package substrate 400 after copper seed layer deposition using an electroless plating technique is illustrated.

[0036] Figure 5 A generalized block diagram of a package substrate 500 is illustrated which undergoes an exposure step, a development step, an etching step, and a stripping step after a dry film photoresist (DFR) lamination process. Figure 6 The package substrate 600 is illustrated after a copper (Cu) adhesion promotion (AP) processing step and dielectric lamination. Figure 7A generalized block diagram of a package substrate 700 is illustrated after laser creation of openings, burr removal (deburring) steps, and copper seed layer deposition using electroless plating techniques. Afterwards, a DFR lamination process is performed, followed by an exposure step, a development step, an etching step, and a stripping step. Afterwards, passive components, such as capacitor 112, are placed.

[0037] In various implementations, capacitor 112 has a thickness different from that of inductor 110, and each of inductor 110 and capacitor 112 has a thickness less than thickness 120 of core layer 102. Furthermore, capacitor 112 is placed in a different dielectric layer 104 than core layer 102 where inductor 110 is placed. Figure 8 A generalized block diagram of a package substrate 800 after a copper (Cu) adhesion promotion (AP) processing step and dielectric lamination is illustrated.

[0038] Fig. 9 A generalized block diagram of a semiconductor chip package 900 is illustrated. As shown, the semiconductor chip package 900 (or chip package 900) uses various types of interconnects. One example is a controlled collapse chip connection (C4) interconnect 910, also known as a flip chip interconnect. Another example is a solder ball 960. Solder ball 960 provides a connection between multiple layers of a package substrate and a motherboard (not shown). Solder mask 940 is an insulating ink that covers the surface of a printed wiring board and protects the circuit pattern. Underfill 930 is a composite material made of an epoxy polymer that is used to compensate for thermal expansion of materials between an integrated circuit (IC) 920 and a package substrate. Integrated circuit 920 can be one of various types of integrated circuits. It should be noted that the package substrate shown uses a plated through hole (PTH) with a corresponding resin 950, and therefore, is not compatible with the package substrate. Figures 1 to 8 Compared to the illustrated signal paths, the package substrate consumes more area and has a smaller spacing density. Figures 1 to 8 The described method replaces the method of creating PTH, provides a thinner core layer 102 and a higher spacing density for signal routing, and allows the placement of multiple embedded passive components located in multiple layers of the package substrate. In addition, these embedded passive components have different thicknesses compared to each other and the thickness is less than the thickness of the core layer 102.

[0039] refer to Fig.10 , shows a generalized view of a method 1000 for efficiently creating a silicon package substrate with multiple layers of embedded passive components. For discussion purposes, this specific implementation (and Fig.11 However, in other implementations, some steps occur in a different order than shown, some steps are performed simultaneously, some steps are combined with other steps, and some steps are not present.

[0040] A semiconductor manufacturing process (or procedure) forms an opening having a first thickness in a core layer of a package substrate by using a laser (block 1002). The process fills the opening with metal (block 1004). The process creates a cavity in the core layer (block 1006). The process places a passive component in the cavity (block 1008). The process deposits a dielectric in the cavity (block 1010). The process deposits a dielectric on both the top and bottom sides of the core layer (block 1012). The process creates stacked vias on the passive components and through holes by forming the opening with a laser and filling the opening with metal (block 1014).

[0041] The process etches away excess metal and deposits dielectric on both the top and bottom sides of the package substrate (block 1016). The process places one or more other passive components on top of the metal layer or dielectric layer where needed (block 1018). The process deposits dielectric on both the top and bottom sides of the package substrate (block 1020). If the desired customizable thickness of the package substrate has not been reached (the "no" branch of conditional block 1022), the control flow of method 1200 returns to block 1014, where the process creates stacked vias on the passive components and through holes by forming openings with a laser and filling the openings with metal. If the desired customizable thickness of the package substrate has been reached (the "yes" branch of conditional block 1022), the process is complete (block 1024). The package substrate is ready to be placed in a chip package.

[0042] refer to Fig.11 , a generalized block diagram of a method 1100 for efficiently creating a chip package having a silicon packaging substrate having multiple layers of embedded passive components is shown. A semiconductor manufacturing process (or process) forms a packaging substrate having multiple signal paths using stacked vias from one side of the packaging substrate to the opposite side of the packaging substrate (block 1102). The process forms a packaging substrate having multiple embedded passive components having different thicknesses in different layers of the packaging substrate (block 1104). In various specific implementations, the packaging substrate includes packaging substrates 100 to 800 ( Figures 1 to 8 ) materials, layers and multiple passive components.

[0043] The process places a first side of the package substrate on a plurality of interconnects of a motherboard (block 1106). The process places an integrated circuit on a second side different from the first side of the package substrate (block 1108). The process completes the connection of a chip package, which may be one of a ball grid array (BGA) surface mount package, a chip scale package (CSP), or a system-in-package (SiP). In addition to the components on the motherboard, a potential, such as at least one power supply voltage, is applied to one or more nodes of the chip package. If the package substrate does not receive data to be transmitted (the "no" branch of conditional block 1110), the package substrate waits for data (block 1112). However, if the package substrate receives data to be transmitted (the "yes" branch of conditional block 1110), the package substrate communicates the data from the first side of the package substrate receiving the data to the second side opposite to the first side of the package substrate (block 1114).

[0044] refer to Fig.12 , shows a specific implementation of a computing system 1200 that utilizes multiple embedded passive components located in multiple layers of a packaging substrate. The computing system 1200 utilizes a chip package 1240, which includes a packaging substrate 1220. The packaging substrate 1220 has multiple embedded passive components located in multiple layers. In various specific implementations, the packaging substrate 1220 includes packaging substrates 100 to 800 ( Figures 1 to 8 ) materials, layers, and multiple passive components. The chip package 1240 uses one of a ball grid array (BGA) surface mount package, a chip scale package (CSP), and a system-level package (SiP). The chip package 1240 communicates with other components on a motherboard (or printed circuit board). In one specific implementation, the computing system 1200 includes a processor 1210 and a memory 1230 in the chip package 1240.

[0045] In another specific implementation, only one of the processor 1210 and the memory 1230 is included in the chip package 1240. Although a single processor is shown, in other specific implementations, the chip package 1240 includes other numbers of processors and various other types of integrated circuits (ICs). The number and type of ICs located in the chip package 1240 are based on design requirements. For ease of illustration, interfaces such as memory controllers, buses or communication fabrics, one or more phase-locked loops (PLLs) and other clock generation circuits, power management units, etc. are not shown. In addition, in the illustrated specific implementation, the chip package 1240 is connected to the disk memory 1254 through the memory bus 1250 and the input / output (I / O) controller and bus 1252.

[0046] It should be understood that in other implementations, the computing system 1200 includes one or more peripheral devices, a network interface, one or more other memory devices, etc. In some implementations, the functionality of the computing system 1200 is incorporated on a system on a chip (SoC). In other implementations, the functionality of the computing system 1200 is incorporated on a peripheral device card that plugs into a motherboard. The computing system 1200 is used in any of a variety of computing devices such as a desktop computer, a server computer, a tablet computer, a laptop computer, a smart phone, a smart watch, a game console, a personal assistant device, etc.

[0047] Processor 1210 includes hardware such as circuits. In various specific implementations, processor 1210 includes one or more processing units. In some specific implementations, each of the processing units includes one or more processor cores capable of general data processing and an associated cache memory subsystem. In such specific implementations, processor 1210 is a central processing unit (CPU). In another specific implementation, the processing core is a computing unit, each computing unit having a highly parallel data micro-architecture with multiple parallel execution paths and associated data storage buffers. In such specific implementations, processor 1210 is a graphics processing unit (GPU), a digital signal processor (DSP) or other.

[0048] In some implementations, the memory 1230 includes one of several types of dynamic random access memory (DRAM). The memory 1230 stores at least a portion of an operating system (OS) 1232, one or more applications represented by code 1234, and at least source data 1236. In various implementations, the memory 1230 stores copies of these software components 1232, 1234, and 1236 with the original copies stored on disk storage 1254. The memory 1230 can also store intermediate and final result data generated by the processor 1210 when executing a particular application of the code 1234.

[0049] In various implementations, the off-chip disk storage 1254 includes one or more hard disk drives (HDDs) and solid-state disks (SSDs) including flash memory storage. The I / O controller and bus 1252 supports a communication protocol with the off-chip disk storage 1254. Although a single operating system 1232 and a single instance of code 1234 and source data 1236 are shown, in other implementations, another number of these software components are stored in the memory 1230 and the disk storage 1254. The operating system 1232 includes instructions for initiating booting of the processor 1210, assigning tasks to hardware circuits, managing resources of the computing system 1200, and hosting one or more virtual environments.

[0050] It should be noted that one or more of the above-mentioned specific implementations include software. In such specific implementations, the program instructions of the implementation method and / or mechanism are communicated or stored on a computer-readable medium. Many types of media configured to store program instructions are available and include hard disks, floppy disks, CD-ROMs, DVDs, flash memories, programmable ROMs (PROMs), random access memories (RAMs) and various other forms of volatile or non-volatile storage devices. In general, a computer-accessible storage medium includes any storage medium that can be accessed by a computer during use to provide instructions and / or data to a computer. For example, a computer-accessible storage medium includes such as magnetic or optical media, such as disks (fixed or removable), tapes, CD-ROMs or DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs or storage media such as blue-rays. The storage medium also includes volatile or non-volatile storage media, such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (RDRAM), static RAM (SRAM), etc.), ROM accessible via a peripheral device interface (such as a universal serial bus (USB) interface, etc.), flash memory, non-volatile memory (e.g., flash memory). The storage medium includes micro-electromechanical systems (MEMS), and storage media accessible via communication media such as a network and / or a wireless link.

[0051] In addition, in various specific implementations, the program instructions include a behavioral level description or a register transfer level (RTL) description of the hardware functionality in a high-level programming language such as C or a design language (HDL) such as Verilog, VHDL, or a database format such as GDS II stream format (GDSII). In some cases, the description is read by a synthesis tool, which synthesizes the description to produce a netlist including a list of gates from a synthesis library. The netlist includes a set of gates, which also represents the functionality of the hardware comprising the system. The netlist is then placed and threaded to produce a data set describing the geometry to be applied to the mask. The mask is then used in various semiconductor manufacturing steps to produce a semiconductor circuit or circuit corresponding to the system. Alternatively, the instructions on the computer-accessible storage medium are a netlist (with or without a synthesis library) or a data set as desired. In addition, the instructions are used by the computer-accessible storage medium such as and Mentor Such vendors' hardware-based types of emulators are used for emulation purposes.

[0052] Although the above embodiments have been described in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to encompass all such variations and modifications.

Claims

1. A device, comprising: one or more integrated circuits (ICs); multiple interconnects to a motherboard; and A packaging substrate configured to transmit data between a given IC of the one or more ICs and the plurality of interconnects through a plurality of signal paths, wherein one or more of the plurality of signal paths include stacked vias from one side of the packaging substrate to an opposite side of the packaging substrate. 2 . The device of claim 1 , wherein the packaging substrate comprises a plurality of embedded passive components, wherein at least two passive components have two different thicknesses. 3 . The device of claim 1 , wherein the packaging substrate comprises a plurality of embedded passive components, wherein at least two passive components are located in two different layers of the packaging substrate. 4 . The apparatus of claim 1 , wherein one or more of the plurality of signal paths comprises an embedded passive component having a first thickness less than a second thickness of a core layer of the packaging substrate. 5 . The apparatus of claim 1 , wherein the spacing of the plurality of signal paths is independent of the area that can be consumed by passive components between the given IC and the packaging substrate. 6 . The apparatus of claim 5 , wherein the pitch is set by a particle size of a laser used during fabrication of the packaging substrate. The apparatus of claim 1 , wherein the plurality of signal paths forgo the use of plated through holes.

8. A method comprising: forming a package substrate including a plurality of signal paths by a semiconductor manufacturing process, wherein one or more signal paths of the plurality of signal paths include stacked vias from one side of the package substrate to an opposite side of the package substrate; placing the first side of the package substrate on a plurality of interconnects by the semiconductor manufacturing process; placing, by the semiconductor manufacturing process, a given IC of one or more integrated circuits (ICs) on a second side of the package substrate different from the first side; as well as In response to receiving data on a given side of the first side and the second side of the packaging substrate, the data is communicated to an opposite side of the packaging substrate different from the given side through the plurality of signal paths. 9 . The method of claim 8 , further comprising forming a plurality of embedded passive components in the package substrate by the semiconductor manufacturing process such that at least two passive components have two different thicknesses. 10 . The method of claim 8 , further comprising forming a plurality of embedded passive components in the package substrate by the semiconductor manufacturing process, such that at least two passive components are located in two different layers of the package substrate.

11. The method of claim 8, further comprising forming one or more of the plurality of signal paths having embedded passive components through the semiconductor manufacturing process, the embedded passive components having a first thickness less than a second thickness of a core layer of the packaging substrate.

12. The method of claim 9, further comprising forming the plurality of signal paths through the semiconductor manufacturing process such that a spacing of the plurality of signal paths is independent of an area that can be consumed by passive components between the given IC and the packaging substrate. 13 . The method of claim 12 , wherein the pitch is set by a particle size of a laser used during fabrication of the package substrate.

14. The method of claim 8, further comprising forming the plurality of signal paths by the semiconductor manufacturing process such that the plurality of signal paths forgo the use of plated through vias.

15. A computing system, comprising: a memory configured to store one or more applications of the workload; and Chip packaging, the chip packaging comprising: one or more integrated circuits (ICs); a plurality of interconnects to a motherboard; and A packaging substrate configured to transmit data between a given IC of the one or more ICs and the plurality of interconnects through a plurality of signal paths, wherein one or more of the plurality of signal paths include stacked vias from one side of the packaging substrate to an opposite side of the packaging substrate. 16 . The computing system of claim 15 , wherein the packaging substrate comprises a plurality of embedded passive components, wherein at least two passive components have two different thicknesses. 17 . The computing system of claim 15 , wherein the packaging substrate comprises a plurality of embedded passive components, wherein at least two passive components are located in two different layers of the packaging substrate. 18 . The computing system of claim 15 , wherein one or more of the plurality of signal paths include embedded passive components having a first thickness that is less than a second thickness of a core layer of the packaging substrate.

19. The computing system of claim 15, wherein the spacing of the plurality of signal paths is independent of the area that can be consumed by passive components between the given IC and the packaging substrate.

20. The computing system of claim 19, wherein the pitch is set by a granularity of a laser used during fabrication of the packaging substrate.

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