FET-based AC-to-DC converter with negative periodic gate pre-charge

Abstract

A power converter circuit includes: a solid state switch connected between a first node and a second node; a capacitor coupled between the second node and a ground reference node; and a control system that monitors a voltage level across the capacitor, and (i) turns on the solid state switch during a positive half-cycle of an AC electrical waveform coupled to the first node to cause the capacitor to be charged when the voltage level across the capacitor is less than a maximum DC voltage level, and (ii) turns off the solid state switch during a negative half-cycle of an AC electrical waveform coupled to the second node to cause the capacitor to be charged when the voltage level across the capacitor is less than a maximum DC voltage level. And (ii) turning off the solid state switch during the positive half cycle of the AC electrical waveform in response to determining that the voltage level across the capacitor has reached the maximum DC voltage level. The control system is configured to generate a regulated threshold voltage for the solid state switch during a negative half-cycle of the AC electrical waveform while maintaining the solid state switch in an off state during the negative half-cycle.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 356,317 filed on June 28, 2022, the disclosure of which is incorporated herein by reference. Background Art

[0003] The present disclosure generally relates to power conversion technology, and more specifically to power conversion technology for converting alternating current (AC) electricity to direct current (DC) electricity. Conventional methods for converting AC electricity to DC electricity use various analog circuit systems to achieve AC to DC voltage conversion. For example, a conventional AC to DC converter includes a transformer-based linear converter, which utilizes a simple diode bridge, a capacitor, and a voltage regulator, wherein the diode bridge is constructed by four independent diodes. Another conventional converter implements a switch mode power supply architecture, which utilizes a high-frequency small transformer and a switching regulator to provide a DC voltage output. However, such conventional methods undesirably require many circuit components, which may cause signal processing delays, inaccuracies, and / or increase the overall cost of implementing an AC to DC converter. Summary of the invention

[0004] Exemplary embodiments of the present disclosure include power converter circuits and methods for converting AC power to DC power, and intelligent electrical devices implementing such power converter circuits.

[0005] For example, an exemplary embodiment includes a power converter circuit including a first solid-state switch connected between a first node and a second node, a first capacitor coupled between the second node and a ground reference node, and a control system configured to control operation of the first solid-state switch. The control system is configured to monitor a voltage level across the first capacitor and (i) in response to determining that the voltage level across the first capacitor is less than a maximum DC voltage level, turn on the first solid-state switch during a positive half-cycle of an AC power waveform coupled to the first node so that a charging current flows from the first node to the second node and charges the first capacitor, and (ii) in response to determining that the voltage level across the first capacitor has reached the maximum DC voltage level, turn off the first solid-state switch during the positive half-cycle of the AC power waveform. The control system is configured to generate a regulation threshold voltage for the first solid-state switch during a negative half-cycle of the AC power waveform while maintaining the first solid-state switch in an off state during the negative half-cycle.

[0006] Another exemplary embodiment includes an electrical device, the electrical device comprising a solid-state AC switch coupled between a power input terminal of the electrical device and a load output terminal, a switch control system configured to control the operation of the solid-state AC switch, and a power converter circuit configured to convert AC power applied to the power input terminal of the electrical device into DC power for operating the switch control system of the electrical device. The power converter circuit comprises a first solid-state switch connected between a first node and a second node, a first capacitor coupled between the second node and a ground reference node, and a control system configured to control the operation of the first solid-state switch. The control system is configured to monitor a voltage level across the first capacitor, and (i) in response to determining that the voltage level across the first capacitor is less than a maximum DC voltage level, turn on the first solid-state switch during a positive half cycle of an AC power waveform coupled to the first node so that a charging current flows from the first node to the second node and charges the first capacitor, and (ii) in response to determining that the voltage level across the first capacitor has reached the maximum DC voltage level, turn off the first solid-state switch during the positive half cycle of the AC power waveform. The control system is configured to generate a regulation threshold voltage for the first solid-state switch during a negative half-cycle of the AC power waveform while maintaining the first solid-state switch in an off state during the negative half-cycle.

[0007] In an exemplary embodiment, the electrical device is a smart solid-state circuit breaker. In another exemplary embodiment, the electrical device is a smart solid-state dimmer switch.

[0008] Another exemplary embodiment includes a method, the method comprising: controlling a first solid-state switch coupled to and located between a first node and a second node to charge a first capacitor coupled to and located between the second node and a ground reference node using a current drawn during a positive cycle of an AC power waveform present at the first node to generate a DC voltage at the second node, wherein controlling the first solid-state switch comprises: monitoring a voltage level across the first capacitor; in response to determining that the voltage level across the first capacitor is less than a maximum DC voltage level, turning on the first solid-state switch during the positive half cycle of the AC power waveform so that a charging current flows from the first node to the second node and charges the first capacitor; in response to determining that the voltage level across the first capacitor has reached the maximum DC voltage level, turning off the first solid-state switch during the positive half cycle of the AC power waveform; and generating a regulation threshold voltage for the first solid-state switch during a negative half cycle of the AC power waveform while maintaining the first solid-state switch in an off state during the negative half cycle.

[0009] Other embodiments are described in the following detailed description of exemplary embodiments, which is to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A power converter circuit according to an exemplary embodiment of the present disclosure is schematically illustrated.

[0011] Figure 2A , 2B 2C and 2D are waveform diagrams showing the operation of an exemplary embodiment according to the present disclosure. Figure 1 Example operating modes of the power converter circuit.

[0012] Figure 3 An intelligent electrical device implementing a power converter circuit according to an exemplary embodiment of the present disclosure is schematically illustrated.

[0013] Figure 4 Schematically illustrates an embodiment of a solid-state AC switch according to an exemplary embodiment of the present disclosure, which can be used in Figure 3 It is implemented in intelligent electrical devices. DETAILED DESCRIPTION

[0014] Embodiments of the present disclosure will now be described in further detail for power converter circuits and methods for converting AC electricity to DC electricity and intelligent electrical devices implementing such power converter circuits. It should be understood that the various features shown in the drawings are schematic illustrations that are not drawn to scale. In addition, throughout the drawings, the same or similar reference numerals are used to represent the same or similar features, elements or structures, and therefore, detailed explanations of the same or similar features, elements or structures will not be repeated for each drawing. Further, the term "exemplary" as used herein means "used as an example, example or illustration". Any embodiment or design described herein as "exemplary" should not be interpreted as being more preferred or advantageous over other embodiments or designs.

[0015] Further, it should be understood that the phrase "configured to" as used in connection with circuits, structures, elements, components, etc. that perform one or more functions or otherwise provide some functionality is intended to cover embodiments in which the circuits, structures, elements, components, etc. are implemented in hardware, software and / or a combination thereof, as well as in embodiments that include hardware, where the hardware may include discrete circuit elements (e.g., transistors, inverters, etc.), programmable elements (e.g., application specific integrated circuit (ASIC) devices, field programmable gate array (FPGA) devices, etc.), processing devices (e.g., central processing unit (CPU) devices, graphics processing unit (GPU) devices, microcontroller devices, etc.), one or more integrated circuits and / or a combination thereof. Thus, by way of example only, when a circuit, structure, element, component, etc. is defined as being configured to provide a specific functionality, this is intended to cover, but not be limited to, embodiments in which the circuit, structure, element, component, etc. is comprised of elements, processing devices and / or integrated circuits that enable it to perform the specific functionality when in an operational state (e.g., connected or otherwise deployed in a system, powered on, receiving input and / or generating output), and to cover embodiments when the circuit, structure, element, component, etc. is in a non-operational state (e.g., not connected or otherwise deployed in a system, not powered on, not receiving input and / or not generating output) or in a partially operational state.

[0016] Figure 1 The power converter circuit 100 according to an exemplary embodiment of the present disclosure is schematically illustrated. Specifically, Figure 1A power converter circuit 100 is schematically shown, which is configured to convert AC power delivered from an AC power source 10 into DC power applied to a DC load 20. In some embodiments, the AC power source 10 includes a utility power source (e.g., AC mains) that supplies an AC voltage waveform with a frequency of 60 Hz and a voltage of 120 V RMS (peak value of about 170 V). In other embodiments, the AC power source 10 can be other AC power sources of different voltage levels and / or frequencies. The power converter circuit 100 includes an input terminal 101 and an output terminal 102, wherein the input terminal 101 is coupled to a terminal (e.g., a line hot terminal) of the AC power source 10, and the output terminal 102 is coupled to a DC input terminal of the DC load 20. The power converter circuit 100 includes a first diode D1, a second diode D2, a Zener diode Z1, a plurality of resistors R1, R2, R3, R4, and R5, a first capacitor C1 (alternatively, a storage capacitor C1), a second capacitor C2, a first solid-state switch 110, a second solid-state switch 120, a latch circuit 130, a first operational amplifier 140 (alternatively, a first comparator), and a second operational amplifier 150 (alternatively, a second comparator). The various components D1, D2, Z1, R1, R2, R3, R4, R5, C1, 120, 130, 140, and 150 together constitute a control system 160 (or control circuit system). The control system 160 is configured to control the operation of the first solid-state switch 110, and thereby control the charging of the storage capacitor C1 to generate a DC voltage V at the output node (node ​​N2) of the power converter circuit 100. DC The current flow (expressed as I Charge ), the details of which will be explained in further detail below.

[0017] In some embodiments, the first solid-state switch 110 and the second solid-state switch 120 each include a metal oxide semiconductor field effect transistor (MOSFET) device. In some embodiments, the first solid-state switch 110 and the second solid-state switch 120 include an N-type MOSFET device. In some embodiments, the first solid-state switch 110 includes a high-voltage MOSFET device. In some embodiments, the first operational amplifier 140 and the second operational amplifier 150 are configured to operate as a voltage comparator. In some embodiments, the latch circuit 130 includes a set-reset (SR) flip-flop circuit, which includes a first input terminal (set S input), a second input terminal (reset R input) and an output terminal Q.

[0018] The first solid-state switch 110 includes a first source / drain terminal (e.g., drain terminal D) coupled to the first node N1, a second source / drain terminal (e.g., source terminal S) coupled to the second node N2, and a gate terminal G coupled to the third node N3. The second solid-state switch 120 includes a first source / drain terminal (e.g., drain terminal D) coupled to the fourth node N4, a second source / drain terminal (e.g., source terminal S) coupled to the ground reference node GND, and a gate terminal G coupled to the output terminal Q of the latch circuit 130.

[0019] The first diode D1 includes an anode terminal coupled to the input terminal 101 and a cathode terminal coupled to the first node N1. The second diode D2 includes an anode terminal coupled to the first node N1 and a cathode terminal coupled to the fifth node N5. The second capacitor C2 is coupled to the fifth node N5 and the ground reference node GND and is located therebetween. The resistor R1 is coupled to the nodes N4 and N5 and is located therebetween. The resistor R2 is coupled to the nodes N3 and N4 and is located therebetween. The Zener diode Z1 includes an anode terminal coupled to the second node N2 and a cathode terminal coupled to the third node N3.

[0020] The first comparator 140 includes: (i) a non-inverting (+) input terminal coupled to the ground reference node GND, (ii) an inverting (-) input terminal coupled to the first node N1 through a resistor R3 and configured to receive an input voltage V IN , and (iii) an output terminal coupled to a reset R input terminal of the latch circuit 130. The first comparator 140 comprises an inverting comparator topology, wherein when the input voltage V IN When the input voltage V IN When the voltage is greater than the ground voltage GND, the output turns to logic "0".

[0021] The second comparator 150 includes: (i) a non-inverting (+) input terminal coupled to a sixth node N6 located between the resistors R4 and R5 and configured to receive an input voltage V TRIP , (ii) an inverting (-) input terminal coupled to a threshold voltage node, the threshold voltage node comprising a preset threshold voltage V REF , and (iii) an output terminal coupled to the set S input terminal of the latch circuit 130. The second comparator 150 includes a non-inverting comparator topology, wherein when the input voltage V TRIP Greater than the threshold voltage V REF When the output of the second comparator 150 changes to logic "1", and when the input voltage V TRIP Less than the threshold voltage V REFThe output changes to a logic "0" when Figure 1 In an exemplary embodiment, resistors R4 and R5 form a resistor divider network, where the input voltage V TRIP (which is generated at node N6) is the DC voltage V across the storage capacitor C1 at the output node N2 of the power converter circuit 100 DC part of.

[0022] In an exemplary configuration, the output of the first comparator 140 controls the reset R input of the latch circuit 130, and the output of the second comparator 150 controls the set S input of the latch circuit 130. The Q output of the latch circuit 130 controls the operation of the second solid-state switch 120. The following truth table illustrates the operation of the latch circuit 130:

[0023]

[0024] When the Q output of the latch circuit 130 is at a logic "0" level (reset state), the second solid-state switch 120 is in an off state, thereby turning on the first solid-state switch 110. On the other hand, when the Q output of the latch circuit 130 is at a logic "1" level (set state), the second solid-state switch 120 is in an on state, thereby turning off the first solid-state switch 110.

[0025] As described above, in an exemplary embodiment, the control system 160 of the power converter circuit 100 is configured to control the operation of the first solid-state switch 110 (e.g., HV NMOS FET), and thereby control the charging of the storage capacitor C1 and the generation of the DC voltage V at the output node N2 of the power converter circuit 100. DC The current flow (I Charge ). More specifically, in an exemplary embodiment, the power converter circuit 100 operates in a "power mode" and a "control mode". In the power mode (alternatively, the energy storage refresh mode), the control system 160 activates the first solid-state switch 110 (conductive state or on state) to allow the charging current I Charge flows and charges the storage capacitor C1 to a predetermined maximum value V DC (Expressed as V DC_MAX ). The first solid-state switch 110 is maintained in the on state to reduce the voltage across the storage capacitor C1 to a value lower than the maximum value V DC_MAX allows the charging current to flow and charge the storage capacitor C1. Once the voltage across the storage capacitor C1 reaches V DC_MAX, the control system 160 will deactivate the first solid-state switch 110 (off state or off state). In addition, as explained in further detail below, in the control mode, the control system 160 is configured to pre-charge the gate terminal of the first solid-state switch 110 (at the third node N3) to the turn-on threshold voltage during the negative half cycle of the AC power source 10.

[0026] The power converter circuit 100 is configured to charge the storage capacitor C1 during the positive half cycle of the AC waveform of the AC power source 10 applied to the input terminal 101. The first diode D1 operates as a half-wave rectifier, which rectifies the input AC waveform to produce a half-wave rectified (positive) voltage on the first node N1, so that the charging current I Charge In other words, the power operation mode of the power converter circuit 100 is configured to charge the storage capacitor C1 only during the positive half cycle of the input AC waveform of the AC power source 10 .

[0027] In addition, the power converter circuit 100 is configured to charge the second capacitor C2 during each positive half cycle of the input AC waveform of the AC power source 10 applied to the input terminal 101. Specifically, during a given positive half cycle, the second diode D2 is forward biased by the rectified voltage at the node N1 and allows the voltage at the node N1 to be applied at the node N5 to charge the second capacitor C2 to the peak voltage of the input AC waveform (e.g., 170V), which in turn causes the Zener diode Z1 to be energized at its Zener voltage V Z (e.g., 10V) and clamped. Figure 1 As schematically shown in FIG. 1 , the cathode terminal of the Zener diode Z1 is coupled to the gate terminal G of the first solid-state switch 110 (at node N3), and the anode terminal of the Zener diode Z1 is coupled to the source terminal S of the first solid-state switch 110 (at node N2). In this exemplary configuration, the Zener diode Z1 is used to connect the gate-to-source voltage V GS (Alternatively, turn-on voltage, threshold voltage) clamped to the Zener voltage V Z , that is, during each positive half-cycle of the input AC waveform, the voltage across nodes N3 and N2 is clamped to V Z In essence, it should be noted that the second diode D2, the second capacitor C2, the resistors R1 and R2, and the Zener diode Z1 implement a switch drive circuit system (e.g., a self-biased drive circuit) configured to generate a regulated threshold voltage across nodes N3 and N2 to drive the first solid-state switch 110, wherein the regulated threshold voltage includes the Zener voltage V of the Zener diode Z1.Z .

[0028] At the beginning of the positive half cycle of the input AC waveform of the AC power source 10 (i.e., when transitioning from the negative half cycle to the positive half cycle), the output of the first comparator 140 transitions from the logic “1” level to the logic “0” level because V IN >GND, whereby a logic “0” level is applied to the reset R input of the latch circuit 130. In addition, assuming that at the beginning of the positive half cycle, the voltage V across the storage capacitor C1 is DC At a level less than V DC_MAX level, so that the voltage V at node N6 TRIP Less than the threshold voltage V REF (i.e., V TRIP <V REF ). In this case, the output of the second comparator 150 will be at a logical logic "0" level, causing the set S input of the latch circuit 130 to be at a logical "0" level. In this state, at the beginning of the positive half cycle, the output Q of the latch circuit 130 is in a "reset" state, where the Q output is set to a logical "0" level, which causes the second solid-state switch 120 to be in an off state due to the logical 0 voltage level applied to the gate terminal G of the second solid-state switch 120.

[0029] In this regard, when transitioning to the positive half cycle of the input AC power waveform, if the voltage V across the storage capacitor C1 is DC At a level less than V DC_MAX level, and where V TRIP <V REF , the control system 160 will operate in a power mode in which the second solid-state switch 120 is off and the first solid-state switch 110 is on, thereby allowing the charging current I Charge From the first node N1 to the second node N2 and charges the storage capacitor C1 to V DC_MAX During power mode, when the voltage across the storage capacitor C1 is lower than V DC_MAX When the fixed Zener voltage V Z Maintaining proper V for the first solid-state switch 110 GS , and the first solid-state switch 110 is maintained in saturation mode, V DS >V GS –V T , where V DS and V T denote the drain-to-source voltage and the threshold voltage of the first solid-state switch 110 , respectively.

[0030] At some point in the positive half cycle of the input AC waveform, when the voltage across the storage capacitor C1 reaches VDC_MAX When the voltage V on node N6 TRIP reaches and exceeds the threshold voltage V REF (V TRIP >V REF ). As a result, the output of the second comparator 150 turns to a logic "1" level, so that the logic "1" level is applied to the set S input of the latch circuit 130. In this case where the reset R input of the latch circuit 130 is at a logic "0" level, in response to the logic "1" level output of the second comparator 150 being applied to the set S input of the latch circuit 130, the output Q of the latch circuit 130 turns to a logic "1" level (i.e., the latch circuit 130 is placed in a set state). The output Q of the logic "1" level turns on the second solid-state switch 120 and substantially couples the fourth node N4 to the potential of the ground reference node GND.

[0031] In this regard, activation of the second solid-state switch 120 substantially couples the cathode of the Zener diode Z1 to the ground GND potential, thereby causing the Zener diode Z1 to be electrically disconnected due to the voltage V at the node N2. DC The forward bias of the Zener diode Z1 further causes the V GS drops to the threshold voltage V of the first solid-state switch 110 T Next, the first solid-state switch 110 is deactivated (turned off) (eg, when the Zener diode Z1 is forward biased, V GS is about -0.7V). The deactivation of the first solid-state switch 110 prevents the charging current I Charge From the first node N1 to the second node N2 (eg, I Charge =0), thereby generating a DC voltage V across the storage capacitor C1. DC limited to a predetermined maximum voltage V DC_MAX .

[0032] It should be noted that when the second solid-state switch 120 is activated at some point during the positive half cycle of the input AC waveform so that the fourth node N4 is coupled to the ground GND potential through the second solid-state switch 120, the second capacitor C2 may be slightly discharged from the peak voltage (e.g., 170 V) as the input voltage of the input AC waveform decreases. However, in order to minimize the amount of discharge, the resistance of the first resistor R1 is selected to be relatively high (e.g., in the mega-ohm range) so that the second capacitor C2 retains a large amount of its maximum charge level obtained during the beginning portion of the positive half cycle of the input AC waveform.

[0033] Next, when transitioning from the positive half-cycle to the negative half-cycle of the input AC waveform, the control system 160 executes a control mode cycle at the start of the negative half-cycle of the AC electrical waveform. The control mode is configured to pre-charge the gate voltage (e.g., turn-on threshold voltage) of the first solid-state switch 110 when preparing for the next power mode operation cycle, which starts in the next positive half-cycle, where if needed, the first solid-state switch 110 is re-activated to recharge the storage capacitor C1 to V during the next positive half-cycle DC_MAX .

[0034] Specifically, at the start of the negative half-cycle, since the voltage at node N1 reaches zero, causing V IN < GND, the output of the first comparator 140 transitions from the logic "0" level to the logic "1" level. Thus, upon transitioning to the negative half-cycle, the logic "1" level is applied to the reset R input of the latch circuit 130. Additionally, in the case where the voltage V across the storage capacitor C1 drops below the level of V DC (due to the power drawn by the DC load 20, the storage capacitor C1 discharges slightly at the end of the positive half-cycle), at the start of the negative half-cycle, the voltage V at the sixth node N6 DC_MAX will be below the threshold voltage V TRIP (V REF < V TRIP < V REF ). In such cases, the output of the second comparator 150 will be set to the logic "0" level, which is applied to the set S input of the latch circuit 130. Thus, at the start of the negative half-cycle, with the logic "1" level applied to the reset R input and the logic "0" level applied to the set S input, the latch circuit 130 will transition to the reset state, where the output Q of the latch circuit 130 will transition to the logic "0" level. The reset of the latch circuit 130 (Q = logic "0") de-activates (turns off) the second solid-state switch 120

[0035] When the second solid-state switch 120 is de-activated at the start of the negative half-cycle of the input AC waveform, since the voltage of the second capacitor C2 (at node N5) is greater than the voltage V at node N2 DC , the Zener diode Z1 becomes reverse-biased (and clamped to the Zener voltage V z ). In this regard, at the start of the negative half-cycle of the input AC waveform, the gate-to-source voltage V of the first solid-state switch 110 GS (turn-on voltage, threshold voltage) is pre-charged and clamped to the Zener voltage of the Zener diode Z1 (e.g., 10V). However, during the negative half-cycle of the input AC waveform, the drain-to-source voltage V of the first solid-state switch 110 DSis kept at 0V, thereby keeping the first solid-state switch 110 in the off state (i.e., the charging current I Charge does not flow) until the next positive half cycle of the input AC waveform, when the voltage at node N1 rises to the voltage at node N2 (i.e., the voltage V across the storage capacitor C1). DC ) above, which then makes the charging current I Charge flows and charges the storage capacitor C1 when needed (if necessary).

[0036] It should be noted that the maximum voltage V across the storage capacitor C1 DC_MAX will vary depending on the DC voltage requirement of the DC load 20. The maximum voltage V DC_MAX The adjustment may be based on the requirements of the DC load 20 connected to the output terminal 102 of the power converter circuit 100. For example, the resistor values ​​R4 and R5 may be set to achieve a given V REF Target V TRIP Or based on a given V TRIP Adjust V REF To configure the maximum voltage V DC MAX .

[0037] Figure 2A , 2B 2C and 2D are waveform diagrams showing the operation of an exemplary embodiment according to the present disclosure. Figure 1 Specifically, Figure 2A An exemplary AC power waveform 200 supplied by the AC power source 10 is schematically illustrated, wherein the AC power waveform 200 comprises a sine wave having a positive half cycle and a negative half cycle. The AC power waveform 200 has a positive peak voltage (VP + ), and has a negative peak voltage (VP - ). For example, for a 120V RMS utility power supply, the positive peak voltage VP + is about 170V and the negative peak voltage VP - is about -170 V. An exemplary AC electrical waveform 200 may be a 60 Hz voltage waveform having a period of about 16.66 milliseconds, wherein the duration of each half cycle is about 8.33 milliseconds.

[0038] Figure 2B A current waveform 210 is depicted which represents a charging current I generated during a power mode cycle executed during a positive half cycle of the input AC power waveform 200 to charge the storage capacitor C1. Charge (up to the maximum charging current I Max ).like Figure 2B As shown, the charging current I Chargeflows until the first solid-state switch 110 responds to the voltage across the storage capacitor C1 reaching the maximum DC voltage level (V DC_MAX ) until it is deactivated (e.g., at time t1 and t4). Specifically, at time t1 and t4, the control system 160 determines V TRIP Exceed V REF (V TRIP >V REF ), and in response, the control system 160 deactivates the first solid-state switch 110 to terminate the charging current I Charge flows to the storage capacitor C1 (i.e., I Charge It should be noted that Figure 1 In the exemplary circuit configuration shown, when the V DS When the charging current I Charge begins to flow (for example, when the voltage at node N1 reaches and begins to exceed the voltage V at node N2 DC When the charging current I Charge The voltage becomes relatively constant when the first solid-state switch 110 transitions from the ohmic mode to the saturation mode, as understood by one of ordinary skill in the art.

[0039] Figure 2C An exemplary DC voltage waveform 220 (V DC Waveform), which represents the DC voltage at node N2 (across storage capacitor C1) of power converter circuit 100 during the positive half-cycle and negative half-cycle of input AC power waveform 200. Specifically, Figure 2C An exemplary energy storage cycle of the power converter circuit 100 over two complete cycles of the AC power waveform 200 is shown. Figure 2C In an exemplary embodiment, the maximum DC voltage level V DC MAX 70V is shown (which is an exemplary, non-limiting value). At the beginning of each positive half cycle of the input AC power waveform 200 (e.g., times t0, t3, and t6), the DC voltage waveform 220 begins to increase to V DC_MAX When V DC_MAX , the first solid-state switch 110 is deactivated (e.g., at times t1 and t4), and the DC voltage waveform 220 decreases (discharging through the storage capacitor C1) for the remainder of the positive half-cycle and throughout the subsequent negative half-cycle (assuming that the power converter circuit 100 supplies DC power to a load connected thereto).

[0040] Next, Figure 2D The gate-to-source voltage (V GS ) Waveform 230. Figure 2D As shown, V GS Waveform 230 is clamped to the Zener voltage V of Zener diode Z1. Z (thereby providing a regulation threshold voltage for the first solid-state switch 110), but when the second solid-state switch 120 is activated, it is substantially reduced to 0V (e.g., -0.7V) during the positive half cycle of the input AC power waveform 200 (e.g., t1 and t4), which pulls the gate terminal G of the first solid-state switch 110 to the ground GND potential, thereby causing the Zener diode Z1 to be forward biased, as discussed above.

[0041] like Figure 2D As further shown, at each transition from a positive half-cycle to a negative half-cycle (eg, at time t2 and t5), due to the deactivation of the second solid-state switch 120, the voltage V GS Added to the Zener voltage V of the Zener diode Z1 Z Specifically, as described above, when the second solid-state switch 120 is deactivated at the beginning of the negative half cycle of the input AC power waveform 200, since the voltage of the second capacitor C2 is greater than the voltage V on the node N2, DC , the Zener diode Z1 becomes reverse biased (and clamped to the Zener voltage Vz). Therefore, at the beginning of each negative half-cycle of the input AC power waveform 200, the gate-to-source voltage V GS (threshold voltage) is pre-charged and clamped to the Zener voltage (eg, 10V) of Zener diode Z1.

[0042] like Figure 2D As shown, although the regulation threshold voltage V of the first solid-state switch 110 GS The first solid-state switch 110 is pre-charged to Vz during the time periods from t2 to t3 and t5 to t6, for example, but during the time periods from t2 to t3 and t5 to t6 of the negative half cycle of the AC power waveform 200, the first solid-state switch 110 remains in the off state, so that no charging current flows to charge the storage capacitor C1 (i.e., the storage capacitor C1 is not charged during the negative half cycle of the AC power waveform 200). However, when the negative half cycle transitions to the positive half cycle (e.g., at time t3 and t6), the pre-charged regulation threshold voltage V GS Allowing the first solid-state switch 110 to turn on and allowing the charging current to recharge the storage capacitor C1 to V DC MAX .

[0043] It should be understood that Figure 1 The power converter circuit 100 may be implemented in various applications. For example, Figure 1The power converter circuit 100 can be used to convert AC power into DC power, where the DC power is used to provide or otherwise generate a regulated DC supply voltage to control a DC power supply component, such as a control circuit system. In some embodiments, the power converter circuit 100 is used to generate a DC supply voltage for a control circuit system of an intelligent electrical device, such as an intelligent solid-state circuit breaker, an intelligent solid-state lighting switch device (e.g., an intelligent dimmer switch), an intelligent circuit breaker device, etc. For example, Figure 3 The intelligent electrical device 300 according to an exemplary embodiment of the present disclosure is schematically shown. Figure 1 A power converter circuit 100 is provided.

[0044] The intelligent electrical device 300 includes a first power input terminal 300-1, a second power input terminal 300-2, a first load terminal 300-3, a second load terminal 300-4, a solid-state AC switch 310, and an intelligent switch control system 320. The intelligent switch control system 320 includes various components and circuit systems, such as the power converter circuit 100 ( Figure 1 ), controller 321, AC switch driver circuit system 322, sensor circuit systems 323 and 324, one or more memory devices 325, and DC to DC conversion circuit system 326, the functions of which will be explained in detail below. In some embodiments, the solid-state AC switch 310 includes a bidirectional solid-state switch, which includes, for example, two solid-state switches connected back to back in series, and exemplary embodiments of which will be described below in conjunction with Figure 4 The intelligent switch control system 320 may include a system-on-chip (SoC) device or a system-in-package (SIP) device that integrates various components 321, 322, 323, 324, 326, 327, and 100 (or parts thereof) in a package structure.

[0045] The intelligent electrical device 300 is configured to control AC power supplied from an AC power source 30 (e.g., AC mains) to an AC load 40. The first power input terminal 300-1 and the second power input terminal 300-2 are configured to connect the intelligent electrical device 300 to a line phase (L) 31 and a neutral phase (N) 32 of the AC power source 30. The first load terminal 300-3 and the second load terminal 300-4 are configured to connect the intelligent electrical device 300 to a load hot line 41 and a load neutral line 42 connected to the AC load 40, respectively. The neutral phase (N) 32 of the AC power source 30 is combined with a ground 33 (GND). The ground 33 is usually connected to a ground rod in a circuit breaker panel, where the ground rod is combined with a neutral rod in the circuit breaker panel. A ground connection is made from the ground rod in the circuit breaker panel to a ground terminal (not shown) of the intelligent electrical device 300. In the event that a ground fault condition occurs within the intelligent electrical device 300 or the AC load 40 , the ground 33 provides an alternative low resistance path for the ground fault return current to flow.

[0046] The intelligent electrical device 300 may be any type of intelligent electrical device configured to switchably connect / disconnect AC power to / from a given load. For example, the intelligent electrical device 300 may be an intelligent solid-state circuit breaker, an intelligent solid-state lighting switch device (e.g., an intelligent dimmer switch), an intelligent circuit interrupter device, an intelligent electrical output (e.g., a ground fault circuit interrupter (GFCI) outlet), etc. The intelligent switch control system 320 implements a control circuit system, control logic, and algorithm configured to intelligently control various functions and operations of the intelligent electrical device 300 according to the device type.

[0047] The power converter circuit 100 is configured to generate an output voltage V DC (as mentioned above), combined with Figure 1 and 2A -2D. The power converter circuit 100 is coupled to nodes N10 and N11, whereby an AC power input is applied to the power converter circuit 100. In an exemplary embodiment, the power converter circuit 100 generates an output voltage V DC , the output voltage is grounded with the neutral point N of the AC power source 30 as the reference. Output voltage V DC is applied to the input of the DC to DC conversion circuit system 326. The DC to DC conversion circuit system 326 is configured to convert the voltage V DC The DC-to-DC conversion circuitry 326 is configured to generate a DC voltage for operation of the power converter circuit 100 (e.g., applied to the second comparator 150 ( Figure 1) threshold voltage V REF and the supply rail voltages of the first comparator 140, the second comparator 150, the latch circuit 130, etc.).

[0048] In some embodiments, the DC-to-DC conversion circuit system 326 includes one or more DC-DC step-down switching regulator circuits (eg, step-down switching regulators) configured to convert the voltage V DC In some embodiments, the DC to DC conversion circuit system 326 is configured to convert the voltage V to a plurality of regulated DC rail voltages with different voltage levels according to the DC supply voltage requirements of the control circuit system of the intelligent switch control system 320 and the AC switch driver circuit system 322 as needed. DC Convert to, for example, one or more industry standard DC voltages, including but not limited to 12V, 10V, 5V, 3.3V, 2.5V, 2.7V, 1.8V, etc.

[0049] In some embodiments, the controller 321 is implemented using at least one intelligent programmable hardware processing device, such as a microprocessor, a microcontroller, an ASIC, an FPGA, a CPU, etc., which is configured to execute a software routine to generate a switch control signal (denoted as S_Con), which is applied to the AC switch driver circuit system 322 to intelligently control the operation of the solid-state AC switch 310, thereby performing various functions according to the device type of the intelligent electrical device 300. In some embodiments, one or more memory devices 325 include volatile random access memory (RAM) and non-volatile memory (NVM), such as flash memory, which is used to store calibration data, operating data and executable code to perform various intelligent operations of the intelligent electrical device 300 according to the device type (e.g., intelligent circuit breaker, intelligent dimmer switch, etc.). For example, in some embodiments where the smart electrical device 300 includes a smart light switch with a dimming function, the controller 321 can perform a PWM (pulse width modulation) process to generate a pulse width modulated switch control signal S_Con, thereby modulating the on-time of the solid-state AC switch 310 during the positive half-cycle and the negative half-cycle of the input AC power, thereby modulating the AC power supplied to the AC load 40.

[0050] exist Figure 3 In an exemplary embodiment of the present invention, the AC switch driver circuit system 322 is configured to generate a gate control signal (denoted as G_Con) in response to a switch control signal S_Con from the controller 321, wherein the gate control signal G_Con is applied to the control terminal of the solid-state AC switch 310 to turn on / off the solid-state AC switch 310. Figure 3Not specifically shown, but in a neutral ground referenced design, some form of isolation circuitry and / or components will be implemented to provide AC-DC isolation and properly drive the solid-state AC switch 310 using the gate control signal G_Con generated by the AC switch driver circuitry 322.

[0051] In some embodiments, the sensor circuit system 323 includes a voltage detection and / or current detection circuit system to sense the line voltage and / or line current at the node N10 on the line side of the solid-state AC switch 310. Further, in some embodiments, the sensor circuit system 324 includes a voltage detection circuit system and / or a current detection circuit system to sense the load voltage and / or load current at the node N12 on the load side of the solid-state AC switch 310. The configuration and type of sensors used for the sensor circuit systems 323 and 324 will vary depending on the application. For example, for a light dimming application, the line-side sensor circuit system 323 may include a voltage phase detector to determine the zero crossing of the AC supply voltage waveform at the node N10 and the polarity transition direction of the AC supply voltage waveform at the node N10 (e.g., the AC supply voltage waveform V S The zero crossing detection is processed by the controller 321 to determine and control the timing of the solid state AC switch 310 being activated and deactivated after detecting the zero crossing voltage of the AC supply voltage waveform at the line sense node N10.

[0052] In some embodiments, for smart circuit breaker applications, the load-side sensor circuit system 324 includes a current detection circuit system to sense the magnitude of the load current at the node N12. In this regard, the controller 321 can utilize the sensor circuit system 324 to detect a fault condition, such as an overcurrent, a short circuit, etc., and allow the controller 321 to generate a switch control signal S_Con to deactivate the solid-state AC switch 310 if a fault condition is detected. In some embodiments, the smart electrical device 300 includes a smart solid-state circuit breaker that is implemented using the exemplary circuit breaker architecture and technology disclosed in U.S. Patent No. 11,373,831, which is commonly assigned and fully incorporated herein by reference.

[0053] like Figure 3 As schematically shown in FIG. 1 , the solid-state AC switch 310 is connected between a line-side node N10 and a load-side node N12 in an electrical path between the first power input terminal 300-1 and the first load terminal 300-3. As described above, in some embodiments, the solid-state AC switch 310 includes a bidirectional solid-state switch device including two serially connected solid-state switches having a common node connection. For example, Figure 4Schematically illustrates an embodiment of a solid-state AC switch according to an exemplary embodiment of the present disclosure, which can be used in Figure 3 It is implemented in intelligent electrical devices.

[0054] More specifically, Figure 4 A bidirectional solid-state switch 400 is schematically shown, the bidirectional solid-state switch comprising a first solid-state switch 401 and a second solid-state switch 402, the two solid-state switches being serially connected between a first node N10 and a second node N12, and coupled back-to-back at a node N13. In some embodiments, the bidirectional solid-state switch 400 comprises a bidirectional MOSFET switch, wherein the first solid-state switch 401 and the second solid-state switch 402 comprise power MOSFET devices, such as N-type enhancement MOSFET devices, having respective gate terminals G, drain terminals D, and source terminals S. The drain terminal D of the first solid-state switch 401 is coupled to the line-side node N10, and the drain terminal D of the second solid-state switch 402 is coupled to the load-side node N12. The source terminals S of the first solid-state switch 401 and the second solid-state switch 402 are typically coupled at a common node N13, thereby implementing a common-source bidirectional MOSFET switch configuration. The gate terminals G of the first solid-state switch 401 and the second solid-state switch 402 are typically connected to a node N14 through respective resistors 410 and 411.

[0055] like Figure 4 As further shown, the first solid-state switch 401 and the second solid-state switch 402 include intrinsic body diodes 401-1 and 402-1, respectively, wherein each intrinsic body diode 401-1 and 402-1 represents a PN junction between a P-type substrate body and an N-doped drain region of a corresponding N-type MOSFET device. It should be noted that the intrinsic body-to-source diodes of the first solid-state switch 401 and the second solid-state switch 402 are not shown because such intrinsic body-to-source diodes are assumed to be short-circuited by a common connection between the source terminal S and the body terminal (e.g., the N+ source region and the P-doped body junction are short-circuited by the source metallization).

[0056] Although Figure 4An exemplary embodiment in which the bidirectional solid-state switch 400 includes two MOSFET devices (e.g., a first solid-state switch 401 and a second solid-state switch 402) is shown, but in some embodiments, each of the first solid-state switch 401 and the second solid-state switch 402 can be implemented using two or more MOSFET devices connected in parallel. This configuration enables enhanced heat dissipation and power handling. In addition, in some embodiments, the bidirectional solid-state switch 400 can be implemented using other types of solid-state switch devices. For example, in some embodiments, the first solid-state switch 401 and the second solid-state switch 402 are implemented using integrated gate bipolar transistor (IGBT) devices, and the emitter terminals of the devices are typically connected at a common node N13. In other embodiments, the first solid-state switch 401 and the second solid-state switch 402 can be implemented using other types of FET devices, including but not limited to GaN (gallium nitride) FET devices, cascaded GaN FET devices, silicon carbide (SiC) junction FET devices, cascaded SiC junction FET devices, etc.

[0057] In all embodiments, the bidirectional solid-state switch 400 is configured to: (i) allow AC current to flow bidirectionally in the electrical path between nodes N10 and N12 when the bidirectional solid-state switch 400 is in the on state, and (ii) interrupt the bidirectional flow of AC current in the electrical path between nodes N10 and N12 when the bidirectional solid-state switch 400 is in the off state. As described above, the bidirectional solid-state switch 400 can be turned on and off by applying appropriate gate control signals G_Con to the gate terminals G of the first solid-state switch 401 and the second solid-state switch 402, which are generally coupled to the node N14.

[0058] The description of the various embodiments of the present disclosure is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable those of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A power converter circuit, comprising: a first solid-state switch connected between the first node and the second node; a first capacitor coupled between the second node and a ground reference node; as well as a control system configured to control operation of the first solid-state switch, wherein the control system is configured to: monitoring a voltage level across the first capacitor, and (i) in response to determining that the voltage level across the first capacitor is less than a maximum direct current (DC) voltage level, applying an alternating current (AC) voltage to the first node; (i) switching on the first solid-state switch during a positive half-cycle of the AC power waveform to allow a charging current to flow from the first node to the second node and charge the first capacitor, and (ii) switching off the first solid-state switch during the positive half-cycle of the AC power waveform in response to determining that the voltage level across the first capacitor has reached the maximum DC voltage level; as well as A regulation threshold voltage is generated for the first solid-state switch during a negative half-cycle of the AC power waveform while maintaining the first solid-state switch in an off state during the negative half-cycle.

2. The power converter circuit of claim 1, wherein the first solid-state switch comprises a high voltage metal oxide semiconductor field effect transistor (MOSFET) device.

3. The power converter circuit of claim 1 , further comprising a first diode having a cathode terminal coupled to the first node and an anode terminal coupled to an input terminal of the power converter circuit, wherein the first diode is configured to rectify the AC electrical waveform applied to the input terminal and generate a half-wave rectified voltage at the first node.

4. The power converter circuit of claim 1 , wherein: The control system includes switch drive circuitry configured to generate the regulated threshold voltage for the first solid-state switch; the switch drive circuitry comprising a Zener diode including an anode terminal coupled to the second node and a cathode terminal coupled to a third node; and The switch drive circuitry is configured to reverse bias the Zener diode during the positive half cycle of the AC power waveform so that a Zener voltage is generated across the third node and the second node; and The Zener voltage comprises the regulation threshold voltage of the first solid-state switch.

5. The power converter circuit of claim 4 , wherein the switch drive circuitry further comprises: a first resistor coupled to and located between the third node and the fourth node; a second resistor coupled to and located between the fourth node and the fifth node; a second capacitor coupled to and between the fifth node and the ground reference node; as well as A second diode includes an anode terminal coupled to the first node and a cathode terminal coupled to the fifth node.

6. The power converter circuit according to claim 5, wherein: the second diode being configured to be forward biased during the positive half cycle and to couple the first node to the fifth node to charge the second capacitor to a peak voltage level of the AC electrical waveform at the first node; and The Zener diode is reverse biased by a potential difference between the fifth node and the second node.

7. The power converter circuit of claim 4, wherein the control system comprises: a second solid-state switch comprising a first terminal coupled to the third node, a second terminal coupled to the ground reference node, and a control terminal; as well as control circuitry configured to apply a control signal to the control terminal of the second solid-state switch to activate the second solid-state switch in response to determining that the voltage level across the first capacitor has reached the maximum DC voltage level; wherein said activation of said second solid-state switch couples said cathode terminal of said Zener diode to said ground reference node and thereby forward biases said Zener diode; and The forward biased Zener diode deactivates the first solid-state switch and terminates the flow of charging current from the first node to the second node during the positive half cycle of the AC power waveform.

8. The power converter circuit of claim 7, wherein the control circuitry is configured to maintain the second solid-state switch in an off state throughout each negative half-cycle of the AC power waveform.

9. The power converter circuit of claim 1, wherein the control system is configured to maintain the first solid-state switch in an off state throughout each negative half-cycle of the AC power waveform.

10. The power converter circuit of claim 1, wherein the control system comprises: a second solid-state switch comprising a first terminal coupled to a control terminal of the first solid-state switch, a second terminal coupled to the ground reference node, and a control terminal; a resistor divider circuit coupled to and between the second node and the ground reference node and configured to generate a trip voltage proportional to a voltage level across the first capacitor; a first comparator configured to compare the trip voltage with a first threshold voltage and generate a first comparator output signal based on a comparison result of the trip voltage with the first threshold voltage; a second comparator configured to compare an input voltage on the first node with a ground reference node voltage and generate a second comparator output signal based on a comparison result of the input voltage and the ground reference node voltage; a latch circuit comprising a first input port configured to receive the first comparator output signal, a second input port configured to receive the second comparator output signal, and an output port coupled to the control terminal of the second solid-state switch; wherein the latch circuit is configured to output a control signal to control activation and deactivation of the second solid-state switch based on logic levels of the first comparator output signal and the second comparator output signal; wherein activation of the second solid-state switch causes the first solid-state switch to turn off; and Wherein deactivation of the second solid-state switch allows the first solid-state switch to turn on during a positive half-cycle of the AC power waveform.

11. The power converter circuit of claim 10, wherein the latch circuit comprises a set-reset flip-flop circuit.

12. An electrical device comprising: a solid-state alternating current (AC) switch coupled between power input terminals and load output terminals of the electrical device; a switch control system configured to control operation of the solid-state AC switch; as well as a power converter circuit configured to convert AC power applied to the power input terminal of the electrical device into direct current (DC) power for operating the switch control system of the electrical device; The power converter circuit comprises: a first solid-state switch connected between the first node and the second node; a first capacitor coupled between the second node and a ground reference node; as well as a control system configured to control operation of the first solid-state switch, wherein the control system is configured to: monitoring a voltage level across the first capacitor and (i) in response to determining that the voltage level across the first capacitor is less than a maximum DC voltage level, turning on the first solid-state switch during a positive half cycle of an AC power waveform coupled to the first node and causing a charging current to flow from the first node to the second node to charge the first capacitor, and (ii) in response to determining that the voltage level across the first capacitor has reached the maximum DC voltage level, turning off the first solid-state switch during the positive half cycle of the AC power waveform; as well as A regulation threshold voltage is generated for the first solid-state switch during a negative half-cycle of the AC power waveform while maintaining the first solid-state switch in an off state during the negative half-cycle.

13. The electrical device of claim 12, wherein the power converter circuit comprises a first diode having a cathode terminal coupled to the first node and an anode terminal coupled to the power input terminal of the electrical device, wherein the first diode is configured to rectify the AC electrical waveform applied to the power input terminal and generate a half-wave rectified voltage at the first node.

14. The electrical device of claim 12, wherein: The control system of the power converter circuit includes switch drive circuitry configured to generate the regulation threshold voltage for the first solid-state switch; the switch drive circuitry comprising a Zener diode including an anode terminal coupled to the second node and a cathode terminal coupled to a third node; and The switch drive circuitry is configured to reverse bias the Zener diode during the positive half cycle of the AC power waveform so that a Zener voltage is generated across the third node and the second node; and The Zener voltage comprises the regulation threshold voltage of the first solid-state switch.

15. The electrical device of claim 14, wherein the switch drive circuit system further comprises: a first resistor coupled to and located between the third node and the fourth node; a second resistor coupled to and located between the fourth node and the fifth node; a second capacitor coupled to and between the fifth node and the ground reference node; as well as a second diode including an anode terminal coupled to the first node and a cathode terminal coupled to the fifth node; wherein the second diode is configured to be forward biased during the positive half cycle and couple the first node to the fifth node to charge the second capacitor to a peak voltage level of the AC electrical waveform at the first node; and The Zener diode is reverse biased due to a potential difference between the fifth node and the second node.

16. The electrical device of claim 14, wherein the control system of the power converter circuit comprises: a second solid-state switch comprising a first terminal coupled to the third node, a second terminal coupled to the ground reference node, and a control terminal; as well as control circuitry configured to apply a control signal to the control terminal of the second solid-state switch to activate the second solid-state switch in response to determining that the voltage level across the first capacitor has reached the maximum DC voltage level; wherein said activation of said second solid-state switch couples said cathode terminal of said Zener diode to said ground reference node and thereby forward biases said Zener diode; and The forward biased Zener diode deactivates the first solid-state switch and terminates the flow of charging current from the first node to the second node during the positive half cycle of the AC power waveform.

17. The electrical device of claim 12, wherein the electrical device is an intelligent solid-state circuit breaker.

18. The electrical device of claim 12, wherein the electrical device is a smart solid-state dimmer switch.

19. A method comprising: Controlling a first solid-state switch coupled to and between a first node and a second node to charge a first capacitor coupled to and between the second node and a ground reference node using a current drawn during a positive half cycle of an alternating current (AC) electrical waveform present at the first node to generate a direct current (DC) voltage at the second node, wherein controlling the first solid-state switch comprises: monitoring a voltage level across the first capacitor; in response to determining that the voltage level across the first capacitor is less than a maximum DC voltage level, turning on the first solid-state switch during the positive half cycle of the AC power waveform to cause a charging current to flow from the first node to the second node and charge the first capacitor; in response to determining that the voltage level across the first capacitor has reached the maximum DC voltage level, turning off the first solid-state switch during the positive half-cycle of the AC power waveform; as well as A regulation threshold voltage is generated for the first solid-state switch during a negative half-cycle of the AC power waveform while maintaining the first solid-state switch in an off state during the negative half-cycle.

20. The method of claim 19, wherein: the regulated threshold voltage comprises a Zener voltage of a Zener diode comprising a cathode terminal coupled to a gate terminal of the first solid-state switch and an anode terminal coupled to a source terminal of the first solid-state switch; Turning off the first solid-state switch includes activating a second solid-state switch so that the Zener diode is placed in a forward biased state, thereby turning off the first solid-state switch and terminating the flow of charging current from the first node to the second node during the positive half cycle of the AC power waveform; and Turning on the first solid-state switch includes deactivating the second solid-state switch so that the Zener diode is placed in a reverse biased state, thereby driving the first solid-state switch using a Zener voltage of the reverse biased Zener diode.

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