Phase mixer non-linear compensation in clock and data recovery circuits

Abstract

A system and method of compensating for phase mixer circuit nonlinearity within a clock and data recovery (CDR) system during active operation. The CDR system includes a compensation circuit and a phase accumulation circuit. The compensation circuit generates a first compensation signal based on the first compensation value. The phase accumulation circuit receives a first compensation signal and a phase accumulator input update signal. A phase accumulation circuit combines a first compensation signal with a phase accumulator input update signal to compensate for a first non-linearity within a phase mixer (PMI) circuit.

Description

Technical Field

[0001] The present disclosure relates to phase mixer circuits of clock and data recovery circuits, and more particularly to a system and method for mitigating differential nonlinearity of a phase mixer circuit during operation. Background Art

[0002] The communication system includes a transmitter circuit and a receiver circuit. The receiver circuit is communicatively connected to the transmitter circuit. The transmitter circuit and the receiver circuit each include a clock generation circuit (e.g., a phase-locked loop (PLL) circuit or other clock generation circuit), which generates a transmitter clock signal and a receiver clock signal, respectively. In addition, the receiver circuit receives a data signal transmitted by the transmitter circuit. Since there may be a difference between the receiver clock signal and the transmitter clock signal, there may be errors in the data signal received by the receiver circuit. In order to mitigate the errors in the received data signal, the receiver circuit includes a clock and data recovery (CDR) circuit, which mitigates the phase difference and frequency difference between the clock signal of the receiver circuit and the clock signal of the transmitter circuit. Summary of the invention

[0003] In one example, a clock and data recovery (CDR) system includes a compensation circuit and a phase accumulation circuit. The compensation circuit generates a first compensation signal based on a first compensation value. The phase accumulation circuit receives the first compensation signal and a phase accumulator input update signal. The phase accumulation circuit combines the first compensation signal with the phase accumulator input update signal to compensate for a first nonlinearity in a phase mixer (PMIX) circuit.

[0004] In one example, a method includes receiving a first compensation value and generating a first compensation signal based on the first compensation value. In addition, the method includes compensating for a first nonlinearity within a PMIX circuit based on the first compensation signal and a phase accumulator input update signal. The method also includes generating a clock signal by the PMIX circuit based on the compensated signal.

[0005] In one example, a non-transitory computer readable medium includes a storage instruction. The instruction, when executed by a processor, causes the processor to provide a compensation circuit for a CDR circuit. The compensation circuit includes an input node for receiving a first compensation value. The compensation circuit also includes a summing element that subtracts a delayed version of the first compensation value from the compensation value to generate a first nonlinear value. The compensation circuit generates a first compensation signal based on the first nonlinear value. The processor also provides a phase accumulation circuit for the CDR circuit. The phase accumulation circuit compensates for a first nonlinearity within the PMIX circuit based on the first compensation signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood through the detailed description given below and the accompanying drawings of the embodiments of the present disclosure. These drawings are used to provide knowledge and understanding of the embodiments of the present disclosure without limiting the scope of the present disclosure to these specific embodiments. In addition, these drawings are not necessarily drawn to scale.

[0007] Figure 1 A block diagram of a communication system according to one or more examples is illustrated.

[0008] Figure 2 A schematic block diagram of a clock and data recovery system for a receiver circuit according to one or more examples is illustrated.

[0009] Figure 3 Illustrated is a graph of a magnitude transfer function of phase error and output phase of a clock and data recovery (CDR) relative to a CDR input phase, according to one or more examples.

[0010] Figure 4 A graph of a CDR circuit phase error magnitude transfer function associated with a delay of a clock and data recovery system is illustrated according to one or more examples.

[0011] Figure 5 Graphs of integral nonlinearity values ​​and associated phase mixer codes are illustrated according to one or more examples.

[0012] Figure 6 The overall nonlinearity of a clock and data recovery circuit is illustrated before and after nonlinearity mitigation according to one or more examples.

[0013] Figure 7 Methods of compensating for nonlinearities within a receiver circuit according to one or more examples are illustrated. DETAILED DESCRIPTION

[0014] Aspects of the present disclosure are directed to systems and methods for providing phase mixer nonlinearity compensation within clock and data recovery circuits.

[0015] The communication system includes a transmitter circuit and a receiver circuit. The receiver circuit receives a data signal from the transmitter circuit. However, since the receiver circuit is separate from the transmitter circuit, the clock signal of the receiver circuit may be different from the clock signal of the transmitter circuit. For example, the phase and frequency of the clock signal of the receiver circuit are different from the phase and frequency of the clock signal of the transmitter circuit. The difference in the phase and / or frequency of the clock signal may cause errors in the received data signal. For example, when the transmitter circuit transmits the data signal based on the clock signal of the transmitter circuit, the rising edge of the data signal is associated with the rising edge of the clock signal of the transmitter circuit. Since the clock signal of the receiver circuit is different from (e.g., has a different phase / frequency) the clock signal of the transmitter circuit, errors may be introduced into the received data signal.

[0016] In one or more examples, the receiver circuit includes a clock and data recovery (CDR) circuit to align a rising edge of a clock signal of the receiver circuit with a rising edge of a data signal. However, due to a phase mixer (PMIX) circuit within the CDR circuit and / or due to a delay of the CDR circuit, the CDR circuit may experience differential non-linearity (DNL).

[0017] A CDR that suffers from DNL or delay cannot fully phase-align the rising edge of the clock signal of the receiver circuit with the rising edge of the data signal, and generates a phase error in the received clock signal. In the following, compensation for nonlinearity and delay of the CDR circuit is described to improve the performance of the corresponding receiver circuit and mitigate errors in the received data signal. The technical advantages of the present disclosure include, but are not limited to, compensating for the nonlinearity of the CDR circuit by a phase mixer (PMIX) code based on a PMIX circuit of the CDR circuit. Compensating for the nonlinearity within the CDR circuit improves the performance of the CDR circuit and improves the alignment of the transmitter circuit clock signal and the receiver circuit clock signal. Therefore, errors in the data signal received by the receiver circuit are compensated.

[0018] Figure 1 A communication system 100 according to one or more examples is illustrated. The communication system 100 includes a transmitter circuit 110 and a receiver circuit 120 that are communicatively connected to each other via a channel 130. In one example, the communication system 100 is a serial communication system. In addition, in one or more examples, the transmitter circuit 110 and the receiver circuit 120 are each part of a serializer deserializer (SerDes). The communication system 100 is included in one or more integrated circuit (IC) devices. For example, the transmitter circuit 110 is included in a first IC device, and the receiver circuit 120 is included in a second IC device.

[0019] The transmitter circuit 110 drives (e.g., transmits) a data signal 132 to the receiver circuit 120 via the channel 130. In one example, the data signal 132 is a serial data signal. The data signal 132 includes one or more symbols. The transmitter circuit 110 converts each symbol into a voltage, which is driven onto the channel 130 and received by the receiver circuit 120. The transmitter circuit 110 uses one or more modulation schemes (e.g., a binary non-return-to-zero modulation scheme or a multi-level digital baseband modulation scheme, etc.). In addition, the transmitter circuit 110 drives the data signal 132 based on a transmitter clock signal. The transmitter clock signal can be generated locally within the transmitter by a clock generation circuit (e.g., a phase-locked loop (PLL) circuit).

[0020] The receiver circuit 120 receives the data signal 132 from the transmitter circuit 110 via the channel 130. In one or more examples, the receiver circuit 120 includes a CDR circuit 122 that generates a clock signal based on the transmitter rate of the data signal 132, and thus generates a clock signal for the transmitter circuit 110. In one example, the frequency and / or phase of the clock signal are adjusted to align with the frequency and / or phase of the reference clock signal. In one or more examples, the CDR circuit 122 adjusts the phase of the clock signal to position the clock signal at a middle position in time of each pulse of the data signal 132 transmitted via the channel 130. In one example, the CDR circuit 122 is part of an equalization circuit that mitigates inter-symbol interference (ISI) via an equalization process. The equalization process includes restoring frequency-dependent amplitude distortion that occurs within the data signal transmitted by the transmitter circuit 110 via the channel 130.

[0021] Receiver circuit 120 also includes signal processing circuit 124 that decodes and processes data signal 132 based on the clock signal generated by CDR circuit 122 .

[0022] In one or more examples, the CDR circuit 122 includes a phase-locked loop (PLL) circuit followed by a mixer (PMIX) circuit 123. In such examples, the CDR circuit 122 generates a clock signal whose frequency is a scalar version of a reference frequency applied to the PLL circuit. In one or more examples, the frequency of the clock signal may not match the frequency of the data signal 132 because there is a delta frequency between the frequency of the PLL circuit of the transmitter circuit 110 and the frequency of the PLL circuit of the receiver circuit 120. The delta frequency can be measured in parts per million (PPM). The CDR circuit 122 compensates for PPM through the use of the PMIX circuit 123. In one or more examples, the rising edge of the clock signal of the receiver circuit 120 provided by the PLL circuit of the receiver circuit 120 is not aligned with the rising edge of the clock signal of the transmitter circuit 110. In one or more examples, the PMIX circuit 123 is used to align the rising edge of the clock signal of the receiver circuit 120 with the rising edge of the clock signal of the transmitter circuit 110, thereby mitigating the PPM between the clock signal of the transmitter circuit and the clock signal of the receiver circuit.

[0023] In one or more examples, the PMIX circuit of the CDR circuit 122 synthesizes multiple clock edges of the corresponding PLL clock signal, and selects the edge of the clock signal that is aligned with the rising edge of the data signal 132 through the use of a feedback mechanism. In one example, for a fixed frequency PPM, if the PMIX circuit 123 generates M phases within 360 degrees of a scaled version of the PLL clock signal period, the PMIX circuit 123 moves from one phase to the next phase within a certain period of time to ensure that the clock signal of the receiver circuit 120 is aligned with the continuous rising edges of the clock signal of the transmitter circuit 110. In one or more examples, the phase change of the clock signal of the receiver circuit 120 per unit time represents the effective frequency of the clock signal at the output of the PMIX circuit 123. Specifically, as shown in Equation 1, if there is a fixed frequency (f) PPM between the clock domain of the transmitter circuit 110 and the clock domain of the receiver circuit 120, the phase (φ) of the clock signal of the receiver circuit relative to the change of time (t) is constant.

[0024]

[0025] Therefore, to mitigate PPM between the receiver circuit clock signal and the transmitter circuit clock signal, the phase of the PMIX circuit advances by equal phase amounts over time, and the phase of the PMIX circuit is linearly spaced within 360 degrees.

[0026] In one or more examples, the performance of the PMIX circuit 123 is negatively affected by process and temperature (PVT) variations and mismatches due to circuit manufacturing and circuit operating conditions. Therefore, the PMIX circuit 123 may not generate a linearly spaced clock signal. In addition, the clock signal generated by the PMIX circuit 123 may be negatively affected by amplitude-dependent phase changes within the PMIX circuit 123. For example, the PMIX circuit 123 generates M phases (where M is equal to or greater than 1) within 360 degrees of a scaled version of the clock signal of the receiver circuit 120. However, these phases have DNL or unequal phase steps. The CDR circuit 122 mitigates at least a portion of the DNL by the use of feedback. However, due to the delay and / or limited loop bandwidth of the CDR circuit 122, not all DNL can be eliminated. For example, if the change occurs at a rate exceeding the bandwidth of the CDR circuit 122, the CDR circuit 122 may not track these changes. Therefore, a sampling phase error (or deterministic jitter) may occur within the receiver circuit 120, thereby degrading the symbol detection performance of the receiver circuit 120 and introducing errors in the received data signal 132. In addition, the sampling phase error repeats with a period that depends on the number of phases in the PMIX circuit 123 and the frequency PPM difference between the transmitter circuit 110 and the receiver circuit 120. The period of the sampling phase error results in a spectral tone in the phase error power spectral density.

[0027] The DNL within the PMIX circuit 123 negatively impacts the performance of the receiver circuit 120. Therefore, compensating for the DNL may improve the performance of the receiver circuit 120. As described in more detail below, the DNL of the PMIX circuit 123 may be compensated during operation of the CDR circuit 122, thereby improving the performance of the receiver circuit 120 and mitigating errors in the received data signal 132.

[0028] Figure 2 A CDR system 200 according to one or more examples is illustrated. The CDR system includes a CDR circuit 201 and a memory 280. The CDR circuit 201 includes a phase detector 210, a phase update gain 220, a frequency accumulator 230, a phase accumulator circuit 240, a PMIX circuit 250, and a compensation circuit 260.

[0029] In one or more examples, CDR circuit 201 receives input signal 202. Input signal 202 may be Figure 1The phase detector 210 receives the input signal 202 and the clock signal 204 and generates an error signal 206 (e.g., a phase error signal). The clock signal 204 is used as a feedback signal. The error signal 206 corresponds to the phase difference between the input signal 202 and the clock signal 204. In one example, the phase detector 210 includes a subtractor 212 that subtracts the clock signal 204 from the input signal 202. The error signal 206 is amplified by an amplifier 214 and then delayed by a delay element 216 to generate a delayed error signal 215. The delay of the delay element 216 is d. The amplifier 214 represents the gain Kp of the phase detector 210.

[0030] In one or more examples, the clock signal 204 has an output phase φ out The output phase φ of the clock signal 204 is out Tracking the phase of the input signal 202 and the phase error φ of the signal 206 err In one example, the phase error φ of signal 206 is err Decrease to zero.

[0031] The delayed error signal 215 is amplified by the amplifier 222 of the phase update gain 220 to generate a signal 223. The amplifier 222 can be represented by a parameter phug, such as the gain of the phase update gain 220. In one or more examples, the phase update gain 220 is referred to as a CDR proportional path (e.g., a phase path). The delayed error signal 215 is received by an amplifier 232, which generates a signal 233. The amplifier 232 is a CDR frequency update gain and can be represented by a parameter frug. The frequency accumulator 230 can be referred to as an integration path (e.g., a frequency path). The signal 233 is added by the summing element 234 of the frequency accumulator 230 with the delayed signal 237 to generate a signal 235, which is delayed by the delay unit 236 of the frequency accumulator 230 to generate a delayed signal 237. The delay of the delay unit 236 is 1 update cycle. Adding the signal 233 to the delayed signal 237 can add the previous value of the signal 235 to the signal 233. Thus, the frequency accumulator 230 functions as a counter. Signal 235 is amplified by amplifier 238 to generate signal 239. Amplifier 238 represents the average (Kint) of the frequency accumulator 230. Amplifiers 232 and 238 function as pre-gain and post-gain of the frequency accumulator 230.

[0032] Summing element 224 adds signal 223 and signal 239 to generate phase accumulator input update signal 225. In one example, phase update gain 220 and frequency accumulator 230 form a loop filter that filters out noise and irrelevant frequency components within delay error signal 215.

[0033] The phase accumulator input update signal 225 is received by the summing element 242 of the phase accumulator circuit 240. The summing element 242 combines the phase accumulator input update signal 225, the delayed signal 245, and the compensation signal 269 to generate a signal 243. By adding the phase accumulator input update signal 225 to the delayed signal 245, the phase accumulator circuit 240 is used as a counter. In one example, the summing element 242 subtracts the delayed signal 245 and the compensation signal 269 from the phase accumulator input update signal 225 to generate a signal 243. The signal 243 is delayed by the delay element 244 of the phase accumulator circuit 240 to generate the delayed signal 245. The delay of the delay element 244 is 1 update cycle. The signal 243 is amplified by the amplifier 246 to generate the signal 247. The amplifier 246 represents the average Kv of the phase accumulator 240.

[0034] Signal 247 is received by PMIX circuit 250. PMIX circuit 250 shifts the corresponding phase by X degrees based on signal 247. X can be in the range of about 0 degrees to about 360 degrees. In one example, the phase of PMIX circuit 250 is shifted by one or more phase steps. Each phase step corresponds to a phase shift of one or more degrees. Each phase step can correspond to a phase shift of the same size. In another example, at least two phase steps correspond to phase shifts of different sizes.

[0035] In one example, PMIX circuit 250 is controlled by 256 PMIX codes. Each of the 256 PMIX codes corresponds to a different phase shift. In one or more examples, PMIX circuit 250 is controlled by more or less than 256 PMIX codes.

[0036] The phase of PMIX circuit 250 is shifted based on signal 247 to generate signal 251. Signal 251 is received by amplifier 252. Signal 251 includes the nonlinearity (INL damage q imp ).

[0037] Signal 251 is amplified by amplifier 252 to generate clock signal 204. Amplifier 252 represents the code versus phase gain (eg, parameter β) response of PMIX circuit 250. In one example, signal 251 may be referred to as a corrupted signal.

[0038] In one or more examples, clock signal 204 is received by a receiver circuit (e.g., Figure 1 The receiver circuit 120 is used to receive the data signal (e.g., Figure 1The rising edge of the data signal 132 of Table 1 is used to shift the phase of the clock signal of the receiver circuit so that it is aligned with the phase of the transmitter clock signal (eg, the clock signal of the transmitter circuit 110 of Table 1).

[0039] Equations 2 and 3 are discrete transfer functions that are expressed with respect to the input signal (φ in ) 202 describes the phase of the clock signal 204 of the CDR circuit 201 (eg, the output phase φ out ) and output phase error φ err .

[0040]

[0041]

[0042] Figure 3 Graph 300 is shown plotting output phase (line 310) and output phase error (line 320) as a function of frequency. Graph 300 illustrates that output phase (line 310) is Figure 2 The phase error (line 320) is a low-pass version of the phase of the input signal 202 (eg, the input phase). In addition, the graph 300 illustrates that the phase error (line 320) is Figure 2 =A high-pass function of the phase of the clock signal 204. Therefore, low frequency variations in the input signal 202 are tracked by the CDR circuit. However, high frequency variations in the input signal 202 are not tracked by the CDR circuit and remain as a residual output phase error.

[0043] In one or more examples, CDR circuit 201 cycles PMIX circuit 250 through each PMIX code and corresponding DNL in the PMIX code to compensate for the frequency PPM deviation between the transmitter circuit clock domain (e.g., the clock domain of transmitter circuit 110) and the receiver circuit clock domain (e.g., the clock domain of receiver circuit 120). In one example, in the presence of frequency offset, phase accumulator 240 increments in equal steps to accumulate the phase of clock signal 204. In one example, here, PMIX circuit 250 has a non-zero DNL, ​​and the DNL is accumulated, resulting in a residual INL at the output of PMIX circuit 250 (e.g., within signal 251). In one example, the impairment value q imp Model the INL and compensate for the value q cmp Used to compensate for INL.

[0044] In one example, each element of the CDR circuit 201 is updated once (eg, performs a corresponding function) at each cycle of the update clock signal of the CDR circuit 201. In one example, at each cycle of the clock signal of the CDR circuit 201, a new compensation value q cmpReceived at input node 261 .

[0045] Equation 4 is a loop equation illustrating an output phase error with an additional error term depending on the INL of the PMIX circuit 250. The additional error term has a high-pass shape, which can mitigate low-frequency components of the INL error profile. However, high-frequency components of the INL error profile are not compensated, resulting in a residual phase error, which degrades the performance of a corresponding receiver circuit (e.g., receiver circuit 120).

[0046]

[0047] In addition, in one or more examples where the cycles of the PMIX code occur at a rate within the bandwidth of the CDR circuit 201, the CDR circuit 201 compensates for the DNL within the CDR circuit 201. However, the compensation for the DNL is limited by the delay and bandwidth of the CDR circuit 201. The limited bandwidth and delay may result in residual uncompensated phase errors (e.g., DNL) that accumulate over time in the PMIX code space. The accumulation of DNL is the integral nonlinearity (INL) of the CDR circuit 201 and / or the PMIX circuit 250 in the PMIX code space. The accumulation of DNL generates excessive phase errors in the CDR circuit 201, thereby reducing the performance of the CDR circuit 201. In one or more examples, the compensation circuit 260 compensates for the accumulation of DNL, ​​thereby improving the performance of the CDR circuit 201.

[0048] The compensation circuit 260 receives the compensation value q from the memory 280 cmp , and generates a compensation signal 269 to compensate for the effect of the accumulated DNL (INL). Equation 5 is when the compensation value q cmp = Damage value q imp 2 is a loop equation of the CDR circuit 201 including the compensation circuit 260.

[0049]

[0050] As shown in Equation 5, compensation circuit 260 compensates for the effect of INL within CDR circuit 201 by creating a high-pass function with a higher bandwidth.

[0051] In one or more examples, the compensation circuit 260 receives the compensation value q associated with the PMIX code used by the PMIX circuit 250 from the memory 280. cmp Memory 280 receives an indication of the PMIX code used by PMIX circuit 250 from CDR circuit 201 and provides a corresponding compensation value q to compensation circuit 260. cmpIn one example, the compensation circuit 260 selects and retrieves the compensation value q associated with the PMIX code applied to the PMIX circuit 250 from the memory 280. cmp For example, compensation circuit 260 receives an indication of a PMIX code generated by PMIX circuit 250 and retrieves the associated compensation value q from LUT 282 of memory 280. cmp .

[0052] The compensation circuit 260 includes an input node 261, a delay element 262, a summing element 264, an amplifier 266, and a delay element 268. The delay of the delay element 262 is 1 update cycle. The input node 261 receives the compensation value q from the memory 280. cmp . Compensation value q cmp The delay element 262 receives and delays the delayed signal 263. The delay element 262 converts the compensation value q cmp The delay corresponds to one cycle of the clock signal. The clock signal may be the CDR circuit 201 clock signal, the clock signal of the corresponding receiver circuit (eg, the receiver circuit 120), or the PMIX update clock signal. The summing element 264 receives the compensation value q cmp and the delayed signal 263, and from the compensation value q cmp The delayed signal 263 is subtracted from the compensation value q to generate a signal 265. The signal 265 may be referred to as a nonlinear signal. cmp The delayed signal 263 is subtracted from the input signal 264 to perform a derivative function based on the compensation value q as the INL of the PMIX circuit 250. cmp A signal 265 is generated as the DNL of the PMIX circuit 250. The signal 265 is amplified by an amplifier 266 to generate an amplified signal 267.

[0053] The delay element 268 delays the amplified signal 267 by one or more cycles of the corresponding clock signal, thereby generating the compensation signal 269. In one example, the delay element 268 delays the amplified signal by "m" cycles of the PMIX update clock period signal, where "m" is equal to or greater than 1.

[0054] In one or more examples, as the delay of the CDR circuit 201 increases (eg, “m” increases), the amount of INL that is compensated decreases. Figure 4Graph 400 of phase error transfer functions for different delay values ​​(e.g., "m" values) is illustrated. For example, line 410 illustrates a phase error transfer function with no compensation applied. Line 420 illustrates a phase error transfer function for a delay of one clock cycle (e.g., "m" is 1). Line 430 illustrates a phase error transfer function for a delay of two clock cycles (e.g., "m" is 2). Line 440 illustrates a phase error transfer function for a delay of three clock cycles (e.g., "m" is 3). Line 450 illustrates a phase error transfer function for a delay of four clock cycles (e.g., "m" is 4). Line 460 illustrates a phase error transfer function for a delay of five clock cycles (e.g., "m" is 5).

[0055] In one or more examples, the compensation value q stored in the memory 280 cmp The compensation value q is determined during startup of the CDR circuit 201 by an evaluation circuit within the CDR circuit 201 or by an external processing system connected to the CDR circuit 201. The clock signal 204 is measured for each PMIX code to determine the compensation value q for each PMIX code. cmp . Compensation value q cmp The nonlinearity of the PMIX circuit 250 can be determined by counting the occurrences of each PMIX code in the corresponding time period. A histogram is determined based on the count values ​​associated with each PMIX code to determine the nonlinearity of the PMIX circuit 250. In other examples, the nonlinearity of the PMIX circuit 250 can be measured by comparing the output phase of the PMIX circuit 250 with the expected input phase of the input signal 202.

[0056] Compensation value q cmp corresponds to a measure of the integral nonlinearity (INL) within the PMIX circuit 250. The compensation value q cmp The deviation between the expected output of the PMIX circuit 250 and the measured output of the PMIX circuit 250 is indicated for each PMIX code. cmp is stored in the memory 280. In one example, the compensation value q cmp is stored in a lookup table (LUT) 282 of the memory 280. The LUT 282 stores each compensation value q cmp and PMIX codes. In one example, the PMIX code includes 256 PMIX codes. In such an example, the LUT 282 includes a value for each PMIX code and an associated compensation value q cmp In one example, the compensation value q cmp Corresponding to the damage value q imp .

[0057] Figure 5 The diagram shows a PMIX circuit with 256 PMIX codes (eg, Figure 2 500 of an example INL distribution of a PMIX circuit 250 of the embodiment of the present invention. Each of the PMIX codes is associated with a different INL value (eg, compensation value q cmp ) is associated with.

[0058] Figure 6 The PMIX circuit (eg, Figure 2 A graph 600 of the distribution of PMIX codes over time for a PMIX circuit 250 of FIG. 600 shows the INL of the PMIX output phase without applying INL compensation (eg, INL impairment q imp ). Another line 620 of the graph 600 illustrates the INL of the PMIX output phase, where compensation of the INL is applied when using a compensation circuit (eg, compensation circuit 260 of CDR circuit 201). Figure 6 As shown, the magnitude of INL is reduced by using a compensation circuit (eg, compensation circuit 260 ) with a CDR circuit, thereby improving the performance of a corresponding receiver circuit.

[0059] In one example, compared to other receiver circuits, including a compensation circuit (e.g., Figure 2 The compensation circuit 260) of the CDR circuit (eg, Figure 2 The CDR circuit 201) is a receiver circuit (eg, Figure 1 The bit error rate (BER) of the receiver circuit 120 of the embodiment of the present invention is reduced. For example, the BER of such a receiver circuit is improved from about 3e-9 to 3e-12. In addition, in one or more examples, when using the compensation technique described above, the signal-to-noise ratio (SNR) of such a receiver circuit is improved by about 3dB.

[0060] Figure 7 A flow chart of a method 700 for compensating for nonlinearity within a receiver circuit (eg, receiver circuit 120) is illustrated. The method 700 comprises Figure 2 At 710 of method 700, a compensation signal for each PMIX code is provided, which is expressed by q cmp At 712 of method 700 , compensation circuit 260 obtains compensation value q from LUT 282 of memory 280 cmp . Compensation value q cmp corresponds to the PMIX code used by PMIX circuit 250 to generate clock signal 204. The compensation signal is generated by compensation circuit 260 according to the compensation value q cmp In one example, the compensation value q cmp corresponds to the INL of the PMIX circuit 250. At 714 of the method 700, the compensation circuit 260 sets the compensation value q cmpConverting from the INL value to the DNL value, where the DNL value represents the compensation signal. In one example, the delay element 262 subtracts the previous compensation value from the current compensation value, performs a derivative function, and generates the compensation signal. The compensation signal corresponds to the DNL of the PMIX circuit 250.

[0061] In one example, during the first period, the PMIX circuit 250 generates the clock signal 204 based on the first PMIX code among the plurality of PMIX codes. The compensation circuit 260 obtains the compensation value q associated with the first PMIX code from the memory 280 during the first period. cmp1 During the second period, the PMIX circuit 250 generates the clock signal 204 based on a second PMIX code among the plurality of PMIX codes. In addition, during the second period, the compensation circuit 260 retrieves a second compensation value q associated with the second PMIX code from the memory. cmp2 , and generates a corresponding compensation signal (eg, compensation signal 269). When PMIX circuit 250 loops through the PMIX code to generate clock signal 204, compensation circuit 260 obtains the corresponding compensation value q from memory 280. cmp .

[0062] At 720 of method 700, nonlinear compensation within the PMIX circuit is performed. For example, a phase accumulation circuit (e.g., Figure 2 The phase accumulation circuit 240 of the embodiment receives the compensation signal (e.g., compensation signal 269) and the phase accumulator input update signal 225. The compensation signal 269 is combined with the phase accumulator input update signal 225 to compensate the PMIX circuit (e.g., Figure 2 For example, at 722 of method 700, the summing element (e.g., Figure 2 The summing element 242 of the phase accumulator inputs an update signal (e.g., Figure 2 The phase accumulator input update signal 225 is subtracted from the DNL compensation value (eg, Figure 2 The compensation signal 269) is used to compensate the PMIX circuit (eg, Figure 2 In one example, reference Figure 2 , combining the compensation signal 269 with the phase accumulator input update signal 225 includes injecting a nonlinearity value (eg, DNL) into the phase accumulator 240 via the compensation signal 269 to compensate for nonlinearities within the PMIX circuit 250 .

[0063] At 730 of method 700, a clock signal is generated by the PMIX circuit. Figure 2, the PMIX circuit 250 generates the clock signal 204 based on the signal 247 generated according to the compensation signal 243. In one or more examples, the PMIX circuit 250 further generates a signal 251 based on the PMIX code to generate the clock signal 204.

[0064] In the above disclosure, the implementation of the present disclosure has been described with reference to its specific example implementation. It is obvious that various modifications may be made to it without departing from the broader spirit and implementation scope of the present disclosure set forth in the appended claims. When the present disclosure relates to some elements of the singular tense, multiple elements may be depicted in the figures, and the same elements may be marked with the same reference numerals. Therefore, the present disclosure and the accompanying drawings should be regarded as illustrative, rather than restrictive.

Claims

1. A clock and data recovery (CDR) system, comprising: A compensation circuit generates a first compensation signal based on the first compensation value; as well as A phase accumulation circuit, wherein the phase accumulation circuit: receiving the first compensation signal and a phase accumulator input update signal, and The first compensation signal is combined with the phase accumulator input update signal to compensate for a first nonlinearity within a phase mixer (PMIX) circuit. 2 . The CDR system of claim 1 , wherein the first compensation value is associated with a first PMIX code among a plurality of PMIX codes of the PMIX circuit. 3 . The CDR system of claim 2 , wherein the compensation circuit is further configured to generate a second compensation signal based on a second compensation value, wherein the second compensation value is associated with a second PMIX code among the plurality of PMIX codes. 4 . The CDR system of claim 2 , wherein the PMIX circuit further generates a clock signal based on the first PMIX code.

5. The CDR system of claim 1 , wherein the compensation circuit comprises: a first delay element, generating a delayed signal according to the first compensation value; a summing element receiving the first compensation value and the delayed signal to generate a nonlinear signal; as well as The second delay element outputs the first compensation signal based on the nonlinear signal. 6 . The CDR system of claim 1 , wherein the first compensation value corresponds to integral nonlinearity (INL), and the compensation circuit is configured to convert the first compensation value from INL to differential nonlinearity (DNL) to generate the first compensation signal. 7 . The CDR system of claim 1 , further comprising a memory configured to store the first compensation value, and wherein the first compensation value is retrieved from the memory by the compensation circuit.

8. The CDR system of claim 7, wherein the PMIX circuit comprises a plurality of PMIX codes, and the memory comprises a corresponding compensation value for each of the plurality of PMIX codes.

9. A method comprising: receiving a first compensation value; generating a first compensation signal based on the first compensation value; compensating for a first nonlinearity within a phase mixer (PMIX) circuit based on the first compensation signal and a phase accumulator input update signal; as well as A clock signal is generated by the PMIX circuit based on the compensation signal.

10. The method of claim 9, wherein the first compensation value is associated with a first PMIX code among a plurality of PMIX codes of the PMIX circuit. 11 . The method of claim 10 , further comprising generating a second compensation signal based on a second compensation value, wherein the second compensation value is associated with a second PMIX code among the plurality of PMIX codes.

12. The method of claim 10, wherein the clock signal is generated based on the first PMIX code.

13. The method of claim 9, wherein the first compensation value corresponds to integral nonlinearity (INL), and generating the first compensation signal comprises converting the compensation value from INL to differential nonlinearity (DNL).

14. The method of claim 9, wherein the first compensation value is received from a memory including a corresponding compensation value for each PMIX code of the PMIX circuit.

15. A non-transitory computer readable medium comprising stored instructions which, when executed by a processor, cause the processor to: A compensation circuit for a clock and data recovery (CDR) circuit is provided, wherein the compensation circuit comprises: An input node receiving a first compensation value; as well as a summing element that subtracts a delayed version of the first compensation value from the compensation value to generate a first non-linearity value, wherein the compensation circuit generates a first compensation signal based on the first non-linearity value; as well as A phase accumulation circuit of the CDR circuit is provided, wherein the phase accumulation circuit compensates for a first nonlinearity within a phase mixer (PMIX) circuit based on the first compensation signal.

16. The non-transitory computer readable medium of claim 15, wherein the processor is further caused to provide a PMIX circuit that generates a clock signal based on the first PMIX code.

17. The non-transitory computer-readable medium of claim 16, wherein the first compensation value is associated with the first PMIX code. 18 . The non-transitory computer readable medium of claim 15 , wherein the compensation circuit further comprises a second delay element that generates the first compensation signal based on the first nonlinearity value.

19. The non-transitory computer readable medium of claim 15, wherein the phase accumulation circuit also receives a phase accumulator input update signal and combines the first compensation signal with the phase accumulator input update signal to compensate for the first nonlinearity within the PMIX circuit.

20. The non-transitory computer-readable medium of claim 15, wherein the processor further provides a memory, the memory comprising a lookup table comprising a corresponding compensation value for each of a plurality of PMIX codes, and wherein the input node receives the first compensation value from the memory.

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