Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device is provided with a semiconductor substrate, an interlayer insulating film provided above the semiconductor substrate and provided with a contact hole having a stepped portion on a side wall, and a contact portion provided in the contact hole, the contact portion having a barrier layer provided on a side wall and a bottom surface of the contact hole. The barrier layer has a first region in contact with the stepped portion and a second region in contact with the side wall of the contact hole in a region different from the first region, and 0.3 T < = t < = 0.95 T is satisfied, where T is the film thickness of the thickest portion of the first region at the earlier stage and t is the film thickness of the thinnest portion of the second region.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Patent document 1 describes a semiconductor device having a structure in which "a step 14c is provided on the side wall of the contact hole 14 at the interface between the HTO film 11 and the BPSG film 12, and due to the step 14c, the width of the upper end side of the contact hole 14 is widened in a step-like manner compared with the width of the bottom side of the contact hole 14."

[0003] Prior art literature Patent Literature Patent Document 1: Japanese Patent Application No. 2019-093015 Patent Document 2: Japanese Patent Application Laid-Open No. 63-205951 Patent Document 3: Japanese Patent Application Laid-Open No. 5-299375 Patent Document 4: Japanese Patent Application Laid-Open No. 7-94448 Patent Document 5: Japanese Patent Application Publication No. 2001-223218 Patent Document 6: Japanese Patent Application No. 2004-515921 Patent Document 7: Japanese Patent Application No. 2007-511087 Patent Document 8: Japanese Patent Application Publication No. 2008-141050 Summary of the invention

[0004] Technical issues It is preferable to make the film thickness of the barrier layer uniform.

[0005] Open to the public In a first embodiment of the present invention, a semiconductor device is provided, comprising: a semiconductor substrate; an interlayer insulating film, which is arranged above the semiconductor substrate and has a contact hole having a step portion on the side wall; and a contact portion, which is arranged in the contact hole, the contact portion having: a barrier layer, which is arranged on the side wall and the bottom surface of the contact hole, the barrier layer having: a first region, which is in contact with the step portion; and a second region, which is in contact with the side wall of the contact hole in a region lower than the first region, and when the film thickness of the thickest part of the first region in the early stage is set to T and the film thickness of the thinnest part of the second region is set to t, 0.3T≤t≤0.95T is satisfied.

[0006] In the above-mentioned semiconductor device, the interlayer insulating film comprises: a first interlayer insulating film, which is arranged in contact with the front surface of the semiconductor substrate; and a second interlayer insulating film, which is arranged above the first interlayer insulating film, and the step portion can be formed at the boundary between the first interlayer insulating film and the second interlayer insulating film.

[0007] In any of the above-mentioned semiconductor devices, the contact portion may be a trench contact portion provided to extend from the front surface of the semiconductor substrate in a depth direction of the semiconductor substrate.

[0008] In any of the above semiconductor devices, the barrier layer may include: a first barrier metal layer provided on the side wall in the contact hole; and a second barrier metal layer stacked on the first barrier metal layer in the contact hole.

[0009] In any of the above semiconductor devices, the second barrier metal layer may be thicker than the first barrier metal layer at a position above the step portion.

[0010] In any of the above-mentioned semiconductor devices, the second barrier metal layer may be thinner in thickness than the first barrier metal layer at a position below the step portion.

[0011] In any of the above semiconductor devices, the film thickness T of the thickest portion of the first region may be greater than or equal to 3 nm and less than or equal to 120 nm, and the film thickness t of the thinnest portion of the second region may be greater than or equal to 1 nm and less than or equal to 114 nm.

[0012] In any of the above semiconductor devices, the thickness of the thickest portion of the first barrier metal layer in the first region may be greater than or equal to 3 nm and less than or equal to 120 nm.

[0013] In any of the above semiconductor devices, the first barrier metal layer may include any one of Ti, TiN, Ta, and TaN.

[0014] In any of the above semiconductor devices, the second barrier metal layer may include any one of TiN and TaN.

[0015] In any of the above-mentioned semiconductor devices, the semiconductor device may include a plug layer provided inside the barrier layer in the contact hole.

[0016] In any of the above semiconductor devices, at least one or both of the barrier layer and the plug layer may be provided above the interlayer insulating film.

[0017] In any of the above semiconductor devices, the plug layer may include any one of tungsten and molybdenum.

[0018] In any of the above semiconductor devices, the sidewall of the contact hole may be forward tapered.

[0019] In any of the above semiconductor devices, the sidewall of the contact hole may be in an inverted tapered shape.

[0020] In any of the above semiconductor devices, a height of the step portion in a direction perpendicular to a tangent direction of the sidewall of the contact hole may be less than or equal to 15% of an opening width of the contact hole on an upper surface of the interlayer insulating film.

[0021] In any of the above semiconductor devices, the barrier layer may have a thickness of 1 nm to 115 nm above the step portion, and a thickness of 1 nm to 114 nm below the step portion.

[0022] In a second embodiment of the present invention, a method for manufacturing a semiconductor device is provided, comprising: a stage of forming an interlayer insulating film having a contact hole with a step portion provided on the side wall above a semiconductor substrate; a stage of providing a barrier layer on the side wall and the bottom surface of the contact hole; and a stage of providing a plug layer on the inner side of the barrier layer in the contact hole, the barrier layer having: a first region which is in contact with the step portion; and a second region which is in contact with the side wall of the contact hole in a region lower than the first region, and when the film thickness of the thickest part of the first region in the early stage is set to T and the film thickness of the thinnest part of the second region is set to t, 0.3T≤t≤0.95T is satisfied.

[0023] In the above-mentioned method for manufacturing a semiconductor device, the stage of setting the barrier layer may include: a stage of setting a first barrier metal layer on the side wall and the bottom surface in the contact hole; and a stage of setting a second barrier metal layer in the contact hole in a manner stacked on the first barrier metal layer.

[0024] Any of the above-mentioned methods for manufacturing a semiconductor device may include a step of etching the first region after the step of providing the first barrier metal layer and before the step of providing the second barrier metal layer.

[0025] In any of the above-mentioned methods for manufacturing a semiconductor device, the thickness of the thickest portion of the first barrier metal layer in the first region may be greater than or equal to 3 nm and less than or equal to 120 nm.

[0026] In any of the above-mentioned methods for manufacturing a semiconductor device, the barrier layer may be formed by a sputtering method.

[0027] In any of the above methods for manufacturing a semiconductor device, the plug layer may be formed by a CVD method.

[0028] In any of the above-mentioned methods for manufacturing a semiconductor device, the second barrier metal layer may be formed by a CVD method.

[0029] It should be noted that the above invention summary does not list all the features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1A An example of a top view of the semiconductor device 100 is shown.

[0031] Figure 1B Show Figure 1A An example of the a-a' section in FIG.

[0032] Figure 2A A plan view showing a modified example of the semiconductor device 100 .

[0033] Figure 2B A plan view showing a modified example of the semiconductor device 100 .

[0034] Figure 2C A cross section taken along the line bb′ of a modification of the semiconductor device 100 is shown.

[0035] Figure 3A It is an enlarged view of a cross section of the semiconductor device 100 .

[0036] Figure 3B It is an enlarged view of a cross section of a semiconductor device 100 as a modification.

[0037] Figure 3C It is an enlarged view of a cross section of a semiconductor device 100 as a modification.

[0038] Figure 4 It is an enlarged view of a cross section of a semiconductor device in a comparative example.

[0039] Figure 5 1 is a flowchart showing an example of a manufacturing process of the semiconductor device 100 .

[0040] Fig. 6A An example of a method for manufacturing the semiconductor device 100 is shown.

[0041] Figure 6B An example of a method for manufacturing the semiconductor device 100 is shown.

[0042] Figure 6C An example of a method for manufacturing the semiconductor device 100 is shown.

[0043] Explanation of symbols 10···semiconductor substrate, 12···emitter region, 14···base region, 15···contact region, 16···accumulation region, 17···well region, 18···drift region, 20···buffer region, 21···front surface, 22···collector region, 23···back surface, 24···collector electrode, 25···connecting portion, 30···dummy groove portion, 31···extension portion, 32···dummy insulator ···interlayer insulating film, 33···connecting portion, 34···dummy conductive portion, 38···interlayer insulating film, 39···step portion, 40···gate trench portion, 41···extending portion, 42···gate insulating film, 43···connecting portion, 44···gate conductive portion, 50···gate metal layer, 52···emitter electrode, 53···front metal layer, 54···contact hole, 55···contact hole contact hole, 56···contact hole, 60···barrier layer, 61···first barrier metal layer, 62···second barrier metal layer, 63···silicide layer, 64···plug layer, 65···contact portion, 70···transistor portion, 71···mesa portion, 80···diode portion, 81···mesa portion, 82···cathode region, 85···extension region, 90···boundary portion, 91··· mesa portion, 100···semiconductor device, 102···edge, 112···gate pad, 120···active portion, 130···gate wiring, 131···gate wiring between active portions, 140···edge terminal structure portion, 161···first region, 162···second region, 163···third region, 381···first interlayer insulating film, 382···second interlayer insulating film DETAILED DESCRIPTION

[0044] Hereinafter, the present invention will be described by way of the embodiments of the invention, but the following embodiments do not limit the invention involved in the claims. In addition, all combinations of features described in the embodiments are not necessarily all essential to the technical means of the invention.

[0045] In this specification, one side in a direction parallel to the depth direction of a semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". One of the two main surfaces of a substrate, layer, or other component is referred to as an upper surface, and the other is referred to as a lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction when a semiconductor device is installed.

[0046] In this specification, sometimes the rectangular coordinate axes of the X-axis, Y-axis and Z-axis are used to explain technical matters. The rectangular coordinate axes are only used to determine the relative positions of the components and are not limited to specific directions. For example, the Z-axis is not limited to indicating the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When the Z-axis direction is recorded without recording the positive or negative, it refers to the direction parallel to the +Z-axis and the -Z-axis.

[0047] In this specification, the right-angled axes parallel to the upper surface and the lower surface of the semiconductor substrate are referred to as the X-axis and the Y-axis. In addition, the axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. In addition, in this specification, the direction including the X-axis and the Y-axis and parallel to the upper surface and the lower surface of the semiconductor substrate is sometimes referred to as the horizontal direction.

[0048] In this specification, when it is recorded as P+ type or N+ type, it means that the doping concentration is higher than the doping concentration of P type or N type, and when it is recorded as P- type or N- type, it means that the doping concentration is lower than the doping concentration of P type or N type.

[0049] Figure 1A FIG. 1 shows an example of a top view of a semiconductor device 100. The semiconductor device 100 of this example is a semiconductor chip including a transistor portion 70. The semiconductor device 100 may be any semiconductor element having a MOS gate structure on a semiconductor substrate 10, and is not limited to a transistor.

[0050] The transistor section 70 is a region obtained by projecting the collector region 22 provided on the back side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The collector region 22 will be described later. The transistor section 70 includes a transistor such as an IGBT. In this example, the transistor section 70 is an IGBT. It should be noted that the transistor section 70 may also be another transistor such as a MOSFET.

[0051] In this figure, the area around the active part of the semiconductor device 100 is shown, and other areas are omitted. For example, an edge terminal structure portion can be provided in the area on the negative side of the Y-axis direction of the semiconductor device 100 in this example. The edge terminal structure portion alleviates the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge terminal structure portion has, for example, a guard ring, a field plate, a surface electric field reduction, and a structure composed of these. It should be noted that in this example, although the edge on the negative side of the Y-axis direction is described for convenience, the same is true for other edges of the semiconductor device 100.

[0052] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate or a silicon carbide substrate. The semiconductor substrate 10 in this example is a silicon substrate. It should be noted that in this specification, when simply referred to as a top view, it means observing from the upper surface side of the semiconductor substrate 10. As described later, the semiconductor substrate 10 has a front surface 21 and a back surface 23.

[0053] The semiconductor device 100 of this example includes a gate groove portion 40, a dummy groove portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front surface 21 of the semiconductor substrate 10. In addition, the semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are examples of a front-side metal layer 53 described later. The gate groove portion 40 is an example of a MOS gate structure provided in the semiconductor device 100. It should be noted that the semiconductor device 100 of this example is a transistor having a MOS gate structure, but may also be a diode having a MOS gate structure.

[0054] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. In addition, the gate metal layer 50 is disposed above the connection portion 25 and the well region 17.

[0055] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing a metal. At least a portion of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi), aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi), aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier layer 60 formed of titanium or a titanium compound, etc., in the lower layer of the region formed of aluminum, etc. The barrier layer 60 will be described later. The emitter electrode 52 and the gate metal layer 50 are provided in a manner separated from each other.

[0056] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 via the interlayer insulating film 38. Figure 1A The interlayer insulating film 38 is omitted. The contact holes 54, 55, and 56 are provided in the interlayer insulating film 38 so as to penetrate therethrough.

[0057] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive portion in the transistor portion 70 via the connection portion 25. A plug layer 64 made of tungsten or the like may be formed inside the contact hole 55. The plug layer 64 will be described later.

[0058] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. Inside the contact hole 56, a plug layer 64 made of tungsten or the like may be formed.

[0059] The connection portion 25 is connected to the front side metal layer such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection portion 25 is arranged between the gate metal layer 50 and the gate conductive portion. The connection portion 25 of this example is arranged in a manner extending along the X-axis direction and can be electrically connected to the gate conductive portion. The connection portion 25 can also be arranged between the emitter electrode 52 and the dummy conductive portion. In this example, the connection portion 25 is not arranged between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is a conductive material such as polysilicon doped with impurities. The connection portion 25 of this example is polysilicon doped with N-type impurities (N+). The connection portion 25 is arranged above the front side 21 of the semiconductor substrate 10 through an insulating film such as an oxide film.

[0060] The gate groove portion 40 is an example of a plurality of groove portions extending along a predetermined extension direction on the front surface 21 side of the semiconductor substrate 10. The gate groove portion 40 is arranged at a predetermined interval along a predetermined arrangement direction (in this example, the X-axis direction). The gate groove portion 40 of this example may have two extension portions 41 and a connecting portion 43, wherein the two extension portions 41 extend along an extension direction (in this example, the Y-axis direction) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and the connecting portion 43 connects the two extension portions 41.

[0061] The connection portion 43 is preferably at least partially formed into a curved shape. By connecting the ends of the two extension portions 41 of the gate groove portion 40, the electric field concentration at the ends of the extension portion 41 can be alleviated. In the connection portion 43 of the gate groove portion 40, the gate metal layer 50 can be electrically connected to the gate conductive portion via the connection portion 25.

[0062] The dummy groove portion 30 is an example of a plurality of groove portions extending along a predetermined extension direction on the front surface 21 side of the semiconductor substrate 10. The dummy groove portion 30 is a groove portion electrically connected to the emitter electrode 52. The dummy groove portion 30 is arranged at a predetermined interval along a predetermined arrangement direction (in this example, the X-axis direction) similarly to the gate groove portion 40. The dummy groove portion 30 of this example has an I-shape on the front surface 21 of the semiconductor substrate 10, but may have a U-shape on the front surface 21 of the semiconductor substrate 10 similarly to the gate groove portion 40. That is, the dummy groove portion 30 may have two extension portions extending along the extension direction, and a connection portion connecting the two extension portions.

[0063] The transistor portion 70 of this example has a structure in which two gate trench portions 40 and two dummy trench portions 30 are repeatedly arranged. That is, the transistor portion 70 of this example has the gate trench portion 40 and the dummy trench portion 30 at a ratio of 1:1. For example, the transistor portion 70 has one dummy trench portion 30 between two extension portions 41.

[0064] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 may be greater than the ratio of the dummy trench portion 30, or the ratio of the dummy trench portion 30 may be greater than the ratio of the gate trench portion 40. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 2:3 or 2:4. In addition, the transistor portion 70 may have all the trench portions as the gate trench portion 40 without the dummy trench portion 30.

[0065] The well region 17 is provided in a region of the second conductivity type which is closer to the front surface 21 side of the semiconductor substrate 10 than the drift region 18 described later. The well region 17 is an example of a well region provided on the peripheral side of the active portion 120. As an example, the well region 17 is of P+ type. The well region 17 is formed in a predetermined range from the end of the active region on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depth of the gate groove portion 40 and the dummy groove portion 30. A portion of the gate groove portion 40 and the dummy groove portion 30 on the side of the gate metal layer 50 is formed in the well region 17. The bottom of the end portions of the gate groove portion 40 and the dummy groove portion 30 in the extension direction may be covered by the well region 17.

[0066] In the transistor portion 70, the contact hole 54 is formed above each region of the emitter region 12 and the contact region 15. The contact hole 54 is not provided above the well region 17 provided at both ends in the Y-axis direction. In this way, one or more contact holes 54 are formed in the interlayer insulating film. One or more contact holes 54 may be provided to extend along the extension direction.

[0067] The mesa portion 71 is a mesa portion provided adjacent to the groove portion in a plane parallel to the front surface 21 of the semiconductor substrate 10. The mesa portion refers to a portion of the semiconductor substrate 10 sandwiched between two adjacent groove portions, and may be a portion from the front surface 21 of the semiconductor substrate 10 to the depth of the deepest bottom of each groove portion. The extension portion of each groove portion may be set as one groove portion. That is, the region sandwiched between two extension portions may be set as the mesa portion.

[0068] In the transistor portion 70, the mesa portion 71 is provided adjacent to at least one of the dummy trench portion 30 and the gate trench portion 40. The mesa portion 71 has the well region 17, the emitter region 12, the base region 14, and the contact region 15 on the front surface 21 of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 are alternately provided in the extension direction.

[0069] The base region 14 is a second conductivity type region provided on the front surface 21 side of the semiconductor substrate 10. As an example, the base region 14 is a P-type. The base region 14 can be provided at both ends of the mesa portion 71 in the Y-axis direction on the front surface 21 of the semiconductor substrate 10. Figure 1A Only the end portion of the base region 14 on one side in the Y-axis direction is shown.

[0070] The emitter region 12 is a region of the first conductivity type having a higher doping concentration than the drift region 18. As an example, the emitter region 12 of this example is of N+ type. An example of a dopant of the emitter region 12 is arsenic (As). The emitter region 12 is provided on the front surface 21 of the mesa portion 71 in contact with the gate groove portion 40. The emitter region 12 can be provided extending from one of the two groove portions sandwiching the mesa portion 71 along the X-axis direction to the other groove portion. The emitter region 12 is also provided below the contact hole 54.

[0071] In addition, the emitter region 12 may or may not be in contact with the dummy trench portion 30. In this example, the emitter region 12 is in contact with the dummy trench portion 30.

[0072] The contact region 15 is a region of the second conductivity type disposed above the base region 14 and having a higher doping concentration than the doping concentration of the base region 14. As an example, the contact region 15 of this example is of P+ type. The contact region 15 of this example is disposed on the front surface 21 of the mesa portion 71. The contact region 15 may be disposed along the X-axis direction from one of the two groove portions sandwiching the mesa portion 71 to the other groove portion. The contact region 15 may or may not be in contact with the gate groove portion 40 or the dummy groove portion 30. The contact region 15 of this example is in contact with the dummy groove portion 30 and the gate groove portion 40. The contact region 15 is also disposed below the contact hole 54.

[0073] Figure 1B Show Figure 1A The a-a' cross section is an example of the a-a' cross section. The a-a' cross section is an XZ plane passing through the emitter region 12 in the transistor portion 70. The semiconductor device 100 of this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the a-a' cross section. The collector electrode 24 is an example of a back side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0074] The drift region 18 is a region of the first conductivity type provided in the semiconductor substrate 10. As an example, the drift region 18 in this example is of N-type. The drift region 18 may be a region remaining without forming other doping regions in the semiconductor substrate 10. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0075] The buffer region 20 is a region of the first conductivity type disposed on the back surface 23 side of the semiconductor substrate 10 closer to the drift region 18. As an example, the buffer region 20 of this example is of N type. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 can function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type. It should be noted that the buffer region 20 can be omitted.

[0076] In the transistor portion 70, the collector region 22 is provided below the buffer region 20. The collector region 22 has the second conductivity type. As an example, the collector region 22 in this example is of the P+ type.

[0077] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal. The material of the collector electrode 24 may be the same as that of the emitter electrode 52, or may be different from that of the emitter electrode 52.

[0078] The base region 14 is a region of the second conductivity type provided above the drift region 18. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0079] The emitter region 12 is provided above the base region 14. The emitter region 12 is provided between the base region 14 and the front surface 21. The emitter region 12 is provided in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30.

[0080] The accumulation region 16 is a region of the first conductivity type provided on the front surface 21 side of the semiconductor substrate 10 relative to the drift region 18. As an example, the accumulation region 16 of this example is of N+ type. However, the accumulation region 16 may not be provided.

[0081] The accumulation region 16 is arranged in contact with the gate groove portion 40. The accumulation region 16 may or may not be in contact with the dummy groove portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. The dose of ion implantation in the accumulation region 16 may be greater than 1.0E+12cm-2 and less than 1.0E+13cm-2. In addition, the dose of ion implantation in the accumulation region 16 may be greater than 3.0E+12cm-2 and less than 6.0E+12cm-2. By providing the accumulation region 16, the carrier injection enhancement effect (IE effect) can be improved and the on-voltage of the transistor portion 70 can be reduced.

[0082] One or more gate groove portions 40 and one or more dummy groove portions 30 are provided on the front side 21. Each groove portion is provided from the front side 21 to the drift region 18. In the region where at least any one of the emitter region 12, the base region 14, the contact region 15 and the accumulation region 16 is provided, each groove portion also penetrates these regions and reaches the drift region 18. The groove portion penetrating the doped region is not limited to the manufacturing in the order of forming the groove portion after forming the doped region. The method of forming the doped region between the groove portions after forming the groove portion is also included in the method of the groove portion penetrating the doped region.

[0083] The gate groove portion 40 has a gate groove formed on the front side 21, a gate insulating film 42 and a gate conductive portion 44. The gate insulating film 42 is formed in a manner covering the inner wall of the gate groove. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate groove. The gate conductive portion 44 is formed inside the gate groove at a position closer to the inside than the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate groove portion 40 is covered by an interlayer insulating film 38 on the front side 21.

[0084] The gate conductive portion 44 includes a region facing the base region 14 adjacent to the mesa portion 71 via the gate insulating film 42 in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel consisting of an inversion layer of electrons is formed in the surface layer of the interface in contact with the gate trench in the base region 14.

[0085] The dummy groove portion 30 may have the same structure as the gate groove portion 40. The dummy groove portion 30 includes a dummy groove formed on the front side 21, a dummy insulating film 32, and a dummy conductive portion 34. The dummy insulating film 32 is formed in a manner covering the inner wall of the dummy groove. The dummy conductive portion 34 is formed inside the dummy groove and is formed at a position further inside than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy groove portion 30 may be covered by an interlayer insulating film 38 on the front side 21.

[0086] The interlayer insulating film 38 is provided above the semiconductor substrate 10. The interlayer insulating film 38 of this example is provided in contact with the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. One or more contact holes 54 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10 are provided in the interlayer insulating film 38. The contact holes 55 and the contact holes 56 can also be provided through the interlayer insulating film 38. The film thickness of the interlayer insulating film 38 is, for example, 1.0 μm, but is not limited thereto. The interlayer insulating film 38 of this example can include a first interlayer insulating film 381 provided in contact with the front surface 21, and a second interlayer insulating film 382 provided above the first interlayer insulating film 381.

[0087] The interlayer insulating film 38 may be a silicon oxide film. The interlayer insulating film 38 may be a BPSG (Boro-phosphoSilicate Glass) film, a BSG (borosilicate glass) film, or a PSG (Phosphosilicate glass) film. The interlayer insulating film 38 may include a high temperature silicon oxide (HTO: High Temperature Oxide) film. The first interlayer insulating film 381 and the second interlayer insulating film 382 may be made of the same material or different materials. In one example, the first interlayer insulating film 381 may be an HTO film, and the second interlayer insulating film 382 may be a BPSG film. In addition, the interlayer insulating film 38 may also be a layer structure of three or more layers.

[0088] Figure 2A A plan view showing a modified example of the semiconductor device 100. In this example, only a part of the components of the semiconductor device 100 is shown, and a part of the components is omitted.

[0089] The semiconductor substrate 10 has an edge 102 in a plan view. The semiconductor substrate 10 of this example has two sets of edge 102 that are opposite to each other in a plan view. In this example, the X axis and the Y axis are parallel to any of the edge 102.

[0090] The semiconductor substrate 10 is provided with an active portion 120. The active portion 120 is a region where a main current flows in the depth direction between the front surface 21 and the back surface 23 of the semiconductor substrate 10 when the semiconductor device 100 operates. An emitter electrode 52 is provided above the active portion 120, but is omitted in this figure.

[0091] The active portion 120 is provided with at least one of a transistor portion 70 including a transistor element such as an IGBT and a diode portion 80 including a diode element such as a freewheeling diode (FWD). Figure 2AIn the example of FIG. 1 , the transistor portion 70 and the diode portion 80 are alternately arranged along a predetermined arrangement direction (in this example, the X-axis direction) of the front surface 21 of the semiconductor substrate 10 . In other examples, only one of the transistor portion 70 and the diode portion 80 may be provided in the active portion 120 .

[0092] In this example, the region where the transistor portion 70 is disposed is marked with a symbol "I", and the region where the diode portion 80 is disposed is marked with a symbol "F". The transistor portion 70 and the diode portion 80 may each have a long side in the extension direction. That is, the length of the transistor portion 70 in the Y-axis direction is greater than the width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is greater than the width in the X-axis direction. The extension direction of the transistor portion 70 and the diode portion 80 may be the same as the long side direction of each groove portion described later.

[0093] The diode portion 80 is a region obtained by projecting a cathode region 82 provided on the back surface 23 side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The cathode region 82 will be described later. On the back surface 23 of the semiconductor substrate 10, a P+ type collector region 22 may be provided in a region other than the cathode region 82. In this specification, an extension region 85 in which the diode portion 80 is extended along the Y-axis direction to the gate wiring described later is sometimes also included in the diode portion 80. The collector region 22 may be provided on the back surface 23 of the extension region 85.

[0094] The semiconductor device 100 may have one or more pads above the semiconductor substrate 10. The semiconductor device 100 of this example has a gate pad 112. The semiconductor device 100 may also have pads such as an anode pad and a cathode pad. In the case of this example, each pad is arranged near the end 102. The vicinity of the end 102 refers to the area between the end 102 and the emitter electrode 52 when viewed from above. When the semiconductor device 100 is installed, each pad can be connected to an external circuit via wiring such as a wire. In addition, the arrangement position of each pad may not be arranged near the end 102.

[0095] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the gate conductive portion 44 of the gate trench portion 40 of the active portion 120. The semiconductor device 100 includes a gate wiring that connects the gate pad 112 and the gate trench portion 40. Figure 2A In FIG. 1 , the gate wiring is marked with oblique hatching.

[0096] The gate wiring of this example has a peripheral gate wiring 130 and an inter-active portion gate wiring 131. The gate wiring may be composed of one of the gate metal layer 50 and the connecting portion 25 or a suitable combination of the two. The peripheral gate wiring 130 and the inter-active portion gate wiring 131 may have the same structure or different structures. The peripheral gate wiring 130 is arranged between the active portion 120 and the end 102 of the semiconductor substrate 10 when viewed from above. The peripheral gate wiring 130 of this example surrounds the active portion 120 when viewed from above. The area surrounded by the peripheral gate wiring 130 when viewed from above may also be set as the active portion 120. In addition, the peripheral gate wiring 130 is connected to the gate pad 112. The peripheral gate wiring 130 is arranged above the semiconductor substrate 10. The peripheral gate wiring 130 may be composed of the gate metal layer 50 and the connecting portion 25.

[0097] The inter-active portion gate wiring 131 is provided between the plurality of active portions 120. Figure 2A In the embodiment, two active portions 120 are arranged side by side in the Y-axis direction. By providing inter-active portion gate wiring 131 between the plurality of active portions 120 inside the semiconductor substrate 10, the variation in wiring length from the gate pad 112 can be reduced for each region of the semiconductor substrate 10.

[0098] The inter-active portion gate wiring 131 is connected to the gate trench portion of the active portion 120. The inter-active portion gate wiring 131 is disposed above the semiconductor substrate 10. The inter-active portion gate wiring 131 of this example is composed of a gate metal layer 50 and a connection portion 25. The gate metal layer 50 may be a metal layer containing aluminum or the like.

[0099] The inter-active portion gate wiring 131 may be connected to the peripheral gate wiring 130. The inter-active portion gate wiring 131 of this example is provided to extend along the X-axis direction so as to cross the active portion 120 from the peripheral gate wiring 130 on one side to the peripheral gate wiring 130 on the other side at the approximate center in the Y-axis direction. When the active portion 120 is divided by the inter-active portion gate wiring 131, the transistor portion 70 and the diode portion 80 may be alternately arranged in the X-axis direction in each divided region.

[0100] The edge termination structure portion 140 is provided on the front surface 21 of the semiconductor substrate 10. The edge termination structure portion 140 is provided between the active portion 120 and the edge 102 in a plan view. The edge termination structure portion 140 of this example is arranged between the peripheral gate wiring 130 and the edge 102. The edge termination structure portion 140 alleviates the electric field concentration on the front surface 21 side of the semiconductor substrate 10. The edge termination structure portion 140 may include at least one of a guard ring, a field plate, and a surface electric field reduction device that surrounds the active portion 120 and is provided in an annular shape.

[0101] Figure 2BFIG. 1 is a top view of a modified example of the semiconductor device 100. The semiconductor device 100 of this example includes a transistor portion 70 and a diode portion 80. Figure 2A An enlarged view of the upper surface of area A in FIG.

[0102] The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 provided inside the front surface 21 side of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion.

[0103] The dummy trench 30 of this example may have a U-shape on the front surface 21 of the semiconductor substrate 10 similarly to the gate trench 40. That is, the dummy trench 30 may have two extending portions 31 extending along the extending direction and a connecting portion 33 connecting the two extending portions 31.

[0104] The semiconductor device 100 of this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other. The transistor portion 70 of this example includes a boundary portion 90 located at the boundary between the transistor portion 70 and the diode portion 80. However, the semiconductor device 100 may not include the boundary portion 90.

[0105] The boundary portion 90 is a region provided in the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 has a contact region 15 on the front surface 21 of the semiconductor substrate 10. The boundary portion 90 of this example does not have an emitter region 12. In one example, the groove portion of the boundary portion 90 is a dummy groove portion 30. The boundary portion 90 of this example is configured in such a manner that both ends in the X-axis direction become dummy groove portions 30.

[0106] The contact hole 54 is provided above the base region 14 in the diode portion 80. The contact hole 54 is provided above the contact region 15 in the boundary portion 90. None of the contact holes 54 is provided above the well regions 17 provided at both ends in the Y-axis direction.

[0107] The mesa portion 91 is provided in the boundary portion 90. The mesa portion 91 has the contact region 15 on the front surface 21 of the semiconductor substrate 10. The mesa portion 91 of this example has the base region 14 and the well region 17 on the negative side in the Y-axis direction.

[0108] The mesa portion 81 is provided in a region sandwiched between adjacent dummy trench portions 30 in the diode portion 80. The mesa portion 81 has a base region 14 on the front surface 21 of the semiconductor substrate 10. The mesa portion 81 of this example has a well region 17 on the negative side in the Y-axis direction.

[0109] The emission region 12 is provided in the mesa portion 71 , but may not be provided in the mesa portion 81 and the mesa portion 91 . The contact region 15 is provided in the mesa portion 71 and the mesa portion 91 , but may not be provided in the mesa portion 81 .

[0110] Figure 2C The bb' cross section of the modified example of the semiconductor device 100 is shown. Figure 2B The semiconductor device 100 of this example includes a collector region 22 and a cathode region 82 on the back surface 23 side of the buffer region 20 .

[0111] The contact region 15 is provided above the base region 14 in the mesa portion 91. The contact region 15 is provided in contact with the dummy trench portion 30 in the mesa portion 91. In other cross sections, the contact region 15 may be provided on the front surface 21 of the mesa portion 71.

[0112] The accumulation region 16 is provided in the transistor section 70 and the diode section 80. In this example, the accumulation region 16 is provided on the entire surface of the transistor section 70 and the diode section 80. However, the accumulation region 16 may not be provided in the diode section 80.

[0113] The cathode region 82 is provided below the buffer region 20 in the diode portion 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor portion 70 and the diode portion 80. That is, the collector region 22 is provided below the boundary portion 90 in this example.

[0114] The semiconductor device 100 may be a power semiconductor device for power control, etc. The semiconductor device 100 of this example may have a vertical semiconductor structure having a back side metal layer on the back side 23 of the semiconductor substrate 10. However, the semiconductor device 100 may also have a horizontal semiconductor structure having no metal layer on the back side 23.

[0115] It should be noted that in this example, a trench gate structure RC-IGBT is used as an example for explanation as the semiconductor device 100. However, the semiconductor device 100 may be a planar gate structure semiconductor device, or may be another semiconductor device such as a diode. The semiconductor device 100 may include an N-channel MOSFET, or may include a P-channel MOSFET.

[0116] Figure 3A 1 is an enlarged view of a cross section of the semiconductor device 100. In this example, an enlarged view of a cross section near a contact portion 65 provided in the contact hole 54 is shown. The cross section of this example is an XZ cross section passing through the emitter region 12 at the front surface 21 of the semiconductor substrate 10. The contact portion 65 includes a barrier layer 60, a silicide layer 63, and a plug layer 64.

[0117] It should be noted that, in this specification, the structure near the contact portion 65 is sometimes described using the contact hole 54, but the same structure can be applied to other contact holes such as the contact hole 55 and the contact hole 56. That is, the barrier layer 60, the silicide layer 63, and the plug layer 64 can also be provided in other contact holes such as the contact hole 55 and the contact hole 56.

[0118] The contact hole 54 has a step portion 39 on the side wall. The step portion 39 may be formed at the boundary between the first interlayer insulating film 381 and the second interlayer insulating film 382. The step portion 39 may be a side wall of the contact hole 54 and a region including at least one inflection point. In addition, the step portion 39 may be a stepped region formed at the boundary between the first interlayer insulating film 381 and the second interlayer insulating film 382.

[0119] The height h of the step portion 39 may be less than 15%, less than 10%, or less than 5% of the opening width d of the contact hole 54 on the upper surface of the interlayer insulating film 38 in the arrangement direction. In this example, the height h of the step portion 39 may be less than 120 nm, less than 80 nm, or less than 40 nm. In this specification, the height h of the step portion 39 may be the height measured in a direction perpendicular to the tangent direction of the side wall of the second interlayer insulating film 382 up to the side wall of the first interlayer insulating film 381.

[0120] In this example, the side wall of the contact hole 54 has a forward tapered slope. The taper angle of the side wall of the contact hole 54 may be greater than or equal to 70 degrees and less than or equal to 90 degrees.

[0121] In this example, the aspect ratio of the contact hole 54 may be greater than 2 or greater than 5. The aspect ratio of the contact hole 54 may be greater than 0.5 or less than 10. In this specification, the aspect ratio of the contact hole 54 refers to a value obtained by dividing the depth of the contact hole 54 in the depth direction of the semiconductor substrate 10 by the opening width d of the contact hole 54 on the upper surface of the interlayer insulating film 38.

[0122] The barrier layer 60 is disposed above the silicide layer 63 in the contact hole 54. The barrier layer 60 is disposed on the bottom surface of the contact hole 54 and the sidewall of the interlayer insulating film 38. The barrier layer 60 of this example is disposed on the upper surface of the silicide layer 63 and the sidewall of the interlayer insulating film 38 in the contact hole 54. The barrier layer 60 may contain titanium (Ti) or tantalum (Ta). The barrier layer 60 of this example includes a first barrier metal layer 61 and a second barrier metal layer 62.

[0123] In addition, the barrier layer of this example has a first region 161 which is a region in contact with the step portion 39, a second region 162 which is a region lower than the first region 161 and in contact with the side wall of the contact hole 54, and a third region 163 which is a region higher than the first region 161 and in contact with the side wall of the contact hole 54.

[0124] The first barrier metal layer 61 is disposed on the sidewall of the interlayer insulating film 38. The first barrier metal layer 61 may also be disposed on the bottom surface of the contact hole 54. The first barrier metal layer 61 may include at least one of titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN). As an example, the first barrier metal layer 61 is Ti.

[0125] The film thickness of the first barrier metal layer 61 in the first region 161 may be greater than 2 nm and less than 119 nm. In addition, the film thickness of the first barrier metal layer 61 in the second region 162 may be greater than 0.5 nm and less than 113 nm. Here, the film thickness of the first barrier metal layer 61 may be the thickness of the first barrier metal layer 61 measured in a direction perpendicular to the tangent direction of the side wall of the contact hole 54.

[0126] The second barrier metal layer 62 is stacked on the first barrier metal layer 61 in the contact hole 54. The second barrier metal layer 62 is provided on the bottom surface of the contact hole 54 in a manner stacked with the silicide layer 63 provided on the front surface 21 of the semiconductor substrate 10. The second barrier metal layer 62 may include at least one of titanium nitride (TiN) and tantalum nitride (TaN). As an example, the second barrier metal layer 62 is TiN.

[0127] The film thickness of the second barrier metal layer 62 in the first region 161 may be greater than 2 nm and less than 119 nm. In addition, the film thickness of the second barrier metal layer 62 in the second region 162 may be greater than 0.5 nm and less than 113 nm. Here, the film thickness of the second barrier metal layer 62 may be the thickness of the second barrier metal layer 62 measured in a direction perpendicular to the tangent direction of the surface of the first barrier metal layer 61.

[0128] The second barrier metal layer 62 may be thicker than the first barrier metal layer 61 above the step portion 39 . Also, the second barrier metal layer 62 may be thinner than the first barrier metal layer 61 below the step portion 39 .

[0129] The silicide layer 63 is provided on the upper surface of the semiconductor substrate 10 below the contact hole 54. The silicide layer 63 of this example is provided on the upper surface of the semiconductor substrate 10. The silicide layer 63 is formed by annealing the first barrier metal layer 61. The silicide layer 63 of this example is a titanium silicide layer formed by annealing Ti formed as the first barrier metal layer 61 on the bottom surface of the contact hole 54. On the bottom surface of the contact hole 54, a part of the first barrier metal layer 61 may remain without being silicided.

[0130] The plug layer 64 is provided above the barrier layer 60 in the contact hole 54. The plug layer 64 may be provided in contact with the second barrier metal layer 62 in the contact hole 54. The plug layer 64 is a conductive material filled in the contact hole 54. The plug layer 64 may be made of a material different from that of the front metal layer 53. For example, the material of the plug layer 64 is tungsten. The material of the plug layer 64 may be molybdenum. The plug layer 64 may not be provided, and the front metal layer 53 may be buried in the contact hole 54.

[0131] The thickness of the barrier layer 60 in the first region 161 is thicker than that in the second region 162. Here, the thickness of the barrier layer 60 refers to the distance from the side wall of the contact hole 54 to the surface of the barrier layer 60 in a direction perpendicular to the tangent direction of the side wall of the contact hole 54.

[0132] When the largest film thickness of the barrier layer 60 in the first region 161 is set to T and the smallest film thickness of the barrier layer 60 in the second region 162 is set to t, it can be 0.3T≤t≤0.95T or 0.5T≤t≤0.9T. That is, the film thickness of the barrier layer 60 can be uniform in the first region 161 and the second region 162. In this specification, the film thickness "uniform" can satisfy 0.3T≤t≤0.95T, 0.5T≤t≤0.9T, or 0.5T≤t≤0.8T. The film thickness T of the barrier layer 60 in the first region 161 can be greater than 3nm and less than 120nm.

[0133] The thickness of the barrier layer 60 above the step portion 39 may be thicker than the thickness of the barrier layer 60 below the step portion 39. In one example, the thickness of the barrier layer 60 above the step portion 39 may be greater than 1 nm and less than 115 nm. In addition, the thickness of the barrier layer 60 below the step portion 39 may be greater than 1 nm and less than 114 nm.

[0134] Two or more step portions 39 may be provided. In addition, a plurality of first regions 161 may be provided by providing two or more step portions 39. A region that contacts the side wall of the contact hole 54 may be a third region 163 at a position above the first region 161 that is closest to the upper surface of the interlayer insulating film 38 among the plurality of first regions 161, and a region that contacts the side wall of the contact hole 54 may be a second region 162 that is different from the first region 161 and the third region 163.

[0135] Here, Figure 4 3 is an enlarged view of a cross section near a contact portion in a comparative example. In the comparative example, the difference between the film thickness of the barrier layer 60 above the step portion 39 and the film thickness of the barrier layer 60 below the step portion 39 is large. In this way, when the film thickness of the barrier layer 60 has a large difference, stress concentration occurs at the portion below the step portion 39 where the film thickness is thinner during a heat treatment such as an annealing treatment, and the barrier layer 60 breaks, and a portion of the semiconductor substrate 10 may be exposed. In this case, the fluoride used in the formation of the subsequent plug layer 64 invades the semiconductor substrate 10, which may affect the performance of the entire semiconductor device.

[0136] On the other hand, in the semiconductor device 100 of the embodiment, the barrier layer 60 has a uniform film thickness. Therefore, stress concentration does not occur during the heat treatment, and the barrier layer 60 can be prevented from breaking, while the performance of the semiconductor device 100 can be ensured.

[0137] Figure 3B FIG. 1 is an enlarged view of a cross section of a semiconductor device 100 as a modified example. In this example, an enlarged view of a cross section near the contact hole 54 is shown. The cross section of this example is an XZ cross section passing through the emitter region 12 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 of this example is different from the semiconductor device 100 of FIG. Figure 3A The embodiment of FIG. 1 is different in that a trench contact portion is provided as the contact portion 65 .

[0138] The trench contact portion has a contact hole 54 and is arranged to extend from the front surface 21 of the semiconductor substrate 10 along the depth direction of the semiconductor substrate 10. The lower end of the trench contact portion in this example is deeper than the lower end of the emitter region 12. The lower end of the trench contact portion may be shallower than the lower end of the emitter region 12. In this example, the lower end of the trench contact portion contacts the base region 14, but may contact a plug region of the second conductivity type having a higher doping concentration than the base region 14.

[0139] The barrier layer 60 may include a first barrier metal layer 61, a second barrier metal layer 62, and a silicide layer 63 in the trench contact portion. The first barrier metal layer 61 is provided in contact with the side wall of the interlayer insulating film 38. The silicide layer 63 is provided in contact with the side wall of the semiconductor substrate 10 and the front surface 21 of the semiconductor substrate 10 in the trench contact portion.

[0140] The second barrier metal layer 62 is stacked with the first barrier metal layer 61, which is provided in contact with the side wall of the interlayer insulating film 38, and the silicide layer 63, which is provided in contact with the side wall and the front surface 21 of the semiconductor substrate 10. The plug layer 64 is provided inside the second barrier metal layer 62 in the contact hole 54.

[0141] Figure 3C 1 is an enlarged view of a cross section of a semiconductor device 100 as a modified example. In this example, an enlarged view of a cross section near a contact hole 54 is shown. The cross section of this example is an XZ cross section passing through the emitter region 12 at the front surface 21 of the semiconductor substrate 10 .

[0142] The semiconductor device 100 of this example is Figure 3A The difference of the embodiment is that the sidewall of the contact hole 54 has an inverse tapered shape. The taper angle of the sidewall of the contact hole 54 may be greater than or equal to 90 degrees and less than or equal to 110 degrees.

[0143] like Figure 3C As shown, a barrier layer 60 including a first barrier metal layer 61 and a second barrier metal layer 62 may be formed between the interlayer insulating film 38 and the front side metal layer 53. In addition to the contact hole 54, the barrier layer 60 may also be formed between the interlayer insulating film 38 and the front side metal layer 53 in a region other than the contact hole 54. In addition, a plug layer 64 may be formed between the interlayer insulating film 38 and the front side metal layer 53. Figure 3C As shown, a plug layer 64 may be formed between the barrier layer 60 and the front-side metal layer 53 .

[0144] It should be noted that, in this example, the case of having a normal contact portion 65 is described, but, for example, the semiconductor device 100 having a multilayer wiring structure may also be configured in the same manner. In addition, the configurations of the contact holes 54, 55, and 56 may not be the linear shapes shown in this example, but may be the following configurations: holes having a configuration in which the dimensions in the arrangement direction and the extension direction are almost the same, square shapes, elliptical shapes, rectangular shapes, shapes extending in the arrangement direction relative to contact holes extending in the extension direction, shapes formed by combining a plurality of contact holes extending in the arrangement direction and a plurality of contact holes extending in the extension direction, and the like.

[0145] Figure 51 is a flowchart showing an example of a manufacturing process of the semiconductor device 100. In step S100, the element structure on the front side 21 of the semiconductor device 100 is formed. In step S100, a process of forming a dummy trench portion 30 and a gate trench portion 40 as the element structure on the front side 21 may be included. In step S100, a process of forming a base region 14, an emitter region 12, a contact region 15, etc. as the element structure on the front side 21 by ion implantation into the semiconductor substrate 10 may be included.

[0146] In step S102, an interlayer insulating film 38 is formed on the semiconductor substrate 10. The interlayer insulating film 38 may be formed by stacking a plurality of insulating films. In this embodiment, as an example, the interlayer insulating film 38 may include a first interlayer insulating film 381 as an HTO film and a second interlayer insulating film 382 as a BPSG film.

[0147] In step S104, contact holes are formed by etching the interlayer insulating film 38. In step S104, contact holes 54, 55, and 56 may be formed in the interlayer insulating film 38. The contact hole etching method may be dry etching, wet etching, or both.

[0148] As an example of etching in step S104, there is the following method: first, the contact holes are formed by dry etching, and then the contact holes are treated for about 5 seconds to 500 seconds using hydrofluoric acid, dilute hydrofluoric acid, etc., in order to remove the etching residues in the contact holes 54, 55, and 56 and remove the natural oxide film on the surface of the exposed semiconductor substrate 10. The processing time of wet etching can be arbitrarily set in view of the film type, film properties, hydrofluoric acid concentration, processing conditions, desired contact shape and size of the interlayer insulating film. In addition, the dry etching process and the wet etching process can be performed continuously, and a process of forming other structures can be performed between the two processes.

[0149] In each contact hole, a step portion 39 may be formed at the boundary between the first interlayer insulating film 381 and the second interlayer insulating film 382. Generally, when the etching speed difference of the plurality of interlayer insulating films used is large, or when the etching process time is long, the step shape of the step portion 39 becomes larger.

[0150] In step S104, by controlling the formation time and formation conditions of the contact holes 54, 55, and 56, the height h of the step portion 39 can be set to be less than 15% of the opening width d of each contact hole on the upper surface of the interlayer insulating film 38. In the case where the first barrier metal layer 61 and the second barrier metal layer 62 are formed by sputtering in the contact holes having the aspect ratio of the degree shown in the present embodiment and the film thickness of each barrier metal layer is set to the film thickness of the degree shown in the present embodiment, by setting the height h of the step portion 39 to be less than 15% of the opening width d of each contact hole on the upper surface of the interlayer insulating film 38, a uniform barrier layer 60 can be formed.

[0151] In step S106, a first barrier metal layer 61 is formed. The first barrier metal layer 61 in this example is a Ti film formed by sputtering. In this example, a case where a Ti film is formed as the first barrier metal layer 61 is described, but a different type of metal (such as Ta, etc.) can also be used to form the first barrier metal layer 61. In addition, when forming the first barrier metal layer 61, it is preferred that a natural oxide film or the like is not formed on the surface of the semiconductor substrate 10 at the bottom of the contact holes 54, 55, and 56, but that the semiconductor substrate 10 is exposed.

[0152] In step S108, the first region 161 of the first barrier metal layer 61 is etched. The etching may be wet etching or dry etching. By etching the first region 161, the film thickness of the first barrier metal layer 61 thickened in the first region 161 in contact with the step portion 39 can be reduced. When etching the first barrier metal layer 61, it is preferred to selectively remove part or all of the first barrier metal layer 61 of the sidewall portion of the contact holes 54, 55, and 56, and the first barrier metal layer 61 on the bottom surface remains.

[0153] As an example of the etching method in step S108, there can be cited a method of selecting an etching time and etching conditions for removing the first barrier metal layer 61 on the side wall and leaving the first barrier metal layer on the bottom surface when the film thickness of the first barrier metal layer 61 on the side wall is relatively thin relative to the film thickness of the first barrier metal layer 61 on the bottom surface. In addition, as another example, there can be cited a method of selectively removing the first barrier metal layer on the side wall by using the etching speed difference between the first barrier metal layer 61 and the silicide layer 63 by performing annealing after the first barrier metal layer 61 is formed, or a method of peeling off the first barrier metal layer 61 on the side wall by etching the interlayer insulating film on the side wall under the conditions of etching the interlayer insulating film in wet etching, etc. In addition, step S108 can also be omitted.

[0154] In step S110, a second barrier metal layer 62 is formed on the first barrier metal layer 61. The second barrier metal layer 62 may be formed on the bottom surface and sidewall of the contact hole 54 so as to be stacked with the first barrier metal layer 61. The second barrier metal layer 62 in this example is a TiN film formed by sputtering or CVD (Chemical Vapor Deposition).

[0155] In step S112, the semiconductor substrate 10 is annealed in a nitrogen environment. The annealing temperature can be above 300 degrees and below 1100 degrees. In addition, the environment during the annealing process can also be an environment mixed with oxygen, pressurized, vacuum environment, etc. The annealing of this example is performed after the second barrier metal layer 62 is formed. The annealing of this example can also be performed before the second barrier metal layer 62 is formed. By annealing in step S112, the portion of the first barrier metal layer 61 that contacts the semiconductor substrate 10 is silicided, thereby forming a silicide layer 63.

[0156] In step S114, the plug layer 64 is formed. In this example, tungsten is formed by CVD to fill the inside of the contact hole 54. The barrier layer 60 can function as a metal diffusion prevention layer when the plug layer 64 is formed. By covering the sidewalls and the bottom surface of the contact hole 54 with the barrier layer 60, when the plug layer 64 is formed by CVD, the material gas of the plug layer 64 can be prevented from invading the semiconductor substrate 10 side. In addition, the plug layer 64 may be made of molybdenum or other materials, and the manufacturing method may be sputtering, evaporation, etc.

[0157] In step S116, the plug layer 64 is etched back. Thus, the unnecessary tungsten film outside the contact hole 54 can be removed. The etch back can be performed by dry etching or CMP (Chemical Mechanical Polishing). When removing the tungsten film, the first barrier metal layer 61 and the second barrier metal layer 62 on the interlayer insulating film 38 can also be removed. The first barrier metal layer 61 and the second barrier metal layer 62 on the interlayer insulating film 38 can also be removed by a process different from the etch back of the plug layer 64. The etch back of the barrier layer 60 and the plug layer 64 can be omitted.

[0158] Fig. 6A An example of a method for manufacturing the semiconductor device 100 is shown. Figure 5 The cross section near the contact hole 54 is illustrated in order to show the flow of the manufacturing method.

[0159] In step S104, the contact hole is formed by etching the interlayer insulating film 38. In this example, the interlayer insulating film 38 includes a first interlayer insulating film 381 and a second interlayer insulating film 382. The first interlayer insulating film 381 and the second interlayer insulating film 382 may be formed of different materials. When the first interlayer insulating film 381 and the second interlayer insulating film 382 are formed of different materials, or even when they are the same materials but have different composition ratios, film properties, etc., a step portion 39 is formed on the side wall of the contact hole 54 by using an etching method and etching conditions with different etching speeds. In addition, after the step portion 39 is formed, the height h of the step portion 39 may be reduced or the step portion 39 may be removed by applying an etching method that makes the etching speed of the side with a narrow opening width relatively faster than that of the plurality of interlayer insulating films 38, or by using a reverse sputtering method using argon as an example.

[0160] In step S106, the first barrier metal layer 61 is formed on the sidewalls of the interlayer insulating film 38 and the upper surface of the semiconductor substrate 10. In this example, the first barrier metal layer 61 is formed on the upper surface of the front surface 21. The first barrier metal layer 61 may also be formed on the upper surface of the interlayer insulating film 38.

[0161] The first barrier metal layer 61 is formed by sputtering. Therefore, the film thickness of the first barrier metal layer 61 is formed thicker near the step portion 39 than in other regions. When the second barrier metal layer 62 is formed by sputtering in this state, due to the influence of the first barrier metal layer 61 formed thicker near the step portion 39, the second barrier metal layer 62 may not be formed with a sufficient thickness at a position below the step portion 39.

[0162] Therefore, in step S108, the first region 161 of the first barrier metal layer 61 is etched to reduce the thickness of the first barrier metal layer 61 near the step portion 39. The etching may be wet etching or dry etching such as reverse sputtering using argon.

[0163] Next, in step S110, a second barrier metal layer 62 is formed on the first barrier metal layer 61. The second barrier metal layer 62 in this example is a TiN film formed by sputtering. In this example, since the thickened first barrier metal layer 61 near the step portion 39 in S108 is removed, the second barrier metal layer 62 is also formed with a sufficient thickness at a position below the step portion 39.

[0164] Specifically, when the maximum film thickness of the barrier layer 60 in the first region 161 of the barrier layer 60 which is arranged in contact with the step portion 39 is set to T, and the minimum film thickness of the barrier layer 60 in the second region 162 which is a region lower than the first region 161 and arranged in contact with the side wall of the contact hole 54 is set to t, it can be 0.3T≤t≤0.95T or 0.5T≤t≤0.9T.

[0165] Figure 6B An example of a method for manufacturing the semiconductor device 100 is shown. Figure 5 FIG. 1 is a cross section of the vicinity of the contact hole 54 in a modified example of the flowchart of the manufacturing method shown.

[0166] exist Figure 6B , a manufacturing method is shown that does not include step S108 of etching the first barrier metal layer 61. In this case, as described above, the film thickness of the first barrier metal layer 61 is formed thicker near the step portion 39 than in other regions. Therefore, when the second barrier metal layer 62 is formed by sputtering, the second barrier metal layer 62 may not be sufficiently formed at a position below the step portion 39.

[0167] Here, in step S110, the second barrier metal layer 62 is formed by the CVD method. By forming the second barrier metal layer 62 by the CVD method, the second barrier metal layer 62 can be formed in a manner surrounding the lower side of the first barrier metal layer 61 thickened near the step portion 39, and the film thickness of the barrier layer 60 can be formed uniformly.

[0168] Figure 6C An example of a method for manufacturing the semiconductor device 100 is shown. Figure 5 A cross section of the vicinity of the contact hole 54 in another modified example of the flowchart of the manufacturing method shown.

[0169] exist Figure 6C , a manufacturing method without step S108 of etching the first barrier metal layer 61 is shown. Fig. 6A Compared with the embodiment of Figure 6C In the embodiment of FIG. 5 , the film thickness of the first barrier metal layer 61 is different. Here, the film thickness of the first barrier metal layer 61 refers to the film thickness of the first barrier metal layer 61 measured in a direction perpendicular to the tangent direction of the side wall of the contact hole 54.

[0170] exist Figure 6C The film thickness of the first barrier metal layer 61 formed in step S106′ is greater than that in Fig. 6ASpecifically, the first barrier metal layer 61 formed in step S106 has a thickness of 5 nm to 30 nm, whereas the first barrier metal layer 61 formed in step S106′ has a thickness of 2.5 nm to 20 nm.

[0171] exist Figure 6C In the embodiment of the present invention, since the first barrier metal layer 61 formed in step S106' is thin, Fig. 6A Compared with the case of step S106 in the above process, the film thickness of the first barrier metal layer 61 near the step portion 39 is reduced. Therefore, even if step S108 of etching the first barrier metal layer 61 is omitted, the second barrier metal layer 62 can be formed sufficiently uniformly.

[0172] The present invention has been described above using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It can be clearly known from the description of the claims that such changes or improvements can also be included in the technical scope of the present invention.

[0173] It should be noted that the execution order of the actions, sequences, steps, stages, etc. in the devices, systems, programs, and methods shown in the claims, specifications, and drawings can be implemented in any order unless it is specifically stated that "before...", "prior to...", etc., and the output of the previous process is not used in the subsequent process. Even if the action flow in the claims, specifications, and drawings is described using "first," "next," etc. for convenience, it does not mean that it must be implemented in this order.

Claims

1. A semiconductor device, characterized in that: have: Semiconductor substrates; an interlayer insulating film disposed above the semiconductor substrate and having a contact hole having a step portion on a side wall; and a contact portion disposed in the contact hole, The contact portion has: a barrier layer disposed on the sidewall and bottom surface of the contact hole, The barrier layer has: a first region that contacts the step portion; and a second region that contacts the side wall of the contact hole in a region below the first region, When the film thickness of the thickest portion of the first region in the early stage is T and the film thickness of the thinnest portion of the second region is t, 0.3T≤t≤0.95T is satisfied.

2. The semiconductor device according to claim 1, wherein: The interlayer insulating film has: A first interlayer insulating film provided in contact with the front surface of the semiconductor substrate; as well as a second interlayer insulating film disposed above the first interlayer insulating film, The step portion is formed at a boundary between the first interlayer insulating film and the second interlayer insulating film.

3. The semiconductor device according to claim 1, wherein: The contact portion is a trench contact portion provided so as to extend from the front surface of the semiconductor substrate along the depth direction of the semiconductor substrate.

4. The semiconductor device according to claim 1, wherein: The barrier layer has: A first barrier metal layer disposed on the sidewall in the contact hole; and A second barrier metal layer is stacked on the first barrier metal layer in the contact hole.

5. The semiconductor device according to claim 4, wherein: The second barrier metal layer is thicker than the first barrier metal layer at a position above the step portion.

6. The semiconductor device according to claim 4, wherein: The second barrier metal layer has a film thickness thinner than the first barrier metal layer at a position below the step portion.

7. The semiconductor device according to claim 1, wherein: The film thickness T of the thickest portion of the first region is greater than or equal to 3 nm and less than or equal to 120 nm, and the film thickness t of the thinnest portion of the second region is greater than or equal to 1 nm and less than or equal to 114 nm.

8. The semiconductor device according to claim 4, wherein: The film thickness of the thickest portion of the first barrier metal layer in the first region is greater than or equal to 3 nm and less than or equal to 120 nm.

9. The semiconductor device according to claim 4, wherein: The first barrier metal layer includes any one of Ti, TiN, Ta, and TaN.

10. The semiconductor device according to claim 4, wherein: The second barrier metal layer includes any one of TiN and TaN.

11. The semiconductor device according to claim 1, wherein: The semiconductor device includes a plug layer provided inside the barrier layer in the contact hole.

12. The semiconductor device according to claim 11, wherein: At least one or both of the barrier layer and the plug layer are provided above the interlayer insulating film.

13. The semiconductor device according to claim 11, wherein: The plug layer includes any one of tungsten and molybdenum.

14. The semiconductor device according to claim 1, wherein: The sidewall of the contact hole is in a forward tapered shape.

15. The semiconductor device according to claim 1, wherein: The sidewall of the contact hole is in an inverted tapered shape.

16. The semiconductor device according to claim 1, wherein: A height of the step portion in a direction perpendicular to a tangent direction of the side wall of the contact hole is 15% or less of an opening width of the contact hole at an upper surface of the interlayer insulating film.

17. The semiconductor device according to any one of claims 1 to 16, wherein: The thickness of the barrier layer is greater than or equal to 1 nm and less than or equal to 115 nm above the step portion. The barrier layer has a thickness of not less than 1 nm and not more than 114 nm at a position below the step portion.

18. A method for manufacturing a semiconductor device, characterized in that: have: A step of forming an interlayer insulating film having a contact hole with a stepped portion provided on a side wall above a semiconductor substrate; A stage of providing a barrier layer on the sidewall and bottom of the contact hole; and In the contact hole, at the stage of providing a plug layer inside the barrier layer, The barrier layer has: a first region in contact with the step portion; as well as a second region that contacts the side wall of the contact hole in a region below the first region, When the film thickness of the thickest portion of the first region in the early stage is T and the film thickness of the thinnest portion of the second region is t, 0.3T≤t≤0.95T is satisfied.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: The stages of setting the barrier layer include: In the contact hole, a first barrier metal layer is provided on the side wall and the bottom surface; and A stage in which a second barrier metal layer is provided in the contact hole so as to be stacked on the first barrier metal layer.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: There is a stage of etching the first region after the stage of providing the first barrier metal layer and before the stage of providing the second barrier metal layer.

21. The method for manufacturing a semiconductor device according to claim 19, wherein: The film thickness of the thickest portion of the first barrier metal layer in the first region is greater than or equal to 3 nm and less than or equal to 120 nm.

22. The method for manufacturing a semiconductor device according to any one of claims 18 to 21, characterized in that: The barrier layer is formed by a sputtering method.

23. The method for manufacturing a semiconductor device according to claim 18, wherein: The plug layer is formed by a CVD method.

24. The method for manufacturing a semiconductor device according to claim 19, wherein: The second barrier metal layer is formed by a CVD method.

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