Thin film transistor and method for manufacturing thin film transistor

Abstract

The invention relates to a thin film transistor and a manufacturing method of the thin film transistor. A manufacturing method of a thin film transistor according to one embodiment may include the steps of: forming a diffusion channel layer on a substrate; forming at least one groove in the diffusion channel layer; forming a diffusion barrier layer in the groove; forming an active layer on the diffusion channel layer and the diffusion barrier layer; forming a source electrode and a drain electrode on the active layer; forming a gate insulating layer between the source electrode and the drain electrode; forming a gate on the gate insulating layer; and performing heat treatment.

Description

Technical Field

[0001] The present invention relates to a thin film transistor and a method for manufacturing the thin film transistor, and in particular to an oxide thin film transistor and a method for manufacturing the oxide thin film transistor. Background Art

[0002] Thin Film Transistor (TFT) is a field effect transistor (FET) manufactured by stacking a semiconductor thin film on an insulating substrate. A thin film transistor (TFT) includes three electrodes (e.g., source, drain, gate) and an active layer (or channel layer) in the form of a thin film disposed between the two electrodes. When voltage is applied to the gate electrode, holes will gather between the source electrode and the drain electrode and form a channel, so that current will flow from the source electrode to the drain electrode. Thin Film Transistor (TFT) is used in display devices such as liquid crystal displays (LCD) or organic light emitting diodes (OLED).

[0003] As examples of materials constituting the active layer of a thin film transistor (TFT), amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), and oxide (Oxide) can be cited. A thin film transistor (TFT) whose active layer is composed of an oxide is called an oxide thin film transistor. As an example of an oxide used for an oxide thin film transistor, indium-gallium-zinc-oxide (In-Ga-Zn-O, IGZO) can be cited. In recent years, various technologies for improving the electrical characteristics of oxide thin film transistors and improving the performance and reliability of oxide thin film transistors are being studied.

[0004] Related prior arts include Korean Patent Publication No. 10-2016-0131339 and Korean Patent Publication No. 10-2022-004795. Summary of the invention

[0005] Technical issues

[0006] An object of the present invention is to provide a thin film transistor and a method for manufacturing the thin film transistor having improved electrical characteristics, performance and reliability compared with the prior art.

[0007] The purpose of the present invention is not limited to the purpose mentioned above, and other purposes and advantages of the present invention not mentioned can be more clearly understood through the embodiments of this specification as described below. In addition, the purposes and advantages of the present invention can be achieved through the structural elements and their combinations recorded in the claims of this specification.

[0008] Solutions to the problem

[0009] According to one embodiment, a thin film transistor may include: a substrate; a diffusion channel layer, arranged on the above substrate; an active layer, arranged on the above diffusion channel layer; a source and a drain, arranged on the above active layer; a gate insulating layer, arranged between the above source and the above drain; a gate, arranged on the above gate insulating layer; and a diffusion barrier layer, formed in the above diffusion channel layer at a position corresponding to the above source and the above drain.

[0010] According to one embodiment, a method for manufacturing a thin film transistor may include the following steps: forming a diffusion channel layer on a substrate; forming at least one groove in the diffusion channel layer; forming a diffusion barrier layer inside the groove; forming an active layer on the diffusion channel layer and the diffusion barrier layer; forming a source and a drain on the active layer; forming a gate insulating layer between the source and the drain; forming a gate on the gate insulating layer; and performing heat treatment.

[0011] Effects of the Invention

[0012] According to the embodiment, during the manufacturing process of the thin film transistor, oxygen is additionally supplied to the active layer through the diffusion barrier layer and the diffusion channel layer in a restricted manner to reduce oxygen vacancies causing defects in the active layer, thereby improving the reliability of the thin film transistor.

[0013] According to the embodiment, a diffusion barrier layer having different density distributions is formed during the manufacturing process of a thin film transistor, thereby having an advantage that the permeability of a reaction substance contained in a reaction gas can be selectively adjusted.

[0014] According to the embodiment, a passivation layer is formed on an active layer during the manufacturing process of a thin film transistor, thereby having the advantage of reducing a thermal budget to stably improve charge mobility without causing thermal damage.

[0015] According to the embodiment, charge traps existing in the passivation layer of the active layer are passivated by hydrogen during the manufacturing process of the thin film transistor, thereby having the advantages of reducing the charge density of the passivation layer and improving the charge mobility.

[0016] According to the embodiment, a high-pressure heat treatment process is performed in a low-temperature environment during the manufacturing process of a thin film transistor, thereby having advantages of preventing degradation of a portion susceptible to heat and improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The structure of the thin film transistor according to the first embodiment is shown.

[0018] Figure 2 A moving path of ions in a reaction gas based on heat treatment in the manufacturing process of the thin film transistor according to the first embodiment is shown.

[0019] Figure 3 The structure of a thin film transistor according to the second embodiment is shown.

[0020] Figure 4 for Figure 3 An enlarged view of part A is shown.

[0021] Figure 5 FIG. 1 is a diagram showing the movement path of ions in a reaction gas based on heat treatment in the manufacturing process of the thin film transistor according to the second embodiment.

[0022] Figure 6 The structure of a thin film transistor according to the third embodiment is shown.

[0023] Figure 7 for Figure 6 An enlarged view of part B is shown.

[0024] Figure 8 FIG. 1 is a diagram showing movement paths of ions in a reaction gas based on heat treatment in a process of manufacturing a thin film transistor according to the third embodiment.

[0025] Figures 9 to 15 A manufacturing process of the thin film transistor according to the third embodiment is shown.

[0026] Fig.16 FIG. 1 is a flow chart showing a method for manufacturing a thin film transistor according to an embodiment.

[0027] Fig.17 1 is a diagram showing the driving current I of the thin film transistor manufactured according to the first embodiment and the thin film transistor that has not been heat treated during the manufacturing process. on and the shutdown current I off of charts. DETAILED DESCRIPTION

[0028] Hereinafter, with reference to the accompanying drawings, the preferred embodiments of the present invention will be described in detail. However, the technical concept of the present invention is not limited to the embodiments described herein, and it can be embodied in other forms. On the contrary, the embodiments introduced herein are provided to make the disclosure thorough and complete and to fully convey the concept of the present invention to ordinary technicians in the technical field to which the present invention belongs.

[0029] In this specification, when it is mentioned that a structural element is formed on another structural element, it means that the structural element can be directly formed on the other structural element or a third structural element is interposed therebetween. In addition, in the drawings, the shapes and sizes of the structural elements may be exaggerated in order to effectively illustrate the technical content.

[0030] Furthermore, in various embodiments of this specification, the terms first, second, third, etc. are used to describe various structural elements, but these structural elements should not be limited by these terms. These terms are only used to distinguish one structural element from another structural element. Therefore, a structural element referred to as a first structural element in one embodiment may be referred to as a second structural element in another embodiment. The various embodiments described and illustrated herein include their complementary embodiments. Furthermore, in this specification, "and / or" is used with the meaning of including at least one of the structural elements listed before and after.

[0031] In the specification, unless the context clearly indicates otherwise, singular expressions include plural expressions. Furthermore, terms such as "including" or "having" indicate that the features, numbers, steps, structural elements or their combinations recorded in this specification are present, but should not be understood to exclude the possibility of the presence or addition of one or more other features or numbers, steps, structural elements or their combinations. Furthermore, in this specification, "connected" includes the case of indirectly connecting multiple structural elements as well as directly connecting multiple structural elements.

[0032] Furthermore, in the following description of the present invention, if it is determined that the detailed description of a well-known function or structure may unnecessarily obscure the gist of the present invention, the detailed description will be omitted.

[0033] Hereinafter, for convenience of explanation, the first direction represents the X axis of the Cartesian coordinate system, and the second direction represents the Z axis of the Cartesian coordinate system. In this case, the first direction is orthogonal to the second direction.

[0034] Figure 1 The structure of the thin film transistor according to the first embodiment is shown. And, Figure 2 A moving path of ions in a reaction gas based on heat treatment in the manufacturing process of the thin film transistor according to the first embodiment is shown.

[0035] The thin film transistor 10 according to the first embodiment may include substrates 110 and 120 , a diffusion channel layer 200 , a metal oxide active layer 300 , a source electrode 400 , a drain electrode 500 , a gate insulating layer 600 , a gate 700 , and a diffusion barrier layer 800 .

[0036] The substrates 110 , 120 may include a base substrate layer 110 and a buffer substrate layer 120 .

[0037] The substrate layer 110 may be a single crystal substrate. A single crystal semiconductor layer may be formed on at least one surface of the substrate layer 110. The single crystal semiconductor layer may be made of any one of silicon (Si), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), indium antimonide (InSb), gallium arsenide (GaAs, III-V semiconductor), gallium phosphide (GaP), indium aluminum arsenic (InAlAs), indium gallium arsenic (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimony (GaAsSb) and indium phosphide (InP), but the constituent material of the single crystal semiconductor layer is not limited thereto.

[0038] To minimize lattice stress, the buffer substrate layer 120 may have a different lattice constant than the base substrate layer 110. In yet another embodiment, the lattice constant and / or crystal structure of the buffer substrate layer 120 may be the same or similar to that of the base substrate layer 110.

[0039] The buffer substrate layer 120 may be a crystalline material formed by epitaxial growth on the base substrate layer 110. The base substrate layer 110 may be doped with impurities of a material different from the base substrate layer 110 to form the buffer substrate layer 120. In one embodiment, a higher-layer buffer substrate layer 120 may be relatively more heavily doped than the base substrate layer 110.

[0040] The lattice constant of each layer may be different in the buffer substrate layer 120. For example, the lattice constant of the buffer substrate layer 120 may gradually increase from a bottom layer to a higher layer.

[0041] The diffusion channel layer 200 may be disposed on the substrates 110 and 120. The diffusion channel layer 200 may also be referred to as a diffusion layer.

[0042] The diffusion channel layer 200 may serve as a channel for the ionized reaction gas provided during the heat treatment of the active layer 300. That is, when the heat treatment is performed, ions generated from the reaction gas may pass through the diffusion channel layer 200. The ionized reaction gas according to one embodiment may include at least one of oxygen ions, hydrogen ions, fluorine ions, and nitrogen ions, but the type of the ionized reaction gas is not limited thereto.

[0043] The diffusion channel layer 200 may be made of oxide such as silicon dioxide (SiO 2 ), but the type of material constituting the diffusion channel layer 200 is not limited thereto.

[0044] The diffusion channel layer 200 may be disposed between the substrates 110 and 120 and the active layer 300. The diffusion channel layer 200 allows the ionized reaction gas supplied from the outside to pass therethrough.

[0045] The diffusion channel layer 200 may be an oxide. Also, the diffusion channel layer 200 may be a low-k dielectric. In one embodiment, the diffusion channel layer 200 may be silicon dioxide (SiO2), but the type of the diffusion channel layer 200 is not limited thereto.

[0046] In one embodiment, the diffusion channel layer 200 may have a thickness of 20 nm to 50 nm.

[0047] In one embodiment, oxygen (O2) or ozone (O3) may be provided as a reaction gas during the heat treatment. In this case, the diffusion channel layer 200 may function as a tunnel through which oxygen ions pass.

[0048] In one embodiment, hydrogen (H2) or deuterium (D2) may be provided as a reaction gas during the heat treatment. In this case, the diffusion channel layer 200 may function as a tunnel through which hydrogen ions pass.

[0049] In another embodiment, during the heat treatment, a reaction gas containing fluorine (F x ) or nitrogen (N x In this case, the diffusion channel layer 200 may be used as a tunnel through which fluorine ions or nitrogen ions pass.

[0050] The active layer 300 may be configured to directly contact the source electrode 400 and the drain electrode 500. The active layer 300 may be electrically connected to the source electrode 400 and the drain electrode 500, respectively.

[0051] The active layer 300 may be a channel region, which is a moving channel for carriers such as holes or electrons. Therefore, the active layer 300 may also be called a channel layer.

[0052] In order to prevent carriers of the active layer 300 from passing through the gate insulating layer 600 and entering the gate 700 when a voltage is applied to the gate 700 , the active layer 300 may be made of a thin film of a high-k dielectric.

[0053] In one embodiment, the active layer 300 may be made of an oxide semiconductor material based on zinc oxide (ZnO).

[0054] In one embodiment, in addition to zinc (Zn), the active layer 300 may further include at least indium (In), gallium (Ga), tin (Sn) or aluminum (Al). For example, the active layer 300 may include at least one of indium-gallium-zinc-oxide (In-Ga-Zn-O, IGZO), indium-tin-zinc-oxide (In-Sn-Zn-O, ISZO), indium-aluminum-zinc-oxide (In-Al-Zn-O, IAZO), tin-aluminum-zinc-oxide (Sn-Al-Zn-O, SAZO) and tin-zinc-oxide (Sn-Zn-O, SZO).

[0055] In one embodiment, the thickness of the active layer 300 may be 8 nm to 12 nm. Preferably, the thickness of the active layer 300 may be 10 nm.

[0056] In one embodiment, the active layer 300 may be formed by a vacuum evaporation process or a solution process. The active layer 300 may be formed by an evaporation process (e.g., physical vapor deposition (PVD) such as sputtering, atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), etc.) or by a solution process (e.g., sol-gel method, colloidal particle method, etc.).

[0057] A passivation layer 310 may be formed at one side of the active layer 300 .

[0058] like Figure 2 As shown, when the diffusion barrier layer 800 is formed in a part of the diffusion channel layer 200, a tunnel through which ions contained in the reaction gas can pass may be formed in the diffusion channel layer 200. Figure 2 In the embodiment, a region of the diffusion channel layer 200 located between two diffusion barrier layers 800 may be defined as a tunnel. In a state where the diffusion channel layer 200 forms a tunnel for ion movement, a heat treatment may be performed in a reaction gas environment to form the passivation layer 310 .

[0059] In one embodiment, the reaction gas may include at least one of oxygen, hydrogen, fluorine, and nitrogen.

[0060] In one embodiment, the passivation layer 310 may be formed by performing a heat treatment in a high-pressure oxygen environment. In another embodiment, the passivation layer 310 may be formed by performing a heat treatment in a high-pressure hydrogen environment. In yet another embodiment, the passivation layer 310 may be formed by performing a first heat treatment in a high-pressure oxygen environment and then performing a second heat treatment in a high-pressure hydrogen environment.

[0061] When the heat treatment is performed in an oxygen atmosphere, oxygen vacancies present in the active layer 300 are reduced, that is, defects are reduced.

[0062] In one embodiment, when the heat treatment is performed in an oxygen environment, the oxygen pressure may be 2 atm to 50 atm. In another embodiment, when the heat treatment is performed in an oxygen environment, the oxygen pressure may be 5 atm to 20 atm.

[0063] In one embodiment, the heat treatment in the oxygen environment may be performed at a temperature ranging from 100° C. to 600° C. In another embodiment, the heat treatment in the oxygen environment may be performed at a temperature ranging from 200° C. to 400° C.

[0064] When heat treatment is performed in a hydrogen atmosphere, oxygen vacancies or charge traps present in the active layer 300 and / or the passivation layer 310 may be passivated by hydrogen ions. Thus, the charge density of the oxide thin film transistor 10 (TFT) is reduced and the charge mobility is increased.

[0065] In one embodiment, when the heat treatment is performed in a hydrogen environment, the hydrogen pressure may be 2 atm to 50 atm. In another embodiment, when the heat treatment is performed in a hydrogen environment, the hydrogen pressure may be 5 atm to 20 atm.

[0066] In one embodiment, the heat treatment in the hydrogen environment may be performed at a temperature ranging from 100° C. to 600° C. In another embodiment, the heat treatment in the hydrogen environment may be performed at a temperature ranging from 200° C. to 400° C.

[0067] When the passivation layer 310 is formed, oxygen vacancies (Oxygen Vacancy) of the active layer 300 may be reduced. When oxygen vacancies are reduced, charge mobility increases, and thus the threshold voltage (Vth) of the oxide thin film transistor 10 (TFT) may be reduced.

[0068] The passivation layer 310 may be locally formed in one region of the active layer 300. The formation region of the passivation layer 310 may be determined by the configuration relationship between the diffusion channel layer 200 and the diffusion barrier layer 800. For example, the position or area of ​​the passivation layer 310 may vary according to the proportion of the diffusion barrier layer 800 in the diffusion channel layer 200 or the position, cross-sectional area or volume of the diffusion barrier layer 800.

[0069] The active layer 300 may be divided into a source region S, a gate region G, and a drain region D. The source region S is a region in contact with the source 400 , the gate region G is a region in contact with the gate insulating layer 600 , and the drain region D is a region in contact with the drain 500 .

[0070] The crystal structures of the active layer 300 may be different in the source region S, the drain region D, and the gate region G. The material constituting the gate region G may be relatively stable compared to the material constituting the source region S or the drain region D. Furthermore, as the source region S or the drain region D is adjacent to the gate region G, the combination of the materials constituting the source region S or the drain region D may be relatively stable.

[0071] When the active layer 300 is formed by the method for manufacturing the thin film transistor 10 according to an embodiment, the switching ratio of the thin film transistor 10 is on / I off The on / off ratio can be greater than that of the prior art.

[0072] The source electrode 400 and the drain electrode 500 may be respectively formed on the active layer 300. The source electrode 400 and the drain electrode 500 may be in direct contact with the active layer 300, respectively.

[0073] The source 400 and the drain 500 may be arranged to be spaced apart from each other. The source 400 may be arranged to face the drain 500 in the first direction. The source 400 may be used as a source electrode. The drain 500 may be used as a drain electrode.

[0074] The source electrode 400 and the drain electrode 500 may electrically connect respective ends of the active layer 300. According to an embodiment, the positions or roles of the source electrode 400 and the drain electrode 500 may be interchanged.

[0075] The gate insulating layer 600 may be disposed between the source electrode 400 and the drain electrode 500. The gate insulating layer 600 may insulate the gate electrode 700 from the active layer 300, the source electrode 400, and the drain electrode 500. The gate insulating layer 600 may prevent parasitic coupling of the substrates 110 and 120 through the gate electrode 700. When the thin film transistor 10 is conducting, the gate insulating layer 600 may prevent an undesirable conducting channel from being formed in the substrates 110 and 120.

[0076] In one embodiment, the gate insulating layer 600 may be made of aluminum oxide (Al 2 O 3 ), but the type of material constituting the gate insulating layer 600 is not limited thereto.

[0077] The gate insulating layer 600 may be formed by an evaporation process. In one embodiment, the gate insulating layer 600 may have a thickness of 10 nm to 20 nm, and preferably, the thickness may be 15 nm.

[0078] The gate 700 may be disposed in the gate insulating layer 600. The gate 700 may be used as a gate electrode for controlling the flow of current through the active layer 300. In the gate region G, the gate 700 may face the active layer 300.

[0079] The gate electrode 700 may be insulated from the source electrode 400 , the drain electrode 500 , and the active layer 300 by the gate insulating layer 600 .

[0080] The gate 700 may be disposed between the source 400 and the drain 500. In one embodiment, the gate 700 may be made of a metal material, such as tin (TiN) and tungsten (W).

[0081] The gate electrode 700 may be formed by an evaporation process, and the length of the gate electrode 700 may be determined by the thickness of the gate insulating layer 600 and the lengths of the source electrode 400 and the drain electrode 500 .

[0082] The diffusion barrier layer 800 may face the source electrode 400 and the drain electrode 500 in the second direction. The diffusion barrier layer 800 may be disposed under the active layer 300. The diffusion barrier layer 800 may be disposed in a manner corresponding to the source region S and the drain region D, respectively.

[0083] Compared with the diffusion channel layer 200, the diffusion barrier layer 800 may be made of a material with a dense structure and high hardness. For example, the diffusion barrier layer 800 may be made of silicon nitride (Si Nitride, Si x N y ). In this case, x may satisfy 1≤x≤3, and y may satisfy 1≤y≤4. For example, the diffusion barrier layer 800 may be made of Si3N4. When the diffusion barrier layer 800 is made of silicon nitride (Si3N4) with a dense structure and high hardness, ions generated from the reaction gas may not be able to pass through the diffusion barrier layer 800. The diffusion barrier layer 800 is arranged at positions corresponding to the source region S and the drain region D, respectively, so as to prevent ions generated from the reaction gas from being injected into the source 400 and the drain 500.

[0084] Therefore, when the heat treatment is performed, ions (e.g., oxygen, hydrogen, fluorine, or nitrogen ions) generated from the reaction gas may not pass through the diffusion barrier layer 800. However, according to an embodiment, a portion of the ions (e.g., oxygen, hydrogen, fluorine, or nitrogen ions) included in the reaction gas may also pass through the diffusion barrier layer 800.

[0085] In one embodiment, when heat treatment is performed together with the reaction gas, the amount of ions directly injected into the active layer 300 through the tunnel formed in the diffusion channel layer 200 may be greater than the amount of ions injected into the active layer 300 through the diffusion barrier layer 800 .

[0086] That is, when the heat treatment is performed together with the reaction gas, the movement path of ions included in the reaction gas, the amount of ions implanted into the active layer 300 , or the implantation position of the ions may be adjusted by the diffusion barrier layer 800 .

[0087] Figure 3 The structure of a thin film transistor according to the second embodiment is shown. Figure 4 for Figure 3 An enlarged view of part A is shown. Figure 5 FIG. 1 shows the movement path of ions in a reaction gas by heat treatment in the manufacturing process of the thin film transistor according to the second embodiment.

[0088] The thin film transistor 10 according to the second embodiment may include substrates 110 and 120, a diffusion channel layer 200, a metal oxide active layer 300, a source electrode 400, a drain electrode 500, a gate insulating layer 600, a gate electrode 700, and a diffusion barrier layer 800. The structure of the thin film transistor 10 according to the second embodiment is the same as that of the thin film transistor 10 according to the first embodiment except for the diffusion barrier layer 800. Therefore, hereinafter, except for the diffusion barrier layer 800, the description of other structural elements will be omitted.

[0089] The diffusion barrier layer 800 may face the source electrode 400 and the drain electrode 500 in the second direction. The diffusion barrier layer 800 may be disposed at the lower portion of the active layer 300. The diffusion barrier layer 800 may be disposed in a manner corresponding to the source region S and the drain region D, respectively.

[0090] The diffusion barrier layer 800 may be made of a material having a dense structure and high hardness compared to the diffusion channel layer 200. Therefore, when the heat treatment is performed, ions (e.g., oxygen, hydrogen, fluorine, or nitrogen ions) contained in the reaction gas may not pass through the diffusion barrier layer 800. However, according to an embodiment, a portion of the ions (e.g., oxygen, hydrogen, fluorine, or nitrogen ions) contained in the reaction gas may also pass through the diffusion barrier layer 800.

[0091] In the first embodiment described above, the diffusion barrier layer 800 is composed of a single layer. However, in another embodiment, the diffusion barrier layer 800 may be composed of multiple layers. For example, Figures 3 to 5 As shown, the diffusion barrier layer 800 according to the second embodiment may include a first diffusion barrier layer 810 and a second diffusion barrier layer 820 .

[0092] The first diffusion barrier layer 810 and the second diffusion barrier layer 820 may be made of different substances. According to an embodiment, the first diffusion barrier layer 810 and the second diffusion barrier layer 820 may also be made of the same kind of substance with different densities.

[0093] The ion permeability of the first diffusion barrier layer 810 and the ion permeability of the second diffusion barrier layer 820 may be different from each other. In one embodiment, the ion permeability of the second diffusion barrier layer 820 may be relatively smaller than the ion permeability of the first diffusion barrier layer 810 .

[0094] Furthermore, the density of the first diffusion barrier layer 810 may be different from the density of the second diffusion barrier layer 820. In one embodiment, the density of the second diffusion barrier layer 820 may be relatively greater than the density of the first diffusion barrier layer 810.

[0095] In one embodiment, the second diffusion barrier layer 820 may have a relatively dense structure compared to the first diffusion barrier layer 810. In one embodiment, the hardness of the second diffusion barrier layer 820 may be relatively greater than the hardness of the first diffusion barrier layer 810.

[0096] In one embodiment, the first diffusion barrier layer 810 may be made of a first material. The first material may be silicon oxynitride (Silicon OxiNitride, Si x O y N z ). In this case, x may satisfy 1≤x≤3, y may satisfy 1≤y≤2, and z may satisfy 1≤z≤3. For example, the first diffusion barrier layer 810 may be SiON or Si2ON2.

[0097] The first diffusion barrier layer 810 may surround the trench T (see Fig.10 ) inner wall. The first diffusion barrier layer 810 may be formed by an evaporation process (e.g., physical vapor deposition (PVD) such as sputtering, atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), etc.), or by a solution process (e.g., sol-gel method, colloidal particle method, etc.). The first diffusion barrier layer 810 may also be formed by a low pressure chemical vapor deposition method (LPCVD).

[0098] In one embodiment, the second diffusion barrier layer 820 may be made of a second material. The second material may be silicon nitride (Si x N y ). In this case, x may satisfy 1≤x≤3, and y may satisfy 1≤y≤4. For example, the second diffusion barrier layer 820 may be Si3N4.

[0099] The second diffusion barrier layer 820 can be formed in a manner of filling the groove-shaped space formed inside the first diffusion barrier layer 810. The second diffusion barrier layer 820 can be formed by an evaporation process (e.g., physical vapor deposition (PVD) such as sputtering, atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), etc.), or by a solution process (e.g., sol-gel method, colloidal particle method, etc.). The second diffusion barrier layer 820 can also be formed by low pressure chemical vapor deposition (LPCVD).

[0100] Reference Figure 4 The diffusion barrier layer 800 may be divided into two regions U in the first direction. a , U b . The first area U a is a region corresponding to the first diffusion barrier layer 810, and the second region U b It is a region corresponding to the second diffusion barrier layer 820 and the first diffusion barrier layer 810 .

[0101] First Area U a The ion permeability of the second region U b The ion permeability of the first region U may be different from each other. a The density of the second region U b The density can be different.

[0102] In the diffusion barrier layer 800 according to one embodiment, each region U a , U b can have different density distributions. For example, Figure 4 In the first area U a Made of a single substance, but in the second region U b In the second region U, the layers are made of two different substances. b In the embodiment, the layered structure may be formed by a first diffusion barrier layer 810 and a second diffusion barrier layer 820, wherein the second diffusion barrier layer 820 is made of a material having a higher density than the first diffusion barrier layer 810. In this case, the first region U a The ion permeability of the second region U b ion permeability.

[0103] According to an embodiment, ions can pass through the first region U a , but the ions may not pass through the second region U b .

[0104] Figure 6 The structure of a thin film transistor according to the third embodiment is shown. Figure 7 for Figure 6 An enlarged view of part B is shown. Figure 8 FIG. 1 shows the movement path of ions in a reaction gas by heat treatment in the manufacturing process of the thin film transistor according to the third embodiment.

[0105] The thin film transistor 10 according to the third embodiment may include substrates 110, 120, a diffusion channel layer 200, a metal oxide active layer 300, a source electrode 400, a drain electrode 500, a gate insulating layer 600, a gate electrode 700, and a diffusion barrier layer 800. The structure of the thin film transistor 10 according to the third embodiment is the same as the structure of the thin film transistor 10 according to the first embodiment or the second embodiment except for the diffusion barrier layer 800. Therefore, hereinafter, except for the diffusion barrier layer 800, the description of other structural elements will be omitted.

[0106] The diffusion barrier layer 800 may face the source electrode 400 and the drain electrode 500 in the second direction. The diffusion barrier layer 800 may be disposed at the lower portion of the active layer 300. The diffusion barrier layer 800 may be disposed in a manner corresponding to the source region S and the drain region D, respectively.

[0107] The diffusion barrier layer 800 may be made of a material having a dense structure and high hardness compared to the diffusion channel layer 200. Therefore, when the heat treatment is performed, ions (e.g., oxygen, hydrogen, fluorine, or nitrogen ions) contained in the reaction gas may not pass through the diffusion barrier layer 800. However, according to an embodiment, a portion of the ions (e.g., oxygen, hydrogen, fluorine, or nitrogen ions) contained in the reaction gas may also pass through the diffusion barrier layer 800.

[0108] In the first embodiment described above, the diffusion barrier layer 800 is composed of a single layer. However, in another embodiment, the diffusion barrier layer 800 may be composed of a plurality of layers. Figures 6 to 8 As shown, the diffusion barrier layer 800 according to the third embodiment may include a first diffusion barrier layer 830, a second diffusion barrier layer 840, and a third diffusion barrier layer 850. However, according to embodiments, the diffusion barrier layer 800 may also be composed of four or more layers.

[0109] The first diffusion barrier layer 830, the second diffusion barrier layer 840, and the third diffusion barrier layer 850 may be made of different materials, but according to embodiments, the first diffusion barrier layer 830, the second diffusion barrier layer 840, and the third diffusion barrier layer 850 may also be made of the same material with different densities.

[0110] The ion permeability of the first diffusion barrier layer 830, the ion permeability of the second diffusion barrier layer 840, and the ion permeability of the third diffusion barrier layer 850 may be different from each other. For example, the ion permeability of the third diffusion barrier layer 850 may be relatively smaller than the ion permeability of the first diffusion barrier layer 830 and the ion permeability of the second diffusion barrier layer 840, and the ion permeability of the second diffusion barrier layer 820 may be relatively smaller than the ion permeability of the first diffusion barrier layer 810.

[0111] Furthermore, the density of the first diffusion barrier layer 830, the density of the second diffusion barrier layer 840, and the density of the third diffusion barrier layer 850 may be different from each other. For example, the density of the third diffusion barrier layer 850 may be relatively greater than the density of the first diffusion barrier layer 830 and the density of the second diffusion barrier layer 840, and the density of the second diffusion barrier layer 840 may be relatively greater than the density of the first diffusion barrier layer 830.

[0112] In one embodiment, the third diffusion barrier layer 850 may have a relatively dense structure compared to the first diffusion barrier layer 830 and the second diffusion barrier layer 840 , and the structure of the second diffusion barrier layer 840 is relatively denser than that of the first diffusion barrier layer 830 .

[0113] In one embodiment, the hardness of the third diffusion barrier layer 850 may be relatively greater than the hardness of the first diffusion barrier layer 830 and the second diffusion barrier layer 840 , and the hardness of the second diffusion barrier layer 820 may be relatively greater than the hardness of the first diffusion barrier layer 810 .

[0114] In one embodiment, the first diffusion barrier layer 830 may be made of a first material. The first material may be silicon oxynitride (Silicon OxiNitride, Si x O y N z ). In this case, x may satisfy 1≤x≤3, y may satisfy 1≤y≤2, and z may satisfy 1≤z≤3. For example, the first diffusion barrier layer 810 may be SiON or Si2ON2.

[0115] The first diffusion barrier layer 830 may surround the trench T (see Fig.10 ) inner wall. The first diffusion barrier layer 830 may be formed by an evaporation process (e.g., physical vapor deposition (PVD) such as sputtering, atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), etc.), or by a solution process (e.g., sol-gel method, colloidal particle method, etc.). The first diffusion barrier layer 830 may also be formed by a low pressure chemical vapor deposition method (LPCVD).

[0116] In one embodiment, the second diffusion barrier layer 840 may be made of a second material. The second material may be silicon nitride (Si x N y ). In this case, x may satisfy 1≤x≤3, and y may satisfy 1≤y≤4. For example, the second diffusion barrier layer 840 may be Si3N4.

[0117] The second diffusion barrier layer 840 can be formed in a manner of filling the inner wall of the first diffusion barrier layer 830 in the shape of a groove. The second diffusion barrier layer 840 can be formed by an evaporation process (for example, physical vapor deposition (PVD) such as sputtering, atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), etc.), or by a solution process (for example, sol-gel method, colloidal particle method, etc.). The second diffusion barrier layer 840 can also be formed by low pressure chemical vapor deposition (LPCVD).

[0118] In one embodiment, the third diffusion barrier layer 850 may be made of a third material. The third material may be silicon nitride (Si x N y ). In this case, x may satisfy 1≤x≤2, and y may satisfy 1≤y≤2. For example, the third diffusion barrier layer 850 may be SiN or Si2N.

[0119] The third diffusion barrier layer 850 can be formed in a manner of filling the groove-shaped space formed inside the second diffusion barrier layer 840. The third diffusion barrier layer 850 can be formed by an evaporation process (e.g., physical vapor deposition (PVD) such as sputtering, atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), etc.), or by a solution process (e.g., sol-gel method, colloidal particle method, etc.). The third diffusion barrier layer 850 can also be formed by low pressure chemical vapor deposition (LPCVD).

[0120] Reference Figure 7 The diffusion barrier layer 800 may be divided into three regions U in the first direction. a , U b , U c . The first area U a is a region corresponding to the first diffusion barrier layer 830, and the second region U b The third region U is a region corresponding to the second diffusion barrier layer 840 and the first diffusion barrier layer 830. c These are regions corresponding to the third diffusion barrier layer 850 , the second diffusion barrier layer 840 , and the first diffusion barrier layer 830 .

[0121] First Area U a Ion permeability of the second region U b Ion permeability of the third region U c The ion permeability of the first region U may be different from each other. a The density of the second region U b The density of the third region U cThe density can be different.

[0122] In the diffusion barrier layer 800 according to one embodiment, each region U a , U b , U c can have different density distributions. For example, Figure 4 In the first area U a Made of a single substance, but in the second region U b In the third region U, the layers can be made of two different materials. c In the second region U, the layers can be made of three different materials. b In the third region U, the layered structure may be formed by a first diffusion barrier layer 830 and a second diffusion barrier layer 840, wherein the second diffusion barrier layer 840 is made of a material having a higher density than the first diffusion barrier layer 830. c In the embodiment, the layered structure may be formed by a first diffusion barrier layer 830, a second diffusion barrier layer 840, and a third diffusion barrier layer 850, wherein the second diffusion barrier layer 840 is made of a material having a higher density than the first diffusion barrier layer 830, and the third diffusion barrier layer 850 is made of a material having a higher density than the second diffusion barrier layer 840. In this case, the first region U a The ion permeability of the second region U b Ion permeability and the third region U c Ion permeability, the second region U b The ion permeability of the third region U c ion permeability.

[0123] According to an embodiment, ions can pass through the first region U a , but the ions may not pass through the second region U b or the third area U c In another embodiment, ions can pass through the first region U a and the second region U b , but the ions may not pass through the third region U c .

[0124] Figures 9 to 15 A manufacturing process of the thin film transistor according to the third embodiment is shown. Fig.16 FIG. 1 is a flow chart showing a method for manufacturing a thin film transistor according to an embodiment.

[0125] First, refer to Fig. 9 and Fig.16 , a diffusion channel layer 200 is formed on the substrates 110 and 120 (step S10). For example, the diffusion channel layer 200 may be made of an oxide such as silicon dioxide (SiO2) and formed by evaporation.

[0126] Afterwards, refer to Fig.10 and Fig.16 , selectively removing any region of the diffusion channel layer 200, thereby forming at least one trench T (step S20). For example, the trench T may be formed by selective etching.

[0127] Afterwards, refer to Fig.11 and Fig.16 , a diffusion barrier layer 800 is formed inside the trench T formed in the diffusion channel layer 200 (step S30 ). Fig.11 The diffusion barrier layer 800 including the first diffusion barrier layer 830, the second diffusion barrier layer 840, and the third diffusion barrier layer 850 according to the third embodiment is shown. In this case, the first diffusion barrier layer 830, the second diffusion barrier layer 840, and the third diffusion barrier layer 850 may be sequentially formed inside the trench T.

[0128] In the process of forming the diffusion barrier layer (step S30), when the diffusion barrier layer 800 according to the second embodiment is formed, the first diffusion barrier layer 810 and the second diffusion barrier layer 820 may be sequentially formed inside the trench T. In the process of forming the diffusion barrier layer (step S30), when the diffusion barrier layer 800 according to the first embodiment is formed, a single substance may be filled inside the trench T, thereby forming the diffusion barrier layer 800.

[0129] Afterwards, refer to Fig.12 and Fig.16 , an active layer 300 is formed on the diffusion channel layer 200 and the diffusion barrier layer 800 (step S40). For example, the active layer 300 may be formed by a vacuum evaporation process or a solution process.

[0130] Afterwards, refer to Fig.13 and Fig.16 , a source electrode 400 may be formed in the source region S on the active layer 300 and a drain electrode 500 may be formed in the drain region D on the active layer 300 (step S50). The order of forming the source electrode 400 and the drain electrode 500 may vary according to the embodiment. The same material as the diffusion channel layer 200 (e.g., silicon dioxide (SiO2)) may be configured on one side of the source electrode 400 and the drain electrode 500.

[0131] Furthermore, a gate insulating layer 600 is formed in the gate region G on the active layer 300 (step S60). The gate insulating layer 600 may be formed between the source 400 and the drain 500. The source 400 and the drain 500 may be arranged side by side with the gate insulating layer 600 in the first direction.

[0132] Then, a gate 700 is formed inside the gate insulating layer 600 (step S70 ).

[0133] The step S50 of forming the source and the drain, the step S60 of forming the gate insulating layer, and the step S70 of forming the gate can be interchanged.

[0134] Afterwards, refer to Fig.16 , the thin film transistor 10 may be subjected to a heat treatment (step S80 ).

[0135] In one embodiment, the step of performing heat treatment S80 may include a step of performing a first heat treatment in an oxygen environment and a step of performing a second heat treatment in a hydrogen environment.

[0136] For example, Fig.14 As shown, the thin film transistor 10 may first be subjected to a first heat treatment in an oxygen-containing reaction gas environment (eg, oxygen (O2) or ozone (O3)). When the first heat treatment is performed, oxygen ions generated from the reaction gas may be injected into the thin film transistor 10 through the diffusion channel layer 200.

[0137] The step of performing the first heat treatment may be performed in an oxygen (O2) or ozone (O3) environment having a concentration of 100%. However, the concentration of the reaction gas containing oxygen may vary according to the embodiment. For example, the step of performing the first heat treatment may be performed using a reaction gas having a concentration of 50% or more, or a concentration of 100%.

[0138] The step of performing the first heat treatment may be performed in a pressure range of 2 atm to 50 atm, preferably in a pressure range of 5 atm to 20 atm. The step of performing the first heat treatment may be performed in any one of wet, dry or supercritical conditions or environments. The first heat treatment may be performed in a temperature range of 100° C. to 600° C., preferably in a temperature range of 200° C. to 400° C.

[0139] When the first heat treatment is performed, oxygen ions may be injected into the active layer 300 through the tunnel formed in the diffusion channel layer 200. However, a relatively small amount of oxygen ions may pass through the diffusion barrier layer 800. However, according to an embodiment, the oxygen ions may not pass through the diffusion barrier layer 800. Therefore, a relatively large amount of oxygen ions may be injected into the active layer 300 corresponding to the gate region G, and a relatively small amount of oxygen ions may be injected into the active layer 300 corresponding to the source region S or the drain region D.

[0140] Therefore, a relatively large amount of oxygen vacancies may be reduced in the active layer 300 corresponding to the gate region G, compared to the active layer 300 corresponding to the source region S or the drain region D.

[0141] On the other hand, as in the second embodiment or the third embodiment, in the case where the diffusion barrier layer 800 is composed of a plurality of layers and is divided into a plurality of regions, the permeability of oxygen ions in each region may be different. For example, as in the third embodiment, in the case where the diffusion barrier layer 800 is divided into the first region U a , the second area U b 、The third area U c In the case of a , the second area U b 、The third area U c Therefore, the reduction amount of oxygen vacancies can be reduced from the first region U a To the third area U c Gradually decrease.

[0142] The second heat treatment may be performed after the first heat treatment. Fig.15 As shown, the thin film transistor 10 may be subjected to a second heat treatment in a reaction gas environment containing hydrogen (eg, hydrogen (H2) or deuterium (D2)). When the second heat treatment is performed, hydrogen ions generated from the reaction gas may be injected into the thin film transistor 10 through the diffusion channel layer 200.

[0143] The step of performing the second heat treatment may be performed in a hydrogen (H2) or deuterium (D2) environment having a concentration of 3% to 10%, preferably 4%. However, the concentration of the reaction gas containing hydrogen may vary according to the embodiment. For example, the step of performing the second heat treatment may also be performed using a reaction gas having a concentration of 50% or more, or a concentration of 100%.

[0144] The step of performing the second heat treatment may be performed in a pressure range of 2 atm to 50 atm, preferably in a pressure range of 5 atm to 20 atm. The step of performing the second heat treatment may be performed in any one of wet, dry or supercritical conditions or environments. The step of performing the second heat treatment may be performed in a temperature range of 100° C. to 600° C., preferably in a temperature range of 200° C. to 400° C.

[0145] When the second heat treatment is performed, hydrogen ions may be injected into the active layer 300 through the tunnel formed in the diffusion channel layer 200. However, a relatively small amount of hydrogen ions may pass through the diffusion barrier layer 800. However, according to an embodiment, the hydrogen ions may not pass through the diffusion barrier layer 800. Therefore, a relatively large amount of hydrogen ions may be injected into the active layer 300 corresponding to the gate region G, and a relatively small amount of hydrogen ions may be injected into the active layer 300 corresponding to the source region S or the drain region D.

[0146] On the other hand, as in the second embodiment or the third embodiment, in the case where the diffusion barrier layer 800 is composed of a plurality of layers and is divided into a plurality of regions, the permeability of hydrogen ions in each region may be different. For example, as in the third embodiment, in the case where the diffusion barrier layer 800 is divided into the first region U a , the second area U b 、The third area U c In the case of a , the second area U b 、The third area U c The order of decreasing.

[0147] The passivation layer 310 is formed on the active layer 300 corresponding to the gate region G through the second heat treatment. Therefore, oxygen vacancies or charge traps present in the active layer 300 and / or the passivation layer 310 may be passivated by hydrogen ions. Therefore, the charge density of the oxide thin film transistor 10 (TFT) is reduced and the charge mobility is improved.

[0148] According to an embodiment, the step S80 of performing the heat treatment may also selectively perform any one of the first heat treatment step and the second heat treatment step.

[0149] Fig.17 1 is a diagram showing the driving current I of the thin film transistor manufactured according to the first embodiment and the thin film transistor that has not been heat treated during the manufacturing process. on and the shutdown current I off of charts.

[0150] exist Fig.17 In the figure, the high performance addressing display (HPA) is a driving current I of the thin film transistor manufactured according to the first embodiment. on and the shutdown current I off NHPA is the driving current I of the thin film transistor that has not undergone the above-mentioned heat treatment step (step S80) in the manufacturing process. on and the shutdown current I off data.

[0151] like Fig.17 As shown, in the manufacturing process of the thin film transistor, when the step of heat treatment (step S80) is performed according to the first embodiment, the switching ratio of the thin film transistor is increased compared with the step of not performing the heat treatment (step S80). on / I off Higher.

[0152] And, if Fig.17 As shown, in the manufacturing process of the thin film transistor, if the heat treatment step (step S80) is not performed, when the current I is turned off off When the drive current Ion However, in the manufacturing process of the thin film transistor, according to the first embodiment, if the step of heat treatment (step S80) is performed, when the off current I off When the drive current I on The reduction phenomenon has been improved.

[0153] As described above, the embodiments are described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments and drawings disclosed in this specification, and a person skilled in the art of the present invention may make various changes. Moreover, in the process of describing the embodiments of the present invention, even if the effects of the configuration according to the present invention are not explicitly described and explained, it should be recognized that other effects that can be predicted by the structure.

Claims

1. A thin film transistor, comprising: substrate; A diffusion channel layer is disposed on the substrate; An active layer, disposed on the diffusion channel layer; A source electrode and a drain electrode are disposed on the active layer; A gate insulating layer, disposed between the source electrode and the drain electrode; A gate, disposed on the gate insulating layer; as well as A diffusion barrier layer is formed in the diffusion channel layer at a position corresponding to the source and the drain.

2. The thin film transistor according to claim 1, wherein: The diffusion barrier layer is made of a single substance.

3. The thin film transistor according to claim 1, wherein: The diffusion barrier layer is composed of a plurality of layers made of a plurality of substances having different ion permeabilities.

4. The thin film transistor according to claim 1, wherein: The diffusion barrier layer is divided into a plurality of regions having different stratifications.

5. The thin film transistor according to claim 4, wherein: The ion permeability of each region is different from each other.

6. The thin film transistor according to claim 1, wherein: The ion permeability of the diffusion barrier layer and the ion permeability of the diffusion channel layer are different from each other.

7. The thin film transistor according to claim 1, wherein: The thin film transistor further includes a passivation layer formed on at least a portion of the active layer.

8. A method for manufacturing a thin film transistor, comprising the following steps: forming a diffusion channel layer on a substrate; forming at least one groove in the diffusion channel layer; forming a diffusion barrier layer inside the trench; forming an active layer on the diffusion channel layer and the diffusion barrier layer; forming a source electrode and a drain electrode on the active layer; forming a gate insulating layer between the source electrode and the drain electrode; forming a gate on the gate insulating layer; and Perform heat treatment.

9. The method for manufacturing a thin film transistor according to claim 8, wherein: The diffusion barrier layer is made of a single substance.

10. The method for manufacturing a thin film transistor according to claim 8, wherein: The diffusion barrier layer is composed of a plurality of layers made of a plurality of substances having different ion permeabilities.

11. The method for manufacturing a thin film transistor according to claim 8, wherein: The diffusion barrier layer is divided into a plurality of regions having different stratifications.

12. The method for manufacturing a thin film transistor according to claim 11, wherein: The ion permeability of each region is different from each other.

13. The method for manufacturing a thin film transistor according to claim 8, wherein: The step of heat treatment comprises the following steps: Performing a first heat treatment in an oxygen environment; and The second heat treatment is performed in a hydrogen environment.

14. The method for manufacturing a thin film transistor according to claim 13, wherein: The first heat treatment or the second heat treatment is performed at a pressure range of 2 atm to 50 atm.

15. The method for manufacturing a thin film transistor according to claim 13, wherein: The first heat treatment or the second heat treatment is performed at a temperature ranging from 100°C to 600°C.

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