Sampling circuit, sine wave peak detection circuit and sine wave peak detection method

Abstract

The invention discloses a sampling circuit which comprises an input port, a sampling output port, a zero-cross detection port, a zero-cross detection circuit, a gear switching circuit and an operational amplifier structure circuit. The operational amplifier structure circuit obtains an input voltage and outputs a sampling signal of the input voltage; the zero-crossing detection circuit obtains an input voltage and outputs a zero-crossing signal of the input voltage; the gear switching circuit obtains a zero-crossing signal, an input voltage and a gear switching threshold value through coupling, and outputs a gear control signal through operation; and the operational amplifier structure circuit controls the sampling proportion of the input voltage according to the gear control signal, so that the sampling proportion is adaptively switched according to the magnitude of the input voltage. The invention further discloses a sine wave peak value detection circuit and a sine wave peak value detection method, when a sampling output port is coupled with a resistor, a post-stage control circuit obtains a sampling signal of a steamed bun waveform, a peak value moment is found through a zero-crossing signal, a peak value sampling result is read, and the problems of cost increase and size increase caused by a large capacitor can be solved.

Description

Technical Field

[0001] The present invention relates to the field of electronic information, and in particular to a sampling circuit, a sine wave peak detection circuit and a sine wave peak detection method. Background Art

[0002] In switching power supplies, it is often necessary to detect the peak value of the input sinusoidal signal for use by the subsequent control circuit. To ensure the normal and reliable operation of the system, the detection circuit is required to respond to the input sinusoidal signal and provide accurate peak information.

[0003] Common voltage peak detection circuits are shown in the attached Figure 1 As shown, the voltage divider network composed of resistors R10 and R20 obtains an output voltage VS after voltage division sampling of the rectified signal VHV. When the output voltage VS is less than the voltage across the capacitor C1, the diode D1 is cut off. At this time, the voltage across the capacitor C1 can represent the peak information of the input sinusoidal signal; when the amplitude of the input sinusoidal signal decreases, the voltage across the capacitor C1 also needs to decrease accordingly, so a suitable discharge resistor R30 needs to be connected in parallel across the capacitor C1.

[0004] In order to ensure accurate peak information of the input sinusoidal signal, the capacitance of capacitor C1 must be large enough or the resistance of discharge resistor R30 must be large enough so that the voltage across capacitor C1 does not drop too much when diode D1 is turned off. However, if capacitor C1 is too large or discharge resistor R30 is too large, the cost and volume will increase; in addition, in this type of circuit, the AC input range is usually 90Vac to 265Vac, and the voltage range processed by the post-stage control circuit is relatively limited, so the fixed sampling ratio will affect the detection accuracy (resolution). Summary of the invention

[0005] In view of the deficiencies in the prior art, the present invention provides a sampling circuit, a sine wave peak detection circuit and a sine wave peak detection method.

[0006] In order to solve the above technical problems, the present invention is solved by the following technical solutions:

[0007] The present invention provides a sampling circuit, comprising an input port, a sampling output port, a zero-crossing detection port, a zero-crossing detection circuit, a gear switching circuit and an operational amplifier structure circuit; the input end of the operational amplifier structure circuit is coupled to the input port to obtain an input voltage, the output end of the operational amplifier structure circuit is coupled to the sampling output port, and the operational amplifier structure circuit outputs a sampling signal of the input voltage to the sampling output port after sampling the input voltage; the input end of the zero-crossing detection circuit is coupled to the input port to obtain the input voltage, the output end of the zero-crossing detection circuit is coupled to the zero-crossing detection port, and the zero-crossing detection circuit performs zero-crossing processing on the input voltage. After detection, a zero-crossing signal of the input voltage is output to the zero-crossing detection port; the gear switching circuit is coupled to the zero-crossing detection circuit to obtain the zero-crossing signal; the gear switching circuit is coupled to the input port to obtain the input voltage, and the gear switching circuit is also electrically connected to a gear switching threshold; the gear switching circuit outputs a gear control signal according to the zero-crossing signal and the result of the operation and processing of the input voltage and the gear switching threshold; the operational amplifier structure circuit is coupled to the gear switching circuit to obtain the gear control signal, and the operational amplifier structure circuit controls the sampling ratio of the input voltage according to the gear control signal.

[0008] Optionally, the gear switching circuit includes a gear detection control module and a third comparator; the inverting input terminal of the third comparator is connected to the gear switching threshold, the non-phase input terminal is coupled to the input port to obtain the input voltage, and the output terminal is coupled to the gear detection control module, the third comparator compares the input voltage with the gear switching threshold and outputs the operation result to the gear detection control module after comparison and operation; the gear detection control module is coupled to the zero-crossing detection circuit to obtain the zero-crossing signal; the gear detection control module is coupled to the operational amplifier structure circuit, and outputs the gear control signal to the operational amplifier structure circuit according to the operation result of the third comparator and the zero-crossing signal.

[0009] Optionally, the operational amplifier structure circuit includes a fourth resistor with variable resistance. The gear detection control module is coupled to the fourth resistor and controls the resistance of the fourth resistor by outputting the gear control signal. The fourth resistor with different resistance values ​​causes the operational amplifier structure circuit to have different sampling ratios for the input voltage.

[0010] Optionally, the operational amplifier structure circuit includes a second comparator and a third resistor; the non-inverting input terminal of the second comparator is coupled to the input port to obtain the input voltage; the third resistor is connected in series with the fourth resistor; one end of the fourth resistor is coupled to the third resistor, and the other end is grounded; one end of the third resistor away from the fourth resistor is coupled to the output terminal of the second comparator and electrically connected to the sampling output port, and the inverting input terminal of the second comparator is coupled between the third resistor and the fourth resistor.

[0011] Optionally, the operational amplifier structure circuit also includes a first comparator, a first resistor and a second resistor; the first resistor and the second resistor are connected in series, one end of the series connection group of the first resistor and the second resistor is coupled to the input port, and the other end is grounded; the positive input end of the first comparator is coupled between the first resistor and the second resistor, and the inverting input end of the first comparator is coupled to the output end of the first comparator; the operational amplifier structure composed of the first comparator, the first resistor and the second resistor outputs a first sampling signal from the output end of the first comparator after performing operation processing on the input voltage; the positive input end of the second comparator is coupled to the output end of the first comparator to obtain the first sampling signal.

[0012] Optionally, the non-phase input terminal of the third comparator is coupled to the output terminal of the first comparator to obtain the first sampling signal, and the third comparator processes the first sampling signal and the gear switching threshold and outputs the operation result from the output terminal of the third comparator.

[0013] Optionally, it also includes a first transistor, the first transistor also includes a first transistor, the first transistor has a drain coupled to the input port, a source coupled to the input end of the zero-crossing detection circuit, and a gate grounded.

[0014] Optionally, the operational amplifier structure circuit is a multi-stage operational amplifier structure.

[0015] The present invention also discloses a sinusoidal wave peak detection circuit, comprising a sampling circuit as described in any of the foregoing, and a post-stage control circuit; the post-stage control circuit is coupled to the sampling circuit to obtain a sampling signal of the input voltage, and the post-stage control circuit obtains a peak sampling result of the input voltage based on the sampling signal of the input voltage.

[0016] Optionally, the post-stage control circuit is coupled to the sampling output port via a capacitor, and the post-stage control circuit directly obtains a peak sampling result of the input voltage.

[0017] Optionally, the post-stage control circuit is coupled to the sampling output port via a resistor to obtain a sampling signal of the input voltage, the post-stage control circuit is coupled to the zero-crossing detection port to obtain a zero-crossing signal of the input voltage, and the post-stage control circuit obtains a peak sampling result of the input voltage based on the sampling signal and the zero-crossing signal of the input voltage.

[0018] Optionally, a third diode is further included, wherein the cathode of the third diode is connected to the sinusoidal wave signal, and the anode of the third diode is coupled to the input port of the sampling circuit and inputs the input voltage of the steamed bun waveform to the input port.

[0019] The present invention also discloses a sine wave peak value detection method, which adopts the above-mentioned sine wave peak value detection circuit and comprises:

[0020] After the sine wave signal is converted into a steamed bun waveform input voltage, it is input into the sampling circuit;

[0021] In the sampling circuit, the operational amplifier structure circuit obtains the input voltage and outputs a sampling signal of the input voltage after operation processing;

[0022] In the sampling circuit, the zero-crossing detection circuit acquires the input voltage and outputs a zero-crossing signal of the input voltage after calculation processing;

[0023] In the sampling circuit, the gear switching circuit obtains the zero-crossing signal of the input voltage, and determines the power frequency period of the input voltage through the zero-crossing signal of the input voltage;

[0024] In the sampling circuit, the gear switching circuit obtains the input voltage, compares the input voltage in each power frequency cycle with the gear switching threshold, and then outputs a gear control signal;

[0025] In the sampling circuit, the operational amplifier structure circuit obtains the gear control signal, and controls the sampling ratio of the input voltage according to the gear control signal, thereby controlling the sampling signal of the input voltage;

[0026] A post-stage control circuit coupled to the sampling circuit obtains a sampling signal of the input voltage, and obtains a peak sampling result of the input voltage according to the sampling signal of the input voltage.

[0027] Optionally, when the post-stage control circuit is coupled to the sampling output port via a capacitor, the post-stage control circuit directly obtains a peak sampling result of the input voltage.

[0028] Optionally, when the post-stage control circuit is coupled to the sampling output port through a resistor and coupled to the zero-crossing detection circuit, the post-stage control circuit obtains a sampling signal and a zero-crossing signal of the input voltage;

[0029] The post-stage control circuit obtains the peak sampling result of the input voltage by performing calculations on the sampling signal and the zero-crossing signal of the input voltage.

[0030] The present invention can directly use the steamed bun wave to obtain the peak sampling result. The peak moment of the steamed bun wave is found by using the zero-crossing signal, and the adopted signal is read by using the peak moment. The adopted signal at the peak moment is the peak sampling result, which can save large capacitors or large resistors, thereby avoiding increasing costs and volume. The gear switching circuit is used to realize the function of adaptively switching the detection gear according to the current input voltage, which has the effect of improving the peak detection accuracy.

[0031] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0033] Figure 1 This is a commonly used peak detection circuit diagram;

[0034] Figure 2 This is a schematic diagram of a sampling circuit in accordance with the present embodiment;

[0035] Figure 3 This is a schematic diagram of a direct peak sampling waveform when the sampling output port is coupled to a capacitor in the second embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of a steamed-wave sampling waveform when the sampling output port is coupled to a resistor in the second embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of high and low voltage gear switching in this embodiment;

[0038] Figure 6 This is a circuit diagram of the second embodiment when the sampling output port is coupled to a capacitor;

[0039] Figure 7 FIG. 4 is a circuit diagram of the second embodiment when the sampling output port is coupled to a resistor. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] Unless otherwise defined, the technical or scientific terms used herein shall have the common meanings understood by persons with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the patent application specification and claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0042] The present invention discloses a sampling circuit, a sine wave peak detection circuit and a sine wave peak detection method. For application scenarios that require input of both sine peak voltage information and a zero-crossing signal, the sine wave peak detection circuit and the sine wave peak detection method disclosed in the present invention expand and improve the traditional peak sampling method, can omit a large capacitor and directly sample a steamed wave and output a zero-crossing signal of a sine wave, so that a subsequent control circuit can use the zero-crossing signal to find the peak moment, thereby reading the sampling signal at the peak moment (i.e., the peak sampling result).

[0043] Embodiment 1:

[0044] The present invention discloses an embodiment of a sampling circuit, Figure 2 A circuit diagram of a sampling circuit of this embodiment is disclosed, as shown in the attached Figure 2 As shown, the sampling circuit of this embodiment includes an input port (HV), a zero-crossing detection port (ZERO), a sampling output port (SENSE), and also includes a zero-crossing detection circuit 30, a gear switching circuit 20 and an operational amplifier structure circuit 10. Among them, the input port (HV) is coupled to the cathode of the third diode D3, and the anode of the third diode D3 is connected to the sinusoidal input voltage Vac. After being processed by the third diode D3, the sinusoidal input voltage Vac outputs a sampling signal of a steamed bun waveform to the input port (HV), and the input port (HV) obtains the input voltage VHV of a steamed bun waveform. The zero-crossing detection circuit 30 is used to detect the zero-crossing signal of the input voltage VHV, and the gear switching circuit 20 is used to perform gear adaptive switching according to the high and low input voltage VHV, thereby controlling the operational amplifier structure circuit 10 to switch the sampling ratio of the input voltage VHV.

[0045] In a sampling circuit embodiment, the gear switching circuit 20 is coupled to the zero-crossing detection circuit 30 to obtain a zero-crossing signal; the gear switching circuit 20 is coupled to the input port (HV) to obtain an input voltage VHV, and the gear switching circuit 20 is also electrically connected to a gear switching threshold; the gear switching circuit 20 outputs a gear control signal according to the zero-crossing signal, the result of the operation and processing of the input voltage VHV and the gear switching threshold. Specifically, the gear switching circuit 20 includes a gear detection control module 21 and a third comparator S3. Among them, the gear switching circuit 20 is coupled to the input port (HV) through an operational amplifier structure circuit 10, and obtains the input voltage processed by the operational amplifier structure circuit 10. The operational amplifier structure circuit 10 of this embodiment is a two-stage operational amplifier structure, so the operational amplifier structure circuit 10 of this embodiment includes the following Figure 2 The first comparator S1, the second comparator S2, the first resistor R1, the second resistor R2, the third resistor R3 and the fourth resistor R4 are shown. It should be understood that in other embodiments, the operational amplifier structure circuit 10 can also be a single-stage operational amplifier structure or a multi-stage operational amplifier structure.

[0046] In one sampling circuit embodiment, the input end of the operational amplifier structure circuit 10 is coupled to the input port (HV) to obtain the input voltage VHV, the output end of the operational amplifier structure circuit 10 is coupled to the sampling output port (SENSE), and the operational amplifier structure circuit 10 outputs the sampling signal of the input voltage VHV to the sampling output port (SENSE) after sampling the input voltage VHV; the operational amplifier structure circuit 10 is coupled to the gear switching circuit 20 to obtain the gear control signal, and the operational amplifier structure circuit 10 controls the sampling ratio of the input voltage VHV according to the gear control signal. Specifically, in the operational amplifier structure circuit 10, the first resistor R1 is connected in series with the second resistor R2, and one end of the series connection group of the first resistor R1 and the second resistor R2 is coupled to the input port (HV), and the other end is grounded. As shown in the attached figure Figure 2 As shown, specifically, one end of the first resistor R1 is coupled to the input port (HV), and the other end is coupled to the second resistor R2, and one end of the second resistor R2 away from the first resistor R1 is grounded.

[0047] Specifically, in the operational amplifier structure circuit 10, the positive electrode of the first comparator S1 is coupled to the connection line between the first resistor R1 and the second resistor R2, and the negative electrode of the first comparator S1 is coupled to the output end of the first comparator S1; the positive input end of the second comparator S2 is coupled to the output end of the first comparator S1 to obtain the output signal of the first comparator S1, the inverting input end of the second comparator S2 is coupled to the output end of the second comparator S2, and the third resistor R3 is coupled between the inverting input end and the output end of the second comparator S2, and the output end of the second comparator S2 is coupled to the sampling output port (SENSE), and the sampling output port (SENSE) is used to output the sampling signal of the input voltage VHV. The third resistor R3 is connected in series with the fourth resistor R4, one end of the fourth resistor R4 is coupled to the third resistor R3, and the other end of the fourth resistor R4 is grounded. The inverting input end of the second comparator S2 is electrically connected between the third resistor R3 and the fourth resistor R4.

[0048] Specifically, in the gear switching circuit 20, after the input voltage VHV is processed by the operational amplifier structure composed of the first comparator S1, the first resistor R1 and the second resistor R2, the first sampling voltage VS is outputted from the output end of the first comparator S1, and the positive input end of the third comparator S3 is coupled to the output end of the first comparator S1, so that the positive input end of the third comparator S3 obtains the first sampling voltage VS. The negative input end of the third comparator S3 is connected to the gear switching threshold, and the gear switching threshold is compared with the first sampling voltage VS and then the comparison result is outputted. The output end of the third comparator S3 is coupled to the gear detection control module 21, so that the gear detection control module 21 obtains the comparison result of the gear switching threshold and the first sampling voltage VS. In addition, the gear detection control module 21 is also coupled to the zero-crossing detection circuit 30, and obtains the zero-crossing signal (that is, the sinusoidal zero-crossing signal VZERO) of the input voltage VHV outputted by the zero-crossing detection circuit 30. The gear detection control module 21 finds each power frequency cycle of the input voltage VHV according to the zero-crossing signal, and outputs the gear control signal adaptively according to the comparison result of the sampling signal of the input voltage VHV in each power frequency cycle (because this embodiment is a two-stage operational amplifier structure, it can be represented by the first sampling voltage VS) and the gear switching threshold. The gear control signal acts on the fourth resistor R4 and is used to control the resistance value of the fourth resistor R4. The different resistance values ​​of the fourth resistor R4 can make the logical operation results of the operational amplifier structure circuit 10 different, so that the operational amplifier structure circuit 10 has different sampling ratios for the input voltage VHV. It should be understood that the fourth resistor R4 is a variable resistor with adjustable resistance.

[0049] In one sampling circuit embodiment, the zero-crossing detection circuit 30 includes a fourth comparator S4. The sampling circuit of this embodiment also includes a first transistor JFET, the drain of the first transistor JFET and the first resistor R1 are commonly coupled to the input port (HV), and the power supply voltage is obtained from the input port (HV), the gate of the first transistor JFET is grounded, the source of the first transistor JFET is coupled to the inverting input terminal of the fourth comparator S4, the non-inverting input terminal of the fourth comparator S4 is connected to the 0V voltage, the output terminal of the fourth comparator S4 is coupled to the zero-crossing detection port (ZERO), and the output signal of the zero-crossing detection port (ZERO) is the zero-crossing signal of the read input voltage VHV (in this embodiment, it is the sinusoidal zero-crossing signal VZERO of the sinusoidal input voltage Vac).

[0050] According to the appended embodiment of the sampling circuit Figure 2 The operational amplifier structure circuit 10 in the embodiment can be deduced through logical operation that the proportional relationship between the sampling signal VSENSE (indicated by VSENSE_pk at the peak moment) and the input voltage VHV (indicated by VHV_pk at the peak moment) is:

[0051] VSENSE=VHV×R2 / (R1+R2)×(R3+R4) / R4

[0052] The peak moment is: VSENSE_pk = VHV_pk × R2 / (R1+R2) × (R3+R4) / R4

[0053] Therefore, the sampling ratio Gain = (R1+R2)R4 / R2(R3+R4), so changing the resistance value of R4 can change the sampling ratio Gain.

[0054] Attached Figure 5 The schematic diagram of high and low voltage gear switching of this embodiment is disclosed as shown in the attached Figure 5 As shown:

[0055] When the peak signal of the sine wave input voltage Vac for several consecutive power frequency cycles (see Appendix Figure 5 When the first sampling voltage VS is higher than a set threshold value, and the first sampling voltage VS is also higher than the gear switching threshold value in a number of consecutive power frequency cycles, the current gear is the high voltage gear. The gear detection control module 21 obtains the comparison result output by the third comparator S3, and after judging the power frequency cycle through the sinusoidal zero-crossing signal VZERO, controls the resistance value of the fourth resistor R4 by outputting the gear control signal, so that the sampling ratio at this time is Gain_HL, that is:

[0056] VSENSE=VHV / Gain_HL

[0057] The peak moment is: VSENSE_pk = VHV_pk / Gain_HL.

[0058] When the peak signal of the sine wave input voltage Vac for several consecutive power frequency cycles (see Appendix Figure 5 When the first sampling voltage VS does not exceed a set threshold value, and the first sampling voltage VS does not exceed the gear switching threshold value in a number of consecutive power frequency cycles, the current gear is low voltage. The gear detection control module 21 obtains the comparison result output by the third comparator S3, and after judging the power frequency cycle through the sinusoidal zero-crossing signal VZERO, controls the resistance value of the fourth resistor R4 by outputting the gear control signal, so that the sampling ratio at this time is Gain_LL, that is:

[0059] VSENSE=VHV / Gain_LL

[0060] The peak moment is: VSENSE_pk = VHV_pk / Gain_LL.

[0061] Among them, the output signal of the zero-crossing detection port (ZERO) (i.e., the sinusoidal zero-crossing signal VZERO) can reflect the power frequency cycle information. Since the fourth resistor R4 is a variable resistor, the sampling ratio Gain switching can be achieved by controlling the resistance value of the fourth resistor R4. So far, this sampling circuit embodiment can realize the function of adaptively switching the gear according to the level of the current input voltage VHV, thereby improving the peak detection accuracy.

[0062] It should be understood that the present invention is Figure 2 The embodiment disclosed in the specification is half-wave rectification, and in other embodiments of full-wave rectification, the sampling circuit technology of the present invention can also be adopted.

[0063] It should be understood that in other embodiments, the operational amplifier structure circuit 10 is not limited to the two-stage operational amplifier structure of this embodiment. The operational amplifier structure circuit 10 adopts a one-stage operational amplifier structure or a multi-stage operational amplifier structure for modulation, and both can realize the modulation of the sampling ratio, thereby realizing the adaptive switching of the detection gear.

[0064] It should be understood that in other embodiments, the zero-crossing detection circuit 30 is not limited to the embodiment shown in the accompanying drawings. Figure 2 The circuit shown can also realize the function of finding the peak moment by using the zero-crossing signal by using other circuits capable of realizing the function of reading the zero-crossing signal.

[0065] Embodiment 2:

[0066] The present invention also discloses an embodiment of a sine wave peak detection circuit, comprising the sampling circuit disclosed in the aforementioned embodiment, and a post-stage control circuit 40. The post-stage control circuit 40 is coupled to the sampling circuit to obtain a sampling signal VSENSE of an input voltage VHV and a zero-crossing signal VZERO of the input voltage VHV. The post-stage control circuit 40 obtains a peak sampling result of the input voltage VHV after performing peak calculation processing on the sampling signal VSENSE of the input voltage VHV and the zero-crossing signal VZERO of the input voltage VHV.

[0067] In the present embodiment of the sine wave peak detection circuit, when the post-stage control circuit 40 is coupled to the sampling output port (SENSE) of the sampling circuit through a capacitor, the post-stage control circuit 40 can directly perform peak sampling to obtain a peak sampling result. Figure 6 A circuit diagram is disclosed when a sampling output port (SENSE) is coupled to a capacitor. Figure 3 That is, the steady-state waveform when the sampling output port (SENSE) is coupled to a capacitor and directly performs peak sampling is disclosed. As can be seen from the figure, at this time, the post-stage control circuit 40 directly obtains the peak sampling signal VSENSE_pk of the input voltage VHV.

[0068] In the present embodiment of the sine wave peak detection circuit, when the post-stage control circuit 40 is coupled to the sampling output port (SENSE) of the sampling circuit through a resistor to obtain the sampling signal of the input voltage VHV, and is coupled to the zero-crossing detection port (ZERO) to obtain the zero-crossing signal of the input voltage VHV, the post-stage control circuit 40 obtains the peak sampling result of the input voltage VHV according to the sampling signal of the input voltage VHV and the zero-crossing signal, and the sine wave sampling can be performed. Figure 7 A circuit diagram is disclosed when a sampling output port (SENSE) is coupled to a resistor. Figure 4 That is, a typical waveform diagram of the steamed bun wave sampling when the sampling output port (SENSE) is coupled to a resistor is disclosed. At this time, the post-control circuit 40 obtains the sampling waveform of the input voltage VHV of the steamed bun wave waveform, and finds the peak moment of the steamed bun wave waveform according to the zero-crossing signal, thereby obtaining the peak sampling signal VSENSE_pk.

[0069] According to the attached Figure 4 As can be seen from the waveform diagram, in this embodiment, the method of using the zero-crossing signal to find the peak moment is: the zero-crossing detection circuit 30 detects the moment of the zero-crossing signal at the end of the previous power frequency cycle of the input voltage VHV of the steamed bun waveform (as shown in the attached figure). Figure 3 , Attachment Figure 4 The moment t0 in the figure) and the moment of the zero-crossing signal at the beginning of the next power frequency cycle (as shown in the figure) Figure 3 , Attachment Figure 4The peak moment t_pk of the next adjacent power frequency cycle is t_pk=t1+(t1-t0) / 2. The peak sampling signal VSENSE at the peak moment t_pk is the peak sampling result of the input voltage VHV, that is, the peak sampling result of the sinusoidal input voltage Vac.

[0070] The sine wave peak detection circuit disclosed in the present invention directly uses a steamed bun wave to obtain a peak sampling result, finds the peak moment of the steamed bun wave by using a zero-crossing signal, and then uses the peak moment to read the sampling signal at this time, thereby obtaining a peak sampling result, which can save large capacitors or large resistors, and avoid increasing costs and volume. The present invention also uses a gear switching circuit 20 to realize the function of adaptively switching the detection gear according to the current input voltage, which has the effect of improving the peak detection accuracy.

[0071] Embodiment three:

[0072] The present invention also discloses an embodiment of a sine wave peak value detection method, which is implemented by using the sine wave peak value detection circuit of the above embodiment, and specifically includes the following steps:

[0073] After the sine wave signal is converted into a steamed bun waveform input voltage, it is input into the sampling circuit; after passing through the third diode D3, the sine wave signal is input into the input port (HV) in the form of a steamed bun waveform input voltage VHV, and the sampling circuit thus obtains the input voltage VHV.

[0074] In the sampling circuit, the operational amplifier structure circuit 10 obtains the input voltage VHV and outputs a sampling signal of the input voltage VHV after operation processing;

[0075] In the sampling circuit, the zero-crossing detection circuit obtains the input voltage VHV and outputs a zero-crossing signal of the input voltage VHV after calculation processing;

[0076] In the sampling circuit, the gear switching circuit 20 obtains the zero-crossing signal of the input voltage VHV, and determines the power frequency period of the input voltage VHV through the zero-crossing signal of the input voltage VHV;

[0077] In the sampling circuit, the gear switching circuit 20 obtains the input voltage VHV, and compares the input voltage VHV in each power frequency cycle with the gear switching threshold value, and then outputs a gear control signal;

[0078] In the sampling circuit, the operational amplifier structure circuit 10 obtains a gear control signal, and controls the sampling ratio of the input voltage VHV according to the gear control signal, thereby controlling the sampling signal of the input voltage VHV; different size comparison results between the input voltage VHV and the gear switching threshold cause the gear switching circuit 20 to have different gear control signal outputs, and different gear control signals control the operational amplifier structure circuit 10 to provide different sampling ratios.

[0079] The post-stage control circuit 40 coupled to the sampling circuit obtains a sampling signal of the input voltage VHV, and obtains a peak sampling result of the input voltage VHV according to the sampling signal of the input voltage VHV.

[0080] When the post-stage control circuit 40 is coupled to the sampling output port (SENSE) of the sampling circuit through a capacitor, the post-stage control circuit 40 directly obtains the peak sampling result of the input voltage VHV.

[0081] When the post-stage control circuit 40 is coupled to the sampling output port (SENSE) of the sampling circuit through a resistor and coupled to the zero-crossing detection circuit 30, the post-stage control circuit 40 obtains the sampling signal and the zero-crossing signal of the input voltage VHV; the post-stage control circuit 40 obtains the peak sampling result of the input voltage VHV after calculating and processing the sampling signal and the zero-crossing signal of the input voltage VHV. The calculation and processing method is to find the peak moment of the steamed bun waveform input voltage VHV sampling signal through the zero-crossing signal, thereby determining the peak sampling signal VSENSE_pk at this time.

[0082] Therefore, the sine wave peak detection method of the present invention can obtain a direct peak sampling result by connecting a capacitor at the sampling output port (SENSE), and can also obtain a sampling signal by connecting a resistor at the sampling output port (SENSE), and then use the zero-crossing signal to find the peak moment of the sampling signal according to the needs of the subsequent control circuit 40, thereby obtaining a peak sampling result. By using the peak moment to read the sampling signal to obtain the peak sampling result of the present invention, large capacitors or large resistors can be omitted, avoiding increased costs and volume. The present invention uses a gear switching circuit 20 to detect the level of the current input voltage, so that the sampling ratio can be adaptively switched, which has the effect of improving the accuracy of peak detection.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

[0084] In conclusion, the above is only a preferred embodiment of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the patent of the present invention.

Claims

1. A sampling circuit, characterized in that: It includes an input port, a sampling output port, a zero-crossing detection port, a zero-crossing detection circuit, a gear switching circuit and an operational amplifier structure circuit; The input end of the operational amplifier structure circuit is coupled to the input port to obtain the input voltage, the output end of the operational amplifier structure circuit is coupled to the sampling output port, and the operational amplifier structure circuit outputs a sampling signal of the input voltage to the sampling output port after sampling the input voltage; The input end of the zero-crossing detection circuit is coupled to the input port to obtain the input voltage, the output end of the zero-crossing detection circuit is coupled to the zero-crossing detection port, and the zero-crossing detection circuit outputs a zero-crossing signal of the input voltage to the zero-crossing detection port after performing zero-crossing detection on the input voltage; The gear switching circuit is coupled to the zero-crossing detection circuit to obtain the zero-crossing signal; the gear switching circuit is coupled to the input port to obtain the input voltage, and the gear switching circuit is also electrically connected to a gear switching threshold; the gear switching circuit outputs a gear control signal according to the zero-crossing signal and a result of arithmetic processing of the input voltage and the gear switching threshold; The operational amplifier structure circuit is coupled to the gear switching circuit to obtain the gear control signal, and the operational amplifier structure circuit controls the sampling ratio of the input voltage according to the gear control signal.

2. The sampling circuit according to claim 1, characterized in that: The gear switching circuit includes a gear detection control module and a third comparator; The inverting input terminal of the third comparator is connected to the gear switching threshold, the non-inverting input terminal is coupled to the input port to obtain the input voltage, and the output terminal is coupled to the gear detection control module. The third comparator compares the input voltage with the gear switching threshold and then outputs the calculation result to the gear detection control module; The gear detection control module is coupled to the zero-crossing detection circuit to obtain the zero-crossing signal; the gear detection control module is coupled to the operational amplifier structure circuit, and outputs the gear control signal to the operational amplifier structure circuit according to the operation result of the third comparator and the zero-crossing signal.

3. The sampling circuit according to claim 2, characterized in that: The operational amplifier structure circuit includes a fourth resistor with variable resistance. The gear detection control module is coupled to the fourth resistor and controls the resistance of the fourth resistor by outputting the gear control signal. The fourth resistor with different resistance values ​​causes the operational amplifier structure circuit to have different sampling ratios for the input voltage.

4. The sampling circuit according to claim 3, characterized in that: The operational amplifier structure circuit includes a second comparator and a third resistor; The non-inverting input terminal of the second comparator is coupled to the input port to obtain the input voltage; The third resistor is connected in series with the fourth resistor; one end of the fourth resistor is coupled to the third resistor, and the other end is grounded; one end of the third resistor away from the fourth resistor is coupled to the output end of the second comparator and electrically connected to the sampling output port together, and the inverting input end of the second comparator is coupled and connected between the third resistor and the fourth resistor.

5. The sampling circuit according to claim 4, characterized in that: The operational amplifier structure circuit also includes a first comparator, a first resistor and a second resistor; The first resistor and the second resistor are connected in series, one end of the series connection group of the first resistor and the second resistor is coupled to the input port, and the other end is grounded; A non-inverting input terminal of the first comparator is coupled between the first resistor and the second resistor, and an inverting input terminal of the first comparator is coupled to an output terminal of the first comparator; The operational amplifier structure formed by the first comparator, the first resistor and the second resistor outputs a first sampling signal from the output end of the first comparator after performing operation processing on the input voltage; The non-inverting input terminal of the second comparator is coupled to the output terminal of the first comparator to obtain the first sampling signal.

6. The sampling circuit according to claim 5, characterized in that: The non-inverting input terminal of the third comparator is coupled to the output terminal of the first comparator to obtain the first sampling signal. The third comparator performs operation processing on the first sampling signal and the gear switching threshold and outputs the operation result from the output terminal of the third comparator.

7. The sampling circuit according to claim 1, characterized in that: It also includes a first transistor, the first transistor also includes a first transistor, the first transistor has a drain coupled to the input port, a source coupled to the input end of the zero-crossing detection circuit, and a gate connected to the ground.

8. The sampling circuit according to claim 1, characterized in that: The operational amplifier structure circuit is a multi-stage operational amplifier structure.

9. A sine wave peak detection circuit, characterized in that: It includes a sampling circuit as described in any one of claims 1-8, and a post-stage control circuit; the post-stage control circuit is coupled to the sampling circuit to obtain a sampling signal of the input voltage, and the post-stage control circuit obtains a peak sampling result of the input voltage according to the sampling signal of the input voltage.

10. The sine wave peak detection circuit according to claim 9, characterized in that: The post-stage control circuit is coupled to the sampling output port via a capacitor, and the post-stage control circuit directly obtains a peak sampling result of the input voltage.

11. The sine wave peak detection circuit according to claim 9, characterized in that: The post-stage control circuit is coupled to the sampling output port through a resistor to obtain a sampling signal of the input voltage, the post-stage control circuit is coupled to the zero-crossing detection port to obtain a zero-crossing signal of the input voltage, and the post-stage control circuit obtains a peak sampling result of the input voltage based on the sampling signal and the zero-crossing signal of the input voltage.

12. The sine wave peak detection circuit according to claim 9, characterized in that: It also includes a third diode, the cathode of the third diode is connected to the sine wave signal, the anode of the third diode is coupled to the input port of the sampling circuit and inputs the input voltage of the steamed bun waveform to the input port.

13. A sine wave peak detection method, characterized in that: The sine wave peak detection circuit as claimed in claim 9 comprises: After the sine wave signal is converted into a steamed bun waveform input voltage, it is input into the sampling circuit; In the sampling circuit, the operational amplifier structure circuit obtains the input voltage and outputs a sampling signal of the input voltage after operation processing; In the sampling circuit, the zero-crossing detection circuit acquires the input voltage and outputs a zero-crossing signal of the input voltage after calculation processing; In the sampling circuit, the gear switching circuit obtains the zero-crossing signal of the input voltage, and determines the power frequency period of the input voltage through the zero-crossing signal of the input voltage; In the sampling circuit, the gear switching circuit obtains the input voltage, compares the input voltage in each power frequency cycle with the gear switching threshold, and then outputs a gear control signal; In the sampling circuit, the operational amplifier structure circuit obtains the gear control signal, and controls the sampling ratio of the input voltage according to the gear control signal, thereby controlling the sampling signal of the input voltage; A post-stage control circuit coupled to the sampling circuit obtains a sampling signal of the input voltage, and obtains a peak sampling result of the input voltage according to the sampling signal of the input voltage.

14. The sine wave peak detection method according to claim 13, characterized in that: When the post-stage control circuit is coupled to the sampling output port through a capacitor, the post-stage control circuit directly obtains the peak sampling result of the input voltage.

15. The sine wave peak detection method according to claim 13, characterized in that: When the post-stage control circuit is coupled to the sampling output port through a resistor and coupled to the zero-crossing detection circuit, the post-stage control circuit obtains a sampling signal and a zero-crossing signal of the input voltage; The post-stage control circuit obtains the peak sampling result of the input voltage by performing calculations on the sampling signal and the zero-crossing signal of the input voltage.

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