Fault monitoring method and device based on multi-core heterogeneity, electronic equipment and chip

Abstract

The invention discloses a fault monitoring method and device based on multi-core heterogeneity, electronic equipment and a chip, and the method comprises the steps: carrying out the fault detection of a second hardware domain through a function management IP core, and obtaining a corresponding detection result; under the condition of determining that the second hardware domain has a fault based on the detection result, sending the detection result to a fault management IP core through the function management IP core based on an inter-core communication mode between the first hardware domain and the second hardware domain; based on the detection result, a corresponding fault processing mode is executed through the fault management IP core so as to correct the fault of the second hardware domain or restart the chip, and the fault processing mode executed by the fault management IP core is pre-configured by the fault processing unit according to the type of the fault.

Description

Technical Field

[0001] The present application relates to the technical field of multi-core heterogeneous fault monitoring, and in particular to a multi-core heterogeneous fault monitoring method, device, electronic device and chip. Background Art

[0002] Chips are usually equipped with fault monitoring and management software to monitor and correct faults in application software in the chip. For example, based on a multi-core heterogeneous chip architecture, fault monitoring and management software and application software are compiled and integrated into an image file. When a fault occurs, the fault monitoring and management software detects the fault and corrects it or restarts the chip to avoid functional failure caused by the fault. However, due to the diversity of functional requirements, operating systems, programming languages ​​and compilers of different application software, it is difficult for the fault monitoring and management software to be compatible with all application software and detect faults of all types of application software when integrated with the application software. In addition, the cost of integrating the fault monitoring and management software with the application software is high. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a multi-core heterogeneous fault monitoring method, device, electronic device and chip, which can execute corresponding fault handling methods according to different types of faults by separately setting fault management domains and fault management IP cores.

[0004] In order to achieve the above-mentioned object, an embodiment of the present application provides a data detection method, which is applied to a chip, wherein the chip includes a first hardware domain and multiple second hardware domains, the first hardware domain interacts with the multiple second hardware domains through inter-core communication, the first hardware domain is provided with a fault processing unit and a fault management IP core, and the second hardware domain is provided with a function management IP core, and the method includes:

[0005] Performing fault detection on the second hardware domain by using the function management IP core to obtain a corresponding detection result;

[0006] In a case where it is determined based on the detection result that the second hardware domain has a fault, sending the detection result to the fault management IP core through the function management IP core based on an inter-core communication mode between the first hardware domain and the second hardware domain;

[0007] Based on the detection result, a corresponding fault handling method is executed by the fault management IP core to correct the fault of the second hardware domain or restart the chip, wherein the fault handling method executed by the fault management IP core is pre-configured by the fault handling unit according to the type of the fault.

[0008] Optionally, based on the detection result, executing a corresponding fault handling method by the fault management IP core includes:

[0009] Performing a polling operation on the fault management IP core by the fault processing unit to obtain the fault type of the second hardware domain represented by the detection result;

[0010] Based on the fault type of the second hardware domain, the fault management IP core is controlled by the fault processing unit to execute a fault processing method for the fault type of the second hardware domain.

[0011] Optionally, the method further includes:

[0012] After acquiring the fault type of the second hardware domain based on the detection result, storing the fault type of the second hardware domain in a first memory of the first hardware domain;

[0013] According to the fault type of the second hardware domain stored in the first memory, the fault handling unit configures a fault handling method corresponding to the fault type of the second hardware domain for the fault management IP core.

[0014] Optionally, based on the fault type of the second hardware domain, controlling the fault management IP core to execute a fault handling method for the fault type of the second hardware domain by the fault handling unit includes:

[0015] When it is determined that the fault type of the second hardware domain is a fault type that cannot be handled by both the second hardware domain and the system of the chip, the fault management IP core outputs a waveform or image corresponding to the fault of the second hardware domain according to the fault type of the second hardware domain, so as to notify the external system to correct the fault of the second hardware domain.

[0016] Optionally, the method of controlling the fault management IP core to execute a fault handling method for the fault type of the second hardware domain by the fault handling unit based on the fault type of the second hardware domain further includes:

[0017] In the case where it is determined that the fault type of the second hardware domain is a fault type of functional failure of the second hardware domain, sending the fault of the second hardware domain to the system of the chip according to the fault type of the second hardware domain through the fault management IP core;

[0018] The fault of the second hardware domain is corrected by powering off or restarting the chip through the system execution of the chip.

[0019] Optionally, the method of controlling the fault management IP core to execute a fault handling method for the fault type of the second hardware domain by the fault handling unit based on the fault type of the second hardware domain further includes:

[0020] In the case where it is determined that the fault type of the second hardware domain is a fault type in which any module in the second hardware domain cannot run, sending the fault of the second hardware domain to the fault processing unit according to the fault type of the second hardware domain through the fault management IP core;

[0021] The fault processing unit performs interrupt processing on the module corresponding to the fault, or switches the function of the module corresponding to the fault to other modules in the second hardware domain except the module corresponding to the fault.

[0022] Optionally, the method of controlling the fault management IP core to execute a fault handling method for the fault type of the second hardware domain by the fault handling unit based on the fault type of the second hardware domain further includes:

[0023] In the case where it is determined that the fault type of the second hardware domain is a fault type that can be processed by the system of the second hardware domain or the chip, the fault of the second hardware domain is corrected according to the fault type of the second hardware domain by the system of the second hardware domain or the chip;

[0024] The fault management IP core outputs a waveform or an image corresponding to the fault of the second hardware domain according to the fault type of the second hardware domain.

[0025] The embodiment of the present application further provides a multi-core heterogeneous fault monitoring device, which is applied to a chip, wherein the chip includes a first hardware domain and multiple second hardware domains, the first hardware domain interacts with the multiple second hardware domains through inter-core communication, the first hardware domain is provided with a fault processing unit and a fault management IP core, and the second hardware domain is provided with a function management IP core, and the device includes:

[0026] an acquisition module configured to perform fault detection on the second hardware domain through the function management IP core to obtain a corresponding detection result;

[0027] a control module configured to, when it is determined based on the detection result that the second hardware domain has a fault, send the detection result to the fault management IP core through the function management IP core based on an inter-core communication mode between the first hardware domain and the second hardware domain;

[0028] A processing module is configured to, based on the detection result, execute a corresponding fault handling method through the fault management IP core to correct the fault of the second hardware domain or restart the chip, wherein the fault handling method executed by the fault management IP core is pre-configured by the fault handling unit according to the type of the fault.

[0029] An embodiment of the present application further provides an electronic device, including a processor and a memory, wherein the memory stores an executable program, and the memory executes the executable program to perform the steps of the above method.

[0030] The embodiment of the present application also provides a chip, including the multi-core heterogeneous fault monitoring device described above, wherein the multi-core heterogeneous fault monitoring device is used to monitor the fault of the second hardware domain of the chip.

[0031] The multi-core heterogeneous fault monitoring method of the embodiment of the present application can execute corresponding fault handling methods according to different types of faults by separately setting up fault management domains and fault management IP cores in the multi-core heterogeneous chip architecture, so that the chip can quickly resume normal operation, and the separately set fault management domain can be compatible with various types of application software, and the fault monitoring management software can be configured according to the functional safety requirements of the system without considering the compatibility of software adaptation. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a flow chart of a multi-core heterogeneous fault monitoring method according to an embodiment of the present application;

[0033] Figure 2 For the embodiments of this application Figure 1 A flowchart of an embodiment of step S300;

[0034] Figure 3 Another flow chart of the multi-core heterogeneous fault monitoring method according to an embodiment of the present application;

[0035] Figure 4 For the embodiments of this application Figure 2 A flowchart of an embodiment of step S320;

[0036] Figure 5 For the embodiments of this application Figure 2 Another flow chart of an embodiment of step S320;

[0037] Figure 6 For the embodiments of this application Figure 2 Another flow chart of an embodiment of step S320;

[0038] Figure 7A schematic diagram of a connection relationship between a first hardware domain and a second hardware domain in an embodiment of the present application;

[0039] Figure 8 A flowchart of a specific embodiment of the present application embodiment of performing fault processing on the second hardware domain through a fault processing CPU and a fault management IP core;

[0040] Fig. 9 This is a schematic diagram of the structure of a multi-core heterogeneous fault monitoring device according to an embodiment of the present application;

[0041] Fig.10 A schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] Various aspects and features of the present application are described herein with reference to the accompanying drawings.

[0043] It should be understood that various modifications may be made to the embodiments of the present application. Therefore, the above description should not be considered as limiting, but only as an example of an embodiment. Other modifications within the scope and spirit of the present application will occur to those skilled in the art.

[0044] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.

[0045] These and other characteristics of the present application will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.

[0046] It should also be understood that although the present application has been described with reference to some specific examples, those skilled in the art will be able to readily implement many other equivalent forms of the present application.

[0047] The above and other aspects, features and advantages of the present application will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.

[0048] Specific embodiments of the present application are described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments applied for are merely examples of the present application, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that obscure the present application. Therefore, the specific structural and functional details applied for herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present application in a variety of ways with substantially any suitable detailed structure.

[0049] This specification may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present application.

[0050] A multi-core heterogeneous fault monitoring method according to an embodiment of the present application is applied to a chip, which can be applied to a vehicle. The chip can be a SOC (System on Chip) or a chip including a SOC, and the chip includes a first hardware domain and multiple second hardware domains; the first hardware domain can be an independently set fault management domain, which is used to manage faults of other hardware domains in the chip; the second hardware domain can be an application domain or other functional domain, and the first hardware domain interacts with the multiple second hardware domains through inter-core communication; the first hardware domain is provided with a fault processing unit and a fault management IP core, the fault processing unit can be a fault processing CPU, the fault processing CPU is used to control the fault management IP core, the fault management IP core is used to monitor the state of the second hardware domain, and to process the faults of the second hardware domain, for example, the fault monitoring management software can be compiled into a separate image file and deployed on the same fault management IP core, and the operation of the fault management IP core is completely independent of the core where the application software is located; the second hardware domain is provided with a functional management IP core, the functional management IP core is used to implement the functions of the second hardware domain, and can also be used to detect faults in the second hardware domain. The method performs fault detection on the second hardware domain through a function management IP core to obtain a corresponding detection result; when it is determined that the second hardware domain has a fault based on the detection result, the detection result is sent to the fault management IP core through the function management IP core based on the inter-core communication method between the first hardware domain and the second hardware domain; and the fault management IP core executes a corresponding fault handling method to correct the fault of the second hardware domain or restart the chip. The present application can execute corresponding fault handling methods according to different faults through a separately set fault management domain and a fault management IP core, and the separately set fault management domain can be compatible with various types of application software.

[0051] The multi-core heterogeneous fault monitoring method is described in detail below with reference to the accompanying drawings. Figure 1 Flow chart of a multi-core heterogeneous fault monitoring method according to an embodiment of the present application, which is applied to a chip, such as Figure 7 As shown, the chip includes a first hardware domain and multiple second hardware domains. The first hardware domain interacts with the multiple second hardware domains through inter-core communication. The first hardware domain is provided with a fault processing unit and a fault management IP core, and the second hardware domain is provided with a function management IP core. Figure 1 As shown, the method comprises the following steps:

[0052] S100, performing fault detection on the second hardware domain by using the function management IP core to obtain a corresponding detection result;

[0053] In this embodiment, the second hardware domain is firstly detected for faults by the function management IP core of the second hardware domain. Specifically, the function management IP core can be used to detect faults in the second hardware domain by hardware self-checking. The function management IP core can realize the functions of the second hardware domain, including data transmission and data storage functions. The second hardware domain is provided with an application processing unit, which can be an application processing CPU. The application processing CPU is used to control the function management IP core to realize the functions of the second hardware domain. For example, the application processing CPU can control the function management IP core to realize the data storage function of the random access memory (RAM). The function management IP core integrates the safety mechanism of hardware self-checking, such as error checking and correcting (ECC). By using the function management IP core to detect faults in the second hardware domain by using ECC checking, the detection result corresponding to the second hardware domain can be obtained, and then it is determined whether the second hardware domain has a fault.

[0054] S200, when it is determined based on the detection result that the second hardware domain has a fault, sending the detection result to the fault management IP core through the function management IP core based on the inter-core communication mode between the first hardware domain and the second hardware domain;

[0055] In this embodiment, the second hardware domain is detected for faults by the function management IP core to obtain the detection result corresponding to the second hardware domain, and when it is determined based on the detection result that the second hardware domain has a fault, the detection result is sent to the fault management IP core by the function management IP core based on the inter-core communication method between the first hardware domain and the second hardware domain. Specifically, after the function management IP core detects the fault of the second hardware domain by hardware self-test, the fault of the second hardware domain can be sent to the fault management IP core through the hardware interrupt line. For example, when the chip is a vehicle chip, the vehicle chip will integrate a safety mechanism associated with the functional safety of the vehicle to meet the requirements of the vehicle's Automotive Safety Integrity Level (ASIL). When the vehicle fails, the function management IP core will detect the faulty second hardware domain based on the hardware safety mechanism and send the fault to the fault management IP core.

[0056] S300, based on the detection result, executing a corresponding fault handling method through the fault management IP core to correct the fault of the second hardware domain or restart the chip, wherein the fault handling method executed by the fault management IP core is pre-configured by the fault handling unit according to the type of the fault.

[0057] In this embodiment, after the detection result of the second hardware domain is sent to the fault management IP core by the function management IP core, the fault management IP core executes the corresponding fault handling method based on the detection result to correct the fault of the second hardware domain or restart the chip. Specifically, the fault management IP core can select a fault response method for the specific fault of the second hardware domain according to the specific fault of the second hardware domain, directly correct the fault of the second hardware domain, or restart the chip to eliminate the fault of the second hardware domain. The fault handling method executed by the fault management IP core is pre-configured by the fault handling unit according to the type of fault. For example, the fault type of the second hardware domain can be divided into a correctable fault type and an uncorrectable fault type. The correctable fault type indicates that a fault has occurred in the second hardware domain but can be automatically corrected by the hardware and has no impact on functional operation. In this case, the fault can be corrected by the second hardware domain itself; the uncorrectable fault type indicates that a fault has occurred in the second hardware domain and the second hardware domain cannot automatically correct the fault, requiring a fault management IP core to correct the fault, or restarting the chip to eliminate the fault. The fault management IP core can pre-configure the fault correction method and the chip restart method according to the specific fault type of the second hardware domain by the fault processing unit. When an uncorrectable fault occurs in the second hardware domain, the fault management IP core selects and executes a fault handling method for the specific fault of the second hardware domain to correct or eliminate the fault of the second hardware domain.

[0058] The multi-core heterogeneous fault monitoring method of the embodiment of the present application configures the fault monitoring management function separately in the first hardware domain, and the operation of the first hardware domain is completely independent of the application software of the second hardware domain in the chip. The present application first performs fault detection on the second hardware domain through the function management IP core in the second hardware domain to obtain the corresponding detection result; when it is determined that the second hardware domain has a fault based on the detection result, the detection result is sent to the fault management IP core of the first hardware domain through the function management IP core based on the inter-core communication method between the first hardware domain and the second hardware domain; the fault management IP core executes the fault handling method for the fault type of the second hardware domain to correct the fault of the second hardware domain or restart the chip. The present application can execute the corresponding fault handling method according to different types of faults by separately setting the fault management domain and the fault management IP core in the multi-core heterogeneous chip architecture, so that the chip can quickly resume normal operation, and the separately set fault management domain can be compatible with various types of application software, and the fault monitoring management software can be configured according to the functional safety requirements of the system without considering the compatibility of software adaptation.

[0059] In one embodiment of the present application, Figure 2 As shown, based on the detection result, the corresponding fault handling method is executed by the fault management IP core, including:

[0060] S310, performing a polling operation on the fault management IP core through the fault processing unit to obtain the fault type of the second hardware domain represented by the detection result;

[0061] In this embodiment, in the process of executing the fault handling method for the fault of the second hardware domain through the fault management IP core, it is first necessary to poll the fault management IP core through the fault handling unit to obtain the fault type of the second hardware domain represented by the detection result. Specifically, when there is a fault in the second hardware domain, the fault management IP core will receive the detection result representing the fault type of the second hardware domain, and the fault of the second hardware domain has different types. The fault handling unit periodically sends inquiries to the fault management IP core, and based on the detection result of the second hardware domain received by the fault management IP core, obtains different fault types of the second hardware domain represented by the detection result.

[0062] For example, the fault types of the second hardware domain may include: fatal fault (Fail Fatal). When the fault type of the second hardware domain is a fatal fault, the chip hardware and the software system running on the chip cannot handle it by themselves, and require external system assistance to enter a safe state (Safe State) or resume operation; Fail Safe (Fail Safe). When the fault type of the second hardware domain is fail safe, the fault of the second hardware domain will cause the chip hardware to fail to function, but the internal hardware of the chip or the software system running on the chip can enter a safe state or resume operation by itself; Fail Operational (Fail Operational). When the fault type of the second hardware domain is faulty operation, the main functions of the chip can be degraded; and Fail Correctable (Fail Correctable). When the fault type of the second hardware domain is a correctable fault, the error caused by the fault can be automatically corrected by the safety mechanism inside the chip, thereby avoiding the failure of the main functions of the chip.

[0063] S320: Based on the fault type of the second hardware domain, control the fault management IP core through the fault processing unit to execute a fault processing method for the fault type of the second hardware domain.

[0064] In this embodiment, after the fault management IP core is polled by the fault processing unit to obtain the fault type of the second hardware domain represented by the detection result, the fault management IP core is controlled by the fault processing unit to execute a fault processing method for the fault type of the second hardware domain based on the fault type of the second hardware domain. Specifically, in the case where the fault of the second hardware domain cannot be corrected by the hardware of the second hardware domain itself, it is necessary to control the fault management IP core to execute a fault processing method for the fault type of the second hardware domain through the fault processing unit. For different types of faults, the fault management IP core will execute different fault processing methods.

[0065] For example, when the fault type of the second hardware domain is a fatal fault, the fault processing unit can control the fault management IP core to execute the operation of notifying the external system so that the external system can correct the fatal fault of the second hardware domain; when the fault type of the second hardware domain is fail-safe, the fault processing unit can control the fault management IP core to execute the operation of restoring the hardware of the second hardware domain to operation; when the fault type of the second hardware domain is faulty operation, the fault processing unit can control the fault management IP core to execute the operation of adjusting the hardware function of the second hardware domain to degraded operation.

[0066] In one embodiment of the present application, Figure 3 As shown, the method also includes:

[0067] S400, after acquiring the fault type of the second hardware domain based on the detection result, save the fault type of the second hardware domain in a first memory of the first hardware domain;

[0068] In this embodiment, the fault processing unit performs a polling operation on the fault management IP core, and after obtaining the fault type of the second hardware domain represented by the detection result, the fault type of the second hardware domain can be stored in the first memory of the first hardware domain. The first memory can be a commonly used memory in the chip, such as a random access memory, a flash memory, and a read-only memory. Different fault types of the second hardware domain, such as fatal faults, fail-safe, faulty operation, and correctable faults, can be stored in the first memory. The different fault types of the second hardware domain are stored in the first memory of the first hardware domain, and the fault processing unit can parse the different fault types of the second hardware domain and obtain fault handling methods for different types of faults in the second hardware domain.

[0069] S500: According to the fault type of the second hardware domain stored in the first memory, configure, by the fault processing unit, for the fault management IP core a fault processing method corresponding to the fault type of the second hardware domain.

[0070] In this embodiment, after different fault types of the second hardware domain are stored in the first memory of the first hardware domain, the fault handling unit can configure the fault management IP core with a fault handling method corresponding to the fault type of the second hardware domain according to the fault type of the second hardware domain stored in the first memory. By configuring the fault management IP core with fault handling methods corresponding to different fault types of the second hardware domain by the fault handling unit, the fault management IP core can respond to the fault of the second hardware domain quickly and execute the corresponding fault handling method for the fault of the second hardware domain when a fault occurs in the second hardware domain. For example, the fault handling unit can configure the fault management IP core with a fault handling method that notifies an external system and enables the external system to correct the fatal fault of the second hardware domain according to the fatal fault of the second hardware domain; the fault handling unit can configure the fault management IP core with a fault handling method that restores hardware operation according to the fault safety of the second hardware domain; the fault handling unit can configure the fault management IP core with a fault handling method that degrades the hardware function according to the fault operation of the second hardware domain.

[0071] In one embodiment of the present application, the fault type based on the second hardware domain, controlling the fault management IP core to execute a fault handling method for the fault type of the second hardware domain by the fault handling unit, includes:

[0072] When it is determined that the fault type of the second hardware domain is a fault type that cannot be handled by both the second hardware domain and the system of the chip, the fault management IP core outputs a waveform or image corresponding to the fault of the second hardware domain according to the fault type of the second hardware domain, so as to notify the external system to correct the fault of the second hardware domain.

[0073] In this embodiment, when it is determined that the fault type of the second hardware domain is a fault type that cannot be processed by the second hardware domain and the chip system, that is, when the fault type of the second hardware domain is a fatal fault, the chip hardware and the software system running on the chip cannot process the fault by themselves. Figure 8 As shown, the fault management IP core can respond to the fault of the second hardware domain, call the pre-configured fault handling method for fatal faults, and output the waveform or image corresponding to the fault of the second hardware domain according to the fault type of the second hardware domain, and display it on the display screen to notify the external system to correct the fatal fault of the second hardware domain, so that the second hardware domain enters a safe state or resumes operation.

[0074] In one embodiment of the present application, Figure 4 As shown, the fault type based on the second hardware domain, through the fault processing unit controlling the fault management IP core to execute a fault processing method for the fault type of the second hardware domain, also includes:

[0075] S3201: When it is determined that the fault type of the second hardware domain is a fault type of functional failure of the second hardware domain, send the fault of the second hardware domain to the system of the chip according to the fault type of the second hardware domain through the fault management IP core;

[0076] S3202: Correct the fault in the second hardware domain by executing a chip power-off or chip restart through the chip system.

[0077] In this embodiment, when it is determined that the fault type of the second hardware domain is a fault type of functional failure of the second hardware domain, that is, when the fault type of the second hardware domain is fail-safe, the internal hardware of the chip or the software system running on the chip can automatically enter a safe state or resume operation, such as Figure 8 As shown, the fault management IP core can respond to the fault of the second hardware domain, call a pre-configured fault handling method for fault safety, and send the fault of the second hardware domain to the chip system according to the fault type of the second hardware domain. The chip system executes chip power-off or chip restart to correct the fault safety of the second hardware domain, so that the second hardware domain can resume normal operation.

[0078] In one embodiment of the present application, Figure 5 As shown, the fault type based on the second hardware domain, through the fault processing unit controlling the fault management IP core to execute a fault processing method for the fault type of the second hardware domain, also includes:

[0079] S3203: When it is determined that the fault type of the second hardware domain is a fault type in which any module in the second hardware domain cannot run, send the fault of the second hardware domain to the fault processing unit through the fault management IP core according to the fault type of the second hardware domain;

[0080] S3204: Perform interrupt processing on the module corresponding to the fault through the fault processing unit, or switch the function of the module corresponding to the fault to other modules in the second hardware domain except the module corresponding to the fault.

[0081] In this embodiment, when it is determined that the fault type of the second hardware domain is a fault type in which any module in the second hardware domain cannot operate, that is, when the fault type of the second hardware domain is a faulty operation, a module in the second hardware domain cannot operate normally, while other modules in the second hardware domain can operate normally, such as Figure 8 As shown, the fault management IP core can respond to the fault of the second hardware domain, call a pre-configured fault handling method for fault operation, send the fault of the second hardware domain to the fault handling unit according to the fault type of the second hardware domain, generate an interrupt handling function based on the fault of the second hardware domain by the fault handling unit, and use the interrupt handling function to perform interrupt handling on the module corresponding to the fault of the second hardware domain; or, switch the function of the module corresponding to the fault to other modules in the second hardware domain except the module corresponding to the fault by the fault handling unit, that is, downgrade the function of the module corresponding to the fault in the second hardware domain, so that the module without fault in the second hardware domain runs the function of the module corresponding to the fault.

[0082] In one embodiment of the present application, Figure 6 As shown, the fault type based on the second hardware domain, through the fault processing unit controlling the fault management IP core to execute a fault processing method for the fault type of the second hardware domain, also includes:

[0083] S3205: When it is determined that the fault type of the second hardware domain is a fault type that can be processed by the system of the second hardware domain or the chip, correct the fault of the second hardware domain according to the fault type of the second hardware domain through the system of the second hardware domain or the chip;

[0084] S3206: Outputting a waveform or an image corresponding to the fault of the second hardware domain according to the fault type of the second hardware domain through the fault management IP core.

[0085] In this embodiment, when it is determined that the fault type of the second hardware domain is a fault type that can be processed by the system of the second hardware domain or chip, that is, when the fault type of the second hardware domain is a correctable fault, the error caused by the fault can be automatically corrected by the safety mechanism inside the chip, and the error caused by the fault of the second hardware domain can be automatically corrected directly by the system of the second hardware domain or chip according to the fault type of the second hardware domain. In this process, the main functions of the chip will not be affected; Figure 8 As shown, the fault management IP core can respond to the fault of the second hardware domain, and output the waveform or image corresponding to the fault of the second hardware domain according to the fault type of the second hardware domain, and display it on the display screen to notify the user of the fault in the second hardware domain.

[0086] Based on the same inventive concept, the embodiment of the present application also provides a multi-core heterogeneous fault monitoring device, which is applied to a chip, wherein the chip includes a first hardware domain and multiple second hardware domains, wherein the first hardware domain interacts with the multiple second hardware domains through inter-core communication, wherein the first hardware domain is provided with a fault processing unit and a fault management IP core, and the second hardware domain is provided with a function management IP core, such as Fig. 9 As shown, the device comprises:

[0087] an acquisition module configured to perform fault detection on the second hardware domain through the function management IP core to obtain a corresponding detection result;

[0088] In this embodiment, the acquisition module can be used to perform fault detection on the second hardware domain through the function management IP core of the second hardware domain. Specifically, the function management IP core can be used to perform fault detection on the second hardware domain through hardware self-checking. The function management IP core can implement the functions of the second hardware domain, including data transmission and data storage functions. The second hardware domain is provided with an application processing unit, and the application processing unit can be an application processing CPU. The application processing CPU is used to control the function management IP core to implement the function of the second hardware domain. For example, the application processing CPU can control the function management IP core to implement the data storage function of the random access memory (RAM). The function management IP core integrates the safety mechanism of hardware self-checking, such as error checking and correcting (ECC). The function management IP core uses the ECC check method to perform fault detection on the second hardware domain, and the detection result corresponding to the second hardware domain can be obtained, thereby determining whether the second hardware domain has a fault.

[0089] a control module configured to, when it is determined based on the detection result that the second hardware domain has a fault, send the detection result to the fault management IP core through the function management IP core based on an inter-core communication mode between the first hardware domain and the second hardware domain;

[0090] In this embodiment, the control module can be used to perform fault detection on the second hardware domain through the function management IP core, obtain the detection result corresponding to the second hardware domain, and when it is determined that the second hardware domain has a fault based on the detection result, the detection result is sent to the fault management IP core through the function management IP core based on the inter-core communication method between the first hardware domain and the second hardware domain. Specifically, after the function management IP core detects the fault of the second hardware domain through hardware self-test, the fault of the second hardware domain can be sent to the fault management IP core through the hardware interrupt line. For example, when the chip is a vehicle chip, the vehicle chip will integrate a safety mechanism associated with the functional safety of the vehicle to meet the requirements of the vehicle's Automotive Safety Integrity Level (ASIL). When the vehicle fails, the function management IP core will detect the faulty second hardware domain based on the hardware safety mechanism and send the fault to the fault management IP core.

[0091] A processing module is configured to, based on the detection result, execute a corresponding fault handling method through the fault management IP core to correct the fault of the second hardware domain or restart the chip, wherein the fault handling method executed by the fault management IP core is pre-configured by the fault handling unit according to the type of the fault.

[0092] In this embodiment, the processing module can be used to, after sending the detection result of the second hardware domain to the fault management IP core through the function management IP core, execute the corresponding fault handling method through the fault management IP core based on the detection result to correct the fault of the second hardware domain or restart the chip. Specifically, the fault management IP core can select a fault response method for the specific fault of the second hardware domain according to the specific fault of the second hardware domain, directly correct the fault of the second hardware domain, or restart the chip to eliminate the fault of the second hardware domain. The fault handling method executed by the fault management IP core is pre-configured by the fault handling unit according to the type of fault. For example, the fault type of the second hardware domain can be divided into a correctable fault type and an uncorrectable fault type. The correctable fault type indicates that a fault has occurred in the second hardware domain but can be automatically corrected by the hardware and has no impact on functional operation. In this case, the fault can be corrected by the second hardware domain itself; the uncorrectable fault type indicates that a fault has occurred in the second hardware domain and the second hardware domain cannot automatically correct the fault, requiring a fault management IP core to correct the fault, or restarting the chip to eliminate the fault. The fault management IP core can pre-configure the fault correction method and the chip restart method according to the specific fault type of the second hardware domain by the fault processing unit. When an uncorrectable fault occurs in the second hardware domain, the fault management IP core selects and executes a fault handling method for the specific fault of the second hardware domain to correct or eliminate the fault of the second hardware domain.

[0093] In the multi-core heterogeneous fault monitoring device of the embodiment of the present application, the function of fault monitoring management is separately configured in the first hardware domain, and the operation of the first hardware domain is completely independent of the application software of the second hardware domain in the chip. The present application first performs fault detection on the second hardware domain through the function management IP core in the second hardware domain to obtain the corresponding detection result; when it is determined that the second hardware domain has a fault based on the detection result, the detection result is sent to the fault management IP core of the first hardware domain through the function management IP core based on the inter-core communication method between the first hardware domain and the second hardware domain; the fault management IP core executes the fault handling method for the fault type of the second hardware domain to correct the fault of the second hardware domain or restart the chip. The present application can execute the corresponding fault handling method according to different types of faults by separately setting the fault management domain and the fault management IP core in the multi-core heterogeneous chip architecture, so that the chip can quickly resume normal operation, and the separately set fault management domain can be compatible with various types of application software, and the fault monitoring management software can be configured according to the functional safety requirements of the system without considering the compatibility of software adaptation.

[0094] In one embodiment of the present application, the processing module is further configured to:

[0095] Performing a polling operation on the fault management IP core by the fault processing unit to obtain the fault type of the second hardware domain represented by the detection result;

[0096] Based on the fault type of the second hardware domain, the fault management IP core is controlled by the fault processing unit to execute a fault processing method for the fault type of the second hardware domain.

[0097] In one embodiment of the present application, the acquisition module is further configured as follows:

[0098] After acquiring the fault type of the second hardware domain based on the detection result, storing the fault type of the second hardware domain in a first memory of the first hardware domain;

[0099] According to the fault type of the second hardware domain stored in the first memory, the fault handling unit configures a fault handling method corresponding to the fault type of the second hardware domain for the fault management IP core.

[0100] In one embodiment of the present application, the processing module is further configured to:

[0101] When it is determined that the fault type of the second hardware domain is a fault type that cannot be handled by both the second hardware domain and the system of the chip, the fault management IP core outputs a waveform or image corresponding to the fault of the second hardware domain according to the fault type of the second hardware domain, so as to notify the external system to correct the fault of the second hardware domain.

[0102] In one embodiment of the present application, the processing module is further configured to:

[0103] In the case where it is determined that the fault type of the second hardware domain is a fault type of functional failure of the second hardware domain, sending the fault of the second hardware domain to the system of the chip according to the fault type of the second hardware domain through the fault management IP core;

[0104] The fault of the second hardware domain is corrected by powering off or restarting the chip through the system execution of the chip.

[0105] In one embodiment of the present application, the processing module is further configured to:

[0106] In the case where it is determined that the fault type of the second hardware domain is a fault type in which any module in the second hardware domain cannot run, sending the fault of the second hardware domain to the fault processing unit according to the fault type of the second hardware domain through the fault management IP core;

[0107] The fault processing unit performs interrupt processing on the module corresponding to the fault, or switches the function of the module corresponding to the fault to other modules in the second hardware domain except the module corresponding to the fault.

[0108] In one embodiment of the present application, the processing module is further configured to:

[0109] In the case where it is determined that the fault type of the second hardware domain is a fault type that can be processed by the system of the second hardware domain or the chip, the fault of the second hardware domain is corrected according to the fault type of the second hardware domain by the system of the second hardware domain or the chip;

[0110] The fault management IP core outputs a waveform or an image corresponding to the fault of the second hardware domain according to the fault type of the second hardware domain.

[0111] Based on the same concept, the embodiment of the present application also provides an electronic device, such as Fig.10 As shown, it includes a processor and a memory, wherein an executable program is stored in the memory, and the memory executes the executable program to perform the steps of the method as described above.

[0112] An embodiment of the present application further provides a chip, comprising the multi-core heterogeneity-based fault monitoring device as described above, wherein the multi-core heterogeneity-based fault monitoring device is used to monitor faults in a second hardware domain of the chip.

[0113] The vehicle in the embodiments of the present application may be "car", "vehicle" and "entire vehicle" or other similar terms including general motor vehicles, such as sedans, SUVs, MPVs, buses, trucks and other cargo or passenger vehicles, watercraft including various ships and boats, and aircraft, etc., including hybrid vehicles, electric vehicles, fuel vehicles, plug-in hybrid vehicles, fuel cell vehicles and other alternative fuel vehicles. Among them, hybrid vehicles refer to vehicles with two or more power sources, and electric vehicles include pure electric vehicles, extended-range electric vehicles, etc., which are not specifically limited in the present application.

[0114] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.

[0115] It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct memory bus random access memory (Direct Rambus RAM, DR RAM).

[0116] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory (storage module) is integrated in the processor.

[0117] It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0118] It should also be understood that the first, second, third, fourth and various numerical numbers involved in this document are only distinctions made for the convenience of description and are not intended to limit the scope of the present application.

[0119] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0120] In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in a processor for execution. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.

[0121] In various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0122] Those skilled in the art will appreciate that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0123] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices and electronic devices can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0124] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0125] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0126] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integration. The available medium can be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk), etc.

[0127] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A multi-core heterogeneous fault monitoring method, characterized in that: Applied in a chip, the chip includes a first hardware domain and multiple second hardware domains, the first hardware domain interacts with the multiple second hardware domains through inter-core communication, the first hardware domain is provided with a fault processing unit and a fault management IP core, and the second hardware domain is provided with a function management IP core, the method includes: Performing fault detection on the second hardware domain by using the function management IP core to obtain a corresponding detection result; In a case where it is determined based on the detection result that the second hardware domain has a fault, sending the detection result to the fault management IP core through the function management IP core based on an inter-core communication mode between the first hardware domain and the second hardware domain; Based on the detection result, a corresponding fault handling method is executed by the fault management IP core to correct the fault of the second hardware domain or restart the chip, wherein the fault handling method executed by the fault management IP core is pre-configured by the fault handling unit according to the type of the fault.

2. The multi-core heterogeneous fault monitoring method according to claim 1, characterized in that: The performing a corresponding fault handling method based on the detection result by the fault management IP core includes: Performing a polling operation on the fault management IP core by the fault processing unit to obtain the fault type of the second hardware domain represented by the detection result; Based on the fault type of the second hardware domain, the fault management IP core is controlled by the fault processing unit to execute a fault processing method for the fault type of the second hardware domain.

3. The multi-core heterogeneous fault monitoring method according to claim 1, characterized in that: The method further comprises: After acquiring the fault type of the second hardware domain based on the detection result, storing the fault type of the second hardware domain in a first memory of the first hardware domain; According to the fault type of the second hardware domain stored in the first memory, the fault handling unit configures a fault handling method corresponding to the fault type of the second hardware domain for the fault management IP core.

4. The multi-core heterogeneous fault monitoring method according to claim 2, characterized in that: The method of controlling the fault management IP core to execute a fault handling method for the fault type of the second hardware domain by the fault handling unit based on the fault type of the second hardware domain includes: When it is determined that the fault type of the second hardware domain is a fault type that cannot be handled by both the second hardware domain and the system of the chip, the fault management IP core outputs a waveform or image corresponding to the fault of the second hardware domain according to the fault type of the second hardware domain, so as to notify the external system to correct the fault of the second hardware domain.

5. The multi-core heterogeneous fault monitoring method according to claim 2, characterized in that: The method of controlling the fault management IP core to execute a fault handling method for the fault type of the second hardware domain by the fault handling unit based on the fault type of the second hardware domain further includes: In the case where it is determined that the fault type of the second hardware domain is a fault type of functional failure of the second hardware domain, sending the fault of the second hardware domain to the system of the chip according to the fault type of the second hardware domain through the fault management IP core; The fault of the second hardware domain is corrected by powering off or restarting the chip through the system execution of the chip.

6. The multi-core heterogeneous fault monitoring method according to claim 2, characterized in that: The method of controlling the fault management IP core to execute a fault handling method for the fault type of the second hardware domain by the fault handling unit based on the fault type of the second hardware domain further includes: In the case where it is determined that the fault type of the second hardware domain is a fault type in which any module in the second hardware domain cannot run, sending the fault of the second hardware domain to the fault processing unit according to the fault type of the second hardware domain through the fault management IP core; The fault processing unit performs interrupt processing on the module corresponding to the fault, or switches the function of the module corresponding to the fault to other modules in the second hardware domain except the module corresponding to the fault.

7. The multi-core heterogeneous fault monitoring method according to claim 2, characterized in that: The method of controlling the fault management IP core to execute a fault handling method for the fault type of the second hardware domain by the fault handling unit based on the fault type of the second hardware domain further includes: In the case where it is determined that the fault type of the second hardware domain is a fault type that can be processed by the system of the second hardware domain or the chip, the fault of the second hardware domain is corrected according to the fault type of the second hardware domain by the system of the second hardware domain or the chip; The fault management IP core outputs a waveform or an image corresponding to the fault of the second hardware domain according to the fault type of the second hardware domain.

8. A multi-core heterogeneous fault monitoring device, characterized in that: Applied in a chip, the chip includes a first hardware domain and multiple second hardware domains, the first hardware domain interacts with the multiple second hardware domains through inter-core communication, the first hardware domain is provided with a fault processing unit and a fault management IP core, the second hardware domain is provided with a function management IP core, the device includes: an acquisition module configured to perform fault detection on the second hardware domain through the function management IP core to obtain a corresponding detection result; a control module configured to, when it is determined based on the detection result that the second hardware domain has a fault, send the detection result to the fault management IP core through the function management IP core based on an inter-core communication mode between the first hardware domain and the second hardware domain; A processing module is configured to, based on the detection result, execute a corresponding fault handling method through the fault management IP core to correct the fault of the second hardware domain or restart the chip, wherein the fault handling method executed by the fault management IP core is pre-configured by the fault handling unit according to the type of the fault.

9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein an executable program is stored in the memory, and the memory executes the executable program to perform the steps of the method according to any one of claims 1 to 7.

10. A chip, characterized in that: It comprises the multi-core heterogeneity-based fault monitoring device as claimed in claim 8, wherein the multi-core heterogeneity-based fault monitoring device is used to monitor the fault of the second hardware domain of the chip.

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