Driver with multiple operating modes

Abstract

The invention discloses a driver with multiple operation modes, and relates to the technical field of drivers. The driver includes a current mode driving circuit and a voltage mode driving circuit. The current mode driving circuit is started in a current mode or a mixed mode to generate a first signal to an output pad according to a first data signal. The voltage mode driving circuit is started in a voltage mode or the mixed mode to generate a second signal to the output pad according to the first data signal, and provides a matched resistor to the output pad in the current mode, the voltage mode or the mixed mode. The output pad outputs the first signal, the second signal, and a combination of the first signal and the second signal in the current mode, the voltage mode, and the mixed mode, respectively, and a swing of the first signal is lower than a swing of the second signal.

Description

Technical Field

[0001] The present application relates to the technical field of drivers, and in particular to a driver with multiple operation modes. Background Art

[0002] Drivers are often used in data transmission applications to increase the driving capability of data signals so that the receiving device can receive the complete signal for subsequent signal processing. If an existing driver with low power consumption is used to provide a higher output swing, the existing driver will still be limited by the power supply voltage and cannot provide the required output swing. On the other hand, if a driver with a different architecture is used to support a higher output swing, the overall power consumption of the driver will increase significantly. As a result, it is difficult for existing drivers to meet the requirements of different scenarios of high output swing and low power consumption. Summary of the invention

[0003] One of the objectives of the present application is to provide a driver with multiple operation modes, wherein the driver can provide different output swings in these operation modes to improve the deficiencies of the prior art.

[0004] In some embodiments, the driver includes a current mode driving circuit and a voltage mode driving circuit. The current mode driving circuit is activated in a current mode or a mixed mode to generate a first signal to an output pad according to a first data signal. The voltage mode driving circuit is activated in a voltage mode or the mixed mode to generate a second signal to the output pad according to the first data signal, and provides a matching resistor to the output pad in the current mode, the voltage mode or the mixed mode. The output pad outputs the first signal in the current mode, the output pad outputs the second signal in the voltage mode, and the output pad outputs a combination of the first signal and the second signal in the mixed mode, and the swing of the first signal is lower than the swing of the second signal.

[0005] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A schematic diagram of a driver according to some embodiments of the present application is drawn;

[0007] Figure 2A According to some embodiments of the present application, Figure 1 Equivalent schematic diagram of the voltage mode driving circuit;

[0008] Figure 2B According to some embodiments of the present application, Figure 2A Schematic diagram of the inverter circuit;

[0009] Figure 3 According to some embodiments of the present application, Figure 1 A schematic diagram of a current mode drive circuit of FIG. 1 ; and

[0010] Figure 4 A schematic diagram of a driver is drawn according to some embodiments of the present application.

[0011] Reference numerals:

[0012] 100: driver;

[0013] 110: current mode drive circuit;

[0014] 120: voltage mode driving circuit;

[0015] 210, 220: inverter circuit;

[0016] 212, 214: inverter;

[0017] 310: current source;

[0018] 400: driver;

[0019] 410: Pre-measurement circuit;

[0020] 420: de-emphasis circuit;

[0021] AVDD, AVDDL: power supply voltage;

[0022] DN, DN1, DN2: data signal;

[0023] DP, DP1, DP2: data signals;

[0024] G1: inverter group;

[0025] I0: current;

[0026] MN1, MN2: transistors;

[0027] MP1, MP2, MP3, MP4: transistors;

[0028] P1, P2: output pads;

[0029] RE: resistance;

[0030] RESD1~RESD4: resistance;

[0031] RN1, RN2, RP1, RP2: resistors;

[0032] S1N, S2N, S1P, S2P: signal;

[0033] S21, S22: sub-signals;

[0034] S41, S42, S51, S52: signal;

[0035] ST: trim signal;

[0036] VSS: Low supply voltage. DETAILED DESCRIPTION

[0037] All words used herein have their ordinary meanings. The definitions of the above words in commonly used dictionaries, including any use examples of the words discussed herein in the content of this application are only examples and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0038] As used herein, "coupled" or "connected" may refer to two or more elements making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or may refer to two or more elements operating or acting on each other. As used herein, the term "circuit" may refer to a device composed of at least one transistor and / or at least one active and passive element connected in a certain manner to process signals.

[0039] Figure 1 A schematic diagram of a driver 100 is drawn according to some embodiments of the present application. The driver 100 is a data driver with multiple operation modes, which can provide corresponding circuit configurations according to the operation requirements of different applications (for example, including, but not limited to, signal swing, power consumption, etc.). In some embodiments, the aforementioned multiple operation modes include voltage mode, current mode, and mixed mode (equivalent to enabling voltage mode and current mode at the same time).

[0040] The driver 100 includes a current mode driving circuit 110 and a voltage mode driving circuit 120. The current mode driving circuit 110 and the voltage mode driving circuit 120 are coupled in parallel to the output pad P1 and the output pad P2. The current mode driving circuit 110 is activated in the current mode or the mixed mode to generate a signal S1N to the output pad P1 according to the data signal DN and to generate a signal S1P to the output pad P2 according to the data signal DP. In some embodiments, the data signal DP and the data signal DP are differential signals. That is, when the data signal DP is at a low level (e.g., corresponding to a logic value of 0), the data signal DN is at a high level (e.g., corresponding to a logic value of 1); and vice versa. Similarly, the signal S1N and the signal S1P may also be differential signals.

[0041] The voltage mode driving circuit 120 is started in the voltage mode or the mixed mode to generate a signal S2N to the output pad P1 according to the data signal DN and generate a signal S2P to the output pad P2 according to the data signal DP. Similarly, the signal S2N and the signal S2P can also be differential signals. On the other hand, the voltage mode driving circuit 120 also provides a matching resistor (e.g., Figure 2A The resistor RESD1 or / and the resistor RESD2) are connected to the output pad P1 and the output pad P2. Since the output pad P1 and the output pad P2 are configured to be coupled to a receiving device (not shown) to transmit the aforementioned signal S1P, signal S1N, signal S2N and signal S2P to the receiving device, in any mode, each of the output pad P1 and the output pad P2 can be provided with a suitable matching resistor via the voltage mode driving circuit 120 to prevent the aforementioned signal from being excessively attenuated by the load effect during the transmission process.

[0042] In some embodiments, the driver 100 further includes a register (not shown) that can generate corresponding circuit configuration parameters according to a mode control signal, so that the aforementioned current mode driving circuit 110 and the voltage mode driving circuit 120 operate in a corresponding one of the voltage mode, the current mode or the mixed mode based on these circuit configuration parameters. In some embodiments, the driver 100 may include a detection circuit that can adjust the mode control signal according to the signal swing required by the current application to switch the aforementioned operation mode. Alternatively, in other embodiments, the user can input the mode control signal through an external circuit or software to switch the aforementioned operation mode.

[0043] In different modes, the signal swings output by the output pads P1 and P2 have different level ranges. For example, the output pad P1 outputs the signal S1N, the signal S2N, and a combination of the signal S1N and the signal S2N in the current mode, the voltage mode, and the mixed mode (i.e., the output pad P1 outputs the signal S1N and the signal S2N simultaneously in the mixed mode), and the swing of the signal S1N is lower than the swing of the signal S2N, and the swing of the signal S2N is lower than the swing of the combination of the signal S1N and the signal S2N (equivalent to a superposition of the signal S1N and the signal S2N). Similarly, the output pad P2 outputs the signal S1P, the signal S2P, and a combination of the signal S1P and the signal S2P in the current mode, the voltage mode, and the mixed mode, respectively (i.e., the output pad P2 outputs the signal S1P and the signal S2P simultaneously in the mixed mode), and the signal swing of the signal S1P is lower than the swing of the signal S2P, and the swing of the signal S2N is lower than the swing of the combination of the signal S1P and the signal S2P (equivalent to a superposition of the signal S1P and the signal S2P).

[0044] Figure 2A According to some embodiments of the present application, Figure 1 In some embodiments, the voltage mode driving circuit 120 can be operated as follows: Figure 2A The inverter circuit 210 and the inverter circuit 220 are shown.

[0045] The inverter circuit 210 includes a transistor MP1, a resistor RP1, a resistor RN1, a resistor RESD1, and a transistor MN1. A first end (e.g., a source) of the transistor MP1 receives a power supply voltage AVDDL, a second end (e.g., a drain) of the transistor MP1 is coupled to a first end of the resistor RP1, and a control end (e.g., a gate) of the transistor MP1 receives a data signal DN. A second end of the resistor RP1 is coupled to a first end of the resistor RN1 and a first end of the resistor RESD1, a second end of the resistor RESD1 is coupled to an output pad P1 and outputs a signal S2N, and a second end of the resistor RN1 is coupled to a first end (e.g., a drain) of the transistor MN1. A second end (e.g., a source) of the transistor MN1 is coupled to ground, and a control end (e.g., a gate) of the transistor MN1 receives a data signal DN.

[0046] In the voltage mode or the mixed mode, when the data signal DN is a logic value of 1, the transistor MP1 is not conducting and the transistor MN1 is conducting to generate a signal S2N with a logic value of 0; or, when the data signal DN is a logic value of 0, the transistor MP1 is conducting and the transistor MN1 is not conducting to generate a signal S2N with a logic value of 1. On the other hand, in the current mode, the data signal DN received by the transistor MP1 will be switched to a signal with a fixed logic value of 0, thereby turning off the transistor MP1. Under this condition, the inverter circuit 210 is not started, and only a signal path including the resistor RESD1, the resistor RN1 and the transistor MN1 is provided to the output pad P1, thereby providing a matching resistor (for example, the resistor RESD1) to the output pad P1. In some embodiments, the resistor RP1 and / or the resistor RN1 can be selectively set, and the present application is not limited thereto. Similarly, the inverter circuit 220 includes a transistor MP2, a resistor RP2, a resistor RN2, a resistor RESD2 and a transistor MN2, which are used to process the data signal DP. The connection relationship and operation of the above elements of the reverse circuit 220 are substantially the same as those of the inverter circuit 210 , and thus will not be described in detail herein.

[0047] Figure 2B According to some embodiments of the present application, Figure 2A Schematic diagram of the inverter circuit 210. In some embodiments, Figure 2AEach of the inverter circuit 210 and the inverter circuit 220 in the embodiment can be implemented by a plurality of inverters. Taking the inverter circuit 210 as an example, the inverter circuit 210 may include a plurality of inverters 212 and a plurality of inverters 214. The plurality of inverters 212 are mainly used to adjust the swing of the signal S2N, and the plurality of inverters 214 are mainly used to adjust the resistance value of the matching resistor. The plurality of inverters 212 and the plurality of inverters 214 are coupled in parallel to the output pad P1, and the circuit structure of each of the plurality of inverters 212 is the same as Figure 2A The inverter circuit 210 of FIG. 1 and the circuit structure of each of the plurality of inverters 214 is also the same as Figure 2A When the plurality of inverters 212 and the plurality of inverters 214 are enabled, the enabled inverters will be equivalently connected in parallel and operate as Figure 2A Inverter circuit 210.

[0048] The plurality of inverters 212 are coupled to the output pad P1 in parallel, and the number of the plurality of inverters 212 that are activated can adjust the swing of the signal S2N. The plurality of inverters 212 can be activated in a voltage mode or a mixed mode to generate a plurality of sub-signals S21 to the output pad P1 according to the data signal DN. The plurality of inverters 214 can be activated in a current mode, a voltage mode, or a mixed mode to generate a plurality of sub-signals S22 to the output pad P1 according to the data signal DN, wherein the plurality of sub-signals S21 and the plurality of sub-signals S22 will be transmitted to the output pad P1 to generate the signal S2N. That is, the superposition of the plurality of sub-signals S21 and the plurality of sub-signals S22 is the signal S2N.

[0049] In some embodiments, the more inverters 212 are activated, the lower the swing of the signal S2N. Specifically, as described above, the plurality of inverters 212 are mainly used to adjust the swing of the signal S2N. Two inverters in the plurality of inverters 212 can form an inverter group. For example, the two leftmost inverters 212 can be configured as the inverter group G1. If the swing of the signal S2N is to be reduced, the data signal DN received by one inverter 212 in the inverter group G1 can be switched to the power supply voltage AVDDL, and the data signal DN received by another inverter 212 in the inverter group G1 can be switched to the ground voltage (or the low power supply voltage VSS). In this way, the two inverters 212 in the inverter group G1 will be activated and have a normally-on state (i.e., one N-type transistor in the inverter group G1 will be turned on by the power supply voltage AVDDL, and one P-type transistor will be turned on by the low power supply voltage VSS, so that the inverter group G1 forms a conductive current path), thereby reducing the swing of the multiple sub-signals S21 generated by the multiple inverters 212. Similarly, if the number of the multiple inverters 212 that are activated is greater, the number of inverter groups with a normally-on state will be greater, so that the swing of the multiple sub-signals S21 will be lower, thereby reducing the swing of the signal S2N. Therefore, it should be understood that the more the number of the multiple inverters 212 that are activated is greater, the greater the power consumption of the voltage-mode driving circuit 120. Based on this, it should be understood that when the swing of the signal S2N is smaller, the power consumption of the voltage-mode driving circuit 120 is greater.

[0050] In some embodiments, the number of inverters 214 that are activated is determined according to a trimming signal ST to adjust the resistance of the matching resistor. In some embodiments, the voltage-mode driving circuit 120 may further include a switching logic circuit (not shown), which may generate a plurality of control bits according to the trimming signal ST, which may be used to activate the plurality of inverters 214 respectively. For example, the driver 100 may determine whether to power the corresponding inverters of the inverters 214 according to the control bits. Alternatively, the driver 100 may perform additional logic operations on the control bits and the data signal DN, and then input the obtained operation results to the inverters 214 respectively to selectively activate the inverters 214. Various control mechanisms that can activate the corresponding number of inverters 214 according to the trimming signal ST are all within the scope of the present application. When the number of inverters 214 that are activated is greater, the number of resistors (labeled as resistors RE) coupled in parallel to the output pad P1 is greater, thereby reducing the resistance of the resistor RESD1 (equivalent to the aforementioned matching resistor).

[0051] In some embodiments, based on Figure 2B Perform equivalent circuit analysis on the circuit (for example, equate it to Figure 2A), it can be seen that the maximum swing of the signal S2N outputted by the voltage mode driving circuit 120 via the output pad P1 in the voltage mode or the mixed mode is half of the power supply voltage AVDDL. If the swing of the signal S2N is to be reduced, the number of the activated inverters 212 must be increased, thereby increasing the power consumption of the voltage mode driving circuit 120.

[0052] Figure 3 According to some embodiments of the present application, Figure 1 Schematic diagram of a current mode driving circuit 110. The current mode driving circuit 110 includes a current source 310, a transistor MP3, a resistor RESD3, a transistor MP4, and a resistor RESD4. The current source 310 is powered by a power supply voltage AVDD and is started in a current mode or a mixed mode to generate a current I0. A first end of the transistor MP3 is coupled to the current source 310 to receive the current I0, a second end of the transistor MP3 is coupled to a first end of the resistor RESD3, and a control end of the transistor MP3 receives a data signal DN. The transistor MP3 can be turned on according to the data signal DN. The second end of the resistor RESD3 is coupled to the output pad P1, and outputs the current I0 as a signal S1N when the transistor MP3 is turned on. The connection relationship between the current source 310, the transistor MP4 and the resistor RESD4 is similar to the connection relationship between the current source 310, the transistor MP3 and the resistor RESD3. The main difference is that the transistor MP4 is turned on according to the data signal DP and the resistor RESD4 is coupled to the output pad P2. Other similar details are not repeated here.

[0053] As mentioned above, the voltage mode driving circuit 120 provides matching resistors to the output pads P1 and P2 regardless of whether it is in the voltage mode, current mode, and / or mixed mode. Therefore, when the data signal DN is a logic value 0 and the data signal DP is a logic value 1, Figure 2A The inverter circuit 210 provides a signal path from the resistor RESD1 to the power supply voltage AVDDL to the output pad P1; or, when the data signal DN is a logic value 1 and the data signal DP is a logic value 0, Figure 2A The inverter circuit 210 provides a signal path from the resistor RESD1 to the ground to the output pad P1, thereby adjusting the equivalent impedance of the output pad P1 relative to the receiving device. Figure 2AThe inverter circuit 220 provides the related operation of the resistor RESD2 to the output pad P2. Based on the above operation and circuit analysis, it can be deduced that the signal S1N outputted by the current mode driving circuit 110 through the output pad P1 in the current mode or the mixed mode will be proportional to the current I0 generated by the current source 310. Or, intuitively speaking, since the output pad P1 outputs the current I0 as the signal S1N when the transistor MP3 is turned on, the larger the current I0 is, the larger the swing of the signal S1N is. Therefore, the larger the swing of the signal S1N is, the larger the current I0 is, so that the power consumption of the current mode driving circuit 110 is greater. By analogy, the signal S1P outputted by the current mode driving circuit 110 through the output pad P2 in the current mode or the mixed mode will also be proportional to the current I0.

[0054] Based on the same analysis, if the swing of the signal S1N generated in the current mode is set to the maximum swing of the signal S2N generated in the voltage mode (i.e., half of the power supply voltage AVDDL), it can be known that the power consumption generated by the current mode driving circuit 110 will be higher than the power consumption generated by the voltage mode driving circuit 120. Based on this, it can be inferred that the current mode driving circuit 110 is more suitable for low swing (for example, significantly less than half of the power supply voltage AVDDL) application scenarios (the power consumption generated at low swing is lower, for example, but not limited to, less than 1 / 3 of the power supply voltage AVDDL), while the voltage mode driving circuit 120 is more suitable for high swing (the power consumption generated at low swing is higher) application scenarios.

[0055] On the other hand, in the mixed mode, the output pad P1 will superimpose the signal S1N and the signal S2N, and output the combination of the signal S1N and the signal S2N to the receiving device. Therefore, the swing of the signal S1N and the signal S2N can be superimposed and become larger. A similar relationship also applies to the signal S1P and the signal S2P output by the output pad P2. Based on this, after considering the power consumption corresponding to the voltage mode, the current mode and the mixed mode, the transmission line application and the swing applicable to the output of the driver 100 in the current mode, the voltage mode and the mixed mode can be summarized as follows:

[0056] Operation Mode Transmission line applications Swing Current Mode Short distance <<AVDDL / 2 Voltage Mode Middle distance ≤AVDDL / 2 Blending Mode Long distance >AVDDL / 2

[0057] In some practical applications, different transmission line distances may be required based on different transmission protocols. For example, three transmission distances are defined in the V-by-one transmission protocol: short reach transmission, middle reach transmission, and long reach transmission. The driver 100 can provide different corresponding configurations in different operation modes to meet the above different transmission distance requirements.

[0058] Figure 4 A schematic diagram of a driver 400 is drawn according to some embodiments of the present application. Compared with the driver 100, in this example, the driver 400 further includes a pre-shoot circuit 410 and a de-emphasis circuit 420, which are mainly used for channel equalization. The pre-shoot circuit 410 can be activated in a mixed mode to generate a signal S41 to the output pad P1 according to the data signal DN1, and generate a signal S42 to the output pad P2 according to the data signal DP1. The de-emphasis circuit 420 can be activated in a mixed mode to generate a signal S51 to the output pad P1 according to the data signal DN2, and generate a signal S52 to the output pad P2 according to the data signal DP1. In some embodiments, the circuit structure of each of the pre-shoot circuit 410 and the de-emphasis circuit 420 can be the same as the circuit structure of the current mode driving circuit 110. In some embodiments, the data signal DN1, the data signal DN, and the data signal DN2 are sequentially separated by a predetermined time difference, and the data signal DP1, the data signal DP, and the data signal DP2 are also sequentially separated by the predetermined time difference. For example, if the data signal DN1 is represented as DN(t), the data signal DN can be represented as DN(t+1), and the data signal DN2 can be represented as DN(t+2). That is, the driver 400 may further include a delay circuit (not shown), which can generate the above-mentioned multiple data signals according to the data signal DN. Similar relationships also apply to the data signal DP1, the data signal DP, and the data signal DP2.

[0059] In summary, the driver provided in some embodiments of the present application has multiple operation modes and can provide different output swings in different operation modes while considering the overall power consumption, so as to be applicable to application requirements of various transmission distances.

[0060] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Technicians in this technical field may change the technical features of the present application based on the explicit or implicit contents of the present application. All these changes may fall within the scope of patent protection sought by the present application. The scope of patent protection of the present application shall be based on the scope of the patent application of this specification.

Claims

1. A driver, characterized in that: include: a current mode driving circuit activated in a current mode or a mixed mode to generate a first signal to an output pad according to a first data signal; as well as a voltage mode driving circuit, which is activated in a voltage mode or the mixed mode to generate a second signal to the output pad according to the first data signal, and provides a matching resistor to the output pad in the current mode, the voltage mode or the mixed mode, The output pad outputs the first signal in the current mode, the output pad outputs the second signal in the voltage mode, and the output pad outputs a combination of the first signal and the second signal in the mixed mode, and the swing of the first signal is lower than the swing of the second signal.

2. The driver according to claim 1, characterized in that The swing of the second signal is lower than the swing of the combination of the first signal and the second signal.

3. The driver according to claim 1, characterized in that The voltage mode driving circuit comprises: a plurality of first inverters activated in the voltage mode or the mixed mode to generate a plurality of first sub-signals to the output pad according to the first data signal; and A plurality of second inverters are activated in the voltage mode, the current mode or the mixed mode to generate a plurality of second sub-signals to the output pad according to the first data signal to provide the matching resistance, wherein the plurality of first sub-signals and one of the plurality of second sub-signals are superimposed to form the second signal.

4. The driver according to claim 3, characterized in that The plurality of first inverters are used to adjust the swing amplitude of the second signal.

5. The driver according to claim 3, characterized in that When more of the plurality of first inverters are enabled, the swing amplitude of the second signal is lower.

6. The driver according to claim 3, characterized in that The number of the activated second inverters is determined according to a trimming signal to adjust the resistance of the matching resistor.

7. The driver according to claim 1, characterized in that When the swing amplitude of the second signal is smaller, the power consumption of the voltage mode driving circuit is greater.

8. The driver according to claim 1, characterized in that The current mode driving circuit comprises: a current source, activated in the current mode or the mixed mode to generate a current; a transistor, turned on according to the first data signal; and A resistor is coupled between the output pad and the transistor, and outputs the current as the first signal when the transistor is turned on.

9. The driver according to claim 1, characterized in that The larger the swing of the first signal is, the greater the power consumption of the current mode driving circuit is.

10. The driver of claim 1, further comprising: a pre-measurement circuit activated in the mixing mode to generate a fourth signal to the output pad according to a second data signal; as well as a de-emphasis circuit activated in the mixing mode to generate a fifth signal to the output pad according to a third data signal, The circuit structure of each of the pre-measurement circuit and the de-emphasis circuit is the same as the circuit structure of the current mode driving circuit, and the second data signal, the first data signal and the third data signal are sequentially separated by a predetermined time difference.

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