An output voltage regulation control circuit for a multi-channel LDO power management chip

Abstract

The invention discloses an output voltage regulation control circuit for a multi-channel LDO power management chip, which includes a reference generation circuit, a low-pass filter circuit, a reference fast start control circuit, and a voltage regulation detection circuit. The reference generation circuit generates a reference voltage V REF to generate a voltage signal V REF1 for the low-pass filter circuit. The low-pass filter circuit outputs a voltage signal V REF2 . The voltage regulation detection circuit outputs a high pulse signal Stepping and an enable signal EN to jointly control the reference fast start control circuit. The first output terminal of the reference fast start control circuit is connected to the input terminal of the low-pass filter circuit, and the second output terminal of the reference fast start control circuit is connected to the output terminal of the low-pass filter circuit. The invention uses a simple combinational logic circuit to achieve a rapid and stable change of the reference voltage during the switching of the internal voltage regulation signal of the LDO, so that the output voltage of the LDO can be smoothly transitioned during the voltage regulation process.

Description

Technical Field

[0001] The invention relates to a voltage regulation control circuit, in particular to an output voltage regulation control circuit of a multi-channel LDO power management chip, and belongs to the technical field of semiconductor integrated circuits. Background Art

[0002] The multi-channel power management chip PMIC has the characteristics of higher integration, higher power density and more comprehensive safety protection functions. It integrates the traditional multi-channel output power supply into one chip, making the multi-power application scenario lower cost and smaller in size, especially suitable for scenarios with limited PCB area such as mobile phones. Taking the multi-channel LDO PMIC as an example, the output voltage of all channels can usually be set through interfaces such as IIC or SPI. When the voltage regulation signal is input, the corresponding channel needs to be able to switch to the target output voltage in a timely and smooth manner to reduce the switching time and the impact of glitches on the load.

[0003] Figure 4 The circuit structure of the traditional LDO internal reference voltage regulation is shown. When we need to adjust the output voltage of the LDO, we will change the voltage signal V by adjusting the resistance value of the variable resistor R2. REF1 The voltage signal V REF1 After passing through the filter resistor Rf, it is transmitted to the voltage signal V REF2 For high-performance LDO, the reference is usually required to have both high power supply rejection ratio and low noise characteristics, which can be achieved by greatly increasing the value of the filter resistor Rf and the capacitor C1. When the filter resistor Rf is increased, the voltage signal V REF1 Passed to the voltage signal V REF2 The delay time will increase a lot, making it difficult for the output voltage VOUT to respond to the voltage regulation action in time. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide an output voltage regulation control circuit of a multi-channel LDO power management chip, so that the LDO output voltage can be smoothly transitioned during the voltage regulation process.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0006] An output voltage regulation control circuit of a multi-channel LDO power management chip includes a reference generation circuit, a low-pass filter circuit, a reference fast start control circuit and a voltage regulation detection circuit. The input end of the reference generation circuit is connected to a reference voltage V REF The output of the reference generation circuit is connected to the input of the low-pass filter circuit and generates a voltage signal V REF1 , the output voltage signal V of the low-pass filter circuit REF2The output end of the voltage regulation detection circuit is connected to the first input end of the reference fast start control circuit and generates a high pulse signal Stepping, the second input end of the reference fast start control circuit is connected to the enable signal EN, the first output end of the reference fast start control circuit is connected to the input end of the low-pass filter circuit, and the second output end of the reference fast start control circuit is connected to the output end of the low-pass filter circuit.

[0007] Furthermore, the reference generation circuit comprises an operational amplifier A 1 、PMOS tube MP 2 , resistor R 1 , N resistors RS 1 ~RS N And N PMOS tubes MS 1 ~MS N , N resistors RS 1 ~RS N The i-th resistor RS i The two ends of the N PMOS tubes MS 1 ~MS N The i-th PMOS tube MS i The source and drain of are connected in parallel to form a switch resistor, and N switch resistors are connected in series to form a variable resistor. One end of the variable resistor is connected to the resistor R 1 One end and operational amplifier A 1 The non-inverting input terminal is connected to the resistor R 1 The other end of the variable resistor is grounded, and the other end of the variable resistor is connected to the PMOS tube MP 2 The drain of the reference circuit is connected to the output terminal of the reference circuit to output the voltage signal V REF1 , PMOS tube MP 2 The source of the PMOS tube MP is connected to the power supply VCC. 2 The gate of the operational amplifier A 1 The output of the operational amplifier A 1 The inverting input terminal of the reference generation circuit is connected to the reference voltage V REF , N PMOS tubes MS 1 ~MS N The gates of the 1 ~S N are connected.

[0008] Furthermore, the low-pass filter circuit includes a resistor R f and capacitor C 4 , resistor R f One end of the low-pass filter circuit is used as the input end and the voltage signal V is input REF1 , resistor R f The other end of the capacitor C 4One end is connected to the output end of the low-pass filter circuit and outputs the voltage signal V REF2 , capacitor C 4 The other end is grounded.

[0009] Furthermore, the reference fast start control circuit includes an NMOS tube MN 2 、NMOS tube MN 1 , capacitor C 5 、PMOS tube MP 3 , OR gate 3 and inverter INV 10 , NMOS tube MN 2 The source of the fast start control circuit is used as the reference to connect the voltage signal V REF1 , NMOS tube MN 2 The drain of the fast start control circuit is used as a reference to connect the voltage signal V REF2 , NMOS tube MN 2 The gate and capacitor C 5 One end of the PMOS tube MP 3 The drain and NMOS tube MN 1 The drain connection, capacitor C 5 The other end is connected to the PMOS tube MP 3 The source of the NMOS tube MN is connected to the power supply VCC. 1 The source of NMOS tube MN is grounded. 1 The gate connection bias voltage signal V BN , PMOS tube MP 3 The gate of the OR gate 3 The output terminal is connected to the OR gate 3 The first input terminal of the inverter INV 10 The output terminal of the inverter INV is connected 10 The input terminal is connected to the enable signal EN, or the OR gate 3 The second input terminal is connected to the high pulse signal Stepping.

[0010] Furthermore, the voltage regulation detection circuit comprises N control signal change state detection circuits and a high pulse signal generating circuit, and the N control signals S 1 ~S N Input the N control signal change state detection circuit input terminals one by one in sequence, and the output terminal of the control signal change state detection circuit outputs a state signal K x , the state signal K output by the N-way control signal change state detection circuit 1 ~K N The high pulse signal generating circuit is input to generate a high pulse signal Stepping.

[0011] Furthermore, the control signal change state detection circuit includes an inverter INV 0 , the first detection branch, the second detection branch and the OR gate 1 , inverter INV 0 The input terminal is connected to the control signal S x , inverter INV 0 The output end of the first detection branch is connected to the input end of the first detection branch and the input end of the second detection branch. The output end of the first detection branch is connected to the OR gate OR 1 The first input terminal is connected to the output terminal of the second detection branch and the OR gate OR 1 The second input terminal is connected to the OR gate 1 The output terminal outputs the status signal K x , the signals output by the first detection branch and the second detection branch are inverted.

[0012] Furthermore, the first detection branch includes an inverter INV 1 、Inverter INV 2 、Inverter INV 3 、Inverter INV 4 , Schmitt trigger SMT 1 , NAND gate 1 and capacitor C 1 , inverter INV 1 The input end of the inverter INV is used as the input end of the first detection branch. 1 The output terminal of the inverter INV 2 The input terminal and NAND gate 1 The first input terminal of the inverter INV is connected 2 The output of the Schmitt trigger SMT 1 The input terminal and capacitor C 1 One end of the capacitor C 1 The other end of the Schmitt trigger SMT 1 The output terminal of the inverter INV 3 The input terminal of the inverter INV 3 The output of the NAND gate 1 The second input terminal is connected to the NAND gate 1 The output terminal of the inverter INV 4 The input terminal of the inverter INV 4 The output end of is used as the output end of the first detection branch.

[0013] Furthermore, the second detection branch includes an inverter INV 5 、Inverter INV 6 、Inverter INV 7, Schmitt trigger SMT 2 , NAND gate 2 and capacitor C 2 , inverter INV 5 The input terminal and the NAND gate 2 The first input terminal of the inverter INV is connected and used as the input terminal of the second detection branch. 5 The output of the Schmitt trigger SMT 2 The input terminal and capacitor C 2 One end of the capacitor C 2 The other end of the Schmitt trigger SMT 2 The output terminal of the inverter INV 6 The input terminal of the inverter INV 6 The output of the NAND gate 2 The second input terminal is connected to the NAND gate 2 The output terminal of the inverter INV 7 The input terminal of the inverter INV 7 The output end of is used as the output end of the second detection branch.

[0014] Furthermore, the high pulse signal generating circuit comprises an OR gate 2 、Inverter INV 8 、Inverter INV 9 、PMOS tube MP 1 、NMOS tube MN 3 , capacitor C 3 and Schmitt trigger SMT 3 , OR gate 2 There are N input terminals and the N input terminals sequentially input the state signal K 1 ~K N , OR gate 2 The output terminal of the inverter INV 8 The input terminal of the inverter INV 8 The output end of the PMOS tube MP 1 The gate and NMOS tube MN 3 The gate is connected and generates a voltage signal V p , PMOS tube MP 1 The source of the PMOS tube MP is connected to the power supply VCC. 1 The drain of the NMOS tube MN 3 The drain capacitor C 3 One end and Schmitt trigger SMT 3 The input terminal is connected to generate a voltage signal V c , NMOS tube MN 3 The source and capacitor C 3The other end of the Schmitt trigger SMT 3 The output terminal of the inverter INV 9 The input terminal of the inverter INV 9 The output end of is used as the input end of the high pulse signal generating circuit and outputs a high pulse signal Stepping.

[0015] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides an output voltage regulation control circuit of a multi-channel LDO power management chip, which uses a simple combinational logic circuit to achieve a rapid and stable change of the reference voltage during the switching of the LDO internal voltage regulation signal, so that the LDO output voltage can be smoothly transitioned during the voltage regulation process; the present invention does not need to introduce a clock signal, and can realize the detection of the switching of any number of voltage regulation signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The present invention is a schematic diagram of an output voltage regulation control circuit of a multi-channel LDO power management chip.

[0017] Figure 2 It is a working waveform 1 of a key node voltage signal of an output voltage regulation control circuit of a multi-channel LDO power management chip of the present invention.

[0018] Figure 3 It is a working waveform 2 of a key node voltage signal of an output voltage regulation control circuit of a multi-channel LDO power management chip of the present invention.

[0019] Figure 4 It is a structural diagram of a voltage regulation circuit of an LDO in the prior art. DETAILED DESCRIPTION

[0020] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0021] like Figure 1 As shown, an output voltage regulation control circuit of a multi-channel LDO power management chip of the present invention comprises a reference generation circuit, a low-pass filter circuit, a reference fast start control circuit and a voltage regulation detection circuit. The input end of the reference generation circuit is connected to a reference voltage V REF The output of the reference generation circuit is connected to the input of the low-pass filter circuit and generates a voltage signal V REF1, the output voltage signal V of the low-pass filter circuit REF2 , the output end of the voltage regulation detection circuit is connected to the first input end of the reference fast start control circuit and generates a high pulse signal Stepping, the second input end of the reference fast start control circuit is connected to the enable signal EN, the first output end of the reference fast start control circuit is connected to the input end of the low-pass filter circuit, and the second output end of the reference fast start control circuit is connected to the output end of the low-pass filter circuit. 1 ~S N When any one or more signals in the voltage regulation detection circuit change, the voltage regulation detection circuit can identify the change and generate a short high pulse signal Stepping to trigger the reset operation of the reference fast start control circuit, so that the voltage signal V REF2 Re-experience the fast charge or fast discharge stage to ensure that the voltage signal V REF2 Quickly reach the set value.

[0022] The reference generation circuit includes an operational amplifier A 1 、PMOS tube MP 2 , resistor R 1 , N resistors RS 1 ~RS N And N PMOS tubes MS 1 ~MS N , N resistors RS 1 ~RS N The i-th resistor RS i The two ends of the N PMOS tubes MS 1 ~MS N The i-th PMOS tube MS i The source and drain of are connected in parallel to form a switch resistor, and N switch resistors are connected in series to form a variable resistor. One end of the variable resistor is connected to the resistor R 1 One end and operational amplifier A 1 The non-inverting input terminal is connected to the resistor R 1 The other end of the variable resistor is grounded, and the other end of the variable resistor is connected to the PMOS tube MP 2 The drain of the reference circuit is connected to the output terminal of the reference circuit to output the voltage signal V REF1 , PMOS tube MP 2 The source of the PMOS tube MP is connected to the power supply VCC. 2 The gate of the operational amplifier A 1 The output of the operational amplifier A 1 The inverting input terminal of the reference generation circuit is connected to the reference voltage V REF , N PMOS tubes MS 1 ~MS N The gates of the 1~S N are connected.

[0023] Among them, N PMOS tubes MS 1 ~MS N Use a large-sized switch tube to ensure that the N resistors RS will not be affected 1 ~RS N Of course, N PMOS tubes MS 1 ~MS N NMOS tubes can also be used, and the corresponding control signal S 1 ~S N Just negate it.

[0024] The low-pass filter circuit includes a resistor R f and capacitor C 4 , resistor R f One end of the low-pass filter circuit is used as the input end and the voltage signal V is input REF1 , resistor R f The other end of the capacitor C 4 One end is connected to the output end of the low-pass filter circuit and outputs the voltage signal V REF2 , capacitor C 4 The other end is grounded.

[0025] Among them, the resistor R f The resistance value is above megohm. f and capacitor C 4 The extremely low bandwidth filter circuit converts the voltage signal V REF1 Part of the power supply fluctuations and noise components are filtered out to obtain a high-quality voltage signal V REF2 For subsequent LDO main loop use. Therefore, the voltage signal V REF1 If there is a change, it is difficult for the change to be quickly reflected by the resistor to the capacitor C. 4 Charging and discharging are used to transmit, and the NMOS tube MN is needed 2 To change the resistor R f Short circuit to speed up the capacitor C 4 The charging and discharging speed of the capacitor C 4 This can also be achieved using a subthreshold current source.

[0026] The reference fast start control circuit includes an NMOS tube MN 2 、NMOS tube MN 1 , capacitor C 5 、PMOS tube MP 3 , OR gate 3 and inverter INV 10 , NMOS tube MN 2 The source of the fast start control circuit is used as the reference to connect the voltage signal VREF1 , NMOS tube MN 2 The drain of the fast start control circuit is used as a reference to connect the voltage signal V REF2 , NMOS tube MN 2 The gate and capacitor C 5 One end of the PMOS tube MP 3 The drain and NMOS tube MN 1 The drain connection, capacitor C 5 The other end is connected to the PMOS tube MP 3 The source of the NMOS tube MN is connected to the power supply VCC. 1 The source of NMOS tube MN is grounded. 1 The gate connection bias voltage signal V BN , PMOS tube MP 3 The gate of the OR gate 3 The output terminal is connected to the OR gate 3 The first input terminal of the inverter INV 10 The output terminal of the inverter INV is connected 10 The input terminal is connected to the enable signal EN, or the OR gate 3 The second input terminal is connected to the high pulse signal Stepping.

[0027] The voltage regulation detection circuit includes N control signal change state detection circuits and high pulse signal generation circuits. 1 ~S N Input the N control signal change state detection circuit input terminals one by one in sequence, and the output terminal of the control signal change state detection circuit outputs a state signal K x , the state signal K output by the N-way control signal change state detection circuit 1 ~K N The high pulse signal generating circuit is input to generate a high pulse signal Stepping.

[0028] The control signal change state detection circuit includes an inverter INV 0 , the first detection branch, the second detection branch and the OR gate 1 , inverter INV 0 The input terminal is connected to the control signal S x , inverter INV 0 The output end of the first detection branch is connected to the input end of the first detection branch and the input end of the second detection branch. The output end of the first detection branch is connected to the OR gate OR 1 The first input terminal is connected to the output terminal of the second detection branch and the OR gate OR 1 The second input terminal is connected to the OR gate 1 The output terminal outputs the status signal K x, the signals output by the first detection branch and the second detection branch are inverted.

[0029] The first detection branch includes an inverter INV 1 、Inverter INV 2 、Inverter INV 3 、Inverter INV 4 , Schmitt trigger SMT 1 , NAND gate 1 and capacitor C 1 , inverter INV 1 The input end of the inverter INV is used as the input end of the first detection branch. 1 The output terminal of the inverter INV 2 The input terminal and NAND gate 1 The first input terminal of the inverter INV is connected 2 The output of the Schmitt trigger SMT 1 The input terminal and capacitor C 1 One end of the capacitor C 1 The other end of the Schmitt trigger SMT 1 The output terminal of the inverter INV 3 The input terminal of the inverter INV 3 The output of the NAND gate 1 The second input terminal is connected to the NAND gate 1 The output terminal of the inverter INV 4 The input terminal of the inverter INV 4 The output end of is used as the output end of the first detection branch.

[0030] The second detection branch includes an inverter INV 5 、Inverter INV 6 、Inverter INV 7 , Schmitt trigger SMT 2 , NAND gate 2 and capacitor C 2 , inverter INV 5 The input terminal and the NAND gate 2 The first input terminal of the inverter INV is connected and used as the input terminal of the second detection branch. 5 The output of the Schmitt trigger SMT 2 The input terminal and capacitor C 2 One end of the capacitor C 2 The other end of the Schmitt trigger SMT 2 The output terminal of the inverter INV 6 The input terminal of the inverter INV 6 The output of the NAND gate2 The second input terminal is connected to the NAND gate 2 The output terminal of the inverter INV 7 The input terminal of the inverter INV 7 The output end of is used as the output end of the second detection branch.

[0031] The high pulse signal generating circuit includes an OR gate 2 、Inverter INV 8 、Inverter INV 9 、PMOS tube MP 1 、NMOS tube MN 3 , capacitor C 3 and Schmitt trigger SMT 3 , OR gate 2 There are N input terminals and the N input terminals sequentially input the state signal K 1 ~K N , OR gate 2 The output terminal of the inverter INV 8 The input terminal of the inverter INV 8 The output end of the PMOS tube MP 1 The gate and NMOS tube MN 3 The gate is connected and generates a voltage signal V p , PMOS tube MP 1 The source of the PMOS tube MP is connected to the power supply VCC. 1 The drain of the NMOS tube MN 3 The drain capacitor C 3 One end and Schmitt trigger SMT 3 The input terminal is connected to generate a voltage signal V c , NMOS tube MN 3 The source and capacitor C 3 The other end of the Schmitt trigger SMT 3 The output terminal of the inverter INV 9 The input terminal of the inverter INV 9 The output end of is used as the input end of the high pulse signal generating circuit and outputs a high pulse signal Stepping.

[0032] Among them, NMOS tube MN 3 It is a tube with inversely proportional size. It can be realized by using a single tube or multiple NMOS tubes in series. 1 It is a tube proportional to its size. When N control signals S 1 ~S N When any one or more bits of the signal change, the voltage signal V pA short low-level pulse will appear correspondingly, passing through the NMOS tube MN 3 And PMOS tube MP 1 The structure of strong pull-up and weak pull-down is formed, and the low-level pulse will be inverted and greatly widened.

[0033] NMOS tube MN 3 A high resistance can be connected in series from the source to the ground to achieve the weak pull-down function. 3 A small current source can be connected in series from the source to ground to achieve a weak pull-down function.

[0034] like Figure 2 and Figure 3 As shown, when the circuit is turned off, the enable signal EN is at a low level. At this time, the enable signal EN passes through the inverter INV 10 AND OR Gate 3 Control PMOS tube MP 3 Turn on, thus the capacitor C 5 Charging is performed to ensure that the reference fast start circuit is turned on when the circuit is turned off.

[0035] When the voltage is adjusted, the voltage detection circuit will generate a high pulse signal Stepping to the OR gate OR 3 Input, OR gate 3 The output is low level and controls the PMOS tube MP 3 For capacitor C 5 Charging is performed so that the voltage signal V REF2 Quickly adjust to the voltage signal V REF1 The voltage regulation detection circuit mainly detects the control signal S in real time. 1 ~S N The specific operation is as follows: Assuming the control signal S 1 ~S N At least one bit has changed, recorded as control signal S x , when the control signal S x When the level changes from low to high, the change is detected by the second detection branch, triggering the status signal K x Output a high level pulse. When the control signal S x When the level changes from high to low, the change is detected by the first detection branch and still triggers the status signal K. x Output a high level pulse. N-way status signal K 1 ~K N Through the OR gate 2 and inverter INV 8 After shaping, the low pulse voltage signal Vp . Voltage signal V p After the PMOS tube MP 1 、NMOS tube MN 3 and capacitor C 3 The low pulse stretching circuit composed of the stepping circuit generates a wider high pulse signal to ensure reliable reset of the reference fast start control circuit.

[0036] The present invention provides an output voltage regulation control circuit of a multi-channel LDO power management chip, which uses a simple combinational logic circuit to realize a rapid and stable change of a reference voltage during the switching process of an LDO internal voltage regulation signal, so that the LDO output voltage can be smoothly transitioned during the voltage regulation process; the present invention does not need to introduce a clock signal, and can realize the detection of switching of any number of voltage regulation signals.

[0037] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. An output voltage regulation control circuit of a multi-channel LDO power management chip, characterized in that: It includes a reference generation circuit, a low-pass filter circuit, a reference fast start control circuit and a voltage regulation detection circuit. The input end of the reference generation circuit is connected to the reference voltage V REF The output of the reference generation circuit is connected to the input of the low-pass filter circuit and generates a voltage signal V REF1 , the output voltage signal V of the low-pass filter circuit REF2 , the output end of the voltage regulation detection circuit is connected to the first input end of the reference fast start control circuit and generates a high pulse signal Stepping, the second input end of the reference fast start control circuit is connected to the enable signal EN, the first output end of the reference fast start control circuit is connected to the input end of the low-pass filter circuit, and the second output end of the reference fast start control circuit is connected to the output end of the low-pass filter circuit; The voltage regulation detection circuit comprises N control signal change state detection circuits and a high pulse signal generating circuit. N Input the N control signal change state detection circuit input terminals one by one in sequence, and the output terminal of the control signal change state detection circuit outputs a state signal K x , the state signals K1~K output by the N-way control signal change state detection circuit N Input a high pulse signal generating circuit to generate a high pulse signal Stepping; The control signal change state detection circuit comprises an inverter INV0, a ​​first detection branch, a second detection branch and an OR gate OR1. The input end of the inverter INV0 is connected to the control signal S x The output end of the inverter INV0 is connected to the input end of the first detection branch and the input end of the second detection branch, the output end of the first detection branch is connected to the first input end of the OR gate OR1, the output end of the second detection branch is connected to the second input end of the OR gate OR1, and the output end of the OR gate OR1 outputs the state signal K x , the signals output by the first detection branch and the second detection branch are inverted; The first detection branch comprises an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, a Schmitt trigger SMT1, a NAND gate NAND1 and a capacitor C1, the input end of the inverter INV1 serves as the input end of the first detection branch, the output end of the inverter INV1 is connected to the input end of the inverter INV2 and the first input end of the NAND gate NAND1, the output end of the inverter INV2 is connected to the input end of the Schmitt trigger SMT1 and one end of the capacitor C1, the other end of the capacitor C1 is grounded, the output end of the Schmitt trigger SMT1 is connected to the input end of the inverter INV3, the output end of the inverter INV3 is connected to the second input end of the NAND gate NAND1, the output end of the NAND gate NAND1 is connected to the input end of the inverter INV4, and the output end of the inverter INV4 serves as the output end of the first detection branch; The second detection branch includes an inverter INV5, an inverter INV6, an inverter INV7, a Schmitt trigger SMT2, a NAND gate NAND2 and a capacitor C2, an input end of the inverter INV5 is connected to the first input end of the NAND gate NAND2 and serves as the input end of the second detection branch, an output end of the inverter INV5 is connected to the input end of the Schmitt trigger SMT2 and one end of the capacitor C2, the other end of the capacitor C2 is grounded, an output end of the Schmitt trigger SMT2 is connected to the input end of the inverter INV6, an output end of the inverter INV6 is connected to the second input end of the NAND gate NAND2, an output end of the NAND gate NAND2 is connected to the input end of the inverter INV7, and an output end of the inverter INV7 serves as the output end of the second detection branch.

2. The output voltage regulation control circuit of a multi-channel LDO power management chip according to claim 1, characterized in that: The reference generation circuit includes an operational amplifier A1, a PMOS tube MP2, a resistor R1, and N resistors RS1-RS N And N PMOS tubes MS1~MS N , N resistors RS1~RS N The i-th resistor RS i The two ends of the N PMOS tubes MS1~MS N The i-th PMOS tube MS i The source and drain of are connected in parallel to form a switch resistor, and N switch resistors are connected in series to form a variable resistor. One end of the variable resistor is connected to one end of the resistor R1 and the in-phase input end of the operational amplifier A1, and the other end of the resistor R1 is grounded. The other end of the variable resistor is connected to the drain of the PMOS tube MP2 and serves as the output end of the reference generation circuit to output the voltage signal V REF1 The source of the PMOS tube MP2 is connected to the power supply VCC, the gate of the PMOS tube MP2 is connected to the output of the operational amplifier A1, and the inverting input of the operational amplifier A1 is connected to the reference voltage V as the input of the reference generation circuit. REF , N PMOS tubes MS1~MS N The gates of the N control signals S1~S N are connected.

3. The output voltage regulation control circuit of a multi-channel LDO power management chip according to claim 1, characterized in that: The low-pass filter circuit includes a resistor R f and capacitor C4, resistor R f One end of the low-pass filter circuit is used as the input end and the voltage signal V is input REF1 , resistor R f The other end is connected to one end of capacitor C4 and serves as the output end of the low-pass filter circuit to output a voltage signal V REF2 , the other end of capacitor C4 is grounded.

4. The output voltage regulation control circuit of a multi-channel LDO power management chip according to claim 1, characterized in that: The reference fast start control circuit comprises an NMOS tube MN2, an NMOS tube MN1, a capacitor C5, a PMOS tube MP3, an OR gate OR3 and an inverter INV 10 The source of NMOS tube MN2 is used as the first output terminal of the reference fast start control circuit to connect the voltage signal V REF1 The drain of NMOS tube MN2 is used as the reference. The second output terminal of the fast start control circuit is connected to the voltage signal V REF2 The gate of NMOS tube MN2 is connected to one end of capacitor C5, the drain of PMOS tube MP3 and the drain of NMOS tube MN1. The other end of capacitor C5 is connected to the source of PMOS tube MP3 and connected to power supply VCC. The source of NMOS tube MN1 is grounded. The gate of NMOS tube MN1 is connected to bias voltage signal V BN The gate of the PMOS tube MP3 is connected to the output end of the OR gate OR3, and the first input end of the OR gate OR3 is connected to the inverter INV 10 The output terminal of the inverter INV is connected 10 The input end of the OR gate OR3 is connected to the enable signal EN, and the second input end of the OR gate OR3 is connected to the high pulse signal Stepping.

5. The output voltage regulation control circuit of a multi-channel LDO power management chip according to claim 1, characterized in that: The high pulse signal generating circuit comprises an OR gate OR2, an inverter INV8, an inverter INV9, a PMOS tube MP1, an NMOS tube MN3, a capacitor C3 and a Schmitt trigger SMT3. The OR gate OR2 is provided with N input terminals and the N input terminals sequentially input state signals K1~K N The output end of the OR gate OR2 is connected to the input end of the inverter INV8, and the output end of the inverter INV8 is connected to the gate of the PMOS tube MP1 and the gate of the NMOS tube MN3 to generate a voltage signal V p The source of the PMOS tube MP1 is connected to the power supply VCC, and the drain of the PMOS tube MP1 is connected to the drain of the NMOS tube MN3, one end of the capacitor C3 and the input end of the Schmitt trigger SMT3 to generate a voltage signal V c The source of the NMOS tube MN3 and the other end of the capacitor C3 are grounded, the output end of the Schmitt trigger SMT3 is connected to the input end of the inverter INV9, and the output end of the inverter INV9 serves as the input end of the high pulse signal generating circuit and outputs the high pulse signal Stepping.

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