Operation method based on storage device, storage device and control circuit

Abstract

The invention provides an operation method based on a storage device, a memory storage device and a memory control circuit unit. The method comprises the steps that an operation instruction is received from a host system, the operation instruction comprises header data, and the header data carries setting information related to target logical operation; obtaining the header data from the operation instruction; and instructing an operational circuit inside the memory storage device to execute the target logical operation according to the header data. Therefore, the cooperative work efficiency between the host system and the memory storage device can be improved.

Description

Technical Field

[0001] The present invention relates to a memory control technology, and in particular to a computing method based on a memory device, a memory storage device and a memory control circuit unit. Background Art

[0002] Portable electronic devices such as mobile phones and notebook computers have grown rapidly in recent years, resulting in a rapid increase in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are very suitable for being built into the various portable electronic devices listed above because they have the characteristics of data non-volatility, power saving, small size, and no mechanical structure.

[0003] On the other hand, with the development of computer technology, more and more data processing involves various logical operations (such as matrix operations), such as image convolution, mod, binarization and / or data compression. Generally speaking, the above operations are performed by the Graphic Processing Unit (GPU) or a dedicated chip in the host system, while the storage device is simply responsible for data storage. However, as the amount of data that needs to be logically operated becomes larger and larger, how to effectively use the host system and the memory storage device to jointly complete the operation task has become one of the topics that technicians in this field have devoted themselves to studying. Summary of the invention

[0004] The present invention provides a computing method based on a storage device, a memory storage device and a memory control circuit unit, which can improve the cooperation efficiency between a host system and the memory storage device.

[0005] An exemplary embodiment of the present invention provides a storage device-based operation method, which is used for a memory storage device, and the operation method includes: receiving an operation instruction from a host system, wherein the operation instruction includes header data, and the header data carries setting information related to a target logical operation; obtaining the header data from the operation instruction; and instructing an operation circuit inside the memory storage device to execute the target logical operation according to the header data.

[0006] In an exemplary embodiment of the present invention, the setting information includes at least one of enabling information related to the target logical operation, type information related to the target logical operation, parameter setting information related to the target logical operation, and logical address information related to the target logical operation, the enabling information is used to indicate the enabling of the target logical operation, the type information is used to indicate the type of the target logical operation, the parameter setting information is used to indicate at least one parameter used by the target logical operation, and the logical address information is used to indicate the logical address corresponding to at least part of the data participating in the target logical operation.

[0007] In an exemplary embodiment of the present invention, the operation instruction also includes first target data, and the step of instructing the operation circuit inside the memory storage device to perform the target logic operation according to the header data includes: instructing the operation circuit to perform the target logic operation on the first target data according to the header data.

[0008] In an exemplary embodiment of the present invention, the step of instructing the operation circuit to perform the target logic operation on the first target data according to the header data includes: reading second target data from a rewritable non-volatile memory module inside the memory storage device according to the header data; and instructing the operation circuit to perform the target logic operation on the first target data and the second target data.

[0009] In an exemplary embodiment of the present invention, the step of instructing the operation circuit inside the memory storage device to perform the target logic operation according to the header data includes: reading third target data from a rewritable non-volatile memory module inside the memory storage device according to the header data; and instructing the operation circuit to perform the target logic operation on the third target data.

[0010] In an exemplary embodiment of the present invention, the operation method also includes: in response to the operation instruction including a write instruction, storing the operation result of the target logical operation in a rewritable non-volatile memory module inside the memory storage device; and in response to the operation instruction including a read instruction, transmitting the operation result back to the host system.

[0011] The exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable non-volatile memory module, an operation circuit and a memory control circuit unit. The connection interface unit is used to connect to a host system. The memory control circuit unit is connected to the connection interface unit, the rewritable non-volatile memory module and the operation circuit. The memory control circuit unit is used to: receive an operation instruction from the host system, wherein the operation instruction includes header data, and the header data carries setting information related to a target logical operation; obtain the header data from the operation instruction; and instruct the operation circuit to perform the target logical operation according to the header data.

[0012] In an exemplary embodiment of the present invention, the operation instruction also includes first target data, and according to the header data, the operation of instructing the operation circuit inside the memory storage device to perform the target logic operation includes: according to the header data, instructing the operation circuit to perform the target logic operation on the first target data.

[0013] In an exemplary embodiment of the present invention, the operation of instructing the operation circuit to perform the target logic operation on the first target data according to the header data includes: reading second target data from the rewritable non-volatile memory module according to the header data; and instructing the operation circuit to perform the target logic operation on the first target data and the second target data.

[0014] In an exemplary embodiment of the present invention, the operation of instructing the operation circuit inside the memory storage device to perform the target logic operation according to the header data includes: reading third target data from the rewritable non-volatile memory module according to the header data; and instructing the operation circuit to perform the target logic operation on the third target data.

[0015] In an exemplary embodiment of the present invention, the memory control circuit unit is also used to: in response to the operation instruction including a write instruction, store the operation result of the target logical operation in a rewritable non-volatile memory module inside the memory storage device; and in response to the operation instruction including a read instruction, return the operation result to the host system.

[0016] An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a memory storage device, wherein the memory storage device includes a rewritable non-volatile memory module, and the memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is used to connect to a host system. The memory interface is used to connect to the rewritable non-volatile memory module. The memory management circuit is connected to the host interface and the memory interface. The memory management circuit is used to: receive an operation instruction from the host system, wherein the operation instruction includes header data, and the header data carries setting information related to a target logical operation; obtain the header data from the operation instruction; and instruct the operation circuit inside the memory storage device to perform the target logical operation according to the header data.

[0017] Based on the above, after configuring the operation circuit supporting the target logic operation in the memory storage device, the host system can send an operation instruction including specially designed header data to the memory storage device to instruct the memory storage device to perform the target logic operation, thereby improving the cooperation efficiency between the host system and the memory storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention;

[0019] Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention;

[0020] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0021] Figure 4 is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0022] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0023] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0024] Figure 7 is a schematic diagram of an operation instruction according to an exemplary embodiment of the present invention;

[0025] Figure 8is a schematic diagram showing a memory storage device assisting a host system in executing a target logic operation according to an exemplary embodiment of the present invention;

[0026] Fig. 9 is a schematic diagram showing a memory storage device assisting a host system in executing a target logic operation according to an exemplary embodiment of the present invention;

[0027] Fig.10 is a flow chart of a computing method based on a storage device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0028] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0029] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment of the present invention. Figure 2 is a schematic diagram of a host system, a memory storage device, and an I / O device according to an exemplary embodiment of the present invention.

[0030] Please refer to Figure 1 and Figure 2 The host system 11 may include a processor 111, a random access memory (RAM) 112, a read only memory (ROM) 113, and a data transmission interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transmission interface 114 may be connected to a system bus 110.

[0031] The host system 11 may be connected to the memory storage device 10 via the data transmission interface 114. For example, the host system 11 may store data to the memory storage device 10 or read data from the memory storage device 10 via the data transmission interface 114. In addition, the host system 11 may be connected to the I / O device 12 via the system bus 110. For example, the host system 11 may transmit an output signal to the I / O device 12 or receive an input signal from the I / O device 12 via the system bus 110.

[0032] In an exemplary embodiment, the processor 111, the random access memory 112, the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of the data transmission interface 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be connected to the memory storage device 10 via a wired or wireless manner.

[0033] In an exemplary embodiment, the memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low power Bluetooth memory storage device (e.g., iBeacon) or other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 may also be connected to various I / O devices such as a global positioning system (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.

[0034] In one exemplary embodiment, the host system 11 is a computer system. In one exemplary embodiment, the host system 11 can be any system that can substantially cooperate with the memory storage device to store data. In one exemplary embodiment, the memory storage device 10 and the host system 11 can respectively include Figure 3 A memory storage device 30 and a host system 31.

[0035] Figure 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention. Figure 3 , the memory storage device 30 can be used in conjunction with a host system 31 to store data. For example, the host system 31 can be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 can be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded storage device 34 includes various types of embedded storage devices that directly connect the memory module to the substrate of the host system, such as an embedded Multi Media Card (eMMC) 341 and / or an embedded Multi Chip Package (eMCP) storage device 342.

[0036] Figure 4is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Figure 4 The memory storage device 10 includes a connection interface unit 41 , a memory control circuit unit 42 , a rewritable non-volatile memory module 43 and a computing circuit 44 .

[0037] The connection interface unit 41 is used to connect to the host system 11. The memory storage device 10 can communicate with the host system 11 via the connection interface unit 41. For example, the connection interface unit 41 can be compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 41 may also comply with the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard or other suitable standards. The connection interface unit 41 and the memory control circuit unit 42 may be packaged in one chip, or the connection interface unit 41 may be disposed outside a chip including the memory control circuit unit 42 .

[0038] The memory control circuit unit 42 is connected to the connection interface unit 41, the rewritable non-volatile memory module 43 and the operation circuit 44. The memory control circuit unit 42 is used to control the rewritable non-volatile memory module 43. For example, the memory control circuit unit 42 can instruct the rewritable non-volatile memory module 43 to perform operations such as writing, reading and erasing data according to the instructions of the host system 11. For example, the memory control circuit unit 42 may include a flash memory controller.

[0039] The rewritable non-volatile memory module 43 is used to store data written by the host system 11. The rewritable non-volatile memory module 43 may include a single level cell (SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one storage cell), a multi level cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one storage cell), a triple level cell (TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one storage cell), a quad level cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one storage cell), other flash memory modules, or other memory modules with the same or similar characteristics.

[0040] The operation circuit 44 is used to perform at least one logical operation. For example, the operation circuit 44 can be used to perform logical operations such as convolution, mod, binarization and / or data compression of an image, and the types of logical operations that the operation circuit 44 can perform are not limited thereto. In addition, the operation circuit 44 may include a graphics processing unit (GPU), a vision processing unit (VPU), a neural network processor (NPU) or other types of hardware circuits specifically used to perform the aforementioned various logical operations.

[0041] Figure 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention. Figure 5 The memory control circuit unit 42 includes a memory management circuit 51 , a host interface 52 and a memory interface 53 .

[0042] The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. For example, the memory management circuit 51 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application specific integrated circuits (ASIC), programmable logic devices (PLD), or other similar devices or combinations of these devices.

[0043] The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 can communicate with the host system 11 through the host interface 52. For example, the host interface 52 can be compatible with the PCI Express standard, the SATA standard, the PATA standard, the IEEE1394 standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards. The memory interface 53 is connected to the memory management circuit 51. The memory management circuit 51 can access the rewritable non-volatile memory module 43 through the memory interface 53.

[0044] In an exemplary embodiment, the memory control circuit unit 42 further includes an error checking and correction circuit 54 , a buffer memory 55 , and a power management circuit 56 .

[0045] The error checking and correction circuit 54 is connected to the memory management circuit 51 and is used to perform error checking and correction operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correction circuit 54 generates a corresponding error correcting code (ECC) and / or error detecting code (EDC) for the data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding error correcting code and / or error detecting code into the rewritable non-volatile memory module 43. Afterwards, when the memory management circuit 51 reads data from the rewritable non-volatile memory module 43, the error correcting code and / or error detecting code corresponding to the data will be read at the same time, and the error checking and correction circuit 54 will perform error checking and correction operations on the read data according to the error correcting code and / or error detecting code.

[0046] The buffer memory 55 is connected to the memory management circuit 51 and is used to temporarily store data. The power management circuit 56 is connected to the memory management circuit 51 and is used to control the power of the memory storage device 10 .

[0047] Figure 6 FIG. 1 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 6 The memory management circuit 51 may logically group the physical units 610 ( 0 ) to 610 (B) in the rewritable non-volatile memory module 43 into a storage area 601 and a spare area 602 .

[0048] In an exemplary embodiment, a physical unit refers to a physical address or a physical programming unit. In an exemplary embodiment, a physical unit may also be composed of multiple continuous or discontinuous physical addresses. In an exemplary embodiment, a physical unit may also refer to a virtual block (VB). A virtual block may include multiple physical addresses or multiple physical programming units. In an exemplary embodiment, a virtual block may include one or more physical erase units.

[0049] In an exemplary embodiment, the physical units 610(0)-610(A) in the storage area 601 are used to store user data (e.g., Figure 1 The user data of the host system 11 of the storage area 601). For example, the physical units 610(0)~610(A) in the storage area 601 can store valid data and invalid data. The physical units 610(A+1)~610(B) in the idle area 602 do not store data (such as valid data). For example, if a physical unit does not store valid data, this physical unit can be associated (or added) to the idle area 602. In addition, the physical units in the idle area 602 (or the physical units that do not store valid data) can be erased. When writing new data, one or more physical units can be extracted from the idle area 602 to store the new data. In an exemplary embodiment, the idle area 602 is also called a free pool.

[0050] In an exemplary embodiment, the memory management circuit 51 may configure the logical units 612(0)-612(C) to map the physical units 610(0)-610(A) in the storage area 601. In an exemplary embodiment, each logical unit corresponds to a logical address. For example, a logical address may include one or more logical block addresses (LBAs) or other logical management units. In an exemplary embodiment, a logical unit may also correspond to a logical programming unit or be composed of multiple continuous or discontinuous logical addresses.

[0051] In an exemplary embodiment, the memory management circuit 51 may record management data describing the mapping relationship between the logical unit and the physical unit (also referred to as logical-to-physical mapping information) in at least one logical-to-physical mapping table. When the host system 11 wants to read data from the memory storage device 10 or write data to the memory storage device 10, the memory management circuit 51 may access the rewritable non-volatile memory module 43 according to the information in the logical-to-physical mapping table.

[0052] In an exemplary embodiment, the host system 11 may send at least one instruction (also referred to as an operation instruction) to the memory storage device 10. The memory management circuit 51 may receive the operation instruction from the host system 11. In particular, the operation instruction may include specially designed header data. The header data may carry setting information related to a specific logical operation (also referred to as a target logical operation). For example, the target logical operation may be a logical operation such as convolution, modulo, binarization and / or data compression supported by the operation circuit 44, and the type of the target logical operation is not limited thereto.

[0053] After receiving the operation instruction, the memory management circuit 51 can obtain the header data from the operation instruction. Then, the memory management circuit 51 can instruct the operation circuit 44 to perform the target logic operation according to the header data. For example, the memory management circuit 51 can set the operation circuit 44 according to the setting information carried by the header data and instruct the operation circuit 44 to perform the target logic operation.

[0054] Figure 7 is a schematic diagram of an operation instruction according to an exemplary embodiment of the present invention. Figure 7 In an exemplary embodiment, the memory management circuit 51 may receive an operation instruction 710 from the host system 11. The operation instruction 710 may include header data 711 and user data 712. The header data 711 may carry setting information related to the target logical operation. For example, the header data 711 may include header description data 713 and header parameter data 714. The header description data 713 may carry data length information related to the header parameter data 714. The data length information may reflect the data length of the header parameter data 714. The header parameter data 714 is used to carry setting information related to the target logical operation. In addition, the user data 712 includes at least part of the data (also referred to as the first target data) to be involved in the target logical operation.

[0055] In an exemplary embodiment, the setting information may include at least one of enabling information related to the target logic operation, type information related to the target logic operation, parameter setting information related to the target logic operation, and logic address information related to the target logic operation. The enabling information is used to indicate the enabling of the target logic operation. For example, the memory management circuit 51 may enable (e.g., enable) the operation circuit 44 according to the enabling information. The type information is used to indicate the type of the target logic operation. For example, the memory management circuit 51 may set the operation circuit 44 according to the type information to control the operation circuit 44 to perform a specific type of target logic operation. The parameter setting information is used to indicate at least one parameter used by the target logic operation. For example, the memory management circuit 51 may set at least one parameter used by the operation circuit 44 when performing the target logic operation according to the parameter setting information. The logic address information is used to indicate the logic address corresponding to at least part of the data participating in the target logic operation. For example, the memory management circuit 51 may read at least part of the data to be participated in the target logic operation from the rewritable non-volatile memory module 43 according to the logic address information. For example, the logic address information may reflect at least one logic address. The memory management circuit 51 can instruct the rewritable non-volatile memory module 43 to read at least a portion of data (also called second target data or third target data) to participate in the target logic operation from the physical address mapped by the at least one logical address according to the logical address information.

[0056] In an exemplary embodiment, the data amount (or data length) of the user data 712 is greater than zero. For example, when the data amount (or data length) of the user data 712 is greater than zero, the operation instruction 710 may be considered to include the user data 712. In an exemplary embodiment, the data amount (or data length) of the user data 712 may be zero. For example, when the data amount (or data length) of the user data 712 is zero, the operation instruction 710 may be considered to not include the user data 712. In addition, the operation instruction 710 may also include a write instruction or a read instruction. The write instruction is used to instruct the memory storage device 10 to perform a data write operation. The read instruction is used to instruct the memory storage device 10 to perform a data read operation.

[0057] In an exemplary embodiment, it is assumed that the operation instruction 710 includes user data 712. According to the operation instruction 710, the memory management circuit 51 may instruct the operation circuit 44 to perform a target logic operation on the first target data carried by the user data 712. For example, after receiving the operation instruction 710, the memory management circuit 51 may set the operation circuit 44 according to the header data 711. Then, the memory management circuit 51 may input the first target data carried by the user data 712 to the operation circuit 44. The operation circuit 44 may perform a target logic operation according to the first target data.

[0058] In an exemplary embodiment, according to the operation instruction 710, the memory management circuit 51 may also read the second target data from the rewritable non-volatile memory module 43. Then, the memory management circuit 51 may instruct the operation circuit 44 to perform a target logic operation on the first target data and the second target data read from the rewritable non-volatile memory module 43. For example, the memory management circuit 51 may instruct the rewritable non-volatile memory module 43 to read the second target data from a specific physical address according to the logical address information in the header data 711 (or the header parameter data 714). After completing the setting of the operation circuit 44, the memory management circuit 51 may input the first target data carried by the user data 712 and the second target data read from the rewritable non-volatile memory module 43 to the operation circuit 44. The operation circuit 44 may perform a target logic operation according to the first target data and the second target data.

[0059] In an exemplary embodiment, it is assumed that the operation instruction 710 does not include the user data 712. According to the operation instruction 710, the memory management circuit 51 can read the third target data from the rewritable non-volatile memory module 43. Then, the memory management circuit 51 can instruct the operation circuit 44 to perform a target logic operation on the third target data. For example, the memory management circuit 51 can instruct the rewritable non-volatile memory module 43 to read the third target data from a specific physical address according to the logical address information in the header data 711 (or the header parameter data 714). After completing the setting of the operation circuit 44, the memory management circuit 51 can input the third target data read from the rewritable non-volatile memory module 43 to the operation circuit 44. The operation circuit 44 can perform a target logic operation according to the third target data.

[0060] In an exemplary embodiment, the memory management circuit 51 may determine the operation instruction (eg Figure 7 In response to the operation instruction 710 including a write instruction or a read instruction, the memory management circuit 51 may store the operation result of the target logic operation in the rewritable non-volatile memory module 43. Thereafter, the memory management circuit 51 may read the operation result from the rewritable non-volatile memory module 43. Alternatively, in response to the operation instruction including a read instruction, the memory management circuit 51 may return the operation result to the host system 11.

[0061] Figure 8 FIG. 1 is a schematic diagram showing a memory storage device assisting a host system in executing a target logic operation according to an exemplary embodiment of the present invention. Figure 8In an exemplary embodiment, the memory management circuit 51 may receive an operation instruction 810 from the host system 11. The operation instruction 810 includes header data 811 and data 812 (ie, user data or first target data). In addition, the operation instruction 810 includes a write instruction instructing to perform a data write operation.

[0062] According to the operation instruction 810, the memory management circuit 51 can start the operation circuit 44 and set the operation circuit 44. For example, according to the enable information in the operation instruction 810, the memory management circuit 51 can start the operation circuit 44. According to the type information in the operation instruction 810, the memory management circuit 51 can set the operation circuit 44 to perform a matrix modulo operation (i.e., a target logical operation). In addition, according to the logical address information in the operation instruction 810, the memory management circuit 51 can read the data 820 (i.e., the second target data) from the rewritable non-volatile memory module 43. Then, the memory management circuit 51 can input the data 812 and 820 to the operation circuit 44. The operation circuit 44 can perform a matrix modulo operation (i.e., a target logical operation) on the data 812 and 820 and generate data 830. The data 830 can reflect the operation result of the target logical operation. After generating the data 830 , in response to a write instruction in the operation instruction 810 , the memory management circuit 51 may store the data 830 in the rewritable non-volatile memory module 43 for subsequent use.

[0063] Fig. 9 FIG. 1 is a schematic diagram showing a memory storage device assisting a host system in executing a target logic operation according to an exemplary embodiment of the present invention. Fig. 9 In an exemplary embodiment, the memory management circuit 51 may receive an operation instruction 910 from the host system 11. The operation instruction 910 includes header data 911. In addition, the operation instruction 910 includes a write instruction instructing to perform a data write operation and a read instruction following the write instruction.

[0064] According to the operation instruction 910, the memory management circuit 51 can start the operation circuit 44 and set the operation circuit 44. For example, according to the enable information in the operation instruction 910, the memory management circuit 51 can start the operation circuit 44. According to the type information in the operation instruction 910, the memory management circuit 51 can set the operation circuit 44 to perform the binary operation of the matrix (i.e., the target logical operation). According to the parameter setting information in the operation instruction 910, the memory management circuit 51 can set the maximum value, minimum value and critical value used in the binary operation to "10", "0" and "5" respectively. That is, in this binary operation, if a certain parameter value is greater than the critical value (i.e., "5"), the parameter value will be adjusted to the set maximum value (i.e., "10"); however, if a certain parameter value is less than the critical value (i.e., "5"), the parameter value will be adjusted to the set minimum value (i.e., "0"). In addition, according to the logic address information in the operation instruction 910, the memory management circuit 51 can read the data 920 (i.e., the third target data) from the rewritable non-volatile memory module 43. Then, the memory management circuit 51 can input the data 920 to the operation circuit 44. The operation circuit 44 can perform a binarization operation (i.e., a target logic operation) on the data 920 and generate data 930. The data 930 can reflect the operation result of the target logic operation.

[0065] After generating the data 930, in response to the read instruction in the operation instruction 910, the memory management circuit 51 may return the data 930 to the host system 11. It should be noted that in the aforementioned exemplary embodiments, the header data in the operation instruction may also include other useful information, depending on practical needs, and the present invention is not limited thereto.

[0066] In an exemplary embodiment, the aforementioned operation mode of further adding additional computing operations performed by the memory storage device 10 during the data reading and / or writing process is also called the Compute-Intensive Read / Write (CIRW) mode. This mode is generally used in scenarios where complex computing tasks need to be performed in computer systems and / or storage systems, such as data analysis, machine learning, image processing, etc. This mode has the following beneficial effects: during the data reading or writing process, not only data is transmitted, but also complex computing processing is performed; data processing is integrated into the storage system, reducing the overhead of data transmission; real-time processing can be performed while data is being read or written, improving processing efficiency; and by performing calculations in the storage system, dependence on the central processing unit (CPU) and network bandwidth is reduced. In addition, in the following exemplary embodiments, the operations performed by the host system 11 can be regarded as performed by Figure 1 The operations performed by the processor 111.

[0067] In an exemplary embodiment, the host system 11 may perform a pre-processing operation on an image (also referred to as a target image) to generate feature data corresponding to the target image. The feature data may reflect image features related to the target image.

[0068] In an exemplary embodiment, the host system 11 may send the operation instruction to the memory storage device 10 according to the characteristic data. The operation instruction may instruct the memory storage device 10 to store the characteristic data in the rewritable non-volatile memory module 43, read the characteristic data from the rewritable non-volatile memory module 43, and / or perform a logic operation (i.e., a target logic operation) on the characteristic data.

[0069] In an exemplary embodiment, the host system 11 may use the image features to train an artificial intelligence model. For example, the artificial intelligence model may include a convolutional neural network (CNN) model, an autoencoder model, a feature pyramid network (FPNs) model, a transformer model, or a capsule network model. A convolutional neural network is a deep learning model specifically designed to process data with a grid structure (such as images).

[0070] Autoencoder models can be used for dimensionality reduction and feature extraction. After training an autoencoder model to encode the key features of an image, the decoder part can be discarded, leaving only the encoder as a feature extractor. This is an unsupervised learning method that is mainly used in areas such as feature learning, data dimensionality reduction, and generative models. An autoencoder consists of an input layer, a hidden layer, and an output layer, and its goal is to learn the intrinsic representation of the data by reconstructing the input data.

[0071] Feature pyramid network models are able to capture features at different scales and are very useful for tasks such as object detection. By pre-extracting multi-scale features, the training of subsequent models can be accelerated. Transformer models were originally designed for natural language processing, but they also perform well on visual tasks. They can learn global contextual information from key areas of an image. Therefore, it has been widely used in computer vision and other fields. Capsule network models try to capture the part-whole hierarchy of objects, which is very useful for identifying objects and their poses in images.

[0072] Capsule network is an architecture designed to improve the performance of traditional convolutional neural networks (CNNs) in image recognition tasks, especially in solving problems such as object pose estimation and translation invariance. The main feature of capsule network is that it uses so-called "capsule" units instead of traditional neurons. These capsule units can not only capture the basic features of the object, but also capture the pose information of the object (such as direction, size, etc.). Each capsule is actually a vector that can represent multiple attributes of a feature, not just a single scalar activation value. Through dynamic routing algorithms, capsule networks can better handle the position and shape changes of objects in images. It should be noted that the artificial intelligence model may also include other types of models, which are not limited by the present invention.

[0073] In an exemplary embodiment, the host system 11 may use a metadata indexing strategy to save the key features of the target image (i.e., the feature data) and the complete target image. In an exemplary embodiment, the host system 11 may create an index file. The index file may record information such as the storage location and size of each key feature of the target image. Thereafter, the host system 11 may query the index file to obtain each key feature of the target image (i.e., the feature data).

[0074] In an exemplary embodiment, during the pre-processing operation, the host system 11 may divide the target image into multiple parts (such as grids) and create a separate file for each part. Thereafter, the file corresponding to each part may be loaded and used independently, thereby improving operational flexibility.

[0075] In an exemplary embodiment, the host system 11 may create corresponding metadata for the target image and each segmented portion. The metadata includes identification information of the target image, location information of each portion of the target image (e.g., grid location), file names or storage locations corresponding to each portion of the target image, or category labels, etc., which are data that helps to identify and / or classify each portion segmented from the target image (also referred to as attribute data).

[0076] In an exemplary embodiment, the host system 11 may record the metadata in the index file. In addition, the host system 11 may store the target image and the portions segmented from the target image in the memory storage device 10.

[0077] In an exemplary embodiment, the target image may be stored in the memory storage device 10 based on a certain storage mode (also referred to as the first storage mode), and the parts segmented from the target image may be stored in the memory storage device 10 based on another storage mode (also referred to as the second storage mode). For example, the first storage mode may include a triple-level cell (TLC) or a quad-level cell (QLC) mode for storage, and the second storage mode may include a single-level cell (SLC) mode. In addition, the first storage mode and the second storage mode may also be adjusted according to practical needs, and the present invention is not limited thereto.

[0078] In an exemplary embodiment, the host system 11 may query the index file to obtain metadata corresponding to a specific portion segmented from the target image. Then, the host system 11 may generate an operation instruction with specific header data based on the obtained metadata. Thereafter, in the aforementioned compute-attached-read-write (CIRW) mode, the host system 11 may access the memory storage device 10 through this operation instruction. In particular, during the period of accessing the memory storage device 10 through this operation instruction, the host system 11 may instruct the memory storage device 10 to perform a target logical operation on the specific portion segmented from the target image through the header data carried by the operation instruction. For relevant operation details, please refer to the aforementioned exemplary embodiments (e.g. Figure 8 and Fig. 9 ) are described and will not be repeated here.

[0079] In an exemplary embodiment, the artificial intelligence model does not need to access the complete image data for training, but can be trained by extracting key information of the image (i.e., specific parts segmented from the target image), thereby improving training efficiency. In other words, by pre-processing (e.g., segmenting) the image data during the storage stage, the time consumption required to load the entire image during training can be reduced. This approach can not only simplify the data preparation process for model training, but also significantly reduce the demand for computing resources.

[0080] In an exemplary embodiment, in the metadata indexing strategy, the host system 11 can select a suitable database to store metadata based on the data access mode and the amount of data. For example, the host system 11 can select a suitable one from a relational database, a NoSQL database, or other types of databases based on the content of the metadata to be stored, the complexity of the created index, and / or the type of artificial intelligence model used in combination, and use the selected database to store the metadata. In particular, a reasonable metadata storage and access design can greatly improve the efficiency of model training and make the storage system more flexible and powerful.

[0081] Fig.10is a flow chart of a computing method based on a storage device according to an exemplary embodiment of the present invention. Fig.10 In step S1001, an operation instruction is received from a host system, wherein the operation instruction includes header data, and the header data carries setting information related to a target logic operation. In step S1002, the header data is obtained from the operation instruction. In step S1003, according to the header data, an operation circuit inside a memory storage device is instructed to execute a target logic operation.

[0082] However, Fig.10 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Fig.10 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Fig.10 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0083] In summary, the computing method based on the storage device, the memory storage device and the memory control circuit unit proposed in the present invention can configure the computing circuit supporting the target logic operation in the memory storage device. Afterwards, the host system can send an operation instruction including specially designed header data to the memory storage device to instruct the memory storage device to perform the target logic operation. Thus, the cooperation efficiency between the host system and the memory storage device can be improved.

[0084] On the other hand, the computing method based on the storage device, the memory storage device and the memory control circuit unit proposed in the present invention can synchronously complete the logical operation of the data during the process of the host system writing data to or reading data from the storage device. Therefore, the computing method based on the storage device, the memory storage device and the memory control circuit unit proposed in the present invention can provide at least one of the following advantages:

[0085] 1. Reduce the hardware specifications and / or implementation costs of a host system (eg, a computer terminal system). For example, the host system may not need to install additional and / or specialized chips.

[0086] 2. The storage device shares the computing task. Whether a dedicated chip or a central processing unit (CPU) is used for matrix calculation, there is always some data that needs to be read out from the storage device and then calculated. However, after using the present invention, the result read out is the result of the calculation, which reduces the computing task of other computing units.

[0087] 3. Improve the overall efficiency of the system. Traditionally, the host system often stores the data after calculation, or reads the data and uses it after calculation. There are two places where time is wasted in this process. One is waiting for the data to be read or written, and the other is processing and calculating the data in the memory. When waiting for data, the process can be suspended, and the CPU can handle other tasks, but the calculation of data still occupies the CPU. However, after using the present invention, the time for data calculation can be hidden in the time for waiting for data transmission.

[0088] 4. Reduce system complexity. For some small systems, such as driving recorders and recording equipment, there are some requirements for data compression and simple calculation. The use of the present invention can further improve the integration of these small systems, thereby simplifying the system, reducing costs, and improving stability.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A computing method based on a storage device, characterized in that: For a memory storage device, the operation method comprises: receiving an operation instruction from a host system, wherein the operation instruction includes header data, and the header data carries setting information related to a target logical operation; acquiring the header data from the operation instruction; and According to the header data, the operation circuit inside the memory storage device is instructed to execute the target logic operation.

2. The operation method according to claim 1, wherein the setting information includes at least one of enabling information related to the target logic operation, type information related to the target logic operation, parameter setting information related to the target logic operation, and logic address information related to the target logic operation, The enabling information is used to indicate the enabling of the target logic operation. The type information is used to indicate the type of the target logical operation, The parameter setting information is used to indicate at least one parameter used by the target logic operation, and The logical address information is used to indicate a logical address corresponding to at least a portion of data participating in the target logical operation.

3. The operation method according to claim 1, wherein the operation instruction further comprises first target data, and the step of instructing the operation circuit inside the memory storage device to perform the target logic operation according to the header data comprises: According to the header data, the operation circuit is instructed to perform the target logic operation on the first target data.

4. The operation method according to claim 3, wherein the step of instructing the operation circuit to perform the target logic operation on the first target data according to the header data comprises: Reading second target data from a rewritable non-volatile memory module inside the memory storage device according to the header data; as well as The operation circuit is instructed to perform the target logic operation on the first target data and the second target data.

5. The operation method according to claim 1, wherein the step of instructing the operation circuit inside the memory storage device to execute the target logic operation according to the header data comprises: Reading third target data from a rewritable non-volatile memory module inside the memory storage device according to the header data; as well as The operation circuit is instructed to perform the target logical operation on the third target data.

6. The operation method according to claim 1, further comprising: In response to the operation instruction including a write instruction, storing the operation result of the target logic operation in a rewritable non-volatile memory module inside the memory storage device; as well as In response to the operation instruction including a read instruction, the operation result is returned to the host system.

7. A memory storage device, characterized in that: include: A connection interface unit for connecting to a host system; Rewritable non-volatile memory module; Operational circuit; as well as A memory control circuit unit connected to the connection interface unit, the rewritable non-volatile memory module and the operation circuit, The memory control circuit unit is used to: receiving an operation instruction from the host system, wherein the operation instruction includes header data, and the header data carries setting information related to a target logical operation; acquiring the header data from the operation instruction; and According to the header data, the operation circuit is instructed to execute the target logic operation.

8. The memory storage device according to claim 7, wherein the setting information comprises at least one of enabling information related to the target logic operation, type information related to the target logic operation, parameter setting information related to the target logic operation, and logic address information related to the target logic operation, The enabling information is used to indicate the enabling of the target logic operation. The type information is used to indicate the type of the target logical operation, The parameter setting information is used to indicate at least one parameter used by the target logic operation. The logical address information is used to indicate a logical address corresponding to at least a portion of data participating in the target logical operation.

9. The memory storage device according to claim 8, wherein the operation instruction further comprises first target data, and according to the header data, the operation of instructing the operation circuit inside the memory storage device to perform the target logic operation comprises: According to the header data, the operation circuit is instructed to perform the target logic operation on the first target data.

10. The memory storage device according to claim 9, wherein, according to the header data, the operation of instructing the operation circuit to perform the target logic operation on the first target data comprises: Reading second target data from the rewritable non-volatile memory module according to the header data; as well as The operation circuit is instructed to perform the target logic operation on the first target data and the second target data.

11. The memory storage device according to claim 7, wherein the operation of instructing the operation circuit inside the memory storage device to perform the target logic operation according to the header data comprises: Reading third target data from the rewritable non-volatile memory module according to the header data; as well as The operation circuit is instructed to perform the target logical operation on the third target data.

12. The memory storage device according to claim 7, wherein the memory control circuit unit is further configured to: In response to the operation instruction including a write instruction, storing the operation result of the target logic operation in a rewritable non-volatile memory module inside the memory storage device; and In response to the operation instruction including a read instruction, the operation result is returned to the host system.

13. A memory control circuit unit, characterized in that: Used to control a memory storage device, wherein the memory storage device includes a rewritable non-volatile memory module, and the memory control circuit unit includes: A host interface for connecting to a host system; A memory interface for connecting to the rewritable non-volatile memory module; and A memory management circuit connected to the host interface and the memory interface, The memory management circuit is used to: receiving an operation instruction from the host system, wherein the operation instruction includes header data, and the header data carries setting information related to a target logical operation; acquiring the header data from the operation instruction; and According to the header data, the operation circuit inside the memory storage device is instructed to execute the target logic operation.

14. The memory control circuit unit according to claim 13, wherein the setting information comprises at least one of enabling information related to the target logic operation, type information related to the target logic operation, parameter setting information related to the target logic operation, and logic address information related to the target logic operation, The enabling information is used to indicate the enabling of the target logic operation. The type information is used to indicate the type of the target logical operation, The parameter setting information is used to indicate at least one parameter used by the target logic operation. The logical address information is used to indicate a logical address corresponding to at least a portion of data participating in the target logical operation.

15. The memory control circuit unit according to claim 13, wherein the operation instruction further comprises first target data, and according to the header data, the operation of instructing the operation circuit inside the memory storage device to perform the target logic operation comprises: According to the header data, the operation circuit is instructed to perform the target logic operation on the first target data.

16. The memory control circuit unit according to claim 15, wherein, according to the header data, the operation of instructing the operation circuit to perform the target logic operation on the first target data comprises: Reading second target data from the rewritable non-volatile memory module according to the header data; as well as The operation circuit is instructed to perform the target logic operation on the first target data and the second target data.

17. The memory control circuit unit according to claim 13, wherein the operation of instructing the operation circuit inside the memory storage device to perform the target logic operation according to the header data comprises: Reading third target data from the rewritable non-volatile memory module according to the header data; as well as The operation circuit is instructed to perform the target logical operation on the third target data.

18. The memory control circuit unit according to claim 13, wherein the memory management circuit is further configured to: In response to the operation instruction including a write instruction, storing the operation result of the target logic operation in a rewritable non-volatile memory module inside the memory storage device; and In response to the operation instruction including a read instruction, the operation result is returned to the host system.

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