Instruction processing method and device, storage medium and electronic device

Abstract

The embodiment of the invention provides an instruction processing method and device, a storage medium and an electronic device.The method comprises the steps that a first type of to-be-processed instructions are determined from multiple to-be-processed instructions according to preset instruction codes, and a first vector parameter is updated into a second vector parameter in an updating mode corresponding to the first type of to-be-processed instructions; and splitting a long vector instruction in other to-be-processed instructions into a plurality of micro-operations based on the second vector parameter, and renaming the other to-be-processed instructions according to the plurality of micro-operations, the other to-be-processed instructions being instructions except the first type of to-be-processed instructions in the plurality of to-be-processed instructions. According to the method and the device, the problem that an execution part circuit in a processor is too complex and too large in area and power consumption due to the appearance of a long vector in a vector instruction in the related technology is solved, and the effects of reducing the design complexity of the execution part circuit and realizing better processing frequency in a limited area are achieved.

Description

Technical Field

[0001] The present application relates to the field of RISC-V high-performance out-of-order processor microarchitecture, and specifically, to an instruction processing method, device, storage medium and electronic device. Background Art

[0002] RISC-V is an open reduced instruction set architecture. It adheres to the RISC design philosophy and the experience and lessons accumulated from decades of development of computer architecture to design a sophisticated instruction set architecture. The modular standard extended instruction subsets include M / A / F / D / C / B / P / V, etc., which can be used in different application fields.

[0003] At present, the RISC-V standard vector extension includes vector addition, subtraction, multiplication, multiplication and accumulation, bitwise logical AND, OR, XOR, comparison, shift, min / max, permutation, reduction and other vector instructions. The instruction length is fixed to 32 bits, 32 general vector registers, conditional mask register Predicate and related control status register CSR, support instruction conditional execution, multiple memory access modes single-step unit-stride, strided, index scatter / gather, etc. In addition, it supports dynamic typing, sets the vector length (grouping of vector registers) and the bit width (sew) of a single element through vsetvl / vsetvli / vsetivli, saves coding space, supports mixed precision, and maintains software compatibility under different vector lengths. The grouping parameters of vector registers are configured through the vsetvl / vsetvli / vsetivli instructions, which can splice multiple vector registers into a larger vector register, up to 8 registers, which is equivalent to the operable register width becoming 8 times the width of the currently implemented hardware register. This feature makes program writing more concise and greatly reduces the amount of executed code. The CSR register VTYPE (vector type, vector parameter, referred to as VTYPE) stores the above-mentioned vector register grouping parameter LMUL (Vector register group multiplier (LMUL) setting, vector register group configuration, referred to as LMUL). After the vsetvl / vsetvli / vsetivli instruction configures this parameter, subsequent vector instructions will group vector registers according to this parameter, and the single vector instruction operation processing width is also based on this group length until a new vsetvl / vsetvl / vsetivli instruction re-updates the parameter. After the update, all subsequent vector instructions younger than the vsetvl / vsetvli / vsetivli instruction must be executed according to the latest configuration value;

[0004] In the related art, the methods for dealing with the above-mentioned problem include the following methods: Method 1, the pipeline of a high-performance processor core is generally divided into multiple processing stages, the instruction cache (cache memory) caches the instructions to be executed, and the instruction fetch process reads the instructions to be executed from the instruction cache and sends them to the instruction decoder for decoding. Figure 3This is a schematic diagram of an instruction processing flow in the related art. When the instruction decoder recognizes that the current instruction is a vsetvl instruction that updates the vector parameter register, the vector pause flag signal is set to 1, indicating that the subsequent vector instructions need to wait for the vsetvl instruction to be executed before the next stage of renaming can be processed. Figure 2 It is a schematic diagram of another instruction processing flow in the related art. After the instruction is decoded, a vector register group value history table is added to predict the value updated by the vsetvl instruction on the register group.

[0005] However, the above-mentioned method 1 is prone to pipeline stalls due to waiting for the completion of the execution of the vsetvl instruction to obtain the vector register grouping value (LMUL) or the bit width (sew) of the vector element, and the design process of renaming according to the instruction granularity in the renaming stage is complicated; although the method 2 can alleviate the stall problem caused by the scheme 1, there is still one vector instruction in the scheme 1 that needs to support register renaming far more than ordinary instructions at the same time because it supports register grouping, and it needs to occupy the read and write ports of multiple renaming mapping tables or needs to perform read and write port arbitration, which is complex in design and has high power consumption and area costs in implementation.

[0006] With respect to the problems existing in the related art in the above-mentioned related art that the execution circuit of the processor in the vector instruction is too complicated, and the area and power consumption are too large, no effective solution has been found so far.

[0007] Application Contents

[0008] The embodiments of the present application provide an instruction processing method, device, storage medium and electronic device to at least solve the problem in the related art that the execution circuit of the processor in the vector instruction is too complicated and the area and power consumption are too large.

[0009] According to one embodiment of the present application, a method for processing instructions is provided, comprising: determining a first category of pending instructions from multiple pending instructions according to a preset instruction code, wherein the first category of pending instructions is used to update a first vector parameter in a speculative value register; updating the first vector parameter to a second vector parameter using an update method corresponding to the first category of pending instructions; splitting long vector instructions in other pending instructions into multiple micro-operations based on the second vector parameter, and renaming the other pending instructions according to the multiple micro-operations, wherein the other pending instructions are instructions in the multiple pending instructions other than the first category of pending instructions.

[0010] According to another embodiment of the present application, a bandwidth adjustment system is provided, including: a determination module, used to determine a first type of pending instructions from multiple pending instructions according to a preset instruction code, wherein the first type of pending instructions is used to update a first vector parameter in a speculative value register; an update module, used to update the first vector parameter to a second vector parameter using an update method corresponding to the first type of pending instructions; a processing module, used to split long vector instructions in other pending instructions into multiple micro-operations based on the second vector parameter, and rename the other pending instructions according to the multiple micro-operations, wherein the other pending instructions are instructions in the multiple pending instructions other than the first type of pending instructions.

[0011] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0012] According to another embodiment of the present application, an electronic device is provided, which may include a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0013] Through the above steps, in the system architecture corresponding to the CPU core, the preset instruction code is used to identify the first type of pending instructions to be executed, so as to speculatively obtain the second vector parameter between the instruction decoders, and then instruct the instruction disassembly subunit configured in the instruction decoding unit to split the long vector instructions in other pending instructions into multiple micro-operations based on the register vector grouping value contained in the second vector parameter, thereby reducing the area and power consumption overhead of the renaming and instruction issuance units for long vector processing through fine-grained micro-operations, and can also reduce the complexity and power consumption overhead of micro-operation disassembly of long vector instructions in the execution unit, that is, by determining the vector parameters in advance and using the vector parameters to disassemble the long vector before executing the corresponding long vector, the problem of excessive complexity of the execution circuit in the processor in the vector instruction in the related art, and excessive area and power consumption overhead is solved, thereby achieving the effect of reducing the design complexity of the execution circuit, and achieving a better processing frequency within a limited area, thereby improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of an instruction processing flow in the related art;

[0015] Figure 2 is a schematic diagram of another instruction processing flow in the related art;

[0016] Figure 3 It is a hardware structure block diagram of a chip of an instruction processing method according to an embodiment of the present application;

[0017] Figure 4 is a flowchart of a method for processing instructions according to an embodiment of the present application;

[0018] Figure 5 is a schematic diagram of the system structure of a method for processing instructions in a CPU chip according to an embodiment of the present application;

[0019] Figure 6 is a schematic diagram of encoding of a Risc-v vector extension instruction vset{i}vl{i} instruction according to an embodiment of the present application;

[0020] Figure 7 It is a schematic diagram of the composition of the vtype_sp update source in the instruction processing method according to the embodiment of the present application;

[0021] Figure 8 is a schematic diagram of a vector register grouping configuration according to an embodiment of the present application;

[0022] Fig. 9 It is a schematic diagram of two different computing resource configurations according to an embodiment of the present application;

[0023] Fig.10 is a structural schematic diagram of an instruction processing device according to an embodiment of the present application;

[0024] Fig.11 It is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0027] Example 1

[0028] The method embodiment provided in the first embodiment of the present application can be executed in a chip, a computer terminal or a similar computing device. Taking running on a chip as an example, Figure 3 FIG. 1 is a hardware structure block diagram of a chip of a method for processing instructions in an embodiment of the present application. Figure 3As shown, the chip 10 may include one or more (only one is shown in the figure) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA), a memory 104 for storing data, and a transmission device 106 for communication functions. It can be understood by those skilled in the art that Figure 3 The structure shown is only for illustration and does not limit the structure of the above electronic device. Figure 3 More or fewer components as shown, or with Figure 3 Different configurations shown.

[0029] The memory 104 can be used to store software programs and modules of application software, such as program instructions / modules corresponding to the instruction processing method in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implementing the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the chip 10 via a network. Examples of the above-mentioned network may include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0030] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by the communication provider of the chip 10. In one example, the transmission device 106 may include a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0031] Optionally, in practical applications, the above instruction processing method can be applied to a CPU processor and a Risc-v CPU core IP or a SOC chip integrating a Risc-vCPU core, and this application does not make too many restrictions on this.

[0032] In this embodiment, a method for processing an instruction is provided. Figure 4 is a flowchart of a method for processing instructions according to an embodiment of the present application, such as Figure 4 As shown, the process may include, but is not limited to, the following steps:

[0033] Step S202, determining a first type of instructions to be processed from a plurality of instructions to be processed according to a preset instruction code, wherein the first type of instructions to be processed are used to update a first vector parameter in a speculative value register;

[0034] In an optional embodiment, the above-mentioned preset instruction code can be a vector extension instruction determined based on the 32-bit instruction code of Risc-v, such as: vset{i}vl{i} instruction code, and the vset{i}vl{i} instruction code includes: vsetvl, vsetvli, vsetivli, etc., wherein vsetvl is used to indicate instructions that require reading registers to obtain configuration values ​​(including but not limited to vselvl), and vsetvli is used to indicate instructions that do not require reading registers and can obtain parameter configuration values ​​from the instruction code (immediate number) (including but not limited to vsetvli and vsetivli); thereby, when the instruction of the above-mentioned vset{i}vl{i} instruction code is identified in the instructions to be processed, the parameters used to update the vector parameter generation unit can be quickly determined according to the content corresponding to the instruction code.

[0035] Step S204, updating the first vector parameter to a second vector parameter using the update method corresponding to the first type of instructions to be processed;

[0036] It should be noted that after the vector parameters configured in the speculative value register are updated using the vsetvl / vsetvli / vsetivli instructions, subsequent vector instructions will group the vector registers according to the second vector parameter, and the operation processing width of a single vector instruction will also be based on this grouping length until a new vsetvl / vsetvl / vsetivli instruction is used to re-update the second vector parameter. After the update, all subsequent vector instructions younger than the vsetvl / vsetvli / vsetivli instruction will be executed according to the latest vector parameter configuration value in the speculative value register.

[0037] Step S206: split the long vector instruction in other pending instructions into multiple micro-operations based on the second vector parameter, and rename the other pending instructions according to the multiple micro-operations, wherein the other pending instructions are instructions in the multiple pending instructions except the first type of pending instructions.

[0038] Through the above steps, in the system architecture corresponding to the CPU core, the preset instruction code is used to identify the first type of pending instructions to be executed, so as to speculatively obtain the second vector parameter between the instruction decoders, and then instruct the instruction disassembly subunit configured in the instruction decoding unit to split the long vector instructions in other pending instructions into multiple micro-operations based on the register vector grouping value contained in the second vector parameter, thereby reducing the area and power consumption overhead of the renaming and instruction issuance units for long vector processing through fine-grained micro-operations, and can also reduce the complexity and power consumption overhead of micro-operation disassembly of long vector instructions in the execution unit, that is, by determining the vector parameters in advance and using the vector parameters to disassemble the long vector before executing the corresponding long vector, the problem of excessive complexity of the execution circuit in the processor in the vector instruction in the related art, and excessive area and power consumption overhead is solved, thereby achieving the effect of reducing the design complexity of the execution circuit, and achieving a better processing frequency within a limited area, thereby improving the user experience.

[0039] It is understandable that the appearance of long vectors in vector instructions causes the naming circuit (such as: the source register of the long vector instruction needs to query multiple registers, the instruction destination register needs to apply for multiple physical registers, the instruction emission circuit (such as: the emission queue needs to save multiple register IDs and perform wake-up operations on multiple registers), and the instruction execution circuit (such as: the long vector circuit disassembles the micro-operations of multiple short vectors, and the pipeline needs to be stalled) to be too complicated, and the area and power consumption overhead is large, so that the vector instructions cannot be executed quickly, and the overall instruction processing effect is greatly reduced. By using the above method, the long vector is disassembled in the instruction decoding unit. After the disassembly, the naming circuit in the back stage of the Pipeline pipeline does not need to perceive the vector register grouping configuration LMUL, the bit width SEW of the vector element changes, and the required disassembly logic circuit is reduced, thereby reducing the circuit complexity of the back stage of the Pipeline pipeline and optimizing the area and power consumption.

[0040] As an optional implementation, the above method can also be applied to high-performance vector computing scenarios, such as: multimedia (audio, video, image, etc.) data processing, digital signal processing, scientific computing and AI and other computing-intensive fields, as well as compiler scalar-to-quantity optimization and other high-performance CPU field application scenarios. In practice, by speculatively acquiring vector parameters, long vector instructions and vector instructions with resource constraints are split and processed, thereby reducing the hardware resource (area, power consumption, etc.) overhead caused by long vector instructions in the pipeline, and achieving a better PPA (performance, power, area, performance, power consumption, area, referred to as PPA) balance.

[0041] In an exemplary embodiment, when the processing method of the above-mentioned instructions is applied in a CPU chip, the corresponding system structure will be added with: a vector parameter generation unit, a vector instruction disassembly subunit is added to the instruction decoding unit, a transmission queue vtype_sp (vector parameter speculative value) is added to the instruction emission unit, and a vtype (vector parameter) speculative correction subunit is added to the vsetvl instruction execution unit.

[0042] Optional, Figure 5 1 is a schematic diagram of a system structure of a method for processing instructions in a CPU chip according to an embodiment of the present application, including:

[0043] Instruction cache unit 32: used to cache instructions retrieved from the next level of cache. When instructions are looped or repeatedly executed, they can be obtained from the instruction cache (cache memory) without having to be obtained from the lower level cache, which reduces the latency of obtaining values ​​and thus improves performance.

[0044] Instruction fetch processing unit 34: used to query and obtain the instruction to be executed from the instruction cache unit according to the instruction fetch instruction, including virtual-to-real address conversion, query whether it hits, if it does not hit, it needs to issue a request to query and obtain from the next layer of cache, and perform alignment operations after obtaining the instruction;

[0045] The instruction pre-decoding unit 36 ​​is used to identify the three instructions vsetvl, vsetvli and vsetivli according to the 32-bit instruction code of Risc-v, and notify the vector parameter generation unit of the identification result;

[0046] Optionally, the encoding contents of the above three instructions vsetvl, vsetvli, vsetivli are as follows Figure 6 As shown, Figure 6 This is a schematic diagram of the encoding of the Risc-v vector extension instruction vset{i}vl{i} instruction according to an embodiment of the present application.

[0047] The vector parameter generating unit 38 is used to determine the vector parameter for processing the subsequent vector instruction; mainly to determine the value of the vector parameter to be stored in the vector parameter speculation value register in a variety of ways.

[0048] Specifically, when it is determined that the current instruction identified by the instruction pre-decoding unit 36 ​​is a vsetvli or vsetivli instruction, an immediate value to be updated in the vtype register is parsed from the 32-bit instruction code corresponding to the vsetvli or vsetivli instruction, and the vector parameter of the vtype_sp register is updated with the immediate value;

[0049] If the current instruction is a vsetvl instruction, the characteristic information of the current thread (such as ASID and VMID, etc.) is used as matching information to search the vector parameter prediction table for matching prediction information. If so, the predicted value of vtype is obtained from the prediction table and updated to the vtype_sp register with the predicted value. It should be noted that if there is no match, the original value can be maintained, or updated to the commonly used LMUL=1 and other preset possible solutions.

[0050] It should be noted that the vector parameter in the vtype_sp register is equivalent to the speculative value of the vtype register, because it can be updated using the vsetvli / vsetivli instructions on the wrong branch path, or updated by prediction using the vsetvl instruction, so it is a speculative value;

[0051] If the vsetvl instruction occurs and the speculation correction subunit in the execution unit detects a speculation failure, the vtype_sp register will be updated with the execution result corresponding to the processing device;

[0052] Optionally, if an interrupt, exception, or other PipelineFlush based on the oldest instruction boundary occurs in the processing device, the vtype_sp register needs to be updated with the value of the vtype register (committed value);

[0053] The instruction decoding unit 40 is responsible for decoding all instructions. When the current instruction is identified as a vector instruction, the vector instruction disassembly subunit is used to split the subsequent vector instructions according to the LMUL value carried by the vector instruction from the vtype_sp register of the vector parameter generation unit;

[0054] The renaming unit 42 is used to rename the split vector instructions.

[0055] It should be noted that the purpose of register renaming is to eliminate the two types of false data hazards between instructions, namely write-after-write and read-after-write, reduce pipeline stalls caused by these two types of false data hazards, and improve ILP (Instruction level parallel, TLP for short), thereby achieving better performance; in high-performance processors, register renaming operations that process multiple instructions in a single clock cycle are usually supported, and the renaming unit generally supports the renaming of scalar registers (general purpose register, scalar register or general purpose register, abbreviated as GPR), vector registers, and CSR (control status register); this unit is generally equipped with a mapping table from logical registers to physical registers to record the mapping relationship between the two.

[0056] Instruction emission unit 44: used to process the disassembled instructions according to the split granularity of the vector instruction. Usually, the emission queue needs to save the register ID of the instruction, which is used to query and determine whether the instruction operands in the emission queue are ready. The instruction can only be emitted after all operands are ready. If it is not ready, the register ID is also used for matching and waking up. It can only be emitted normally after waking up.

[0057] In actual applications, the vsetvl instruction will obtain the speculative vector parameter value, i.e., the vtype_sp value, from the vector parameter generation unit and then carry the value to each downstream processing unit. In the instruction issuance unit, each type of instruction (such as integer instructions, floating-point instructions, memory access instructions, etc.) has one or more issuance queues. The vtype_sp value carried by vsetvl must be saved in the issuance queue storing the vsetvl instruction. After the instruction is issued, the vtype_sp value must also be passed to the vsetvl execution unit for vtype speculative correction judgment.

[0058] Instruction execution unit 46: responsible for the execution of the vsetvl instruction. The key to the execution of the vsetvl instruction is to obtain the configuration value of the vector parameter vtype from the general register, and use the configuration value to update the vtype register in the instruction submission stage; another key function is to correct the vtype speculative value, and compare the vtype configuration value in the execution result of vsetvl with the vtype_sp transmitted from the instruction issuance unit. If the two are not equal, it means that the speculation has failed, and if they are equal, it means that the speculation has succeeded; if the speculation fails, it is necessary to initiate flushPipeline to invalidate the instructions on the pipeline and correct the value of the vtype_sp register in the vector parameter generation unit. Then, after completing the instructions on the invalid pipeline, all instructions younger than the vsetvl instruction will not use the vtype_sp speculative value of the failed speculation for instruction splitting, and the younger instructions will use the corrected speculative value for instruction splitting.

[0059] In an exemplary embodiment, before updating the first vector parameter to the second vector parameter using the update method corresponding to the first type of pending instructions, the method further includes: determining the number of instructions of the first type of pending instructions existing in the multiple pending instructions; when the number of instructions is greater than a preset number, determining the update time for each instruction of the multiple first types of pending instructions to update the first vector parameter, and obtaining multiple update times; determining multiple update intervals based on the time relationship of the multiple update times, wherein the target other pending instructions processed in each update interval use the target second vector parameter most recently updated in the update interval.

[0060] Simply put, when using the first type of pending instructions to update the first vector parameter in the speculative value register, when it is determined that there are multiple first type pending instructions, in order to avoid abnormal disassembly of subsequent long vector instructions caused by unordered vector parameter updates, it is necessary to identify the time when each first type of pending instruction updates the vector parameter currently stored in the speculative value register during the update, and then use the latest vector parameter in the current clock cycle to update when using the updated vector parameter to disassemble the long vector.

[0061] In an exemplary embodiment, the vector parameter generation unit can process multiple vtype vector parameter updates in the same clock cycle. For example, if there are two vsetvli instructions in the same clock cycle to update the vtype vector parameter, the vtype_sp vector parameter speculative value register will be updated with the latest value at the same time. In addition, the order relationship between the vector instruction that needs to use the vtype value and the vset{i}vl{i} update value must be ensured to ensure that the vector instruction can obtain a reasonable vtype_sp.

[0062] For example, there are 4 instruction sequences in the same clock, as follows:

[0063] / / cycle-1 clock cycle 1

[0064] vsetvli t0,a0,e8,m2 / / LMUL=2

[0065] vadd.vv vd,vs2,vs1,vm

[0066] vsetvli t0,a0,e16,m8 / / LMUL=8

[0067] vsub.vv vd,vs2,vs1,vm

[0068] / / cycle-2 clock cycle 2

[0069] vmul.vv vd,vs2,vs1

[0070] vadd.vv vd,vs2,vs1,vm

[0071] vsetvli t0,a0,e16,m8 / / LMUL=4

[0072] vsub.vv vd,vs2,vs1,vm,

[0073] The order of instructions from top to bottom is getting newer and newer. In clock cycle 1, the vadd instruction should be split according to LMUL=2, so the LMUL carried by the vadd instruction to the decoding unit should be equal to 2, and the vsub instruction should carry LMUL=8 to the decoding unit for instruction splitting; at the end of clock cycle 1, the immediate update value of the second instruction (that is, LMUL=8) should be updated to the vtype_sp register; further, in clock cycle 2, the vmul and vadd instructions should carry the value of vtype_sp updated in clock cycle 1 (that is, vtype with LMUL=8) to the decoding code, and the last vsub should carry the value to be updated by the third vsetvli instruction (that is, LMUL=4) to the decoding unit for instruction splitting.

[0074] In an exemplary embodiment, the first vector parameter is updated to a second vector parameter using an update method corresponding to the first type of pending instructions, including: when the first type of pending instructions is an immediate instruction, updating the first vector parameter to a second vector parameter according to encoding information of the immediate instruction; when the first type of pending instructions is a non-immediate instruction, updating the first vector parameter to a second vector parameter using a prediction value associated with the non-immediate instruction.

[0075] That is to say, if the instruction to be processed is identified as a vsetivli / vsetvli instruction (immediate value) under the vset{i}vl{i} extended instruction, the configuration value can be obtained according to the encoded immediate value of the instruction itself, and the current vtype speculative value (the value of the vtype_sp register) can be updated with this configuration value. All subsequent vector instructions will carry this vtype speculative value to the instruction decoding unit until a new vset{i}vl{i} instruction is used to update or the instruction submission part repairs the vtype speculative value, or the current value saved in the vtype_sp register is corrected after the vector parameter speculation fails.

[0076] If the instruction to be processed is identified as a vsetvl instruction (non-immediate value) under the vset{i}vl{i} extended instruction, a vtype prediction value is obtained by prediction based on thread feature information, and vtype_sp (vtype speculative value) is updated with the prediction value; wherein the non-immediate value is used to indicate that the configuration value needs to be obtained through a register.

[0077] In addition, it should be noted that if the instruction to be processed is not any of the vset{i}vl{i} extended instructions, the current vtype speculative value needs to be maintained, and subsequent vector instructions carry the current vtype speculative value to the instruction decoding unit until a new vset{i}vl{i} instruction or instruction submission unit updates the speculative value of the vector parameter generation unit.

[0078] In an exemplary embodiment, updating the first vector parameter to a second vector parameter according to the encoding information of the immediate instruction includes: determining a first configuration value of a vector register group configuration and a second configuration value corresponding to a bit width of a vector element according to the encoding information of the immediate instruction; and updating the first vector parameter to a second vector parameter using the first configuration value and the second configuration value.

[0079] In an exemplary embodiment, the first vector parameter is updated to the second vector parameter by using a prediction value associated with the non-immediate instruction, including: determining characteristic information corresponding to a thread that processes the non-immediate instruction; searching for a prediction value matching the characteristic information in a preset vector parameter prediction table, and using the prediction value to update the first vector parameter to the second vector parameter.

[0080] In an exemplary embodiment, after using the predicted value to update the first vector parameter to the second vector parameter, the method further includes: obtaining an execution result corresponding to the non-immediate instruction, and determining an actual value corresponding to the execution result; comparing the actual value and the predicted value to determine whether the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is valid based on the comparison result.

[0081] It is understandable that since the vsetvl instruction (equivalent to the above non-immediate instruction) is mostly used to restore the context after thread switching, the thread history record can be used for prediction, but the prediction may be wrong. In order to determine the wrong prediction in a timely and effective manner, the vsetvl instruction can carry the vtype prediction value obtained from the prediction table and bring it to the execution unit along with the vsetvl instruction itself. When the execution unit has obtained the source operand, the instruction is executed and the execution result is obtained. By comparing the execution result with the vtype prediction value, whether the prediction is normal is detected;

[0082] In an exemplary embodiment, the actual value and the predicted value are compared to determine whether a speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is valid based on the comparison result, including: when the actual value is the same as the predicted value, determining that the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is valid; when the actual value is different from the predicted value, determining that the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is invalid.

[0083] Optionally, when the execution result of the execution unit is not equal to the vtype prediction value, it indicates that the prediction is wrong, the speculation fails, and a new vtype prediction value needs to be re-determined; if the execution result of the execution unit is equal to the vtype prediction value, the speculation succeeds, and the vtype prediction value is used to split and rename multiple long vectors in the clock cycle after the vsetvl instruction.

[0084] In an exemplary embodiment, when the actual value is different from the predicted value, after determining that the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is invalid, the method further includes: updating the first vector parameter in the speculative value register using the actual value to obtain a third vector parameter; identifying a target pending instruction to be processed after the non-immediate instruction among the multiple pending instructions; when the target pending instruction is a long vector, using the third vector parameter to split the target pending instruction into multiple target micro-operations; and renaming the target pending instruction according to the multiple target micro-operations.

[0085] In an exemplary embodiment, since all pending instructions newer than the vsetvl instruction are processed based on the vtype prediction value, when speculation fails, in order to ensure that these pending instructions newer than the vsetvl instruction can be effectively processed, flush invalid pipeline instruction processing is performed on these pending instructions, that is, the vtype prediction values ​​carried in these pending instructions are invalidated, so that the vector instructions cannot be split according to the vtype prediction values ​​of the failed speculation. Afterwards, the value of vtype_sp needs to be updated with the execution result of the vsetvl instruction, and instruction fetching and execution are restarted from the next instruction of the vsetvl instruction to ensure that the instructions after re-fetching can be subsequently processed based on the correct vtype_sp value.

[0086] Obviously, the embodiments described above are only some embodiments of the present application, not all embodiments. In order to better understand the above method, the above process is described below in conjunction with the embodiments, but it is not intended to limit the technical solutions of the embodiments of the present application, specifically:

[0087] In an exemplary embodiment, a RISC-V vector instruction processing method is provided, which specifically includes the following steps:

[0088] Step 1: Pre-decode the instruction fetched back to identify whether the instruction is a vset{i}vl{i} instruction. And determine the source of the vector parameter for updating the speculative value in the vtype_sp register based on the identification result. Figure 7 1 is a schematic diagram of the composition of the vtype_sp update source in the instruction processing method according to the embodiment of the present application. The specific situation involved is as follows:

[0089] Case 1: Since vsetvl is obtained through the prediction table and is a speculative prediction value, the execution unit compares the execution result of the vsetvl instruction with the prediction value. If they do not match, it means the prediction is wrong and the vtype speculation fails. It is necessary to synchronize the execution result of the vsetvl instruction to correct the speculative value saved in the vtype_sp register, that is, the execution unit will send the correct vtype value to restore the vtype_sp speculative value, and subsequent instructions will be split based on the restored speculative value.

[0090] Case 2: If it is a vsetvl instruction (non-immediate value, that is, the configuration value needs to be obtained through a register), the vtype prediction value is obtained by predicting based on the thread feature information, and the vtype_sp (vtype speculative value) is updated with the prediction value; wherein the above prediction is used to indicate that the vtype prediction value of the corresponding thread is searched in the vector parameter register prediction table according to the thread feature information.

[0091] Case 3: If it is a vsetivli / vsetvli instruction (immediate value), the configuration value obtained from the encoded immediate value of the instruction itself can be used to update the current vtype speculative value (the value of the vtype_sp register). All subsequent vector instructions will carry this vtype speculative value to the instruction decoding unit until a new vset{i}vl{i} instruction is used to update it or the instruction submission part repairs the vtype speculative value, or vtype_sp is corrected after the vector parameter speculation fails.

[0092] It should be noted that if it is not a vset{i}vl{i} instruction, the current vtype speculative value is maintained, and subsequent vector instructions carry the current vtype speculative value to the instruction decoding unit until a new vset{i}vl{i} instruction or instruction submission unit updates the speculative value;

[0093] Case 4: When a branch prediction error occurs or an interrupt or exception causes a Pipelineflush to invalidate instructions on the pipeline, the value in the vtype vector parameter register needs to be restored, and the value in the vtype_sp vector parameter speculative value register also needs to be restored, because the vset{i}vl{i} instruction on the instruction stream before the flush point will update vtype to an inaccurate value.

[0094] Step 2: The instruction decoding unit disassembles the vector instruction according to the configuration value of LMUL in the vtype speculative value.

[0095] For example, if LMUL=8, it means that 8 vector registers form a group, and the vector length is 8*VLEN, where VLEN is a constant parameter determined by the specific implementation and used to specify the width of a single vector register, such as 128-bit. Figure 8 It is a schematic diagram of the vector register grouping configuration according to an embodiment of the present application.

[0096] The instruction decoding unit disassembles a vector instruction affected by LMUL into 8 uops (micro-operations) according to the VLEN granularity, and a single uop is equivalent to the vector length when LMUL=1; since the decoding unit will only output a specific number of decoded instructions per clock, there is a maximum number limit, such as: a maximum of 4 decoded instructions are output per clock cycle, then the above-mentioned vector instruction will require 2 clock cycles to complete the disassembly.

[0097] If long vector instructions are not decomposed, such as LMUL=8, then a vector instruction with two source operands and one destination operand needs to read the renaming mapping of 8x2=16 registers and apply for 8 free physical registers as the destination registers. High-performance processor cores generally process multiple instructions in a single clock. For example, for 4 instructions, a single clock cycle requires 8x16=128 renaming mapping table read ports to obtain the mapping relationship. At the same time, a single clock cycle requires 32 free physical registers. In addition, the instruction issuance unit needs to save multiple source registers and destination registers, and multiple source registers need to be compared during instruction wakeup, which reduces the area and power consumption. The power consumption is relatively large. If the long vector instruction is disassembled and processed at the granularity of LMUL=1, the processing logic related to the registers in the back-end pipeline can be reduced to 1 / 8 of the original, which greatly simplifies the complexity and area of ​​the design, and the power consumption overhead; high-performance processing is generally a high-frequency design, and the frequency generally reaches more than 3GHz. After the instruction is disassembled and simplified, the design can achieve a better frequency; in addition, the renaming unit has 128 read ports, or the wakeup circuits of multiple registers of the instruction issuance unit will cause congestion due to excessive connections in the local area in physical implementation, which is not conducive to physical implementation, and may further make the timing worse and the power consumption overhead greater.

[0098] In an exemplary embodiment, in order to achieve a balance between area, power consumption and performance, the execution units of some special vector instructions (e.g., the area of ​​a single execution unit is large) will not be equipped with execution units according to the maximum number of vector elements vlmax; assuming that the bit width of the vector element sew=16bit, VLEN=128bit, then vlmax=128 / 16=8, and then the instruction decoder can disassemble the vector instruction through the sew configuration, and the method of obtaining sew is the same as LMUL, which is obtained from the previous vector parameter generation unit, and the vector parameter generation unit also processes sew in the same way;

[0099] Disassembling the instruction decoder reduces the complexity, area, and power consumption of further disassembly in the execution unit and the emission unit. Because most execution units process instructions in a pipeline manner, instructions enter the pipeline back to back. If an instruction in the middle needs to be disassembled, the pipeline needs to be stalled to give up resources for the disassembled uop to process, which is easy to cause Pipelinebubble and cause Pipeline Flush, flush those instructions that have been issued but cannot enter the execution unit for execution, because the instruction disassembly temporarily stalls the pipeline process and cannot enter the execution unit. After flushing, it will be re-issued, which wastes a lot of power consumption. If the instruction is disassembled in the emission unit, it is necessary to add a disassembly logic circuit for each record entry in the emission queue. Usually, the emission queue is composed of multiple record entries. If each record entry requires a set of disassembly logic, the area and power consumption overhead will also be large. Through the above disassembly process, the instruction decoding unit only needs to disassemble according to the decoding width. Generally, the decoding width is much smaller than the number of emission queue entries. After disassembly, the later stage of the Pipeline (renaming, emission unit, etc.) does not need to perceive the changes in LMUL and SEW. Therefore, the circuit complexity of the later stage of the Pipeline is reduced, and the area and power consumption are optimized.

[0100] Step 3: The rename unit processes the instructions according to the uop granularity;

[0101] It should be noted that after the above processing, although LMUL=8, the vector register width seen by the renaming unit is always the VLEN width, which is not affected by the change of the vector register grouping configuration LMUL; the renaming unit does not need more renaming mapping table read ports and read port arbitration logic to adapt to the situation of LMUL>1, and does not need to allocate 8 times (the maximum LMUL is 8) the number of free registers per clock cycle, which also simplifies the free physical register allocation and management logic, and can achieve better timing, power consumption, and area.

[0102] Step 4: The emission unit processes the instructions after disassembly according to the uop granularity. Normally, the emission queue needs to save the register ID (identification, identifier, abbreviated as ID) of the instruction, which is used to query and determine whether the instruction operands in the emission queue are ready. The emission can only be carried out after all operands are ready. If they are not ready, the register ID is also used for matching and awakening. After awakening, it can be normally emitted; after the decoding unit disassembles the vector instruction, the entry of the emission queue only needs to save the register ID with uop and VLEN as the granularity, and does not need to save the register ID of the entire instruction. It should be noted that since the maximum LMUL is 8, the maximum number of register IDs for a single instruction is 8 times that of a single uop), that is, the emission unit does not need to be affected by the change of LMUL, which can greatly reduce the area overhead of saving the register ID; in addition, the process of waking up the instruction of the emission queue needs to compare the register ID saved in the entry, so the register ID is less, the corresponding number of comparators is also less, and the area and power consumption are naturally reduced. And it is necessary to check whether all source operands are ready. If there are more registers, the timing will naturally be worse. After the instruction is disassembled, it is only necessary to determine the number of registers at the uop granularity, and the timing will be better.

[0103] Step 5: The execution unit processes the disassembled instructions according to the uop granularity. There is no need to configure the computing components according to the vector bit width configured by LMUL, such as: LMUL=8, the vector width is 8 times the physical register width. At this time, if the execution components are equipped with 8 times the number, the area and power consumption will be relatively large, and when the value of LMUL is configured to be relatively small, the execution components cannot be fully utilized.

[0104] Fig. 9 It is a schematic diagram of the composition of two different computing resource configurations according to the embodiment of the present application. In order to realize the 128-bit VLEN constant parameter, it supports the comparison between 4 32-bit dividers and 32 dividers. If the dividers are equipped according to the maximum vector (vector register group configuration LMUL=8), when LMUL=1, 32-4=28 dividers will be idle, the surface efficiency is very low, and LMUL=1 is used more often; therefore, a more balanced design is to equip computing resources (such as the number of dividers) according to the VLEN width, and to achieve a better balance between area and performance by disassembling UOPs; as shown above, disassembling uops in the decode stage (before rename) is the best way. The later it is, the more information needs to be transmitted in the pipeline, and the greater the power consumption and area overhead will be;

[0105] In an exemplary embodiment, the optional embodiment of the present application also provides a solution for fast recovery of a vsetvl speculation failure, such as Figure 5 As shown, the vsetvl instruction can carry the vtype prediction value obtained from the prediction table and carry it to the execution unit along with the vsetvl instruction itself. The execution unit has obtained the source operand, can execute the instruction and obtain the execution result. By comparing the execution result and the vtype prediction value, it can be detected whether the prediction is normal. If they are not equal, it means that the prediction is wrong and the speculation fails; if they are equal, the speculation succeeds; because all instructions newer than vsetvl are processed based on the prediction value (or speculation value), if the speculation fails, it is necessary to flush all the instructions newer than vsetvl, and then restart the instruction fetching and execution from the next instruction of vsetvl, but before that, the value of vtype_sp needs to be updated with the execution result of vsetvl to ensure that the instruction after re-fetching can be subsequently processed based on the correct vtype_sp value (such as disassembling uop).

[0106] It should be noted that since the source operand of the vsetvl instruction (used to update the vtype register) comes from the GPR (general purpose register), it is possible that the source operand is the result of the execution of another older instruction, and has not been processed by register renaming, the source operand cannot be obtained in the pre-decoding and decoding stages of the instruction, and the vector instruction disassembly depends on the vtype vector parameter. Among them, one solution is that the vsetvl instruction pauses on the pipeline to wait for the old instruction result, and then processes it after the result is obtained, but the pipeline pause caused by this (the vsetvl instruction depends on the return of memory access data. If there are multiple cache misses, this time will be very long. If it does not depend on the results of other instructions, it will generally pause for 5 to 10 time cycles, which is related to the specific micro-architecture implementation), which will block the subsequent out-of-order execution of instructions, and the performance will be greatly affected. Another solution is to use thread feature information for prediction, because the vsetvl instruction is mostly used for context recovery after thread switching, and the thread history record can be used for prediction. However, the prediction may be wrong. In this case, there must be a detection and quick recovery method for such prediction errors. There is no need to wait until the instruction reaches the submission stage to check whether the prediction is correct, thereby achieving better performance. Because the thread feature information is relatively clear and the probability of prediction errors is relatively high, prediction can reduce pipeline stalls and significantly improve performance.

[0107] Optionally, in practical applications, the above implementation may also be applied to the following specific scenarios:

[0108] Scenario 1: All general-purpose CPU cores that support vector instructions;

[0109] Scenario 2: Apply to DSP processor, vector processor or GPU;

[0110] Scenario 3: When applied to processors that only support scalar operations, some complex scalar instructions may need to be speculatively disassembled based on a certain configuration parameter and quickly recovered after speculation fails;

[0111] Scenario 4: Applied in SOC chips, for example, in the main control SOC chip of communication equipment (routers, switches, base station controllers, etc.), used to control and manage various operations of communication equipment; or used in baseband signal processing SOC chips.

[0112] Through the above embodiments, vector instruction disassembly is performed by speculatively obtaining vector parameter information (including LMUL, but not limited to LMUL, such as SEW) in advance, without pausing the pipeline to wait for the execution result of vsetvl; if Vsetvl may depend on the results of other instructions, the waiting time will be relatively long, and the pipeline pause time will be relatively long. By predicting and obtaining the vtype value in advance, the pipeline pause can be reduced, thereby achieving better performance; by disassembling long vector instructions, the design complexity of the CPU core back-end pipeline (including renaming unit and instruction issuance unit, instruction execution unit, etc.) can be reduced, the area and power consumption overhead can be reduced, and better surface effect and energy efficiency can be achieved. Furthermore, high-performance processing cores generally submit instructions sequentially. Through the above-mentioned fast recovery method after prediction failure, there is no need to wait for the vsetvl instruction to reach the submission stage to detect whether the vtype prediction is correct. Instead, the vsetvl instruction is immediately restored after obtaining the instruction result in the instruction execution stage, thereby reducing the time from the completion of instruction execution to the submission of the instruction, and recovering in advance to achieve better performance; because instructions are queued and submitted in sequence according to programorder, if there are more instructions before vsetvl, the time from the completion of instruction execution to the submission of the instruction will be longer. By using the fast recovery method in the above-mentioned embodiment to immediately recover after the instruction execution is completed, this time can be reduced to achieve better performance.

[0113] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory / random access memory (ROM / RAM), a disk, or an optical disk), and may include a number of instructions to enable a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0114] Example 2

[0115] In the present embodiment, a method for processing instructions is also provided, and the device is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made are not repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware is also possible and conceivable.

[0116] Fig.10 is a schematic diagram of a structure of an instruction processing device according to an embodiment of the present application, such as Fig.10 As shown, the device may include:

[0117] A determination module 72, configured to determine a first type of instructions to be processed from a plurality of instructions to be processed according to a preset instruction code, wherein the first type of instructions to be processed are used to update a first vector parameter in a speculative value register;

[0118] An updating module 74, configured to update the first vector parameter to a second vector parameter using an updating method corresponding to the first type of instructions to be processed;

[0119] The processing module 76 is used to split the long vector instruction in other pending instructions into multiple micro-operations based on the second vector parameter, and rename the other pending instructions according to the multiple micro-operations, wherein the other pending instructions are instructions in the multiple pending instructions other than the first type of pending instructions.

[0120] Through the above-mentioned device, in the system architecture corresponding to the CPU core, the preset instruction code is used to identify the first type of pending instructions to be executed, so as to speculatively obtain the second vector parameter between the instruction decoders, and then instruct the instruction disassembly subunit configured in the instruction decoding unit to split the long vector instructions in other pending instructions into multiple micro-operations based on the register vector grouping value contained in the second vector parameter, thereby reducing the area and power consumption overhead of the renaming and instruction issuance units for long vector processing through fine-grained micro-operations, and can also reduce the complexity and power consumption overhead of micro-operation disassembly of long vector instructions in the execution unit, that is, by determining the vector parameter in advance, and using the vector parameter to disassemble the long vector between the execution of the corresponding long vector, the problem of too complex execution circuit in the processor in the vector instruction in the related art, and too large area and power consumption overhead is solved, thereby achieving the effect of reducing the design complexity of the execution circuit, and achieving a better processing frequency within a limited area, thereby improving the user experience.

[0121] As an optional implementation, the above-mentioned device may also include: a time module, used to determine the number of instructions of the first type of pending instructions existing in the multiple pending instructions before updating the first vector parameter to the second vector parameter using the update method corresponding to the first type of pending instructions; when the number of instructions is greater than a preset number, determine the update time for each instruction in the multiple first types of pending instructions to update the first vector parameter, and obtain multiple update times; determine multiple update intervals based on the time relationship of the multiple update times, wherein the target other pending instructions processed in each update interval use the target second vector parameter most recently updated in the update interval.

[0122] As an optional implementation, the above-mentioned update module is also used to, when the first type of pending instructions is an immediate instruction, update the first vector parameter to a second vector parameter according to the encoding information of the immediate instruction; when the first type of pending instructions is a non-immediate instruction, update the first vector parameter to a second vector parameter through a predicted value associated with the non-immediate instruction.

[0123] As an optional implementation, the above-mentioned update module is also used to determine the first configuration value of the vector register group configuration and the second configuration value corresponding to the bit width of the vector element according to the encoding information of the immediate instruction; and use the first configuration value and the second configuration value to update the first vector parameter to the second vector parameter.

[0124] As an optional implementation, the above-mentioned update module is also used to determine the characteristic information corresponding to the thread that processes the non-immediate instruction; search for a prediction value matching the characteristic information in a preset vector parameter prediction table, and use the prediction value to update the first vector parameter to a second vector parameter.

[0125] As an optional implementation, the update module further includes: a comparison unit, for obtaining the execution result corresponding to the non-immediate instruction after updating the first vector parameter to the second vector parameter using the predicted value, and determining the actual value corresponding to the execution result; comparing the actual value with the predicted value to determine whether the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is valid based on the comparison result.

[0126] As an optional implementation, the comparison unit is further used to determine that, when the actual value is the same as the predicted value, a speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is valid; and to determine that, when the actual value is not the same as the predicted value, the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is invalid.

[0127] As an optional implementation, the update module further includes: an update unit, configured to update the first vector parameter in the speculative value register using the actual value to obtain a third vector parameter; identify a target pending instruction to be processed after the non-immediate instruction among the multiple pending instructions; when the target pending instruction is a long vector, use the third vector parameter to split the target pending instruction into multiple target micro-operations; and rename the target pending instruction according to the multiple target micro-operations.

[0128] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0129] To facilitate the understanding of the technical solution provided by the present application, a detailed explanation will be given below in combination with embodiments of specific scenarios.

[0130] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0131] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0132] An embodiment of the present application further provides an electronic device, which may include a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0133] Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0134] S1, determining a first type of instructions to be processed from a plurality of instructions to be processed according to a preset instruction code, wherein the first type of instructions to be processed is used to update a first vector parameter in a speculative value register;

[0135] S2, updating the first vector parameter to a second vector parameter using an update method corresponding to the first type of instructions to be processed;

[0136] S3, splitting the long vector instructions in other pending instructions into multiple micro-operations based on the second vector parameter, and renaming the other pending instructions according to the multiple micro-operations, wherein the other pending instructions are instructions in the multiple pending instructions other than the first category of pending instructions.

[0137] Alternatively, a person skilled in the art may understand that: Fig.11 The structure shown is for illustration only, and the electronic device may also be a smart phone (such as an Android phone, an iOS phone, etc.), a tablet computer, a PDA, a mobile Internet device (MID), a PAD, or other terminal devices. Fig.11 The structure of the electronic device is not limited. Fig.11 More or fewer components (such as network interfaces, etc.) as shown in, or with Fig.11 Different configurations are shown.

[0138] Among them, the memory 902 can be used to store software programs and modules, such as the program instructions / modules corresponding to the instruction processing method and device in the embodiment of the present disclosure. The processor 904 executes various functional applications and data processing by running the software programs and modules stored in the memory 902, that is, realizing the above-mentioned instruction processing method. The memory 902 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 902 may further include a memory remotely located relative to the processor 904, and these remote memories may be connected to the terminal via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. As an example, Fig.11 As shown, the memory 902 may include but is not limited to the determination module 72, update module 74, and processing module 76 in the processing method device of the above instructions. In addition, it may also include but is not limited to other module units in the processing method device of the above instructions, which will not be repeated in this example.

[0139] Optionally, the transmission device 906 is used to receive or send data via a network. Specific examples of the above-mentioned network may include a wired network and a wireless network. In one example, the transmission device 906 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices and routers via a network cable so as to communicate with the Internet or a local area network. In one example, the transmission device 906 is a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0140] In addition, the electronic device further includes: a display 908, configured to display the instructions to be processed; and a connection bus 910, configured to connect various module components in the electronic device.

[0141] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0142] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0143] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0144] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for processing an instruction, characterized in that: include: Determining a first type of pending instructions from a plurality of pending instructions according to a preset instruction code, wherein the first type of pending instructions is used to update a first vector parameter in a speculative value register; Using the update method corresponding to the first type of pending instructions, the first vector parameter is updated to a second vector parameter; Based on the second vector parameter, a long vector instruction in other pending instructions is split into multiple micro-operations, and the other pending instructions are renamed according to the multiple micro-operations, wherein the other pending instructions are instructions in the multiple pending instructions except the first type of pending instructions.

2. The method according to claim 1, characterized in that Before updating the first vector parameter to a second vector parameter using the update method corresponding to the first type of instructions to be processed, the method further includes: Determining the number of instructions of the first category of pending instructions existing in the plurality of pending instructions; When the number of instructions is greater than a preset number, determining an update time for each of a plurality of first-category to-be-processed instructions to update the first vector parameter, to obtain a plurality of update times; A plurality of update intervals are determined according to the time relationship of the plurality of update times, wherein the target other instructions to be processed in each update interval use the target second vector parameters of the most recently updated target in the update interval.

3. The method according to claim 1, characterized in that Updating the first vector parameter to a second vector parameter using an update method corresponding to the first type of instructions to be processed includes: When the first type of to-be-processed instruction is an immediate instruction, updating the first vector parameter to a second vector parameter according to encoding information of the immediate instruction; In a case where the first type of to-be-processed instruction is a non-immediate instruction, the first vector parameter is updated to a second vector parameter by using a prediction value associated with the non-immediate instruction.

4. The method according to claim 3, characterized in that Updating the first vector parameter to a second vector parameter according to the encoding information of the immediate instruction includes: Determine, according to the encoding information of the immediate instruction, a first configuration value of the vector register group configuration and a second configuration value corresponding to the bit width of the vector element; The first vector parameter is updated to a second vector parameter using the first configuration value and the second configuration value.

5. The method according to claim 3, characterized in that: Updating the first vector parameter to a second vector parameter using a prediction value associated with the non-immediate instruction comprises: Determine characteristic information corresponding to the thread processing the non-immediate instruction; A prediction value matching the feature information is searched in a preset vector parameter prediction table, and the first vector parameter is updated to a second vector parameter using the prediction value.

6. The method according to claim 5, characterized in that After updating the first vector parameter to a second vector parameter using the predicted value, the method further includes: Obtaining an execution result corresponding to the non-immediate instruction, and determining an actual value corresponding to the execution result; The actual value and the predicted value are compared to determine whether a speculative operation of updating the first vector parameter to a second vector parameter using the predicted value is valid according to the comparison result.

7. The method according to claim 6, characterized in that Comparing the actual value with the predicted value to determine whether a speculative operation of updating the first vector parameter to a second vector parameter using the predicted value is valid according to the comparison result, comprising: In the case where the actual value is the same as the predicted value, determining that a speculative operation of updating the first vector parameter to a second vector parameter using the predicted value is valid; In the case where the actual value is not the same as the predicted value, it is determined that the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is invalid.

8. The method according to claim 7, characterized in that In the case where the actual value is different from the predicted value, after determining that the speculative operation of updating the first vector parameter to the second vector parameter using the predicted value is invalid, the method further includes: Using the actual value to update the first vector parameter in the speculative value register, to obtain a third vector parameter; identifying a target pending instruction among the plurality of pending instructions to be processed after the non-immediate instruction; In the case where the target instruction to be processed is a long vector, splitting the target instruction to be processed into a plurality of target micro-operations using the third vector parameter; The target to-be-processed instruction is renamed according to the multiple target micro-operations.

9. An instruction processing device, characterized in that: include: A determination module, configured to determine a first type of instructions to be processed from a plurality of instructions to be processed according to a preset instruction code, wherein the first type of instructions to be processed is used to update a first vector parameter in a speculative value register; An updating module, configured to update the first vector parameter to a second vector parameter using an updating method corresponding to the first type of instructions to be processed; A processing module is used to split a long vector instruction in other instructions to be processed into multiple micro-operations based on the second vector parameter, and rename the other instructions to be processed according to the multiple micro-operations, wherein the other instructions to be processed are instructions in the multiple instructions to be processed except the first type of instructions to be processed.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 8 when executed by a processor.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 8 are implemented.

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