Equipment awakening method and electronic equipment

Abstract

The invention provides an equipment awakening method and electronic equipment, and the method comprises the steps: mainly utilizing the characteristic that an SDA can be switched from a high level to a low level when I2C communication starts each time, configuring a pin function corresponding to the SDA into a level falling edge to trigger a first external interruption in advance, and opening the first external interruption when slave equipment enters a sleep mode. If the master device sends the I2C data to the slave device in the sleep mode through the I2C bus, the first external interruption can be triggered, the first external interruption can wake up the slave device from the sleep mode in time before communication occurs on the I2C bus, it is guaranteed that the slave device responds to the I2C data sent by the master device smoothly, and the situation that the slave device fails is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of electronic devices, and in particular to a device wake-up method and an electronic device. Background Art

[0002] The master device has certain requirements for the power consumption of the slave device. For example, if the master device is a laptop and the slave device is a touchpad, when the laptop enters sleep mode, it will send a sleep command to the touchpad through the inter-integrated circuit (I2C) bus, instructing the touchpad to enter sleep mode, thereby reducing power consumption. However, after the touchpad enters sleep mode, if the laptop still sends commands to the touchpad through the I2C bus, and the touchpad fails to respond to this command in time because it is in sleep mode, it will cause the touchpad to fail. Summary of the invention

[0003] The present application provides a device wake-up method and an electronic device, which can wake up a slave device in time to avoid failure of the slave device.

[0004] In the first aspect, an embodiment of the present application provides a device wake-up method, which is applied to a slave device, and the slave device performs internal integrated circuit I2C communication with a master device. The method includes: when the slave device is in a sleep mode, when a first signal is detected, a first external interrupt is triggered, wherein the first external interrupt is turned on when the slave device is in the sleep mode, and the first signal is a signal that the I2C bus (serial data, SDA) switches from a high level to a low level when the master device performs I2C bus data transmission, and the pin function of SDA is configured to trigger the first external interrupt by a falling edge of the level; after the first external interrupt is triggered, the sleep mode is exited and the first external interrupt is turned off.

[0005] In the technical solution of the present application, the characteristic that SDA switches from a high level to a low level each time I2C communication starts is mainly utilized, and the pin function corresponding to SDA is pre-configured to trigger the first external interrupt on the falling edge of the level, and the first external interrupt is turned on when the slave device enters the sleep mode. If the master device sends I2C data to the slave device in the sleep mode through the I2C bus, the above-mentioned first external interrupt will be triggered. The first external interrupt can wake up the slave device from the sleep mode in time before communication occurs on the I2C bus, ensuring that the slave device responds smoothly to the I2C data sent by the master device and avoiding the failure of the slave device.

[0006] Optionally, in a possible implementation of the first aspect, after exiting the sleep mode and turning off the first external interrupt, the method further includes: receiving the first I2C data sent by the master device through the I2C bus; parsing the first I2C data to obtain a first instruction; if the first instruction is a wake-up instruction, not entering the sleep mode; if the first instruction is not a wake-up instruction, turning on the first external interrupt and entering the sleep mode. It can be understood that by configuring the first external interrupt, the slave device can temporarily exit the sleep mode before receiving the I2C data (an example of the first I2C data), and then process the I2C data. Further, the slave device can parse the I2C data to obtain the instruction corresponding to the I2C data (an example of the first instruction). If the instruction is a wake-up instruction, the sleep mode will not be entered subsequently. If the received I2C data is parsed and the instruction corresponding to the I2C data is not a wake-up instruction, it means that the master device only wants the slave device to temporarily exit the sleep mode to process the instruction. After processing, the slave device continues to remain in the sleep mode, so the slave device will turn on the first external interrupt and re-enter the sleep mode. After the instruction is processed, the slave device will continue to detect the level state corresponding to SDA in the I2C bus until the slave device determines that it has received the wake-up instruction and exits the sleep mode.

[0007] Optionally, in another possible implementation of the first aspect, the above-mentioned not entering the sleep mode when the first instruction is a wake-up instruction includes: when the first instruction is a wake-up instruction, clearing a preset sleep flag, wherein the clearing of the sleep flag is used to indicate that the slave device does not enter the sleep mode. It is understandable that if a wake-up instruction is detected, the sleep flag corresponding to the sleep mode needs to be cleared, and in the subsequent processing flow, when it is detected that the sleep flag is cleared, the sleep mode is not entered. Therefore, by detecting the state of the sleep flag corresponding to the sleep mode, it can be determined whether to enter the sleep mode, which simplifies the process design.

[0008] Optionally, in another possible implementation of the first aspect, before the slave device is in sleep mode, the method further includes: in the system initialization stage, configuring SDA to trigger a first external interrupt by a falling edge; turning off the first external interrupt. Among them, SDA needs to be configured in the system initialization stage, that is, in the system initialization stage of the slave device, in addition to normally configuring SDA and the serial clock line (Serial Clock Line, SCL) in the I2C bus and initializing the I2C bus, SDA also needs to be configured as an external interrupt triggered by a falling edge. In addition, since there is usually no need for a sleep mode in the system initialization stage, the first external interrupt needs to be turned off after the SDA configuration is completed.

[0009] Optionally, in yet another possible implementation of the first aspect, the method further includes: in response to a sleep instruction sent by the master device via the I2C bus, turning on a first external interrupt; and entering the sleep mode after the first external interrupt is turned on. It is understandable that, when the slave device is not in the sleep mode, the slave device can process various instructions received from the master device via the I2C bus until it is detected that the master device has sent a sleep instruction, at which time the first external interrupt is turned on to ensure that the slave device can be successfully awakened and then enter the sleep mode.

[0010] Optionally, in another possible implementation of the first aspect, in response to a sleep instruction sent by the master device via the I2C bus, opening the first external interrupt includes: receiving second I2C data sent by the master device via the I2C bus when not in sleep mode; parsing the second I2C data to obtain a second instruction; and opening the first external interrupt when the second instruction is a sleep instruction. It should be understood that in non-sleep mode, the slave device first receives the I2C data sent by the master device via the I2C bus to obtain a specific instruction, and when it is determined that the instruction detected (an example of the second instruction) is a sleep instruction, the first external interrupt is opened to ensure that the subsequent slave device can be successfully awakened.

[0011] Optionally, in another possible implementation of the first aspect, when the second instruction is a sleep instruction, the method further includes: in response to a sleep instruction sent by the master device through the I2C bus, setting a preset sleep flag, wherein the sleep flag is set to indicate that the slave device enters a sleep mode. It is understandable that if a sleep instruction is detected, it is necessary to set the flag corresponding to the sleep mode, and in the subsequent processing flow, when it is detected that the sleep flag is set, it is prepared to enter the sleep mode. Therefore, by detecting the state of the sleep flag corresponding to the sleep mode, it is possible to determine whether to enter the sleep mode, thereby simplifying the process design.

[0012] Optionally, in yet another possible implementation of the first aspect, the master device is a personal computer (PC), and the slave device is a touchpad.

[0013] In a second aspect, an embodiment of the present application provides a device waking up an apparatus, which includes a unit composed of software and / or hardware for executing the device waking up method of the first aspect.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the electronic device can implement any one of the methods of the first aspect described above.

[0015] In a fourth aspect, an embodiment of the present application provides a chip system, which is applied to an electronic device. The chip system includes one or more processors, and the one or more processors are used to call computer instructions to enable the electronic device to execute any one of the methods of the above-mentioned first aspect.

[0016] Optionally, the chip system also includes a memory, and the memory is electrically connected to the processor.

[0017] Optionally, the chip system may also include a communication interface.

[0018] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, which includes instructions. When the instructions are executed on an electronic device, the electronic device can execute any one of the methods of the first aspect above.

[0019] In a sixth aspect, an embodiment of the present application provides a computer program product, which includes a computer program. When the computer program is executed by an electronic device, the electronic device can implement any one of the methods of the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0021] Figure 1 It is a schematic diagram of an applicable scenario of an embodiment of the present application; Figure 2 This is a schematic diagram of a hardware connection between a master device and a slave device provided in an embodiment of the present application; Figure 3 is a block diagram of a software system of an electronic device provided in an embodiment of the present application; Figure 4 It is a flowchart of a device wake-up method provided in an embodiment of the present application; Figure 5 It is a schematic diagram of a process of initializing a slave device provided in an embodiment of the present application; Figure 6 It is a schematic diagram of a process of entering a sleep mode from a device provided in an embodiment of the present application; Figure 7 This is a schematic diagram of a process for waking up a slave device provided in an embodiment of the present application; Figure 8 It is a timing interaction diagram of the device wake-up method provided in an embodiment of the present application; Fig. 9 It is a structural diagram of a device waking up an apparatus provided in an embodiment of the present application; Fig.10 It is a structural schematic diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0023] Figure 1 Schematic diagram of an applicable scenario of an embodiment of the present application. Figure 1 As shown, the scenario includes at least a master device 10 and a slave device 11. The master device 10 and the slave device 11 communicate with each other through the I2C bus. The I2C bus is a simple, bidirectional, two-wire synchronous serial bus, which is mainly used to connect integrated circuit devices such as microcontrollers, sensors, and memories within a short distance. It has the advantages of simplicity, low cost, and easy implementation. The I2C bus adopts a master-slave architecture. A master device can control multiple slave devices. The master device is responsible for generating clock signals and initiating communication, and the slave device responds after receiving instructions from the master device.

[0024] Figure 1 The master device 10 in the figure is shown by taking a laptop computer as an example, and the slave device 11 is shown by taking a touchpad as an example. It should be understood that the embodiment of the present application does not limit the types of the master device 10 and the slave device 11. The master device 10 and the slave device 11 can be any device that supports the I2C communication function and whose computing power can meet the program code running requirements of the technical solution provided by the present application. For example, in other embodiments of the present application, the master device 10 can also be a mobile phone, a tablet computer, a desktop computer, a laptop computer, a handheld computer, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook, and a cellular phone, a personal digital assistant (personal digital assistant, PDA), an augmented reality (augmented reality, AR) device, a virtual reality (virtual reality, VR) device, an artificial intelligence (artificial intelligence, AI) device, a wearable device, a vehicle-mounted device, a smart home device and / or a smart city device. In other embodiments of the present application, the slave device 11 can also be a hard disk, a printer, a keyboard, a mouse, a sensor, etc.

[0025] Figure 2 Schematic diagram of hardware connection between the master device and the slave device in the embodiment of the present application. Figure 2As shown in the figure, the I2C bus is a serial bus composed of a serial data line SDA and a serial clock line SCL. Among them, SCL is the clock signal line in I2C communication. The SCL signal is provided by the master device and is used to synchronize the data transmission of all devices on the I2C bus. The frequency of the SCL signal is determined by the clock speed of the I2C bus and can usually be set to different values ​​such as 100kHz, 400KHz, and 1MHz. The changing edge of the SCL signal is used to transmit and receive timing data. SDA is the data signal line in I2C communication. The SDA signal can be provided by the master device or the slave device and is used to transmit data on the I2C bus. The data changes the high and low levels on the SDA signal under the clock synchronization of the SCL signal to realize data transmission. Multiple devices can exist on SDA at the same time, but only one device can actively send data, and other devices need to be in the receiving state.

[0026] In the related art, the master device has certain requirements for the power consumption of the slave device. For example, when the master device is a laptop and the slave device is a touchpad, when the laptop enters sleep mode (such as deep sleep mode), a sleep instruction is sent to the touchpad through the internal integrated circuit bus, instructing the touchpad to enter sleep mode, thereby reducing power consumption. However, after the touchpad enters sleep mode, if the laptop still sends instructions to the touchpad through the I2C bus, and the touchpad fails to respond to this instruction in time because it is in sleep mode, it will cause the touchpad to fail. In response to the above problems, it is necessary to wake up the slave device from sleep mode when data is sent on the I2C bus to ensure that the slave device can process data in time.

[0027] In one embodiment, if the control unit inside the slave device supports wake-up by I2C interrupt, then the I2C interrupt wake-up function can be configured according to the chip manual corresponding to the microcontroller unit. For example, when the slave device is in sleep mode, before each communication occurs on the I2C bus, the I2C interrupt is triggered to wake up the slave device in time, and then the slave device can normally receive the I2C data sent by the master device through the I2C bus and process the I2C data. Optionally, the control unit inside the slave device can be a microcontroller unit (MCU).

[0028] In another embodiment, if the control unit inside the slave device does not support wake-up by I2C interrupt, but only supports wake-up by external interrupt (EXTI), then a new general-purpose input / output (GPIO) pin can be added to the slave device, and the function of the GPIO pin can be configured as an external interrupt, and the slave device can be woken up by the external interrupt. For example, before the slave device enters the sleep mode, the interrupt function of the GPIO pin is enabled, and a suitable trigger condition (such as rising edge, falling edge or double edge trigger) is selected, and then the slave device enters the sleep mode. When the slave device is in the sleep mode, if the master device sends I2C data through the I2C bus, an external interrupt will be triggered, thereby waking up the slave device. However, this method needs to ensure that the external interrupt must wake up the slave device in time before communication occurs on the I2C bus. Once the time when the external interrupt is triggered is later than the time when the master device sends the I2C data, the slave device will not be able to receive the I2C data normally. In addition, this method increases the hardware cost and hardware complexity due to the addition of a new GPIO pin.

[0029] In view of this, an embodiment of the present application provides a device wake-up method, which mainly utilizes the characteristic that SDA switches from a high level to a low level each time an I2C communication starts, and pre-configures the pin function corresponding to SDA to trigger the first external interrupt on the falling edge of the level, and turns on the first external interrupt when the slave device enters the sleep mode. If the master device sends I2C data to the slave device in the sleep mode through the I2C bus, the above-mentioned first external interrupt will be triggered. Based on the characteristics of the above-mentioned I2C communication, it can be understood that the time when the level change of SDA occurs must be earlier than the time when the master device sends the I2C data, so through the above-mentioned first external interrupt, the slave device can be awakened from the sleep mode in time before the communication occurs on the I2C bus, so that the slave device can smoothly respond to the I2C data sent by the master device, avoiding the failure of the slave device. In addition, this method can also use one less GPIO pin, reducing the hardware cost and hardware complexity.

[0030] Reference Figure 3 , shows a block diagram of a software system of an electronic device provided by an embodiment of the present application. Figure 3 As shown, the layered architecture of the electronic device divides the software into several layers, each with a clear role and division of labor. The layers communicate with each other through software interfaces. In some embodiments, the software system of the electronic device is divided into four layers, namely, the application layer (also called the application layer), the system layer, the driver layer, and the hardware layer from top to bottom. Optionally, the software architecture may also include other layers, which are not limited here.

[0031] The application layer can include idle tasks, which are tasks scheduled by the software system when the system has no other tasks to execute. Idle tasks are always in a ready state and are called once all tasks are suspended to ensure that the software system remains responsive when there is no activity.

[0032] The system layer is responsible for managing and coordinating system resources. The system layer includes multiple functional modules, such as the system status control module and the system initialization module. The system status control module can monitor and manage the running status of the software system, including task scheduling, resource allocation, process management, etc. The system initialization module is responsible for various initialization tasks when the software system starts, including hardware detection, system configuration, service startup, etc.

[0033] The driver layer is the part that interacts directly with the hardware device and is responsible for controlling and managing the drivers of the hardware device. The driver layer includes the internal integrated circuit I2C driver module and the general input and output GPIO driver module. The I2C driver module is used to manage I2C bus communication. The GPIO driver module is used to manage GPIO pins.

[0034] The hardware layer contains all the hardware components of the electronic device, including the internal integrated circuit I2C bus and the external interrupt EXTI. The I2C bus is used to connect integrated circuit devices such as microcontrollers, sensors, and memories over a short distance. EXTI is responsible for processing external interrupts. For example, when the level state of the GPIO pin changes (for example, from high level to low level), EXTI will detect this change and generate an interrupt signal to notify the software system to perform corresponding processing.

[0035] In the above Figure 3 Based on the software architecture shown, Figure 4 A flow chart of a device wake-up method provided in an embodiment of the present application is shown. The method can be executed by a control unit in a slave device. The slave device can be an electronic device that does not have an I2C wake-up function. I2C communication is performed between the slave device and the master device.

[0036] Below Figure 4 The steps shown are introduced.

[0037] Step 401: When a slave device is in a sleep mode, a first external interrupt is triggered when a first signal is detected.

[0038] In an embodiment of the present application, the first external interrupt is turned on when the slave device is in sleep mode, and the first signal is a signal that SDA in the I2C bus switches from a high level to a low level when the master device performs I2C bus data transmission. The pin function of SDA is configured to trigger the first external interrupt by a falling edge of the level.

[0039] Among them, sleep mode is a low-power state of electronic devices. In sleep mode, the slave device will shut down most of the internal circuits and only retain the necessary parts (such as wake-up sources, timers, etc.) so that it can quickly return to normal working state when needed. Optionally, the sleep mode can be a deep sleep mode, a hibernation mode, etc. The first external interrupt is used to instruct the slave device to interrupt the currently executed program and execute the subsequent steps when SDA switches from a high level to a low level.

[0040] In one embodiment, during the system initialization phase of the slave device, the pin function of SDA is configured as a first external interrupt triggered by a falling edge of the level, and after the SDA configuration is completed, the first external interrupt is turned off. SDA can be configured during the system initialization phase, that is, during the system initialization phase of the slave device, in addition to configuring SDA and SCL in the I2C bus normally and initializing the I2C bus, SDA also needs to be configured as an external interrupt triggered by a falling edge of the level. In addition, since there is usually no need for a sleep mode during the system initialization phase, the first external interrupt needs to be turned off after the SDA configuration is completed.

[0041] It should be noted that at the beginning of each I2C communication, the master device will first generate and send a start signal (an example of the first signal), which is also the start mark of the I2C bus data transmission. The action corresponding to the start signal is that the SDA pin of I2C changes from a high level to a low level. After the start signal, the I2C bus starts data transmission. For example, when the master device sends I2C data to the slave device through the I2C bus, the master device first generates a start signal and sends it to the slave device, waiting for the slave device to respond. If the slave device responds, the master device sends I2C data to the slave device. Based on the above configuration of the SDA pin function, if the master device subsequently sends I2C data to the slave device in sleep mode through the I2C bus, the above-mentioned first external interrupt will be triggered.

[0042] In one embodiment, after SDA switches from a high level to a low level, it can be maintained for at least a certain time, such as 4.7 microseconds, to ensure that the slave device can correctly identify the start signal.

[0043] In one embodiment, the first external interrupt can be configured using the following steps. First, define an interrupt initialization structure for storing the configuration parameters of the first external interrupt. The interrupt initialization structure can be a structure containing multiple fields, and different fields can be used to represent interrupt lines, modes, trigger modes, etc. Then, by calling the GPIO_ConfigEXTILine function, the corresponding EXTI channel number is obtained according to the GPIO channel number used by SDA in the I2C bus. Then configure the EXTI initialization structure, assign the previously obtained EXTI channel number to the corresponding field of the structure, and select the corresponding EXTI channel. For example, the following code can be used to select the corresponding EXTI channel: EXTI_InitStructure.EXTI_Line= extiLine. In the process of configuring the EXTI initialization structure, the EXTI channel is also configured to interrupt mode, allowing the EXTI channel to generate an interrupt when a state change is detected. For example, the following code can be used to configure the corresponding EXTI channel to interrupt mode: EXTI_InitStructure.EXTI_Mode= EXTI_Mode_Interrupt. In the process of configuring the EXTI initialization structure, the interrupt trigger mode is also set to falling edge trigger, that is, the external interrupt will only be triggered when the SDA pin switches from high level to low level. For example, the following code can be used to configure the corresponding EXTI channel into interrupt mode: EXTI_InitStructure.EXTI_Trigger =EXTI_Trigger_Falling. Finally, the EXTI_InitPeripheral function is called and the configured structure is passed to the function to complete the initialization of the external interrupt. The EXTI_InitPeripheral function usually sets the relevant hardware registers according to the configuration parameters in the structure to make the EXTI channel effective.

[0044] Step 402: after the first external interrupt is triggered, exit the sleep mode and disable the first external interrupt.

[0045] In the embodiment of the present application, step 402 should be completed before the slave device receives the I2C data sent by the master device through the I2C bus, that is, the shorter the time taken for this step, the better. In addition, when the slave device exits the sleep mode, the first external interrupt needs to be turned off immediately to avoid affecting the reception of subsequent I2C data. If the time to complete this step is later than the time when the master device transmits the I2C data, the slave device will not be able to respond to the I2C data, resulting in failure of the slave device.

[0046] The device wake-up method provided in the above embodiment mainly utilizes the characteristic that SDA switches from a high level to a low level each time I2C communication starts, and pre-configures the pin function corresponding to SDA to trigger the first external interrupt on the falling edge of the level, and turns on the first external interrupt when the slave device enters the sleep mode. If the master device sends I2C data to the slave device in the sleep mode through the I2C bus, the above-mentioned first external interrupt will be triggered. Based on the characteristics of the above-mentioned I2C communication, it can be understood that the time when the level change of SDA occurs must be earlier than the time when the master device sends the I2C data, so through the above-mentioned first external interrupt, the slave device can be awakened from the sleep mode in time before the communication occurs on the I2C bus, so that the slave device can smoothly respond to the I2C data sent by the master device, avoiding the failure of the slave device. In addition, this method can also use one less GPIO pin, reducing the hardware cost and hardware complexity.

[0047] It can be understood that by configuring the first external interrupt, the slave device can temporarily exit the sleep mode before receiving the I2C data (an example of the first I2C data), and then process the I2C data. The slave device can further parse the I2C data to obtain the instruction corresponding to the I2C data (an example of the first instruction). If the instruction is a wake-up instruction, the slave device will no longer enter the sleep mode. In other words, the slave device can first receive the first I2C data sent by the master device through the I2C bus, and then parse the first I2C data to obtain the first instruction. If the first instruction is a wake-up instruction, the sleep mode will not be entered. If the first instruction is not a wake-up instruction, the first external interrupt is turned on, and the sleep mode is entered after the first external interrupt is turned on. Specifically, if the received I2C data is parsed and the instruction corresponding to the I2C data is not a wake-up instruction, it means that the master device only wants the slave device to temporarily exit the sleep mode to process the instruction. After processing, the slave device continues to remain in the sleep mode, so the slave device will turn on the first external interrupt and re-enter the sleep mode. For another example, if the parsed command is not a wake-up command, it may be that the first external interrupt is triggered by level jitter. In order to prevent similar accidents, the slave device will also turn on the first external interrupt and re-enter the sleep mode. After the command is processed, the slave device will continue to detect the level state corresponding to SDA in the I2C bus until the slave device determines that it has received a wake-up command and exits the sleep mode.

[0048] In one embodiment, the slave device can determine whether to enter the sleep mode by detecting the state of the sleep flag corresponding to the sleep mode, that is, the slave device can clear the preset sleep flag when the first instruction is a wake-up instruction, wherein the sleep flag is cleared to indicate that the slave device does not enter the sleep mode. It should be noted that the sleep flag is a flag used to indicate whether the slave device can enter the sleep mode. The sleep flag is usually a Boolean value that can be stored in a certain location or register in the memory. For example, the sleep flag can be cleared by setting the sleep flag to "0" or "false". When the slave device detects that the sleep flag is "0" or "false", it will not enter the sleep mode subsequently.

[0049] The above embodiment describes the process of waking up the slave device. The following describes the process of the slave device entering the sleep mode.

[0050] In one embodiment, when the slave device is not in sleep mode, it can respond to the sleep instruction sent by the master device through the I2C bus, turn on the first external interrupt, and then enter the sleep mode after the first external interrupt is turned on. It can be understood that when the slave device is not in sleep mode, the slave device can process various instructions received from the master device via the I2C bus until it detects that the master device has sent a sleep instruction, at which time the first external interrupt is turned on to ensure that the slave device can be successfully awakened and finally enter the sleep mode.

[0051] In one embodiment, the slave device can determine whether to enter the sleep mode by detecting the state of the sleep flag corresponding to the sleep mode, that is, the slave device can set the preset sleep flag in response to the sleep instruction sent by the master device through the I2C bus when it is not in the sleep mode, wherein the sleep flag is set to indicate that the slave device enters the sleep mode; after the sleep flag is set, the first external interrupt is turned on. It can be understood that if the sleep instruction is detected, the flag corresponding to the sleep mode needs to be set. In the subsequent processing flow, when the sleep flag is detected to be set, it is ready to enter the sleep mode. Therefore, by detecting the state of the sleep flag corresponding to the sleep mode, it can be determined whether to enter the sleep mode, which simplifies the process design. In addition, after the sleep flag is set, the first external interrupt needs to be turned on to avoid affecting the subsequent wake-up process. For example, the sleep flag can be set by setting the sleep flag to "1" or "true". When the slave device detects that the sleep flag is "1" or "true", it enters the sleep mode subsequently.

[0052] In one embodiment, in a non-sleep mode, the slave device first receives the I2C data sent by the master device via the I2C bus to obtain a specific instruction, and when it is determined that the instruction (an example of the second instruction) detected is a sleep instruction, the first external interrupt is turned on to ensure that the subsequent slave device can be successfully awakened. That is, when the slave device is not in sleep mode, it first receives the second I2C data sent by the master device via the I2C bus, then parses the second I2C data to obtain the second instruction, and finally turns on the first external interrupt when the second instruction is a sleep instruction.

[0053] In the above Figure 3 Based on the software architecture shown, Figure 5 FIG. 1 shows a schematic diagram of a process of initializing a slave device provided in an embodiment of the present application. Figure 5 As shown, the system initialization module performs the relevant configuration and initialization operations of the internal integrated circuit. Specifically, first, the pin functions of SCL and SDA in the I2C bus used by the slave device can be configured to open-drain pull-up mode, and the I2C bus is initialized to determine the slave device. In addition, it is also necessary to configure the pin function corresponding to SDA in the I2C bus to the first external interrupt triggered by the falling edge of the level, and turn off the first external interrupt.

[0054] It should be noted that both SDA and SCL in the I2C bus are open-drain outputs, connected to the positive power supply through a pull-up resistor. When I2C communication is not in progress, SDA and SCL remain at a high level. Open-drain output means that the output port controls the level state through the switch of a transistor. Specifically, an NPN transistor is connected to the output port, the collector of which is connected to the output port, and the emitter is grounded. When a low level is required to be output, the transistor is turned on, the output port is grounded, and a low level is formed; when a high level is required to be output, the transistor is turned off, and the output port is in a floating state, that is, a high impedance state. In order to achieve a complete output function, open-drain output usually needs to be combined with an external pull-up resistor. When the output port is in a high impedance state, the external pull-up resistor pulls the output port up to the required high level. Therefore, open-drain output can achieve low-level output by controlling the conduction and cutoff of the transistor, while the high-level output is provided by the external pull-up resistor. Through the combination of multiple open-drain output ports, multiple devices can control the bus while avoiding output conflicts and level interference.

[0055] In the embodiment of the present application, the I2C bus protocol supports multiple master-slave devices to share a bus. If push-pull output is used, short circuits may occur between different master devices. Therefore, the present application will configure the pin functions of SCL and SDA in the I2C bus to open-drain pull-up mode during the system initialization phase. Normally, the open-drain output cannot directly output a high level, but by connecting a pull-up resistor at the drain, the level conversion can be achieved. The I2C bus consists of two lines, SDA and SCL. The output stage of all connected devices must be open-drain and connected to the power supply through a pull-up resistor to ensure the realization of the "line and" function. According to the I2C bus specification, when the I2C bus is idle, both SDA and SCL remain at a high level. When a master device (such as device A) needs to start I2C communication, device A will switch SDA from a high level to a low level when SCL is at a high level, as a start signal. Then device A will check the level state of SDA again. This is because, in the "wired AND" logic, if device A pulls SDA high while another device has already pulled it low, then device A will find that SDA is not high but low when checking, which means that other devices have occupied the I2C bus first, and device A can only choose to give up. On the contrary, if SDA remains high, it means that device A can successfully occupy the bus and start communication. Therefore, during the system initialization phase, the SCL and SDA pins need to be set to open-drain outputs and connected to appropriate pull-up resistors.

[0056] In the above Figure 3 Based on the software architecture shown, Figure 6 FIG. 1 is a flow chart showing a process of a slave device entering a sleep mode provided in an embodiment of the present application. Figure 6 As shown, first, when the master device enters the sleep mode by default or enters the sleep mode in response to the user's operation, a sleep instruction is sent to the slave device through the internal integrated circuit I2C bus, triggering the I2C hardware interrupt and generating a signal. When the I2C driver module recognizes the signal, it receives and parses the I2C data, and distributes the I2C data to the system status control module. The system status control module identifies the received I2C data, and if a sleep instruction is detected, the sleep flag is set. Then the idle task obtains the sleep flag from the system status control module. If it is detected that the sleep flag is set, the system status control module is notified to prepare to enter the sleep mode. Finally, the system status control module controls the GPIO driver module to turn on the first external interrupt, and the slave device enters the sleep mode.

[0057] In the above Figure 3 Based on the software architecture shown, Figure 7 FIG. 2 shows a schematic diagram of a process for waking up a slave device provided by an embodiment of the present application. Figure 7As shown, the master device sends a wake-up command to the slave device. First, SDA will switch from high level to low level, triggering the first external interrupt, and the slave device exits sleep mode. Then the GPIO driver module will immediately turn off the first external interrupt to prevent the first external interrupt from affecting I2C communication. At this time, since the slave device is in normal working state, I2C communication can be carried out normally. Specifically, the I2C hardware interrupt is triggered, and the I2C driver module receives and parses the I2C data and distributes the I2C data to the system status control module. The system status control module identifies the received I2C data. If a wake-up command is detected, the sleep flag is cleared. Then the idle task will obtain the sleep flag from the system status control module. If it is detected that the sleep flag is cleared, no operation is performed and the sleep mode is not entered subsequently.

[0058] Figure 8 This is a timing interaction diagram of the device wake-up method provided in the embodiment of the present application. Figure 8 The specific interaction process of the above solution is illustrated by way of example.

[0059] Step 801: The processing unit of the slave device performs related configuration and initialization operations of the I2C bus.

[0060] In an embodiment of the present application, first, the pin functions of SCL and SDA in the I2C bus used by the slave device can be configured to an open-drain pull-up mode, and the I2C bus can be initialized to determine the slave device.

[0061] It can be understood that the processing unit here may include the above-mentioned system initialization module.

[0062] Step 802: The processing unit configures the pin function corresponding to SDA to trigger a first external interrupt when the level falls, and disables the first external interrupt.

[0063] It should be noted that at the beginning of each I2C communication, the master device first generates and sends a start signal, which is also the start mark of the I2C bus data transmission. The action corresponding to the start signal is that the SDA pin of the I2C changes from a high level to a low level. After the start signal, the I2C bus starts data transmission. Therefore, based on the configuration of the SDA pin function in step 802, if the subsequent master device sends I2C data to the slave device in sleep mode through the I2C bus, the first external interrupt will be triggered.

[0064] It can be understood that the processing unit here may include the above-mentioned system initialization module.

[0065] Step 803: The user instructs the master device to enter sleep mode.

[0066] In another embodiment, the master device can automatically enter sleep mode if it does not receive any input (such as keystrokes, sensor signals, etc.) for a period of time. The master device can also use a timer to periodically check the system status and enter sleep mode if there is no activity for a set period of time. The master device can also decide whether to enter sleep mode based on conditions such as battery power and temperature. For example, when the battery power is below a certain threshold, the system can automatically enter sleep mode to protect the battery.

[0067] In another embodiment, the slave device itself may also enter sleep mode (active or passive). For this scenario, the following steps are also applicable.

[0068] Step 804: The master device sends I2C data including a sleep instruction to the slave device via the I2C bus.

[0069] In the embodiment of the present application, when the master device enters the sleep mode, it sends a sleep instruction to the slave device through the I2C bus, triggers the I2C hardware interrupt, and executes subsequent steps 805-807.

[0070] Step 805: triggering an I2C hardware interrupt.

[0071] In an embodiment of the present application, a signal is generated when an I2C hardware interrupt is triggered. When the I2C driver module in the slave device recognizes the signal, it receives and parses the I2C data, distributes the I2C data to the system status control module, and then executes subsequent steps.

[0072] Step 806: The processing unit confirms receipt of the sleep instruction and sets a sleep flag.

[0073] In an embodiment of the present application, if a sleep instruction is detected, the system status control module will set the flag corresponding to the sleep mode. In the subsequent processing flow, the idle task will obtain the sleep flag from the system status control module. If it is detected that the sleep flag is set, the system status control module will be notified to prepare to enter the sleep mode.

[0074] It can be understood that the processing unit here may include the above-mentioned idle tasks.

[0075] Step 807: The processing unit turns on the first external interrupt and then enters the sleep mode.

[0076] In an embodiment of the present application, when the slave device is not in sleep mode, the slave device can process various instructions received from the master device via the I2C bus until it detects that the master device has sent a sleep instruction. At this time, the first external interrupt is turned on to ensure that the slave device can be awakened smoothly and finally enter sleep mode.

[0077] It can be understood that the processing unit here may include the above-mentioned system state control module.

[0078] Step 808: The master device sends I2C data including any instructions.

[0079] Step 809: triggering a first external interrupt.

[0080] In the embodiment of the present application, no matter whether the master device sends I2C data containing any instruction to the slave device in the sleep mode through the I2C bus, the first external interrupt will be triggered.

[0081] Step 810: The processing unit exits the sleep mode and disables the first external interrupt.

[0082] It is understandable that at this time, the slave device only temporarily exits the sleep mode at the hardware level to respond to the I2C data sent by the master device, and does not completely exit the sleep state. If the I2C data does not include a wake-up command, the slave device will re-enter the sleep mode after processing the I2C data.

[0083] It can be understood that the processing unit here may include the above-mentioned external interrupt and GPIO driver modules.

[0084] In step 811 , the processing unit determines whether the received command is a wake-up command. If so, step 813 is executed; if not, step 812 is executed.

[0085] It can be understood that the processing unit here may include the above-mentioned idle tasks.

[0086] Step 812: The processing unit enables the first external interrupt and enters a sleep mode.

[0087] In the embodiment of the present application, if the received I2C data is parsed and the instruction corresponding to the I2C data is not a wake-up instruction, it means that the master device only wants the slave device to temporarily exit the sleep mode to process the instruction, and the slave device continues to remain in the sleep mode after processing, so the slave device will turn on the first external interrupt and re-enter the sleep mode. After this step, the slave device will continue to detect the level state corresponding to SDA in the I2C bus until the slave device determines that it has received a wake-up instruction and exits the sleep mode.

[0088] It can be understood that the processing unit here may include the above-mentioned system state control module.

[0089] Step 813: The processing unit determines that a wake-up instruction is received and cancels the sleep flag.

[0090] In the embodiment of the present application, after step 813 is executed, the slave device does not subsequently enter the sleep mode and ends the sleep state.

[0091] It can be understood that the processing unit here may include the above-mentioned idle tasks.

[0092] The device wake-up method provided in the above embodiment mainly utilizes the characteristic that SDA switches from a high level to a low level each time I2C communication starts, and pre-configures the pin function corresponding to SDA to trigger the first external interrupt on the falling edge of the level, and turns on the first external interrupt when the slave device enters the sleep mode. If the master device sends I2C data to the slave device in the sleep mode through the I2C bus, the above-mentioned first external interrupt will be triggered. Based on the characteristics of the above-mentioned I2C communication, it can be understood that the time when the level change of SDA occurs must be earlier than the time when the master device sends the I2C data, so through the above-mentioned first external interrupt, the slave device can be awakened from the sleep mode in time before the communication occurs on the I2C bus, so that the slave device can smoothly respond to the I2C data sent by the master device, avoiding the failure of the slave device. In addition, this method can also use one less GPIO pin, reducing the hardware cost and hardware complexity.

[0093] The above mainly introduces the method of the embodiment of the present application in conjunction with the accompanying drawings. It should be understood that although the various steps in the flowcharts involved in the various embodiments described above are displayed in sequence, these steps are not necessarily performed in sequence in the order shown in the figure. Unless clearly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the various embodiments described above may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a part of the steps or stages in other steps. The device of the embodiment of the present application is introduced below in conjunction with the accompanying drawings.

[0094] Reference Fig. 9 , is a schematic diagram of the structure of a device wake-up apparatus provided in an embodiment of the present application. For the sake of convenience, only the parts related to the embodiment of the present application are shown. Fig. 9 As shown, the device awakening device 900 includes a processing unit 901. The device awakening device 900 can be integrated in an electronic device. For another example, the device awakening device 900 can also be used to execute Figure 4 or Figure 8 The process shown.

[0095] The device waking-up apparatus 900 can be used to execute any one of the above methods. For example, the processing unit 901 can be used to execute step 401 and step 402.

[0096] The device wake-up device provided in the embodiment of the present application mainly utilizes the characteristic that SDA switches from a high level to a low level each time an I2C communication starts, and pre-configures the pin function corresponding to SDA to trigger the first external interrupt on the falling edge of the level, and turns on the first external interrupt when the slave device enters the sleep mode. If the master device sends I2C data to the slave device in the sleep mode through the I2C bus, the above-mentioned first external interrupt will be triggered. Based on the characteristics of the above-mentioned I2C communication, it can be understood that the time when the level change of SDA occurs must be earlier than the time when the master device sends the I2C data, so through the above-mentioned first external interrupt, the slave device can be awakened from the sleep mode in time before the communication occurs on the I2C bus, so that the slave device can smoothly respond to the I2C data sent by the master device, avoiding the failure of the slave device. In addition, this method can also use one less GPIO pin, reducing the hardware cost and hardware complexity.

[0097] It should be noted that the above explanations of the device wake-up method embodiment are also applicable to the device wake-up apparatus 900 of this embodiment, and will not be repeated here.

[0098] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0099] Fig.10 Schematic diagram of the structure of the electronic device provided in the embodiment of the present application. Fig.10 As shown, the electronic device 1000 of this embodiment includes: at least one processor 1010 ( Fig.10Only one processor is shown in the figure), a memory 1020, and a computer program 1021 stored in the memory 1020 and executable on at least one processor 1010. When the processor 1010 executes the computer program 1021, the steps in the above-mentioned device wake-up method embodiment are implemented.

[0100] The electronic device 1000 may be a computing device such as a desktop computer, a notebook, a PDA, or a cloud server. The electronic device may include, but is not limited to, a processor 1010 and a memory 1020. Those skilled in the art will appreciate that Fig.10 This is merely an example of the electronic device 1000 and does not constitute a limitation on the electronic device 1000 . The electronic device 1000 may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the electronic device 1000 may also include input and output devices, network access devices, etc.

[0101] The processor 1010 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0102] In some embodiments, the memory 1020 may be an internal storage unit of the electronic device 1000, such as a hard disk or memory of the electronic device 1000. In other embodiments, the memory 1020 may also be an external storage device of the electronic device 1000, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device 1000. Further, the memory 1020 may also include both an internal storage unit of the electronic device 1000 and an external storage device. The memory 1020 is used to store an operating system, an application program, a boot loader, data, and other programs, such as program codes of a computer program. The memory 1020 may also be used to temporarily store data that has been output or is to be output.

[0103] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0104] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0105] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0106] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the sentences "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0107] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0108] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0109] In the embodiments provided in the present application, it should be understood that the disclosed devices / electronic devices and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0110] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0111] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0112] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electric carrier signals and telecommunication signals.

[0113] The present application implements all or part of the processes in the above-mentioned embodiment method, and may also be completed through a computer program product. When the computer program product runs on an electronic device, the electronic device can implement the steps in the above-mentioned method embodiments when executing the computer program product.

[0114] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application is described in detail with reference to the above embodiments, a person skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A device wake-up method, characterized in that: Applied to a slave device, the slave device performs inter-integrated circuit I2C communication with a master device, and the method comprises: When the slave device is in the sleep mode, a first external interrupt is triggered when a first signal is detected, wherein the first external interrupt is turned on when the slave device is in the sleep mode, and the first signal is a signal that a serial data line SDA in the I2C bus switches from a high level to a low level when the master device performs I2C bus data transmission, and the pin function of the SDA is configured to trigger the first external interrupt at a falling edge of the level; After the first external interrupt is triggered, the sleep mode is exited and the first external interrupt is disabled.

2. The method according to claim 1, characterized in that After exiting the sleep mode and disabling the first external interrupt, the method further includes: Receiving first I2C data sent by the master device through the I2C bus; Parsing the first I2C data to obtain a first instruction; When the first instruction is a wake-up instruction, not entering the sleep mode; When the first instruction is not the wake-up instruction, the first external interrupt is enabled and the sleep mode is entered.

3. The method according to claim 2, characterized in that The step of not entering the sleep mode when the first instruction is a wake-up instruction includes: In the case where the first instruction is a wake-up instruction, a preset sleep flag is cleared, wherein the clearing of the sleep flag is used to indicate that the slave device does not enter the sleep mode.

4. The method according to any one of claims 1 to 3, characterized in that: Before the slave device is in sleep mode, the method further includes: In the system initialization stage, the SDA is configured to trigger the first external interrupt at a falling edge; Disable the first external interrupt.

5. The method according to claim 4, characterized in that The method further comprises: In response to a sleep instruction sent by the master device through the I2C bus, enabling the first external interrupt; After the first external interrupt is turned on, the sleep mode is entered.

6. The method according to claim 5, characterized in that The step of enabling the first external interrupt in response to a sleep instruction sent by the master device via the I2C bus comprises: When not in the sleep mode, receiving second I2C data sent by the master device through the I2C bus; Parsing the second I2C data to obtain a second instruction; When the second instruction is the sleep instruction, the first external interrupt is enabled.

7. The method according to claim 6, characterized in that In the case where the second instruction is the sleep instruction, the method further includes: In response to a sleep instruction sent by the master device via the I2C bus, a preset sleep flag is set, wherein the setting of the sleep flag is used to instruct the slave device to enter the sleep mode.

8. The method according to any one of claims 1 to 3, wherein the master device is a personal computer (PC), and the slave device is a touch panel.

9. An electronic device, characterized in that: The electronic device includes: one or more processors, and a memory; The memory is coupled to the one or more processors, and the memory is used to store computer program codes, wherein the computer program codes include computer instructions, and the one or more processors call the computer instructions to enable the electronic device to perform the method as claimed in any one of claims 1 to 8.

10. A chip system, characterized in that: The chip system is applied to an electronic device, and the chip system includes one or more processors, and the one or more processors are used to call computer instructions so that the electronic device executes the method as described in any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium comprises instructions, which, when executed on an electronic device, enable the electronic device to perform the method as claimed in any one of claims 1 to 8.

12. A computer program product, characterized in that The computer program product comprises a computer program, and when the computer program is run on an electronic device, the electronic device is caused to perform the method according to any one of claims 1 to 8.

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