Memory system, apparatus for encoding, and method of controlling memory system

Abstract

A storage system, an apparatus for encoding, and a method of controlling the storage system. The method comprises the following steps: acquiring an information bit; encoding the information bits using internal codes to obtain a plurality of internal code words; encoding the plurality of internal codewords using an external code to generate an external codeword; and storing the external codeword in a storage device, where at least one of the internal code and the external code includes a generalized concatenated code (GCC), and where the external codeword includes a hierarchical GCC (H-GCC) codeword.

Description

Technical Field

[0001] Apparatus and methods consistent with embodiments relate to managing storage devices and, more particularly, to error correction coding using generalized hierarchical concatenated codes. Background Art

[0002] Generally, a NAND chip, such as may be used in a flash memory device, may have a structure including a block of word lines (WLs), each of which includes a bit line (BL). A NAND cell may be formed at the intersection of the WL and the BL.

[0003] To allow fast NAND access, each WL can be divided into RAUs (random access units). To allow high reliability access, each RAU is protected with an error correction code (ECC). The ECC code length can have a specific length and can accommodate a specific number of information bits. In ECC, longer codes can achieve better reliability, and there is a motivation to have a longer ECC. On the other hand, the RAU structure can limit the length of the ECC code to a specific length.

[0004] Therefore, there is a need for an encoding scheme that uses local ECC for each RAU to maintain and improve read speed and decode time while also achieving improved reliability associated with longer code rates. Summary of the invention

[0005] According to one aspect of the present disclosure, a storage system includes: a storage device, the storage device being configured to store a plurality of codewords; at least one processor, the at least one processor being configured to: obtain information bits; encode the information bits using an inner code to obtain a plurality of inner codewords; encode the plurality of inner codewords using an outer code to generate an outer codeword; and store the outer codeword in the storage device, wherein at least one of the inner code and the outer code comprises a generalized concatenated code (GCC), and wherein the outer codeword comprises a hierarchical GCC (H-GCC) codeword.

[0006] According to one aspect of the present disclosure, an apparatus for encoding information bits for storage in a storage device includes: a memory interface configured to communicate with the storage device; and at least one processor configured to: obtain information bits; encode the information bits using polar codes to obtain a plurality of polar codewords; encode the plurality of polar codewords using generalized concatenated codes (GCCs) to obtain hierarchical GCC (H-GCC) codewords, wherein constituent codes of the GCCs include a first Reed-Solomon (RS) code and a second RS code; and control the memory interface to transmit the H-GCC codewords to the storage device.

[0007] According to one aspect of the present disclosure, a method for controlling a storage system is performed by at least one processor and includes: obtaining information bits; encoding the information bits using an internal code to obtain multiple internal codewords; encoding the multiple internal codewords using an external code to generate external codewords; and storing the external codewords in a storage device, wherein at least one of the internal code and the external code includes a generalized concatenated code (GCC), and wherein the external codeword includes a hierarchical GCC (H-GCC) codeword.

[0008] According to one aspect of the present disclosure, a method for encoding information bits for storage in a storage device is performed by at least one processor and includes: obtaining information bits; encoding the information bits using polar codes to obtain a plurality of polar codewords; encoding the plurality of polar codewords using generalized concatenated codes (GCCs) to obtain hierarchical GCC (H-GCC) codewords, wherein constituent codes of the GCCs include a first Reed-Solomon (RS) code and a second RS code; and transmitting the H-GCC codewords to the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent from the following description in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram of a computer system according to an embodiment;

[0011] Figure 2A is a block diagram of a host storage system according to an embodiment;

[0012] Figure 2B is a block diagram of an ECC engine according to an embodiment;

[0013] Figure 2C is a block diagram of an ECC encoding circuit according to an embodiment;

[0014] Figure 3 is a block diagram of a memory system according to an embodiment;

[0015] Figure 4 is a block diagram of a memory device according to an embodiment;

[0016] Figure 5 is a block diagram of a UFS system according to an embodiment;

[0017] Figure 6 is a block diagram of a memory system according to an embodiment;

[0018] Figure 7is a diagram of a 3D V-NAND structure suitable for a UFS device according to an embodiment;

[0019] Figure 8 shows an example code structure of an H-GCC codeword according to an embodiment;

[0020] Fig. 9 An example of a NAND memory block according to an embodiment is shown;

[0021] Fig.10 shows an example code structure of a GCC S-polar code according to an embodiment;

[0022] Fig.11 shows an example code structure of a GCC S-RS code according to an embodiment;

[0023] Fig. 12A shows an example of a sequential encoding algorithm that may be used to perform GCC encoding according to an embodiment;

[0024] Fig. 12B shows an example encoding order according to an embodiment;

[0025] Fig. 12C is a flow chart of an encoding process according to an embodiment;

[0026] Fig.13 An example of a code structure of an H-GCC code is shown;

[0027] Fig.14 shows examples of internal transformation spaces and external transformation spaces according to an embodiment;

[0028] Fig.15 An example of a code structure of an H-GCC code according to an embodiment is shown;

[0029] Fig.16 The corresponding Fig.15 An example of an RS code with an H-GCC code structure;

[0030] Fig.17A An example of a process for constructing a transfer matrix according to an embodiment is shown;

[0031] Fig. 17B is a method for constructing a Fig.17A Flow chart of the processing of the transfer matrix;

[0032] Fig.18A is a block diagram of an encoder for encoding information bits to generate output codewords according to an embodiment;

[0033] Fig.18B According to the use of the embodiment Fig.18AA flowchart of a process for an encoder to generate an output codeword;

[0034] Fig.19A An example of overhead allocation for H-GCC codewords according to an embodiment is shown;

[0035] Fig.19B shows an example of a row order change that may be performed on an S-RS codeword according to an embodiment;

[0036] Fig. 20A shows an example of a sequential encoding algorithm that may be used to perform H-GCC encoding according to an embodiment;

[0037] Fig. 20B shows an example encoding order according to an embodiment;

[0038] Fig. 20C is a flow chart of the encoding process;

[0039] Fig.21 is a flow chart of a process for controlling a storage system according to an embodiment; and

[0040] Fig. 22 is a block diagram of a data center according to an embodiment. DETAILED DESCRIPTION

[0041] In flash memory, data can be stored and read at the granularity of random access units (RAUs). Error correction codes (ECC) can be applied to RAU data to provide fast reads with high reliability. RAUs can include a predetermined number of information bits, while the NAND structure and hardware architecture limit the number of encoding bits. Therefore, the structure can define constraints on the number of information bits K and the code length N.

[0042] ECC codes may provide higher gains for larger code lengths, so to allow reading of the RAU with high throughput and low complexity, it may be advantageous to increase the code length despite the RAU constraints.

[0043] Accordingly, embodiments of the present disclosure may relate to a hierarchical ECC code that includes two levels and may be referred to as a hierarchical generalized concatenated code (H-GCC). In an embodiment, the first level of the H-GCC may use a generalized concatenated code (GCC) and a local P L parity bits to protect RAUs with a fixed number of information bits K and a fixed length N. The second level of H-GCC may include using the first level as a constituent code and inserting an additional P for each RAU G GCC with a global parity bit.

[0044] The H-GCC according to an embodiment may allow decoding of the RAU with high throughput and fixed information and code length, thereby achieving relatively high throughput, while the second level provides coding gain from a longer effective code length.

[0045] The embodiments discussed below may relate to various constructions of H-GCC code structures and various methods of performing systematic encoding using the H-GCC encoding algorithm. According to embodiments, the constituent codes and code parameters of the H-GCC codes discussed herein may be selected according to different objectives (e.g., correctability, complexity, power, etc.).

[0046] Figure 1 is a diagram of a system 1000 in which an embodiment may be applied. Figure 1 The system 1000 may be, for example, a mobile system such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Figure 1 The system 1000 is not necessarily limited to a mobile system, and may be a PC, a laptop, a server, a media player, or an automotive device (eg, a navigation device).

[0047] Reference Figure 1 , the system 1000 may include a main processor 1100, a memory (e.g., 1200a and 1200b), and a storage device (e.g., 1300a and 1300b). In addition, the system 1000 may include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0048] The main processor 1100 may control all operations of the system 1000, and more specifically, may control operations of other components included in the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, an application processor, or the like.

[0049] The main processor 1100 may include at least one central processing unit (CPU) core 1110, and also include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. In some embodiments, the main processor 1100 may further include an accelerator 1130, which is a dedicated circuit for high-speed data operations such as artificial intelligence (AI) data operations. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), etc., and is implemented as a chip physically separated from other components of the main processor 1100.

[0050] The memories 1200a and 1200b may be used as main storage devices of the system 1000. Although the memories 1200a and 1200b may respectively include volatile memories, such as static random access memory (SRAM) and / or dynamic random access memory (DRAM), etc., the memories 1200a and 1200b may respectively include non-volatile memories, such as flash memory, phase change random access memory (PRAM) and / or resistive random access memory (RRAM), etc. The memories 1200a and 1200b may be implemented in the same package as the main processor 1100.

[0051] The storage devices 1300a and 1300b may be used as non-volatile storage devices, which are configured to store data regardless of whether they are powered on, and have a larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may include memory controllers (STRG CTRL) 1310a and 1310b and non-volatile memories (NVM) 1320a and 1320b, respectively, which are configured to store data via the control of the memory controllers 1310a and 1310b. Although the NVMs 1320a and 1320b may include V-NAND flash memories having a two-dimensional (2D) or three-dimensional (3D) structure, the embodiments are not limited thereto and the NVMs 1320a and 1320b may include other types of NVMs, such as PRAM and / or RRAM, etc.

[0052] The storage devices 1300a and 1300b may be physically separated from the main processor 1100 and included in the system 1000, or may be implemented in the same package as the main processor 1100. In addition, the storage devices 1300a and 1300b may have a type of SSD or memory card, and may be removably combined with other components of the system 1000 through an interface such as a connection interface 1480 to be described later. The storage devices 1300a and 1300b may be devices to which a standard protocol such as Universal Flash Storage (UFS), Embedded Multimedia Card (eMMC), or NVMe is applied, but are not limited thereto.

[0053] The image capture device 1410 can capture still images or moving images. The image capture device 1410 may include a camera, a camcorder, and / or a webcam, etc.

[0054] The user input device 1420 may receive various types of data input by a user of the system 1000 and includes a touch pad, a keypad, a keyboard, a mouse, a microphone, and the like.

[0055] The sensor 1430 may detect various types of physical quantities that may be obtained from the outside of the system 1000 and convert the detected physical quantities into electrical signals. The sensor 1430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyro sensor, etc.

[0056] The communication device 1440 may transmit and receive signals between other devices outside the system 1000 according to various communication protocols. The communication device 1440 may include an antenna, a transceiver, a modem, or the like.

[0057] Display 1450 and speaker 1460 may be used as output devices configured to output visual information and auditory information, respectively, to a user of system 1000 .

[0058] The power supply device 1470 may appropriately convert power supplied from a battery embedded in the system 1000 and / or an external power source, and supply the converted power to each component of the system 1000 .

[0059] The connection interface 1480 may provide a connection between the system 1000 and an external device that is connected to the system 1000 and is capable of transmitting and receiving data to and from the system 1000. The connection interface 1480 may be implemented by using various interface schemes, for example, Advanced Technology Attachment (ATA), Serial ATA (SATA), External Serial ATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) interface, UFS interface, Embedded UFS (eUFS) interface, Compact Flash (CF) card interface, and the like.

[0060] Figure 2A is a block diagram of a host storage system 10 according to an exemplary embodiment.

[0061] The host storage system 10 may include a host 100 and a storage device 200. In addition, the storage device 200 may include a memory controller 210 and an NVM 220. According to an exemplary embodiment of the present invention, the host 100 may include a host controller 110 and a host memory 120. The host memory 120 may be used as a buffer memory configured to temporarily store data to be transmitted to or received from the storage device 200.

[0062] The storage device 200 may include a storage medium configured to store data in response to a request from the host 100. As an example, the storage device 200 may include at least one of an SSD, an embedded memory, and a removable external memory. When the storage device 200 is an SSD, the storage device 200 may be a device that complies with the NVMe standard. When the storage device 200 is an embedded memory or an external memory, the storage device 200 may be a device that complies with the UFS standard or the eMMC standard. Both the host 100 and the storage device 200 may generate a packet and send the packet according to the adopted standard protocol.

[0063] When the NVM 220 of the storage device 200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 200 may include various other types of NVM. For example, the storage device 200 may include a magnetic random access memory (MRAM), a spin transfer torque MRAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FRAM), a PRAM, a RRAM, and various other types of memory.

[0064] According to an embodiment, the host controller 110 and the host memory 120 may be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller 110 and the host memory 120 may be integrated in the same semiconductor chip. As an example, the host controller 110 may be any one of a plurality of modules included in an application processor (AP). The AP may be implemented as a system on chip (SoC). In addition, the host memory 120 may be an embedded memory included in the AP or a memory module external to the AP.

[0065] The host controller 110 may manage an operation of storing data (eg, write data) of the buffer area of ​​the host memory 120 in the NVM 220 or an operation of storing data (eg, read data) of the NVM 220 in the buffer area.

[0066] The memory controller 210 may include a host interface 211, a memory interface 212, and a CPU 213. In addition, the memory controller 210 may further include a flash translation layer (FTL), a packet manager 215, a buffer memory 216, an ECC engine 217, and an advanced encryption standard (AES) engine 218. The memory controller 210 may further include a working memory (not shown) in which the FTL 214 is loaded. The CPU 213 may execute the FTL 214 to control data write and read operations on the NVM 220.

[0067] The host interface 211 may transmit and receive packets to and from the host 100. The packets transmitted from the host 100 to the host interface 211 may include commands or data to be written to the NVM 220, etc. The packets transmitted from the host interface 211 to the host 100 may include responses to commands or data read from the NVM 220, etc. The memory interface 212 may transmit data to be written to the NVM 220 to the NVM 220 or receive data read from the NVM 220. The memory interface 212 may be configured to comply with a standard protocol such as Toggle or Open NAND Flash Interface (ONFI).

[0068] The FTL 214 may perform various functions, such as an address mapping operation, a wear leveling operation, and a garbage collection operation. The address mapping operation may be an operation of converting a logical address received from the host 100 into a physical address for actually storing data in the NVM 220. The wear leveling operation may be a technique for preventing excessive degradation of a specific block by allowing the blocks of the NVM 220 to be used evenly. As an example, the wear leveling operation may be implemented by using a firmware technique that balances the erase counts of physical blocks. The garbage collection operation may be a technique for ensuring available capacity in the NVM 220 by erasing an existing block after copying valid data of the existing block to a new block.

[0069] The packet manager 215 may generate a packet according to a protocol agreed to an interface of the host 100, or parse various types of information from a packet received from the host 100. In addition, the buffer memory 216 may temporarily store data to be written to or read from the NVM 220. Although the buffer memory 216 may be a component included in the memory controller 210, the buffer memory 216 may be outside the memory controller 210.

[0070] The ECC engine 217 may perform error detection and correction operations on read data read from the NVM 220. More specifically, the ECC engine 217 may generate parity bits for write data to be written to the NVM 220, and the generated parity bits may be stored together with the write data in the NVM 220. During reading of data from the NVM 220, the ECC engine 217 may correct errors in the read data by using the read data and the parity bits read from the NVM 220, and output the error-corrected read data.

[0071] The AES engine 218 may perform at least one of an encryption operation and a decryption operation on data input to the memory controller 210 by using a symmetric key algorithm.

[0072] Figure 2B for Figure 2ADetailed diagram of the ECC engine 217. Figure 2B , the ECC engine 217 may include an ECC encoding circuit 510 and an ECC decoding circuit 520. In response to the ECC control signal ECC_CON, the ECC encoding circuit 510 may generate parity bits ECCP[0:7] for write data WData[0:63] to be written to memory cells of the memory cell array 221. The parity bits ECCP[0:7] may be stored in the ECC cell array 223. According to an embodiment, in response to the ECC control signal ECC_CON, the ECC encoding circuit 510 may generate parity bits ECCP[0:7] for write data WData[0:63] to be written to memory cells including defective cells of the memory cell array 221.

[0073] In response to the ECC control signal ECC_CON, the ECC decoding circuit 520 may correct the error bit data by using the read data RData[0:63] read from the memory cells of the memory cell array 221 and the parity bits ECCP[0:7] read from the ECC cell array 223, and output the error-corrected data[0:63]. According to an embodiment, in response to the ECC control signal ECC_CON, the ECC decoding circuit 520 may correct the error bit data by using the read data RData[0:63] read from the memory cells including the defective cells of the memory cell array 221 and the parity bits ECCP[0:7] read from the ECC cell array 223, and output the error-corrected data[0:63].

[0074] Figure 2C for Figure 2B FIG. 5 is a diagram of an ECC encoding circuit 510 .

[0075] Reference Figure 2C , the ECC encoding circuit 510 may include a parity generator 511, which receives the 64-bit write data WData[0:63] and the basic bits B[0:7] in response to the ECC control signal ECC_CON, and generates the parity bits ECCP[0:7] by using an XOR array operation. The basic bits B[0:7] may be bits used to generate the parity bits ECCP[0:7] of the 64-bit write data WData[0:63], for example, b'00000000 bits. The basic bits B[0:7] may use other specific bits instead of the b'00000000 bits.

[0076] Figure 3 FIG. 1 is a block diagram of a storage system 15 according to an embodiment. Figure 3, the memory system 15 may include a memory device 17 and a memory controller 16. The memory system 15 may support a plurality of channels CH1 to CHm, and the memory device 17 may be connected to the memory controller 16 through the plurality of channels CH1 to CHm. For example, the memory system 15 may be implemented as a memory device such as an SSD.

[0077] The memory device 17 may include a plurality of NVM devices NVM11 to NVMmn. Each of the NVM devices NVM11 to NVMmn may be connected to one of the plurality of channels CH1 to CHm through a path corresponding thereto. For example, the NVM devices NVM11 to NVM1n may be connected to the first channel CH1 through paths W11 to W1n, and the NVM devices NVM21 to NVM2n may be connected to the second channel CH2 through paths W21 to W2n. In an exemplary embodiment, each of the NVM devices NVM11 to NVM1n may be implemented as an arbitrary storage element that may be operated according to a separate command from the memory controller 16. For example, each of the NVM devices NVM11 to NVM1n may be implemented as a chip or a die, but the embodiments of the present disclosure are not limited thereto.

[0078] The memory controller 16 may send and receive signals to and from the memory device 17 through the plurality of channels CH1 to CHm. For example, the memory controller 16 may send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device 17 through the channels CH1 to CHm, or receive data DATAa to DATAm from the memory device 17.

[0079] The memory controller 16 may select one from among the NVM devices NVM11 to NVMmn connected to each of the channels CH1 to CHm by using a corresponding one of the channels CH1 to CHm, and transmit and receive signals to and from the selected NVM device. For example, the memory controller 16 may select the NVM device NVM11 from among the NVM devices NVM11 to NVM1n connected to the first channel CH1. The memory controller 16 may transmit a command CMDa, an address ADDRa, and data DATAa to the selected NVM device NVM11 through the first channel CH1, or receive data DATAa from the selected NVM device NVM11.

[0080] The memory controller 16 may transmit and receive signals to and from the memory device 17 in parallel through channels different from each other. For example, the memory controller 16 may transmit a command CMDa to the memory device 17 through the first channel CH1 while transmitting a command CMDb to the memory device 17 through the second channel CH2. For example, the memory controller 16 may receive data DATAa from the memory device 17 through the first channel CH1 while receiving data DATAb from the memory device 17 through the second channel CH2.

[0081] The memory controller 16 may control all operations of the memory device 17. The memory controller 16 may send signals to the channels CH1 to CHm and control each of the NVM devices NVM11 to NVMmn connected to the channels CH1 to CHm. For example, the memory controller 16 may send a command CMDa and an address ADDRa to the first channel CH1 and control one selected from the NVM devices NVM11 to NVM1n.

[0082] Each of the NVM devices NVM11 to NVMmn may operate via the control of the memory controller 16. For example, the NVM device NVM11 may program data DATAa based on a command CMDa, an address ADDRa, and data DATAa provided to the first channel CH1. For example, the NVM device NVM21 may read data DATAb based on a command CMDb and an address ADDb provided to the second channel CH2, and transmit the read data DATAb to the memory controller 16.

[0083] although Figure 3 An example is shown in which the storage device 17 communicates with the memory controller 16 through m channels and includes n NVM devices corresponding to each channel, but the number of channels and the number of NVM devices connected to one channel may be changed.

[0084] Figure 4 FIG. 3 is a block diagram of a storage device 300 according to an exemplary embodiment. Figure 4 , the memory device 300 may include a control logic circuit 320, a memory cell array 330, a page buffer 340, a voltage generator 350, and a row decoder 360. The memory device 300 may further include Figure 6 The memory interface circuit 310 is shown. In addition, the memory device 300 may further include column logic, a pre-decoder, a temperature sensor, a command decoder and / or an address decoder.

[0085] The control logic circuit 320 may control all various operations of the memory device 300. The control logic circuit 320 may output various control signals in response to a command CMD and / or an address ADDR from the memory interface circuit 310. For example, the control logic circuit 320 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

[0086] The memory cell array 330 may include a plurality of memory blocks BLK1 to BLKz (where z is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. The memory cell array 330 may be connected to the page buffer 340 through the bit lines BL, and connected to the row decoder 360 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL.

[0087] In an exemplary embodiment, the memory cell array 330 may include a 3D memory cell array including a plurality of NAND strings. Each NAND string may include a plurality of memory cells, each of which is connected to a word line vertically stacked on a substrate. U.S. Patent Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Patent Publication No. 2011 / 0233648 are incorporated herein by reference. In an exemplary embodiment, the memory cell array 330 may include a 2D memory cell array including a plurality of NAND strings arranged in a row direction and a column direction.

[0088] The page buffer 340 may include a plurality of page buffers PB1 to PBn (where n is an integer greater than or equal to 3), which may be connected to the memory cells respectively through a plurality of bit lines BL. The page buffer 340 may select at least one of the plurality of bit lines BL in response to the column address Y-ADDR. Depending on the operation mode, the page buffer 340 may operate as a write driver or a sense amplifier. For example, during a programming operation, the page buffer 340 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, the page buffer 340 may sense the current or voltage of the selected bit line BL and sense the data stored in the memory cell.

[0089] The voltage generator 350 may generate various voltages for program, read, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator 350 may generate a program voltage, a read voltage, a program verification voltage, and an erase voltage as the word line voltage VWL.

[0090] The row decoder 360 may select one of a plurality of word lines WL and select one of a plurality of string selection lines SSL in response to the row address X-ADDR. For example, the row decoder 360 may apply a program voltage and a program verification voltage to the selected word line WL during a program operation, and apply a read voltage to the selected word line WL during a read operation.

[0091] Figure 5 2 is a diagram of a UFS system 2000 according to an embodiment. The UFS system 2000 may be a system conforming to the UFS standard announced by the Joint Electronic Engineering Design Development Council (JEDEC), and includes a UFS host 2100, a UFS device 2200, and a UFS interface 2300. Figure 5 To the extent that the description conflicts, Figure 1 The above description of system 1000 can also be applied to Figure 5 UFS system 2000.

[0092] Reference Figure 5 , the UFS host 2100 may be connected to the UFS device 2200 through the UFS interface 2300. Figure 1 When the main processor 1100 is an application processor, the UFS host 2100 may be implemented as a part of the application processor. The UFS host controller 2110 and the host memory 2140 may correspond to Figure 1 The UFS device 2200 may correspond to the main processor 1100 and the controller 1120 and the memories 1200a and 1200b. Figure 1 The storage devices 1300a and 1300b, and the UFS device controller 2210 and the NVM 2220 may correspond to Figure 1 Memory controllers 1310a and 1310b and NVMs 1320a and 1320b.

[0093] The UFS host 2100 may include a UFS host controller 2110, an application 2120, a UFS driver 2130, a host memory 2140, and a UFS interconnect (UIC) layer 2150. The UFS device 2200 may include a UFS device controller 2210, an NVM 2220, a storage interface 2230, a device memory 2240, a UIC layer 2250, and a regulator 2260. The NVM 2220 may include a plurality of storage elements 2221. Although each storage element 2221 may include a V-NAND flash memory having a 2D structure or a 3D structure, each storage element 2221 may include another NVM, such as a PRAM and / or an RRAM, etc. The UFS device controller 2210 may be connected to the NVM 2220 through a storage interface 2230. The storage interface 2230 may be set to comply with a standard protocol such as Toggle or ONFI.

[0094] The application 2120 may refer to a program that wants to communicate with the UFS device 2200 to use the functions of the UFS device 2200. The application 2120 may send an input-output request (IOR) to the UFS driver 2130 for an input / output (I / O) operation on the UFS device 2200. The IOR may refer to a data read request, a data storage (or write) request, and / or a data erase (or discard) request, but is not limited thereto.

[0095] The UFS driver 2130 may manage the UFS host controller 2110 through a UFS-Host Controller Interface (UFS-HCI). The UFS driver 2130 may convert the IOR generated by the application 2120 into a UFS command defined by the UFS standard, and send the UFS command to the UFS host controller 2110. One IOR may be converted into a plurality of UFS commands. Although the UFS command may be basically defined by the SCSI standard, the UFS command may be a command dedicated to the UFS standard.

[0096] The UFS host controller 2110 may transmit the UFS command converted by the UFS driver 2130 to the UIC layer 2250 of the UFS device 2200 through the UIC layer 2150 and the UFS interface 2300. During transmission of the UFS command, the UFS host register 2111 of the UFS host controller 2110 may function as a command queue (CQ).

[0097] The UIC layer 2150 on the UFS host 2100 side may include a Mobile Industry Processor Interface (MIPI) M-PHY 2151 and a MIPI UniPro 2152 , and the UIC layer 2150 on the UFS device 2200 side may also include a MIPI M-PHY 2251 and a MIPI UniPro 2252 .

[0098] The UFS interface 2300 may include a line configured to transmit a reference clock signal REF_CLK, a line configured to transmit a hardware reset signal RESET_n of the UFS device 2200 , a pair of lines configured to transmit a pair of differential input signals DIN_t and DIN_c, and a pair of lines configured to transmit a pair of differential output signals DOUT_t and DOUT_c.

[0099] The frequency of the reference clock signal REF_CLK provided from the UFS host 2100 to the UFS device 2200 may be one of 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz, but is not limited thereto. The UFS host 2100 may change the frequency of the reference clock signal REF_CLK during operation, that is, during a data transmission / reception operation between the UFS host 2100 and the UFS device 2200. The UFS device 2200 may generate a clock signal having various frequencies from the reference clock signal REF_CLK provided by the UFS host 2100 by using a phase-locked loop (PLL). And, the UFS host 2100 may set the data rate between the UFS host 2100 and the UFS device 2200 by using the frequency of the reference clock signal REF_CLK. That is, the data rate may be determined according to the frequency of the reference clock signal REF_CLK.

[0100] The UFS interface 2300 may support multiple channels, each of which may be implemented as a pair of differential lines. For example, the UFS interface 2300 may include at least one receiving channel and at least one transmitting channel. Figure 5 In the embodiment, a pair of lines configured to transmit a pair of differential input signals DIN_T and DIN_C may constitute a receiving channel, and a pair of lines configured to transmit a pair of differential output signals DOUT_T and DOUT_C ​​may constitute a transmitting channel. Figure 5 One transmission channel and one reception channel are shown in FIG. 1 , but the number of transmission channels and the number of reception channels may be changed.

[0101] The receiving channel and the transmitting channel may transmit data based on a serial communication scheme. Due to the structure in which the receiving channel is separated from the transmitting channel, full-duplex communication between the UFS host 2100 and the UFS device 2200 may be enabled. That is, while receiving data from the UFS host 2100 through the receiving channel, the UFS device 2200 may transmit data to the UFS host 2100 through the transmitting channel. In addition, control data (e.g., commands) from the UFS host 2100 to the UFS device 2200 and user data to be stored in the NVM 2220 of the UFS device 2200 or read from the NVM 2220 by the UFS host 2100 may be transmitted through the same channel. Therefore, between the UFS host 2100 and the UFS device 2200, in addition to a pair of receiving channels and a pair of transmitting channels, there is no need to further provide a separate channel for data transmission.

[0102] The UFS device controller 2210 of the UFS device 2200 may control all operations of the UFS device 2200. The UFS device controller 2210 may manage the NVM 2220 by using a logical unit (LU) 2211, which is a logical data storage unit. The number of LUs 2211 may be 8, but is not limited thereto. The UFS device controller 2210 may include an FTL, and convert a logical data address (e.g., a logical block address (LBA)) received from the UFS host 2100 into a physical data address (e.g., a physical block address (PBA)) by using address mapping information of the FTL. A logical block configured to store user data in the UFS system 2000 may have a size within a predetermined range. For example, the minimum size of a logical block may be set to 4Kbyte.

[0103] When a command from the UFS host 2100 is applied to the UFS device 2200 through the UIC layer 2250 , the UFS device controller 2210 may perform an operation in response to the command and transmit a completion response to the UFS host 2100 when the operation is completed.

[0104] As an example, when the UFS host 2100 intends to store user data in the UFS device 2200, the UFS host 2100 may send a data storage command to the UFS device 2200. When receiving a response (“Ready to Transfer” response) indicating that the UFS host 2100 is ready to receive user data (Ready to Transfer) from the UFS device 2200, the UFS host 2100 may send the user data to the UFS device 2200. The UFS device controller 2210 may temporarily store the received user data in the device memory 2240, and store the user data temporarily stored in the device memory 2240 in a selected location of the NVM 2220 based on the address mapping information of the FTL.

[0105] As another example, when the UFS host 2100 intends to read user data stored in the UFS device 2200, the UFS host 2100 may send a data read command to the UFS device 2200. The UFS device controller 2210, which has received the command, may read the user data from the NVM 2220 based on the data read command, and temporarily store the read user data in the device memory 2240. During the read operation, the UFS device controller 2210 may detect and correct errors in the read user data by using an ECC engine embedded therein. More specifically, the ECC engine may generate parity bits for write data to be written to the NVM 2220, and the generated parity bits may be stored in the NVM 2220 together with the write data. During the reading of data from the NVM 2220, the ECC engine may correct errors in the read data by using the read data and the parity bits read from the NVM 2220, and output the error-corrected read data.

[0106] In addition, the UFS device controller 2210 may transmit user data temporarily stored in the device memory 2240 to the UFS host 2100. Also, the UFS device controller 2210 may further include an AES engine. The AES engine may perform at least one of an encryption operation and a decryption operation on data transmitted to the UFS device controller 2210 by using a symmetric key algorithm.

[0107] The UFS host 2100 may sequentially store commands to be sent to the UFS device 2200 in the UFS host register 2111, which may be used as a common queue, and sequentially send the commands to the UFS device 2200. In this case, even when the previously sent command is still being processed by the UFS device 2200, that is, even before receiving a notification that the previously sent command has been processed by the UFS device 2200, the UFS host 2100 may send the next command on standby in the CQ to the UFS device 2200. Therefore, during the processing of the previously sent command, the UFS device 2200 may also receive the next command from the UFS host 2100. The maximum number of commands (or queue depth) that can be stored in the CQ may be, for example, 32. Also, the CQ may be implemented as a circular queue in which the start and end of the command line stored in the queue are indicated by a head pointer and a tail pointer.

[0108] Each of the plurality of storage elements 2221 may include a storage cell array and a control circuit configured to control the operation of the storage cell array. The storage cell array may include a 2D storage cell array or a 3D storage cell array. The storage cell array may include a plurality of storage cells. Although each storage cell is a single-layer cell (SLC) configured to store 1 bit of information, each storage cell may be a cell configured to store 2 or more bits of information, such as a multi-layer cell (MLC), a triple-layer cell (TLC), and a quad-layer cell (QLC). The 3D storage cell array may include a vertical NAND string in which at least one storage cell is vertically oriented and located on another storage cell.

[0109] Voltages VCC, VCCQ, and VCCQ2, etc., may be applied to the UFS device 2200 as power supply voltages. The voltage VCC may be a main power supply voltage for the UFS device 2200, and may be in the range of 2.4V to 3.6V. The voltage VCCQ may be a power supply voltage mainly used to supply a low voltage to the UFS device controller 2210, and may be in the range of 1.14V to 1.26V. The voltage VCCQ2 may be a power supply voltage mainly used to supply a voltage lower than the voltage VCC and higher than the voltage VCCQ to an I / O interface such as the MIPI M-PHY 2251, and may be in the range of 1.7V to 1.95V. The power supply voltage may be provided to the various components of the UFS device 2200 by the regulator 2260. The regulator 2260 may be implemented as a group of unit regulators, which are respectively connected to different power supply voltages among the above-mentioned power supply voltages.

[0110] Figure 6 FIG. 2 is a block diagram of a storage system 20 according to an embodiment. Figure 6 , the memory system 20 may include a memory device 300 and a memory controller 400. The memory device 300 may correspond to one of the NVM devices NVM11 to NVMmn, which is based on Figure 3 The memory controller 400 may communicate with one of the plurality of channels CH1 to CHm. The memory controller 400 may correspond to Figure 2A A storage controller 210 is provided.

[0111] The memory device 300 may include first to eighth pins P11 to P18 , a memory interface circuit 310 , a control logic circuit 320 , and a memory cell array 330 .

[0112] The memory interface circuit 310 may receive a chip enable signal nCE from the memory controller 400 through the first pin P11. The memory interface circuit 310 may send and receive signals to and from the memory controller 400 through the second to eighth pins P12 to P18 in response to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., a low level), the memory interface circuit 310 may send and receive signals to and from the memory controller 400 through the second to eighth pins P12 to P18.

[0113] The memory interface circuit 310 can receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 400 through the second to fourth pins P12 to P14. The memory interface circuit 310 can receive a data signal DQ from the memory controller 400 through the seventh pin P17, or send the data signal DQ to the memory controller 400. The command CMD, the address ADDR, and the data can be transmitted via the data signal DQ. For example, the data signal DQ can be transmitted through a plurality of data signal lines. In this case, the seventh pin P17 may include a plurality of pins corresponding to the plurality of data signals DQ, respectively.

[0114] The memory interface circuit 310 may obtain a command CMD from a data signal DQ received in an enable interval (e.g., a high level state) of a command latch enable signal CLE based on a switching time point of the write enable signal nWE. The memory interface circuit 310 may obtain an address ADDR from a data signal DQ received in an enable interval (e.g., a high level state) of an address latch enable signal ALE based on a switching time point of the write enable signal nWE.

[0115] In an exemplary embodiment, the write enable signal nWE may be maintained at a static state (e.g., a high level or a low level) and switched between a high level and a low level. For example, the write enable signal nWE may be switched in a section where a command CMD or an address ADDR is sent. Therefore, the memory interface circuit 310 may obtain a command CMD or an address ADDR based on a switching time point of the write enable signal nWE.

[0116] The memory interface circuit 310 may receive a read enable signal nRE from the memory controller 400 through a fifth pin P15. The memory interface circuit 310 may receive a data strobe signal DQS from the memory controller 400 through a sixth pin P16, or may transmit the data strobe signal DQS to the memory controller 400.

[0117] In the data (DATA) output operation of the memory device 300, the memory interface circuit 310 may receive a read enable signal nRE switched by the fifth pin P15 before outputting the data DATA. The memory interface circuit 310 may generate a data strobe signal DQS, which is switched based on the switching of the read enable signal nRE. For example, the memory interface circuit 310 may generate a data strobe signal DQS based on the switching start time of the read enable signal nRE, which starts switching after a predetermined delay (e.g., tDQSRE). The memory interface circuit 310 may send a data signal DQ including data DATA based on the switching time point of the data strobe signal DQS. Therefore, the data DATA may be aligned with the switching time point of the data strobe signal DQS and sent to the memory controller 400.

[0118] In the data (DATA) input operation of the memory device 300, when the data signal DQ including the data DATA is received from the memory controller 400, the memory interface circuit 310 may receive the switched data strobe signal DQ and the data DATA. The memory interface circuit 310 may obtain the data DATA from the data signal DQ based on the switching time point of the data strobe signal DQS. For example, the memory interface circuit 310 may sample the data signal DQ at the rising edge and the falling edge of the data strobe signal DQS and obtain the data DATA.

[0119] The memory interface circuit 310 may transmit the ready / busy output signal nR / B to the memory controller 400 through the eighth pin P18. The memory interface circuit 310 may transmit the state information of the memory device 300 to the memory controller 400 through the ready / busy output signal nR / B. When the memory device 300 is in a busy state (i.e., when an operation is being performed in the memory device 300), the memory interface circuit 310 may transmit the ready / busy output signal nR / B indicating the busy state to the memory controller 400. When the memory device 300 is in a ready state (i.e., when an operation is not being performed or completed in the memory device 300), the memory interface circuit 310 may transmit the ready / busy output signal nR / B indicating the ready state to the memory controller 400. For example, when the memory device 300 reads data DATA from the memory cell array 330 in response to a page read command, the memory interface circuit 310 may transmit the ready / busy output signal nR / B indicating the busy state (e.g., a low level) to the memory controller 400. For example, when the memory device 300 programs the data DATA to the memory cell array 330 in response to a program command, the memory interface circuit 310 may transmit a ready / busy output signal nR / B indicating a busy state to the memory controller 400 .

[0120] The control logic circuit 320 may control all operations of the memory device 300. The control logic circuit 320 may receive the command / address CMD / ADDR obtained from the memory interface circuit 310. The control logic circuit 320 may generate control signals for controlling other components of the memory device 300 in response to the received command / address CMD / ADDR. For example, the control logic circuit 320 may generate various control signals for programming data DATA to the memory cell array 330 or reading data DATA from the memory cell array 330.

[0121] The memory cell array 330 may store the data DATA obtained from the memory interface circuit 310 via the control of the control logic circuit 320. The memory cell array 330 may output the stored data DATA to the memory interface circuit 310 via the control of the control logic circuit 320.

[0122] The memory cell array 330 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present invention is not limited thereto, and the memory cells may be RRAM cells, FRAM cells, PRAM cells, thyristor RAM (TRAM) cells, or MRAM cells. Hereinafter, an embodiment in which the memory cells are NAND flash memory cells will be mainly described.

[0123] The memory controller 400 may include first to eighth pins P21 to P28 and a controller interface circuit 410. The first to eighth pins P21 to P28 may correspond to the first to eighth pins P11 to P18 of the memory device 300, respectively.

[0124] The controller interface circuit 410 may send a chip enable signal nCE to the memory device 300 through the first pin P21. The controller interface circuit 410 may send and receive signals to and from the memory device 300 through the second to eighth pins P22 to P28, wherein the memory device 300 is selected by the chip enable signal nCE.

[0125] The controller interface circuit 410 can send the command latch enable signal CLE, the address latch enable signal ALE and the write enable signal nWE to the memory device 300 through the second to fourth pins P22 to P24. The controller interface circuit 410 can send or receive the data signal DQ to or from the memory device 300 through the seventh pin P27.

[0126] The controller interface circuit 410 may transmit the data signal DQ including the command CMD or the address ADDR together with the switched write enable signal nWE to the memory device 300. The controller interface circuit 410 may transmit the data signal DQ including the command CMD to the memory device 300 by transmitting the command latch enable signal CLE having an enable state. Also, the controller interface circuit 410 may transmit the data signal DQ including the address ADDR to the memory device 300 by transmitting the address latch enable signal ALE having an enable state.

[0127] The controller interface circuit 410 may transmit the read enable signal nRE to the memory device 300 through the fifth pin P25. The controller interface circuit 410 may receive the data strobe signal DQS from the memory device 300 or transmit the data strobe signal DQS to the memory device 300 through the sixth pin P26.

[0128] In the data (DATA) output operation of the memory device 300, the controller interface circuit 410 may generate a switched read enable signal nRE and send the read enable signal nRE to the memory device 300. For example, before outputting the data DATA, the controller interface circuit 410 may generate a read enable signal nRE that changes from a static state (e.g., a high level or a low level) to a switched state. Therefore, the memory device 300 may generate a switched data strobe signal DQS based on the read enable signal nRE. The controller interface circuit 410 may receive a data signal DQ including data DATA and a switched data strobe signal DQS from the memory device 300. The controller interface circuit 410 may obtain data DATA from the data signal DQ based on the switching time point of the data strobe signal DQS.

[0129] In the data (DATA) input operation of the memory device 300, the controller interface circuit 410 may generate a switched data strobe signal DQS. For example, before sending the data DATA, the controller interface circuit 410 may generate a data strobe signal DQS that changes from a static state (e.g., a high level or a low level) to a switched state. The controller interface circuit 410 may send a data signal DQ including the data DATA to the memory device 300 based on the switching time point of the data strobe signal DQS.

[0130] The controller interface circuit 410 may receive the ready / busy output signal nR / B from the memory device 300 through the eighth pin P28. The controller interface circuit 410 may determine the status information of the memory device 300 based on the ready / busy output signal nR / B.

[0131] Figure 7FIG. 1 is a diagram of a 3D V-NAND structure applicable to a UFS device according to an embodiment of the present invention. When a memory module of the UFS device is implemented as a 3D V-NAND flash memory, each of a plurality of memory blocks included in the memory module may be composed of Figure 7 The equivalent circuit shown in .

[0132] Figure 7 The memory block BLKi shown in may refer to a 3D memory block having a 3D structure formed on a substrate. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

[0133] Reference Figure 7 , the memory block BLKi may include a plurality of memory NAND strings (e.g., NS11 to NS33) connected between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells (e.g., MC1, MC2, ..., and MC8), and a ground selection transistor GST. Although Figure 7 It is shown that each of the plurality of storage NAND strings NS11 to NS33 includes eight memory cells MC1, MC2, ..., and MC8, but the present invention is not limited thereto.

[0134] The string selection transistor SST can be connected to the string selection lines SSL1, SSL2 and SSL3 corresponding thereto. Each of the plurality of memory cells MC1, MC2, ... and MC8 can be connected to a corresponding one of the gate lines GTL1, GTL2, ... and GTL8. The gate lines GTL1, GTL2, ... and GTL8 can correspond to word lines, respectively, and some of the gate lines GTL1, GTL2, ... and GTL8 can correspond to virtual word lines. The ground selection transistor GST can be connected to the ground selection lines GSL1, GSL2 and GSL3 corresponding thereto. The string selection transistor SST can be connected to the bit lines BL1, BL2 and BL3 corresponding thereto, and the ground selection transistor GST can be connected to the common source line CSL.

[0135] Word lines (eg, WL1) of the same level may be commonly connected, and ground selection lines GSL1, GSL2, and GSL3 and string selection lines SSL1, SSL2, and SSL3 may be separated from each other. Figure 7 A case is shown in which the memory block BLK is connected to eight gate lines GTL1 , GTL2 , . . . , and GTL8 and three bit lines BL1 , BL2 , and BL3 , but the present invention is not limited thereto.

[0136] As discussed above, embodiments of the present disclosure may involve the construction of a family of codes that may be referred to as H-GCC codes and have code dimension and code length constraints suitable for applying ECC in flash memory.

[0137] The H-GCC code structure may include: 2 If a systematic encoder is used, the H-GCC codeword may include K information bits for each constituent code, P total parity check bits (where P=NK), and the P total parity check bits may be divided into local parity check bits P that may be used to protect the constituent codes. L and a global parity bit P that can be shared between the constituent codes G .

[0138] The constituent codes may be GCC codes with internal structures and corresponding transforms that can be used to generate transform spaces. For each constituent code, the transform space includes M 2 Each of them is m bits. 2 The symbols can be combined to generate Reed-Solomon (RS) code words in the transform space, thereby obtaining the concatenation of GCC and RS codes.

[0139] Figure 8 An example code structure of an H-GCC codeword according to an embodiment is shown. According to an embodiment, an H-GCC code may also be understood to be constructed using a cascade of GCC codes, an example of which will be discussed in more detail below. Figures 9 to 21 Various embodiments of H-GCC codes and corresponding parity check matrices and encoder algorithms are disclosed. For example, according to the embodiments discussed below, a GCC sequential encoder may be used as a base encoder for local parity bits, and the global parity bits may be considered as linear constraints. As another example, according to the embodiments discussed below, a constraint may be imposed on the overhead bit positions, and if the constraint is satisfied, the sequential encoder may be applicable to H-GCC.

[0140] Fig. 9An example of a NAND memory block according to an embodiment is shown. Generally, a NAND cell can store T bits, where T depends on the specific type of NAND memory cell. For example, a flash memory device in which each cell stores one bit (BPC) can be referred to as a single-level cell (SLC), a flash memory device that stores two BPCs can be referred to as a multi-level cell (MLC), a flash memory device that stores three BPCs can be referred to as a triple-level cell (TLC), a flash memory device that stores four BPCs can be referred to as a quad-level cell (QLC), and a flash memory device that stores five BPCs can be referred to as a penta-level cell (PLC). For example, the memory block 900 can be a TLC NAND memory block. As discussed above, a NAND chip can have a structure of Z blocks including word lines (WLs), where each WL includes M bit lines (BLs).

[0141] To allow for fast NAND access, each WL of the NAND memory device can be divided into random access units (RAUs). Generally, if the number of bits to be stored in an RAU is N, the WL can be divided into M / N sections, where each section will include T RAUs, which have N BLs, representing one of the T bits, which can be, for example, the least significant bit (LSB), the center significant bit (CSB), or the most significant bit (MSB). Accordingly, the number of RAUs in such a block will be Z*T*M / N.

[0142] To allow for highly reliable access, each RAU can be protected with ECC. For example, the ECC code length for an RAU can be length N, and it can accommodate K < N information bits. Generally, a longer ECC code can provide better reliability, so it can be advantageous to use a longer ECC. However, the RAU structure can accommodate an ECC of at most a specific length (e.g., length N).

[0143] To provide a longer ECC code, some ECC schemes can divide M non-equally into sections of length N 1 ,N 2 ..N M / N such that where N i ≠N j . In this way, it may be possible to combine RAUs and encode them together with a global parity bit.

[0144] However, the constraint N i ≠N j does not allow for a great deal of flexibility in combining RAUs. For example, the constraint N i ≠N jIt is not allowed to connect RAUs belonging to the same region together, for example by encoding the MSB, CSB and LSB together, and some losses may also be introduced in the decoding process. Therefore, embodiments may provide for using an efficient encoder algorithm based on the N i =N j The H-GCC coding scheme of hierarchical codes of GCC codes is feasible under the condition of .

[0145] According to an embodiment, the symbol may be used herein and [n] * =[0,1,2,...n]. Vectors can be represented by lowercase bold letters (e.g., v), and matrices can be represented by uppercase bold letters (e.g., A). The Kronecker product between an NxM matrix A and a matrix B can be defined according to the following equations 1 and 2:

[0146]

[0147]

[0148] The NxN identity matrix can be represented as N In addition, u φ can represent indices from a vector u of size n

[0149] According to an embodiment, G may represent a polar code generation matrix, φ t The static frozen set of polar codes at level t, P t It can be expressed as corresponding to φ t , P(n,k,φ) can represent the polar code of length n, dimension k and static frozen set φ, and The union of the static frozen sets of polar codes up to level j can be expressed as shown in Equation 3 below:

[0150]

[0151] According to an embodiment, α may represent a Galois Field primitive, and BCH(n,k,t) may represent a Bose-Chaudhuri-Hocquenghem (BCH) code of length n, dimension k, and error correction capability t. t The BCH transform corresponding to stage t can be represented.

[0152] According to an embodiment, RS(n,F) may represent an RS code of length n (symbols), where F=d min -1. In addition, R t The RS transform corresponding to level t can be represented.

[0153] According to an embodiment, Ps(n, k, α) may represent a polariton code of length n, dimension k, and static and dynamic frozen sets α. In addition, according to the following formula 4, δ t It can represent the dynamic frozen set of polariton codes of level t, α t Static and dynamic frozen sets of polariton codes of level t can be represented.

[0154] α t =φ t ∪δ t (Formula 4)

[0155] In addition, Z t It can be expressed as corresponding to α t Polariton code conversion.

[0156] Embodiments may use nested codes that can be used as constituent codes. The nested codes may be codes from the same family: length n and dimension k j of Among them, for j 1 <j 2 and j 1 ,j 2 ∈[M],

[0157] Codeword It can also be a codeword But with some linear constraints in and Make the code The effective dimensions of Reduce to

[0158] The transformation may refer to the application of the codeword c to the i (i∈[L],c i ∈{0,1} n ) and returns the codeword i which can be called the transformed space The linear operation T of the side information can be expressed according to the following equations 5 and 6:

[0159] s i =T·c i (Formula 5)

[0160]

[0161] According to an embodiment, the polar codeword c∈{0,1} n The reversible polarization transformation matrix G and the frozen space u∈{0,1} can be used according to the following equations 7 and 8 n To express:

[0162] c=G·u (Formula 7)

[0163] u=G -1 ·c (Formula 8)

[0164] The position in u Some bits at may be known and may be referred to as frozen bits. The number of frozen bits |φ| may represent the code overhead, so that the dimension of the polar code may be k=n-|φ|. A polar code of length n and dimension k may be denoted as P(n,k,φ), where c∈P(n,k,φ).

[0165] The union-find set of frozen bits can be expressed as And a frozen set can be represented as The corresponding nested polar code can be expressed as (j∈[st] * ), their corresponding dimensions are

[0166] According to the following formula 9, the nested code family can be expressed as

[0167]

[0168] Matrix U φ can be a matrix of |φ| on n that can select positions from a vector of length n and the corresponding transformation P φ , as shown in Equation 10 below:

[0169]

[0170] You can use the matrix To represent the transformation of the nested code, for the convenience of expression, the matrix can be expressed as The transformation space can include |φ t |Units and symbols t , as shown in Equation 11 below:

[0171] s t =P t ·c,t∈[M] Equation 11

[0172] The transformed spatial symbol of the polar codeword c can be defined according to the following equation 12:

[0173]

[0174] According to an embodiment, the code BCH (n, k, t) may be a BCH code of length n, dimension k, and error correction capability t. The parity check matrix of such a BCH code may be defined using primitives α, as shown in the following equation 13:

[0175]

[0176] For a set of error correction parameters t j ,j∈[M] * (making With corresponding dimension k j ), the BCH nested code family can be expressed as BCH(n,k 0→M ,t 0→M ), and can be based on the following

[0177] Formula 14 is used to express:

[0178]

[0179] For some j, the BCH code t j-1 →t j The coset can be represented as It can be defined according to the following formula 15:

[0180]

[0181] Then, the BCH transform can be defined according to Equation 16, where the corresponding transform space symbol is expressed according to Equation 17, and the transform space is defined according to the following Equation 18:

[0182]

[0183] s j =B j ·c (Formula 17)

[0184]

[0185] According to an embodiment, the code RS(n,F) may be an RS code of length n and minimum distance F+1.

[0186] The parity check matrix of such an RS code can be represented using primitive α, as shown in the following Equation 19:

[0187]

[0188] The error correction parameter set can be expressed as F t (t=0,1,2,…M) so that

[0189] The RS nested code family can be expressed as RS(n,F0→M ), and can be expressed using the following equation 20:

[0190]

[0191] RS code F t →F r ,F t ≤F r The coset can be represented as And it can be expressed using the following formula 21:

[0192]

[0193] Then, the RS transform can be defined according to Equation 22, where the corresponding transform space symbols are expressed according to Equation 23, and the transform space is defined according to the following Equation 24:

[0194]

[0195] s t =R t ·c (Formula 23)

[0196]

[0197] According to an embodiment, the polariton code may be understood as an extension of the polariton code. The polariton code may include static and dynamic frozen bits, both of which may be defined on a frozen space and generated using a polarization transformation matrix G.

[0198] The static freeze bit can be located at the index And the dynamic freeze bit can be located at the index Where

[0199] The static freeze bit can be represented as u i =f i , i∈φ, where f i ∈{0,1}. For the index set In constraint Next, dynamic freeze position u i (i∈δ) can satisfy the following equation 25:

[0200]

[0201] For the union-find t∈[M],α t The union of static and dynamic frozen sets can be represented and can be expressed according to the following Equation 26:

[0202] α t =φt ∪δ t (Formula 26)

[0203] In formula 26, and

[0204] Polariton Code Freezeset and the corresponding dimensions The polariton code nested code family can be expressed as And it can be expressed according to the following formula 27:

[0205]

[0206] The corresponding transformation can be expressed as And for convenience, you can use the symbol The transformation space can include |α t | bits, and the symbol s can be expressed according to Equation 28 t , where the transformed space symbol of codeword i is defined according to the following equation 29:

[0207] s t =Z t c,t∈[M] (Eq. 28)

[0208]

[0209] According to an embodiment, a GCC may be a code that includes several constituent codes belonging to a nested family of codes, a transform to a transform space, and a list of codes in the transform space, where there is a mapping between codewords and transform symbols.

[0210] Fig.10 An example code structure of a GCC S-polar code according to an embodiment is shown. Fig.10 As shown in , the GCC S-polar code can refer to the concatenation of the polar code and the RS code. For example, the GCC S-polar code can be related to the set of nested polar codes as shown in Equation 9, which has a corresponding and query set of frozen bit positions. t∈[M] and and frozen sets

[0211] Constraints can be added according to Equation 30 and Equation 31

[0212]

[0213]

[0214] Accordingly, the GCC S-polar code can satisfy the following equation 32:

[0215]

[0216] For example, the L polar codes may each belong to one of the nested codes of equation 9, where With length n and dimension k h(i) , (i∈[L]), where k h(1) ≥…≥k h(L) The function h(i) can map codeword i to the corresponding polarization nested code, such that h(1) = 0 and h(L) = M. According to an embodiment, L ≥ M, because several polarization codewords belong to the same polarization code. For the set of static bits definition And the [m·M]x[n] transformation matrix P can be defined according to the following formula 33:

[0217]

[0218] The corresponding transformation space symbol s can be expressed according to the following equation 34: i,t :

[0219] for and

[0220] Next, for all t∈[M], the symbol [s i＝1,t ,s i＝2,t ,…s i＝L,t ] T A vector of length L and dimension K can be defined as t RS codeword C t ∈RS(L,F t ), where K 1 ≤K 2 …≤K M , or equivalently in K 1 ≤K 2 …≤K M In the case where 0≤F t ≤L

[0221] According to an embodiment, in and There can be a direct relationship between t Equal to dimension less than k 1 -t·m The number of rows. This relationship can be expressed according to the following equation 35:

[0222] F t =|{i|k f(i) <k 1 -t·m}| (Formula 35)

[0223] The GCC S-polar code can be expressed according to the following equation 36:

[0224]

[0225] The GCC S-polar code is described above using the polar code as a component code, but the embodiment is not limited thereto. For example, in an embodiment, other component codes may be used, such as a BCH code or a polar subcode.

[0226] Fig.11 An example code structure of a GCC S-RS code according to an embodiment is shown. Fig.11 As shown in , the GCC S-RS code may refer to the concatenation of an RS code and an RS code.

[0227] For example, the GCC S-RS code can be used with the m ) is related to the set of nested RS codes defined in ), as shown in Equation 20. Constraints can be added according to Equations 37 and 38:

[0228]

[0229] |f 0 |=nk 0 (Formula 38)

[0230] Accordingly, the GCC S-RS code can satisfy the following equation 39:

[0231] f M -f 0 =M·m (Formula 39)

[0232] For example, L RS codes may all belong to one of the nested codes, where c i ∈RS(n,f h(i) )(i∈[L]), with length n and dimension k h(i) , where f h(1) ≤…≤f h(L) The function h(i) can map the codeword i to the corresponding RS nested code, so that h(1) = 0 and h(L) = M. The [m·M]x[n] change matrix R can be defined according to the following equation 40:

[0233]

[0234] for and The corresponding transformation space symbol s can be expressed according to the following formula 41 i,t :

[0235] s i,t =R t ·c i(Formula 41)

[0236] Next, for all t∈[M], the symbol [s i＝1,t ,s i＝2,t ,…s i＝L,t ] T A vector of length L and dimension K can be defined as t RS codeword C t ∈RS(L,F t ), where K 1 ≤K 2 …≤K M , or equivalently, F 1 ≥F 2 …≥F M .

[0237] The GCC S-RS code can be expressed according to the following equation 42:

[0238]

[0239] FIG. 12A to FIG. 12C Examples of encoding processes involving GCC codes (such as the GCC codes discussed above). According to an embodiment, the GCC encoding process may use any of the above elements (such as the GCC codes discussed above). Figure 2A The storage device 200 discussed above Figure 2B The ECC encoding circuit 510 or any other component discussed may be performed.

[0240] Fig. 12A An example of a sequential encoding algorithm that can be used to perform GCC encoding is shown, presented in pseudo code as Algorithm 1. According to an embodiment, the GCC system encoder can be applied to any GCC code parameter. For example, according to an embodiment, the GCC system encoder can perform an encoding operation corresponding to Algorithm 1 on a GCC codeword according to the following equation 43:

[0241]

[0242] The GCC encoder algorithm may include cross-activation of a coset polar code encoder and a RS system encoder. In an embodiment, the coset polar code encoder may be expressed according to the following equation 44:

[0243] c=ENC Polar (i,u φ ) (Formula 44)

[0244] According to Equation 44, the coset polar code encoder can receive the information bit i and the frozen value u at the position φ φ , and can return the system codeword c, where |u φ|=|φ| and |i|=n-|φ|. According to an embodiment, the information bit may be located in the first bit [n-|φ|].

[0245] The RS system encoder can be expressed according to the following equation 45:

[0246] v=ENC RS (u,F) (Equation 45)

[0247] The RS system encoder according to equation 45 can receive the information symbol u and return the RS codeword symbol v to use d min =F+1 generates a RS codeword where |u|=LF and |v|=L.

[0248] Fig. 12B An example encoding sequence that may correspond to the GCC encoder algorithm discussed above is shown. Fig. 12B As shown in , the number of codes for information bits is And the number of overhead bits is The information bit position can be provided by the following equation 46:

[0249]

[0250] like Fig. 12B As shown in , in operation 1221A, a polar code encoder may be used to determine the GCC parity check bits of the polar codeword when i=[1,2]. In operation 1221B, a transformation may be used to determine the transformation space of the polar codeword when i=[1,2], for example, as shown in equation 34. In operation 1221C, an RS encoder may be used to determine the RS parity check bits of the RS codeword when t=1.

[0251] like Fig. 12B As further shown in FIG. 1 , in operation 1222A, a polarization coset encoder may be used to determine a GCC parity check bit of a polarization codeword when i=[3, 4, 5] based on the transformed space symbol of t=1 generated in operation 1221C. In operation 1222B, a transform may be used to determine a transformed space of a polarization codeword when i=[3, 4, 5]. In operation 1222C, an RS encoder may be used to determine an RS parity check bit of an RS codeword when t=2.

[0252] like Fig. 12BAs further shown in FIG. 1 , in operation 1223A, a polarization coset encoder may be used to determine a GCC parity check bit of a polarization codeword when i=[6] based on the transformed space symbol of t=[1,2] generated in operations 1221C and 1222C. In operation 1223B, a transform may be used to determine a transformed space of a polarization codeword when i=[6]. In operation 1223C, an RS encoder may be used to determine an RS parity check bit of an RS codeword when t=3.

[0253] like Fig. 12B As further shown in FIG. 12, in operation 1224A, a polarization coset encoder may be used to determine a GCC parity check bit of a polar codeword when i=[7] based on the transformed space symbols of t=[1,2] generated in operations 1221C, 1222C, and 1223C. In operation 1224B, a transform may be used to determine a transformed space of a polar codeword when i=[7]. In operation 1224C, an RS encoder may be used to determine an RS parity check bit of an RS codeword when t=3.

[0254] like Fig. 12B As further shown in FIG. 12, in operation 1225A, a polarization coset encoder may be used to determine the GCC parity bits of the polar codeword when i=[8] based on the transformed space symbols of t=[1,2] generated in operations 1221C, 1222C, 1223C, and 1224C.

[0255] According to an embodiment, operations 1221A, 1222A, 1223A, 1224A and 1225A may correspond to "step a" of Algorithm 1, operations 1221B, 1222B, 1223B and 1224B may correspond to "step b" of Algorithm 1, and operations 1221C, 1222C, 1223C and 1224C may correspond to "step c" of Algorithm 1.

[0256] Fig. 12C is a flowchart of the encoding process according to the embodiment. Fig. 12CThe process 1200 shown in may correspond to some or all of Algorithm 1 discussed above. In an embodiment, some or all of the process 1200 may be performed using a polarization coset encoder (e.g., the polarization coset encoder discussed above). For example, in operation 1231, the process 1200 may include encoding a next polarization codeword. In operation 1232, the process 1200 may include updating a transform space corresponding to the encoded polarization codeword. In operation 1233, the process 1200 may include determining whether the last polarization codeword has been reached. Based on determining that the last polarization codeword has been reached (in operation 1233, "yes"), the process 1200 may proceed to operation 1234 and output a GCC codeword. Based on determining that the last polarization codeword has not been reached (in operation 1233, "no"), the process 1200 may proceed to operation 1235, which may include determining whether the next polarization codeword has the same degree as the polarization codeword encoded in operation 1231. Based on a determination that the next polar codeword does have the same degree ("yes" in operation 1235), process 1200 may return to operation 1231. Based on a determination that the next polar codeword does not have the same degree ("no" in operation 1235), process 1200 may proceed to operation 1236.

[0257] In operation 1236, the process 1200 may include encoding the next RS codeword. In operation 1237, the process 1200 may include determining whether the last RS codeword has been reached. Based on the determination that the last RS codeword has been reached ("yes" in operation 1237), the process 1200 may proceed to operation 1238, which may include updating the polarization codeword based on the encoding result of the RS codeword, and then return to step 1231. Based on the determination that the last RS codeword has not been reached, the process 1200 may proceed to operation 1239, which may include determining whether the next RS codeword has the same degree. Based on the determination that the next RS codeword does have the same degree ("yes" in operation 1235), the process 1200 may return to operation 1236. Based on the determination that the next RS codeword does not have the same degree ("no" in operation 1235), the process 1200 may proceed to operation 1238.

[0258] According to an embodiment, the GCC encoding process discussed above may use any of the elements described herein (e.g., Figure 2A The storage device 200 discussed above Figure 2B The ECC encoding circuit 510 or any other component discussed may be performed.

[0259] According to an embodiment, the definition of GCC may alternatively be by polar codes (as constituent codes), or by BCH codes (as constituent codes), and different systematic encoders may be used.

[0260] Fig.13 An example of a code structure of an H-GCC code according to an embodiment is shown. Fig.13 As shown in , H-GCC code can use GCC nested code family and to M 2 In an embodiment, H-GCC may be an independent L 2 GCC code (corresponding to L 2 RAU), these GCC codes are all of length N, dimension N, and have P L local parity bits and P G global parity bits, and use M in the transformation space 2 RS code.

[0261] According to an embodiment, the H-GCC code may be related to the GCC code corresponding to the RAU, as discussed above. For example, the H-GCC code may correspond to the L represented by the following equation 47: 2 GCC codeword w p (p∈[L 2 ]):

[0262]

[0263] GCC code can be dimension L 1 Polar Code With Dimension and F t =L 1 -K t RS code C t ∈RS(L 1 ,F t ) cascade.

[0264] The GCC cascade may be implemented as discussed above with respect to Equation 34, as shown below in Equation 48:

[0265] s t,i =P t ·c i ,i∈[L 1 ],t∈[M 1 ] (Formula 48)

[0266] With respect to the H-GCC code structure, this transform space may be referred to as an internal transform space.

[0267] To construct the second transformation space, which can be called the external transformation space, first, we can define the number D t ,t∈[M 1 ],0≤D t ≤L 1 -K t and corresponding transformation A list of As shown, for example, in Equation 21.

[0268] The external transformation space can be defined as t,q , as shown in Equation 49 and Equation 50, which can be equivalent to each other:

[0269]

[0270]

[0271] For each t, ​​the transformation can be defined according to the following equation 51:

[0272]

[0273] Fig.14 An example of an internal transformation space and an external transformation space according to an embodiment is shown. Fig.14 As shown in , the GCC code length can be N = L 1 n, and the cost is Where P L It may correspond to the local overhead of the RAU.

[0274] This can be done by replacing the L discussed above 2 The GCC codewords are concatenated with the RS code to define the next level of H-GCC.

[0275] The space symbol (t,q) (t∈[1,M 1 ],q∈[1,D t ]) with j RS codes j∈M 2 and A mapping j = M(t,q) is defined between them, so that the symbol S can be defined according to Formula 52 j , and can be based on S j The following equation 53 represents the corresponding transformation:

[0276]

[0277]

[0278] For each component code w p Apply the transformation. p The polar code of the constituent code can be expressed as Accordingly, the transformation space symbol can be defined according to equation 54, and the transformation can be defined according to the following equation 55:

[0279]

[0280]

[0281] By defining M 2 RS code W j ∈RS(L 2 ,Q j ) to perform RS code concatenation, where j∈[1,M 2 ]and is the RS code dimension, and Q j =L 2 -I J .

[0282] The RS code word W can be expressed according to equation 56 j , and the corresponding parity check matrix can be expressed according to the following equation 57

[0283]

[0284]

[0285] Through each component code w p The additional (global) cost of the allocation is 2 can be constant and can be equal to Thus we get dimension K = NP L -P G .

[0286] In an embodiment, L 2 The concatenation of GCC codes is used to represent Fig.13 The H-GCC code shown in is as shown in the following equation 58:

[0287]

[0288] By using the transformation of Eq. 33 and transforming p The polarization code is defined as w p , the corresponding transformation P can be obtained. The resulting transformation matrix can be defined as shown in Equation 59.

[0289]

[0290] Then, the code set of the S-RS decoder can be expressed according to the following equation 60:

[0291]

[0292] S-RS codeword W t Can include RS codewords The RS codeword Can be defined in symbols As shown in Equation 61 below:

[0293]

[0294] Fig.15 An example of the H-GCC code structure discussed above is shown. In an embodiment, the S-RS codeword W t Can include L 2 RS code and transformation Accordingly, the following transformation space expressed as Equation 62 can be formed:

[0295]

[0296] Fig.16 An example of the corresponding RS code is shown, where for p∈[L 2 ],q∈[D t ],t∈[M 1 ],j∈[M 2 ], Q t,q =Q M(t,q) =Q j .

[0297] The hierarchical codes discussed above can be linear codes with a parity check matrix. For example, an H-GCC codeword can be a concatenation of GCC constituent codes: The code composed of GCC can be a cascade of polar codes:

[0298] FIG. 17A to FIG. 21 It can be used to illustrate an example of an encoding process of an H-GCC code such as the encoding process discussed above. According to an embodiment, the H-GCC encoding process can use any of the above elements (e.g., the above with respect to Figure 2A The storage device 200 discussed above is relative to Figure 2B The ECC encoding circuit 510 or any other component discussed may be performed.

[0299] According to an embodiment, an H-GCC encoder corresponding to one or more of the H-GCC codes discussed above may receive a signal for L 2 K information bits for each RAU in the RAUs, and L 2 Each has a local parity check P that enables each RAU to decode separately Land can be used to jointly decode L 2 Additional global parity bit P for each RAU G Code word.

[0300] FIG. 17A to FIG. 18B The first example H-GCC encoding process is described. FIG. 19A to FIG. 20B , a first example H-GCC encoding process may be performed using a simple system encoder with linear constraints. In an embodiment, the first example H-GCC encoding process may involve Fig.14 The H-GCC code structure discussed.

[0301] In an embodiment, a basic encoder for performing the first example H-GCC encoding process may include L 2 In an embodiment, the basic encoder may correspond to the following Fig.17A and Fig. 17B The basic encoder discussed in 1713, and L 2 Each of the GCC encoders may correspond to the above FIG. 12A to FIG. 12C Discussion of the GCC coder.

[0302] The GCC code for this basic encoder may correspond to the code that can be used as w p The GCC codeword of the nested code is shown in the following equation 63:

[0303]

[0304] The information bit and the balance bit may be located at the information index γ, as shown above for the codeword w p As shown in Formula 46. In an embodiment, Formula 64 may be satisfied:

[0305] |γ|=NP L (Formula 64)

[0306] Next, you can define additional Balance the bit position so that |β p |=P G The information bit can be located at α p =γ\β p and |α p |=NP L -P G . β p The choice should be such that the transfer matrix T for H-GCC coding c is reversible. Fig.18A and Fig.18B Discussion of the transfer matrix T c .

[0307] The H-GCC constraint may specify that all words in the transform space parity check shall be 0. This constraint may be used to specify a constraint matrix P that may be used to perform encoding of the H-GCC codewords c and the constraint vector d w = 0. Fig.17A and Fig. 17B Discuss examples of this encoding.

[0308] The constraint matrix P can be formed as follows c Using the transformations defined in equations 54 and 55 above, the transformation space can be defined according to equation 65 below:

[0309]

[0310] The transformation space may include M which can be expressed as shown in the following equation 66: 2 RS code W j ∈RS(L 2 ,Q j )(j∈[1,M 2 ]).

[0311] To ensure that the word is an H-GCC codeword, W j All RS code words can satisfy the following formula 67:

[0312]

[0313] Alternatively, H can be used according to the above formula 19 F The total number of constraints can be expressed as follows:

[0314]

[0315] Using these constraints, we can Fig.18A and Fig.18B Discuss the generation of the transfer matrix T c .

[0316] Based on information bit α p and equilibrium position β p (p∈[L 2 ]), constraint matrix P c , transfer matrix T c and the basic encoder, the H-GCC encoding according to the first example can be as follows with respect to Fig.17A and Fig. 17B In an embodiment, the parameters of the first example H-GCC coding scheme can be expressed as shown in the following equations 69, 70 and 71, where k c represents the length of the input vector of the basic encoder, and nc Represents the length of the codeword of the basic encoder:

[0317] L c =L 2 ·P G (Formula 69)

[0318] k c =L 2 ·(K+P L ) (Formula 70)

[0319] n c =L 2 ·N (Formula 71)

[0320] Fig.17A 1 is a block diagram of an example of an encoder 1700A for encoding information bits according to a first example H-GCC encoding process to generate an output H-GCC codeword according to an embodiment. In an embodiment, the encoder 1700A may include a constraint transformation module 1711, a transfer matrix module 1712, a basic encoder 1713, and a constraint matrix module 1714.

[0321] The basic encoder 1713 may be a system encoder that may receive an input vector i and output a codeword c. The encoder 1700A may also include a constrained transformation module 1711 that may be used to find a transformation between the input of the basic encoder 1713 and the product vector d. The encoder 1700A may also include a transfer matrix module 1712 that may apply a transfer matrix that may transform the product vector d into a balanced bit b. In an embodiment, the basic encoder 1713 may receive a codeword that may have a length k. c The input vector i is taken as input, and the input vector i can be encoded according to the following formula 72 to output the codeword c.

[0322] c=ENC 0 (i) Formula 72

[0323] In an embodiment, ENC 0 (i) may correspond to a GCC encoder, for example, any of the GCC encoders discussed above. According to the H-GCC encoding scheme, the following L in the form of Equation 73 may be applied c A set of affine constraints, where

[0324] P c c = d w (Formula 73)

[0325] like Fig.17AAs shown in FIG. 1 , the constraint transformation module 1711 may receive an input vector i as input and may apply a linear constraint transformation to output a preliminary constraint vector d that may have a length L. * In an embodiment, the constraint transformation module 1711 may include a module that can encode the input vector i to obtain a preliminary codeword c i Then, the constraint transformation module 1711 can convert the preliminary codeword c i Multiply by the constraint matrix P c , to obtain the initial constraint vector d * .

[0326] To enforce the constraint, the input vector i can be expanded to include an additional L which can be a balancing bit denoted as b. c In addition, the input vector i used as input to the encoder 1700A may have a length k c and may include a length k c -L c The information bits in the information vector i′ may also include information bits having a length L c In an embodiment, the index set for the information bits in i may be referred to as a set α, such that i α = i′, and the set of indices for the balance bits in i can be called the set β, such that i β = b, and |α∩β| = 0. The set β positions in the index of i can be tailored to the specific problem, for example, to the specific code being used, and are not necessarily consecutive.

[0327] In an embodiment, the balance bit can be used to make the output codeword c out To determine the equilibrium position b and the preliminary constraint vector d * The relationship between them can be assembled into a transfer matrix T c . Transformation matrix T c Can be used to convert the standard basis {e 0 , e 1 , ..., e L-1}(where e k,k =1 and e k,j≠k =0) into a basis that can be used in encoder 1700A.

[0328] Fig. 17B 17 is a flow chart of a process 1700B for generating an output codeword using encoder 1700A according to an embodiment. Fig.17A and Fig. 17BIn operation 1721, the process 1700B may include placing the information vector i′ into the input vector i and setting the balancing bit b to zero. In operation 1722, the process 1700B may include encoding the input vector i using the basic encoder 1713 to obtain the preliminary codeword c i In operation 1723, process 1700B may include using constraint transformation module 1711 to calculate a preliminary constraint vector d i At operation 1724, process 1700B may include using transfer matrix module 1712 to calculate the initial constraint vector d i and the target constraint vector d w To calculate the balancing bit b. In operation 1725, the process 1700B may include updating the input vector i by placing the balancing bit b into the input vector i, and setting the information vector i′ to zero. In operation 1726, the process 1700B may include encoding the updated input vector i using the basic encoder 1713 to obtain the preliminary codeword c b In operation 1727, process 1700B may include obtaining a preliminary codeword c i With the preliminary codeword c b The sum of the two generates the output codeword c out In an embodiment, the output codeword c out May correspond to an H-GCC codeword.

[0329] Fig.18A The method for constructing the transfer matrix T according to the embodiment is shown. c An example of processing. Fig.18B is a method for constructing a Fig.18A The transfer matrix T c 1800B. Fig.18A As shown in FIG. 1 , for each j from j=0 to j=L-1, a different input vector i is input into the constraint transformation module 1711 to obtain a constraint vector Then the constraint vector is assembled into the transfer matrix T c middle.

[0330] For example, in operation 1821, process 1800 may include setting equal to the basis vector e j In operation 1822, the process 1800 may include placing the balancing bit b into the input vector i and setting the information vector i′ of the input vector i to 0. In operation 1823, the process 1800 may include using the constraint transformation module 1711 to calculate the constraint vector Then, at operation 1824, process 1800 may include placing the constraint vector into a matrix that can be used as a transposed transfer matrix. The transfer matrix T of the jth row c In the jth column of Fig.17A As shown in , the balancing bits b can be grouped and aligned on the right side of the input vector i, but the embodiment is not limited thereto. For example, in an embodiment, the balancing bits b can be interleaved at any position in the input vector i.

[0331] In an embodiment, the transfer matrix T may be used c Make any L with equilibrium position b c length vector. To achieve this, the transfer matrix T c It may be fully ranked. If the transfer matrix T c is not completely sorted, then the set β can change. b to d * The transformation is linear and can be expressed according to the following equation 74:

[0332] d * =T c b Formula 74

[0333] according to Fig.18A and Fig.18B Calculate the transfer matrix T c can be invertible. As a result, for any constraint vector The constraint vector can be found according to the following formula 75 The balance position

[0334]

[0335] FIG. 19A to FIG. 20C The second example H-GCC encoding process is described. FIG. 19A to FIG. 20C , the second example H-GCC encoding can be performed using a sequential encoder. In an embodiment, the second example H-GCC encoding process may involve the above Figure 15 to Figure 16 The H-GCC code structure discussed.

[0336] According to the second example H-GCC encoding process, the additional parity bit β can be calculated according to the following equations 76 and 77: p The choice imposes constraints:

[0337] |β p |=P G (Formula 76)

[0338]

[0339] These constraints may allow the second example H-GCC encoding process to be performed using a sequential encoder.

[0340] Codeword Can have local dimension k i and basic local cost nk i Additional global overhead bits can be added Can generate information bits, and the corresponding RS code overhead can be determined according to the above formula 35

[0341] Additional global overhead bits The corresponding additional overhead can be generated according to the following equation 78

[0342]

[0343] For the S-RS code, additional overhead Can be defined and As discussed above with respect to the S-RS code.

[0344] Additional global overhead bits The choice of can satisfy the following constraints. For example, the additional global overhead bit It may have a ladder structure according to the following formula 79:

[0345]

[0346] Additional global overhead bits The global parity check budget can be satisfied according to the following equation 80:

[0347]

[0348] The S-RS code can satisfy the following equations 81 and 82:

[0349]

[0350]

[0351] Equation 82 can be an equality between sets, which means that there can be order changes So that the following equation 83 is satisfied:

[0352]

[0353] The order change can also be achieved by changing the order of the S-RS rows. Make Applying formula 35, we get

[0354] Fig.19AAn example of overhead allocation for H-GCC codewords corresponding to the second example H-GCC encoding process according to an embodiment is shown. Fig.19A For t = 2, The S-RS codeword may have F t =3,D t =3 and In an embodiment, Fig.19A For t=M 2 The S-RS codeword can have F t =0. In the embodiment, Fig.19A The code structure shown in may correspond to Fig.15 The code structure.

[0355] For S-RS code t, the GCC system encoder can be applied, as described above for FIG. 12A to FIG. 12C In the embodiment, the order is changed t (p) may be applied first to the S-RS row. The order change followed by GCC encoding and the reverse order change may be represented by "S-RS Encoder()".

[0356] Fig.19B An example of a row order change that may be performed on an S-RS codeword in order to use the S-RS codeword in a sequential H-GCC encoder according to an embodiment is shown. Specifically, Fig.19B shows the row order before and after the change Fig.19A For t=2, the S-RS codeword in Fig.19B As can be seen in , the S-RS codeword for t=2 may have a staircase structure after the row order is changed, and thus may be suitable for a sequential H-GCC encoder.

[0357] Figures 20A to 20C Referring to the second example H-GCC encoding process discussed above. According to an embodiment, the second example H-GCC encoding process may use any of the above elements (e.g., Figure 2A The storage device 200 discussed above Figure 2B This may be performed by a sequential encoder included in the ECC encoding circuit 510 or any other element discussed.

[0358] Fig. 20A An example of a sequential encoding algorithm that can be used to perform H-GCC encoding is shown, presented in pseudo code as Algorithm 2. The sequential H-GCC encoder algorithm may include cross-activation of a coset polar code encoder and an S-RS encoder. In an embodiment, the coset polar code encoder may be represented as "polar encoder()" in Algorithm 2. In an embodiment, the coset polar code encoder may correspond to Equation 44 discussed above.

[0359] Fig. 20B An example encoding sequence that may correspond to the sequential H-GCC encoder algorithm discussed above is shown. Fig. 20B As shown in FIG. 2 , in operation 21A, a polar code encoder may be used to determine i 1 =[1],i 2 =[1],i 3 =[1,2], the local overhead bits of the polar codeword. In operation 21B, the transformation may be used to determine i 1 =[1],i 2 =[1],i 3 =[1,2], the transformation space of the polar codeword. In operation 2021C, an S-RS encoder may be used to determine the overhead parity bits of the S-RS codeword at t=1.

[0360] like Fig. 20B As further shown in FIG. 20, in operation 2022A, a polar code encoder may be used to determine i 1 =[2,3,4],i 2 =[2],i 3 = [3], the local overhead bits of the polar codeword. In operation 2022B, the transformation may be used to determine i 1 =[2,3,4],i 2 =[2],i 3 =[3], the transformation space of the polar codeword. In operation 2022C, an S-RS encoder may be used to determine the overhead parity bits of the S-RS codeword at t=2.

[0361] like Fig. 20B As further shown in FIG. 20, in operation 2023A, a polar code encoder may be used to determine i 1 =[5],i 2 =[3,4,5,6],i 3 = [4.5], the local overhead bits of the polar codeword. In operation 2023B, the transformation may be used to determine i 1 =[5],i 2 =[3,4,5,6],i 3 =[4,5], the transformation space of the polar codeword. In operation 2023C, an S-RS encoder may be used to determine the overhead parity bits of the S-RS codeword at t=3.

[0362] like Fig. 20B As further shown in FIG. 20, in operation 2024A, a polar code encoder may be used to determine i 1 =[6],i 2 =[7],i 3= []. In operation 2024B, the transformation may be used to determine i 1 =[6],i 2 =[7],i 3 =[ ] Transformation space of polar codewords. In operation 2024C, an S-RS encoder may be used to determine overhead parity bits of the S-RS codewords at t=4.

[0363] like Fig. 20B As further shown in FIG. 20, in operation 2025A, a polar code encoder may be used to determine i 1 =[7],i 2 =[],i 3 =[6,7,8], local overhead bits of the polar codeword. In operation 2025B, the transformation may be used to determine i 1 =[7],i 2 =[],i 3 =[6,7,8], the transformation space of the polar codeword. In operation 2025C, an S-RS encoder may be used to determine the overhead parity bits of the S-RS codeword at t=5.

[0364] like Fig. 20B As further shown in FIG. 20, in operation 2026A, a polar code encoder may be used to determine i 1 =[8],i 2 =[8],i 3 = [] when the local overhead bits of the polar codeword.

[0365] According to an embodiment, operations 2021A, 2022A, 2023A, 2024A, 2025A and 2026A may correspond to "step a" of Algorithm 2, operations 2021B, 2022B, 2023B, 2024B and 2025B may correspond to "step b" of Algorithm 2, and operations 2021C, 2022C, 2023C and 2024C may correspond to "step c" of Algorithm 2.

[0366] Fig. 20C is a flowchart of the encoding process according to the embodiment. Fig. 20CThe process 2000C shown in may correspond to some or all of Algorithm 2 discussed above. For example, in operation 2031, the process 2000C may include encoding the next polar codeword of the current frame. In operation 2032, the process 2000C may include updating the transform space corresponding to the encoded polar codeword. In operation 2033, the process 2000C may include determining whether the last frame has been reached. Based on determining that the last frame has not been reached ("No" in operation 2033), the process 2000C may set the next frame as the current frame and may return to operation 2031. Based on determining that the last frame has been reached ("Yes" in operation 2033), the process 2000C may proceed to operation 2034.

[0367] In operation 2034, the process 2000C may include determining whether the last polarization codeword of each frame has been reached. Based on determining that the last polarization codeword has been reached ("yes" in operation 2034), the process 2000C may proceed to operation 2035 and output the H-GCC codeword. Based on determining that the last polarization codeword has not been reached ("no" in operation 2034), the process 2000C may proceed to operation 2036, which may include determining whether the next polarization codeword has the same degree as the polarization codeword encoded in operation 2031. Based on determining that the next polarization codeword does have the same degree ("yes" in operation 2036), the process 2000C may return to operation 2031. Based on determining that the next polarization codeword does not have the same degree ("no" in operation 2036), the process 2000C may proceed to operation 2037.

[0368] In operation 2037, the process 2000C may include encoding the next S-RS codeword. In operation 2038, the process 2000C may include determining whether the last S-RS codeword has been reached. Based on the determination that the last S-RS codeword has been reached ("yes" in operation 2038), the process 2000C may proceed to operation 2039, which may include updating the polarization codeword based on the encoding result of the S-RS codeword, and then returning to step 2031. Based on the determination that the last S-RS codeword has not been reached, the process 2000C may proceed to operation 2040, which may include determining whether the next RS codeword has the same degree. Based on the determination that the next S-RS codeword does have the same degree ("yes" in operation 2039), the process 2000C may return to operation 2037. Based on the determination that the next S-RS codeword does not have the same degree ("no" in operation 2039), the process 2000C may proceed to operation 2040.

[0369] According to an embodiment, the H-GCC encoding process discussed above may use any of the elements described herein (e.g., Figure 2A The storage device 200 discussed above Figure 2B The ECC encoding circuit 510 or any other component discussed may be performed.

[0370] According to an embodiment, the H-GCC code may be alternatively defined with a polariton code as a constituent code, or with a BCH code as a constituent code, and different systematic encoders may be used.

[0371] Fig.21 is a flow chart of a process 2100 for controlling a storage device according to an embodiment. In some implementations, Fig.21 One or more processing blocks of may be performed by any one or more of the encoders discussed above.

[0372] like Fig.21 As shown in , in operation 2101, process 2100 may include obtaining information bits.

[0373] like Fig.21 As further shown in FIG. 21 , at operation 2102 , process 2100 may include encoding information bits using an inner code to obtain a plurality of inner codewords.

[0374] like Fig.21 As further shown in FIG. 21 , in operation 2103 , process 2100 may include encoding the plurality of inner codewords using an outer code to generate an outer codeword.

[0375] In an embodiment, at least one of the inner code and the outer code may include a generalized concatenated code (GCC), and the outer codeword may include a hierarchical GCC (H-GCC) codeword.

[0376] like Fig.21 As further shown in FIG. 21 , at operation 2104 , process 2100 may include storing the external codeword in a storage device.

[0377] In an embodiment, the H-GCC codeword may include multiple frames, each frame of the multiple frames has the same length, each frame of the multiple frames may include the same number of local parity bits generated based on the inner code, and each frame of the multiple frames may include the same number of global parity bits generated based on the outer code.

[0378] In an embodiment, each frame of the plurality of frames may be stored in a random access unit (RAU) included in the storage device.

[0379] In an embodiment, the inner code may include a GCC, the constituent codes of the inner code include a polar code and a first Reed-Solomon (RS) code, and the outer code may include a second RS code. In an embodiment, the H-GCC code structure may correspond to the above-discussed Fig.13 and Fig.14 .

[0380] In an embodiment, the inner code may include a polar code, the outer code may include a GCC, and the constituent codes of the outer code include a first Reed-Solomon (RS) code and a second RS code. In an embodiment, the H-GCC code structure may correspond to the above-discussed Fig.15 .

[0381] In an embodiment, the outer codeword may include multiple frames, and the encoding of the information bits may include: applying a polarization code to the information bits to generate local parity bits; and placing the local parity bits into multiple inner codewords, and the encoding of the multiple inner codewords may include: applying a first transformation to the multiple inner codewords to generate multiple symbol sets in a transformation space, wherein each symbol set in the multiple symbol sets corresponds to an inner codeword among the multiple inner codewords; combining the multiple symbol sets into an outer codeword; applying a first RS code and a second RS code to the outer codeword to generate a global parity bit; and placing the global parity bit into the multiple inner codewords to generate an H-GCC codeword. In an embodiment, the H-GCC encoding process may correspond to the above-discussed FIG. 19A to FIG. 20C .

[0382] In an embodiment, the plurality of inner codewords may include a first inner codeword and a second inner codeword, the plurality of symbol sets may include a first symbol set generated based on the first inner codeword, the first symbol set may be used to generate at least one first global parity check bit among the global parity check bits, and the at least one first global parity check bit may be used to apply a polar code to the second inner codeword. In an embodiment, the H-GCC code structure may correspond to the above-discussed FIG. 20A to FIG. 20C .

[0383] In an embodiment, the first set of symbols may be reordered before the first RS code and the second RS code are applied. In an embodiment, the reordering may correspond to the above discussion. Fig.19B .

[0384] although Fig.21 Example blocks of process 2100 are shown, but in some implementations, process 2100 may include Fig.21Additional boxes, fewer boxes, different boxes, or boxes arranged differently than the boxes depicted in the process 2100. Additionally or alternatively, two or more of the boxes in the process 2100 may be arranged and combined in any order, or performed in parallel.

[0385] Accordingly, embodiments may relate to a family of H-GCC hierarchical codes that may be represented as a concatenation of a GCC constituent code and an RS code. The H-GCC code may correspond to L 2 GCC codewords and transformation j∈[M 2 ],t∈[M 1 ],d t ∈[D t ] and parameters and the mapping M(t,d t ) and RS code W j ∈RS(L 2 ,Q j ),j∈[M 2 In an embodiment, the H-GCC code may have a length of L 2 N and dimension L 2 ·K. H-GCC code can include L 2 The average length N = L 1 n. Local expenses and additional global overhead The composition code w p .

[0386] The equivalent construction of H-GCC code can be compared with the set of S-RS code words t∈[M 1 ] is related. The parity check matrix of the code can be expressed according to the following equation 84:

[0387]

[0388] Embodiments can also be used with GCC code Each of these uses the GCC sequential encoder to generate P L The local parity check bits are related to the system encoder. In order to satisfy the global constraint, the balance bit position β is selected p , and generate the constraint generator matrix T c .

[0389] Embodiments may also relate to a systematic sequential encoder including cross-activation of a polar code coset encoder and an S-RS encoder. The S-RS encoder may use an order change on the RS rows in order to enable the sequential encoder.

[0390] Fig. 22 FIG. 3 is a diagram of a data center 3000 to which a storage device is applied according to an embodiment.

[0391] Reference Fig. 22 , the data center 3000 may be a facility that collects various types of data and provides services, and is referred to as a data storage center. The data center 3000 may be a system for operating a search engine and a database, and may be a computing system used by a company (such as a bank) or a government agency. The data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. According to an embodiment, the number of applications 3100 to 3100n and the number of storage servers 3200 to 3200m may be selected differently. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be different from each other.

[0392] The application server 3100 or the storage server 3200 may include at least one of the processors 3110 and 3210 and the memories 3120 and 3220. Now, the storage server 3200 will be described as an example. The processor 3210 may control all operations of the storage server 3200, access the memory 3220, and execute instructions and / or data loaded into the memory 3220. The memory 3220 may be a double data rate synchronous DRAM (DDR SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, or a non-volatile DIMM (NVMDIMM). In some embodiments, the number of processors 3210 and memories 3220 included in the storage server 3200 may be selected differently. In an embodiment, the processor 3210 and the memory 3220 may provide a processor-memory pair. In an embodiment, the number of processors 3210 and the number of memories 3220 may be different from each other. The processor 3210 may include a single-core processor or a multi-core processor. The above description of the storage server 3200 may be similarly applied to the application server 3100. In some embodiments, the application server 3100 may not include the storage device 3150. The storage server 3200 may include at least one storage device 3250. According to embodiments, the number of storage devices 3250 included in the storage server 3200 may be variously selected.

[0393] The application servers 3100 to 3100n can communicate with the storage servers 3200 to 3200m through the network 3300. The network 3300 can be implemented by using a fiber channel (FC) or Ethernet. In this case, FC can be a medium for relatively high-speed data transmission, and an optical switch with high performance and high availability can be used. According to the access method of the network 3300, the storage servers 3200 to 3200m can be set to file storage, block storage, or object storage.

[0394] In an embodiment, the network 3300 may be a network dedicated to storage, such as a storage area network (SAN). For example, the SAN may be an FC-SAN, which uses an FC network and is implemented according to the FC protocol (FCP). As another example, the SAN may be an Internet Protocol (IP)-SAN, which uses a transmission control protocol (TCP) / IP network and is implemented according to a SCSI or Internet SCSI (iSCSI) protocol over TCP / IP. In another embodiment, the network 3300 may be a general network, such as a TCP / IP network. For example, the network 3300 may be implemented according to protocols such as FC over Ethernet (FCoE), network attached storage (NAS), and NVMe over fabric (NVMe-oF).

[0395] Hereinafter, the application server 3100 and the storage server 3200 will be mainly described. The description of the application server 3100 may be applied to another application server 3100n, and the description of the storage server 3200 may be applied to another storage server 3200m.

[0396] The application server 3100 may store data requested to be stored by a user or client in one of the storage servers 3200 to 3200m through the network 3300. In addition, the application server 3100 may obtain data requested to be read by a user or client from one of the storage servers 3200 to 3200m through the network 3300. For example, the application server 3100 may be implemented as a network server or a database management system (DBMS).

[0397] The application server 3100 may access a memory 3120n or a storage device 3150n included in another application server 3100n through the network 3300. Alternatively, the application server 3100 may access a memory 3220 to 3220m or a storage device 3250 to 3250m included in the storage servers 3200 to 3200m through the network 3300. Therefore, the application server 3100 may perform various operations on the data stored in the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. For example, the application server 3100 may execute an instruction for moving or copying data between the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. In this case, data may be moved from the storage devices 3250 to 3250m of the storage servers 3200 to 3200m through the storage 3220 to 3220m of the storage servers 3200 to 3200m or directly to the storage 3120 to 3120n of the application servers 3100 to 3100n. The data moved through the network 3300 may be data encrypted for security or privacy.

[0398] The storage server 3200 will now be described as an example. The interface 3254 can provide a physical connection between the processor 3210 and the controller 3251 and a physical connection between the network interface card (NIC) 3240 and the controller 3251. For example, the interface 3254 can be implemented using a direct attached storage (DAS) solution, where the storage device 3250 is directly connected to a dedicated cable. For example, the interface 3254 can be implemented using various interface solutions, such as ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, USB interface, SD card interface, MMC interface, eMMC interface, UFS interface, eUFS interface, and CF card interface.

[0399] The storage server 3200 may further include a switch 3230 and a network interconnect (NIC) 3240. The switch 3230 may selectively connect the processor 3210 to the storage device 3250 or selectively connect the NIC 3240 to the storage device 3250 via the control of the processor 3210.

[0400] In an embodiment, the NIC 3240 may include a network interface card and a network adapter. The NIC 3240 may be connected to the network 3300 through a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. The NIC 3240 may include an internal memory, a digital signal processor (DSP), and a host bus interface, and is connected to the processor 3210 and / or the switch 3230 through the host bus interface. The host bus interface may be implemented as one of the above examples of the interface 3254. In an embodiment, the NIC 3240 may be integrated with at least one of the processor 3210, the switch 3230, and the storage device 3250.

[0401] In the storage servers 3200 to 3200m or the application servers 3100 to 3100n, the processor may send a command to the storage devices 3150 to 3150n and 3250 to 3250m or the memories 3120 to 3120n and 3220 to 3220m and program or read data. In this case, the data may be data in which an error is corrected by an ECC engine. The data may be data on which a data bus inversion (DBI) operation or a data masking (DM) operation is performed, and may include cyclic redundancy coding (CRC) information. The data may be data encrypted for security or privacy.

[0402] The storage devices 3150 to 3150n and 3250 to 3250m may send control signals and command / address signals to the NAND flash memory devices 3252 to 3252m in response to a read command received from the processor. Therefore, when data is read from the NAND flash memory devices 3252 to 3252m, a read enable (RE) signal may be input as a data output control signal, and thus, the data may be output to the DQ bus. The data strobe signal DQS may be generated using the RE signal. Depending on the rising edge or falling edge of the write enable (WE) signal, the command and address signals may be latched in the page buffer.

[0403] The controller 3251 may control all operations of the storage device 3250. In an embodiment, the controller 3251 may include an SRAM. The controller 3251 may write data to the NAND flash memory device 3252 in response to a write command, or read data from the NAND flash memory device 3252 in response to a read command. For example, a write command and / or a read command may be provided from a processor 3210 of the storage server 3200, a processor 3210m of another storage server 3200m, or processors 3110 and 3110n of application servers 3100 and 3100n. The DRAM 3253 may temporarily store (or buffer) data to be written to the NAND flash memory device 3252 or data read from the NAND flash memory device 3252. And, the DRAM 3253 may store metadata. Here, the metadata may be user data or data generated by the controller 3251 for managing the NAND flash memory device 3252. The storage device 3250 may include a secure element (SE) for security or privacy.

[0404] As is traditional in the field, embodiments are described and illustrated in the accompanying drawings according to functional blocks, units and / or modules. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, storage elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. Alternatively, each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and a processor that performs other functions (e.g., one or more programmed microprocessors and associated circuits). In addition, without departing from the scope, each block, unit and / or module of the embodiment can be physically divided into two or more discrete blocks, units and / or modules that interact with each other. Additionally, the blocks, units and / or modules of the embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope.

[0405] The various operations of the above-described methods may be performed by any suitable means capable of performing the operations, such as various hardware and / or software components, circuits and / or modules.

[0406] The software may include an ordered listing of executable instructions for implementing logical functions and may be implemented in any "processor readable medium" for use by or in conjunction with an instruction execution system, device or apparatus such as a single-core or multi-core processor or a system containing a processor.

[0407] The blocks or steps of the methods or algorithms and functions described in conjunction with the embodiments disclosed herein may be implemented directly in hardware, in a software module executed by a processor, or in a combination of the two. If implemented in software, the functions may be stored as one or more instructions or codes on a tangible, non-transitory computer-readable medium. The software module may reside in a random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD ROMs, or any other form of storage medium known in the art.

[0408] The foregoing illustrates example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the embodiments without materially departing from the scope thereof.

Claims

1. A storage system, comprising: A storage device, the storage device being configured to store a plurality of codewords; as well as at least one processor, the at least one processor being configured to: Get information bits; Encoding the information bits using an inner code to obtain a plurality of inner code words; encoding the plurality of inner codewords using an outer code to generate an outer codeword; as well as storing the external codeword in the storage device, wherein at least one of the inner code and the outer code comprises a GCC, i.e., a generalized concatenated code, and The external codeword includes an H-GCC codeword, which is a hierarchical GCC codeword.

2. The storage system according to claim 1, wherein: The H-GCC codeword includes a plurality of frames, wherein each of the plurality of frames has the same length, wherein each of the plurality of frames comprises a same number of local parity bits generated based on the inner code, and Each of the plurality of frames includes a same number of global parity bits generated based on the outer code.

3. The storage system according to claim 2, wherein: Each frame of the plurality of frames is stored in a corresponding random access unit included in the storage device.

4. The storage system according to claim 1, wherein: The internal code includes the GCC, The constituent codes of the inner code include a polar code and a first RS code, the RS code is a Reed-Solomon code, and Wherein, the external code includes a second RS code.

5. The storage system according to claim 1, wherein: The inner code includes a polar code, wherein the external code includes the GCC, and The constituent codes of the external code include a first RS code and a second RS code.

6. The storage system according to claim 5, wherein: The outer codeword includes a plurality of frames, The at least one processor is further configured to perform the following operations to encode the information bits: applying the polar code to the information bits to generate local parity bits; and placing the local parity bits into the plurality of inner codewords, and The at least one processor is further configured to perform the following operations to encode the multiple internal codewords: applying a first transform to the plurality of inner codewords to generate a plurality of sets of symbols in a transform space, wherein each set of symbols in the plurality of sets of symbols corresponds to an inner codeword in the plurality of inner codewords; combining the plurality of sets of symbols into the outer codeword; applying the first RS code and the second RS code to the outer codeword to generate a global parity bit; and The global parity bits are placed into the plurality of inner codewords to generate the H-GCC codewords.

7. The storage system according to claim 6, wherein: The plurality of inner codewords include a first inner codeword and a second inner codeword, The multiple symbol sets include a first symbol set generated based on the first internal codeword, wherein the first symbol set is used to generate at least one first global parity bit among the global parity bits, and The at least one first global parity bit is used to apply the polar code to the second inner codeword.

8. The storage system according to claim 6, wherein: The plurality of sets of symbols are changed in order before the first RS code and the second RS code are applied.

9. An apparatus for encoding information bits for storage in a storage device, the apparatus comprising: a memory interface configured to communicate with the memory device; as well as at least one processor, the at least one processor being configured to: Get information bits; Encoding the information bit using a polar code to obtain a plurality of polar code words; Encoding the multiple polar codewords using GCC to obtain an H-GCC codeword, wherein constituent codes of the GCC include a first RS code and a second RS code, the GCC is a generalized concatenated code, the H-GCC codeword is a hierarchical GCC codeword, and the RS code is a Reed-Solomon code; as well as The memory interface is controlled to transmit the H-GCC codeword to the storage device.

10. The device according to claim 9, wherein: The H-GCC codeword includes a plurality of frames, wherein each of the plurality of frames has the same length, Each of the plurality of frames comprises a same number of local parity bits generated based on the polar code, and Each of the multiple frames includes a same number of global parity bits generated based on the GCC.

11. The device according to claim 10, wherein: Each frame of the plurality of frames is stored in a corresponding random access unit included in the storage device.

12. The device according to claim 9, wherein: The H-GCC codeword includes a plurality of frames, The at least one processor is further configured to perform the following operations to encode the information bits: applying the polar code to the information bits to generate local parity bits; and placing the local parity bits into the plurality of polar codewords, and The at least one processor is further configured to perform the following operations to encode the multiple polar codewords: applying a transform to the plurality of polarization codewords to generate a plurality of sets of symbols in a transform space, wherein each set of symbols in the plurality of sets of symbols corresponds to a polarization codeword in the plurality of polarization codewords; combining the plurality of symbol sets; applying the first RS code and the second RS code to the combined plurality of symbol sets to generate global parity bits; and The global parity check bits are placed into the multiple polar codewords to generate the H-GCC codeword.

13. The device according to claim 12, wherein: The multiple polarization codewords include a first polarization codeword and a second polarization codeword, The multiple symbol sets include a first symbol set generated based on the first polarization codeword, wherein the first symbol set is used to generate at least one first global parity bit among the global parity bits, and The at least one first global parity bit is used to apply the polar code to the second polar codeword.

14. The device according to claim 12, wherein: The plurality of sets of symbols are changed in order before the first RS code and the second RS code are applied.

15. A method for controlling a storage system, the method being executed by at least one processor and comprising the following operations: Get information bits; Encoding the information bits using an inner code to obtain a plurality of inner code words; encoding the plurality of inner codewords using an outer code to generate an outer codeword; as well as storing the external codeword in a storage device, wherein at least one of the inner code and the outer code comprises a GCC, i.e., a generalized concatenated code, and The external codeword includes an H-GCC codeword, which is a hierarchical GCC codeword.

16. The method according to claim 15, wherein: The H-GCC codeword includes a plurality of frames, wherein each of the plurality of frames has the same length, wherein each of the plurality of frames comprises a same number of local parity bits generated based on the inner code, and Each of the plurality of frames includes a same number of global parity bits generated based on the outer code.

17. The method according to claim 16, wherein: Each frame of the plurality of frames is stored in a corresponding random access unit included in the storage device.

18. The method according to claim 16, wherein: The internal code includes the GCC, The constituent codes of the inner code include a polar code and a first RS code, the RS code is a Reed-Solomon code, and Wherein, the external code includes a second RS code.

19. The method according to claim 15, wherein: The inner code includes a polar code, wherein the external code includes the GCC, and The constituent codes of the external code include a first RS code and a second RS code.

20. The method according to claim 19, wherein: The outer codeword includes a plurality of frames, and The encoding of the information bit includes: applying the polar code to the information bits to generate local parity bits; and placing the local parity bits into the plurality of inner codewords, and wherein encoding the plurality of inner codewords comprises: applying a first transform to the plurality of inner codewords to generate a plurality of sets of symbols in a transform space, wherein each set of symbols in the plurality of sets of symbols corresponds to an inner codeword in the plurality of inner codewords; combining the plurality of sets of symbols into the outer codeword; applying the first RS code and the second RS code to the outer codeword to generate a global parity bit; and The global parity bits are placed into the plurality of inner codewords to generate the H-GCC codewords.

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