AXI Protocol-Based Bus Timeout Monitoring Method, Device and System

Abstract

Embodiments of the present application disclose a bus timeout monitoring method, device, and system based on the AXI protocol, which are applied to a bus timeout monitoring system including at least one AXI master and at least one AXI slave. A plurality of communication channels sharing a watchdog counter are provided between the AXI master and the AXI slave. The method includes: initiating an access request to a target AXI slave through a target communication channel, and recording request information associated with the access request in a register array in the target communication channel; obtaining a timeout time point corresponding to the access request; if, when the value of the watchdog counter reaches the timeout time point, no response information from the target AXI slave is received, determining that the access request has timed out; triggering an interrupt, and reporting the request timeout according to the information recorded in the register array. The technical solution of the embodiments of the present application can address the timeout problem in AXI transmission and ensure the accuracy and real-time nature of timeout detection.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular, to a bus timeout monitoring method, device, and system based on the AXI (Advanced eXtensible Interface) protocol. Background Art

[0002] The AMBA (Advanced Microcontroller Bus Architecture) bus protocol is a high-performance, highly compatible, and highly extensible on-chip interconnection protocol for chips, including APB (Advanced Peripheral Bus), AHB (Advanced High-performance Bus), AXI (Advanced eXtensible Interface), ACE (AXI Coherency Extensions), CHI (Coherent Hub Interface), etc., and is widely used in the design of various types of SoC (System on Chip) chips.

[0003] Currently, the AXI protocol supports the following features: Out-of-order transmission, Outstanding transmission, and Interleaving transmission.

[0004] In a complex SoC, the AXI host and slave are connected through an interconnect matrix. As the chip scale expands and the chip core frequency increases, the matrix from the host to the slave becomes more complex and flexible. However, the robustness of the AXI protocol itself is not sufficient to meet all complex scenarios. Therefore, when the AXI host and slave interact, there may be a transaction stuck or no response for a long time, resulting in abnormal bus transmission. Summary of the Invention

[0005] To solve the above technical problems, embodiments of this application provide a bus timeout monitoring method, device, system, electronic device, storage medium, and program product based on the AXI protocol.

[0006] Other features and advantages of this application will become apparent through the following detailed description, or be learned in part through the practice of this application.

[0007] In a first aspect, a bus timeout monitoring method based on the AXI protocol is provided, which is applied to a bus timeout monitoring system. The bus timeout monitoring system includes at least one AXI master and at least one AXI slave. A plurality of communication channels are provided between the AXI master and the AXI slave, and the plurality of communication channels share a watchdog counter. The method is executed by the AXI master and includes: initiating an access request to a target AXI slave through a target communication channel, and recording request information associated with the access request into a register array in the target communication channel; obtaining a timeout time point corresponding to the access request; if the response information of the target AXI slave is not received when the value of the watchdog counter reaches the timeout time point, determining that the access request times out; triggering an interrupt, and reporting the request timeout according to the information recorded in the register array.

[0008] In an embodiment of the present application, based on the foregoing solution, after initiating the access request to the target AXI slave through the target communication channel, the method further includes: obtaining a timeout threshold corresponding to the access request, and obtaining the timeout time point according to the initiation time of the access request and the timeout threshold; recording the timeout time point into a timeout register corresponding to the register array; and turning on a comparator corresponding to the timeout register, where the comparator is used to determine whether the value of the watchdog counter reaches the timeout time point.

[0009] In an embodiment of the present application, based on the foregoing solution, the obtaining the timeout threshold corresponding to the access request includes: obtaining an initial time threshold for the target AXI slave; obtaining the access type of the access request, and adjusting the initial time threshold according to the access type to obtain the timeout threshold corresponding to the access request.

[0010] In an embodiment of the present application, based on the foregoing solution, the number of the access requests includes a plurality, and one access request corresponds to one register array and one comparator; the method further includes: if the response information of the target AXI slave is received before the value of the watchdog counter reaches the timeout time point, searching for a target register array from a plurality of register arrays according to the response information, and searching for a target comparator from a plurality of comparators; clearing the information recorded in the target register array, and stopping the target comparator.

[0011] In one embodiment of the present application, based on the foregoing solution, the information recorded in the register array includes an access ID; the finding of the target register array from multiple register arrays and the finding of the target comparator from multiple comparators according to the response information include: extracting a response ID from the response information; retrieving the access ID recorded in each register array according to the response ID to obtain a target access ID that matches the response ID; using the register array that records the target access ID as the target register array, and determining the target comparator corresponding to the target register.

[0012] In one embodiment of the present application, based on the foregoing solution, the reporting of request timeout according to the information recorded in the register array includes: reading the request information from the register array; determining the access type of the access request according to the type of the register array, and generating the timeout information for reporting according to the request information and the access type of the access request.

[0013] In one embodiment of the present application, based on the foregoing solution, the bus timeout monitoring protocol system includes at least two AXI masters and at least two AXI slaves; before recording the request information corresponding to the access request into the register array in the target communication channel, it further includes: obtaining the slave address of the target AXI slave; obtaining the master number and the unique master identifier of the AXI master itself, and splicing the master number and the unique master identifier to obtain master information; generating the request information according to the master information and the slave address.

[0014] In a second aspect, a bus timeout monitoring device based on the AXI protocol is provided, which is applied to a bus timeout monitoring system. The bus timeout monitoring system includes at least one AXI master and at least one AXI slave, and multiple communication channels are arranged between the AXI master and the AXI slave. The multiple communication channels share a watchdog counter. The device is deployed on the AXI master and includes: a sending module configured to initiate an access request to a target AXI slave through a target communication channel and record the request information associated with the access request into the register array in the target communication channel; an obtaining module configured to obtain the timeout time point corresponding to the access request; a monitoring module configured to determine that the access request times out if the response information from the target AXI slave is not received when the value of the watchdog counter reaches the timeout time point; and a reporting module configured to trigger an interrupt and report the request timeout according to the information recorded in the register array.

[0015] In a third aspect, a bus timeout monitoring system includes at least one AXI master and at least one AXI slave. A plurality of communication channels are provided between the AXI master and the AXI slave. The plurality of communication channels share a watchdog counter for counting. A plurality of register arrays for recording information are provided in the communication channels. The AXI master is configured to execute the bus timeout monitoring method based on the AXI protocol as described in any one of the above.

[0016] In an embodiment of the present application, based on the foregoing solution, the system further includes an interrupt controller for generating an interrupt based on a trigger of the AXI master. A plurality of comparators respectively corresponding to the plurality of register arrays are further provided in the communication channels. The comparators are used to determine whether the value of the watchdog counter reaches the timeout time point.

[0017] In a fourth aspect, an electronic device is provided, including: one or more processors; a storage device for storing one or more programs, which, when executed by the one or more processors, cause the electronic device to implement the bus timeout monitoring method based on the AXI protocol as described in any one of the above.

[0018] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor of an electronic device, the electronic device is caused to execute the bus timeout monitoring method based on the AXI protocol as described above.

[0019] In a sixth aspect, an embodiment of the present application provides a computer program product, including a computer program. The computer program is stored in a computer-readable storage medium, and a processor of an electronic device reads and executes the computer program from the computer-readable storage medium, causing the electronic device to execute the bus timeout monitoring method based on the AXI protocol as described above.

[0020] In the technical solution provided by the embodiment of the present application, in order to address the timeout problem in AXI transmission, a design scheme of sharing a watchdog counter is proposed, allowing multiple communication channels between AXI masters and slaves to share a watchdog counter, thereby significantly reducing the power consumption and hardware area occupation of the system. When the master initiates an access request, relevant request information will be recorded in the register array, and by detecting whether the watchdog counter reaches the timeout time point of the access request, it is determined whether the response information from the slave is received, ensuring the accuracy and real-time nature of timeout detection.

[0021] When a timeout occurs, the interrupt mechanism will be automatically triggered, and the information recorded in the register array will be reported, enabling the chip to quickly locate the problem, ensuring that the AXI bus can still operate stably in high-performance and high-concurrency complex scenarios, effectively handling timeout problems, avoiding data loss or system suspension caused by transmission delays or device abnormalities, and further improving the robustness and processing efficiency of the bus.

[0022] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and do not limit this application. Brief Description of the Drawings

[0023] The drawings herein are incorporated into the specification and form a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application. Obviously, the drawings in the following description are only some embodiments of this application, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0024] Figure 1 It is a schematic diagram of an implementation environment related to this application.

[0025] Figure 2 It is a flowchart of the steps of a bus timeout monitoring method based on the AXI protocol shown in an exemplary embodiment of this application.

[0026] Figure 3 It is another exemplary embodiment of this application showing Figure 2 A flowchart of the steps of adding a record of the timeout time point based on the above.

[0027] Figure 4 It is another exemplary embodiment of this application showing Figure 2 A flowchart of the process of adding a record clearing process based on the above.

[0028] Figure 5 It is another exemplary embodiment of this application showing Figure 2 A flowchart of step S240 in an exemplary embodiment in

[0029] Figure 6 It is a schematic structural diagram of the timeout monitoring of the AXI host and slave shown in an exemplary embodiment of this application.

[0030] Figure 7 It is a structural block diagram of a bus timeout monitoring device based on the AXI protocol shown in an exemplary embodiment of this application.

[0031] Figure 8 It shows a schematic structural diagram of a computer system of an electronic device suitable for implementing the embodiments of this application. Detailed Implementation Modes

[0032] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation modes described in the following exemplary embodiments do not represent all implementation modes consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0033] The block diagrams shown in the drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0034] The flowcharts shown in the drawings are merely exemplary illustrations and do not necessarily include all contents and operations, nor do they necessarily need to be executed in the described order. For example, some operations can be decomposed, while some operations can be combined or partially combined, so the actual execution order may change according to the actual situation.

[0035] Next, with reference to the drawings and embodiments, the present application will be further described in detail. It should be specifically noted that the following embodiments are only used to illustrate the present application, but do not limit the scope of the present application. Similarly, the following embodiments are only partial embodiments of the present application rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0036] In the description, claims, and above-mentioned drawings of the present application, terms such as "first" and "second" are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein, for example, can be implemented in an order other than those illustrated or described herein. In addition, in the embodiments shown in the drawings, the indication of directions (such as up, down, left, right, front, and back) is used to explain that the structures and movements of various elements of the present application are not absolute but relative. When these elements are in the positions shown in the drawings, these explanations are appropriate. If the description of the positions of these elements changes, then the indication of these directions also changes accordingly. Additionally, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these process, method, product, or device.

[0037] It should also be noted that: "a plurality of" mentioned in the present application means two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.

[0038] Please refer to Figure 1 , Figure 1 which is a schematic diagram of an application scenario of a bus timeout monitoring method based on the AXI protocol shown in an exemplary embodiment of the present application. As Figure 1 shown, it includes at least one AXI host 10 and at least one AXI slave 20. A plurality of communication channels 30 are provided between the AXI host 10 and the AXI slave 20. For example, the plurality of communication channels include read channels and write channels; the plurality of communication channels 30 share a watchdog counter 40. The host can send access requests to the slave through the communication channels, and a register array is provided in the communication channels.

[0039] The AXI host initiates an access request to the target AXI slave through the target communication channel, and records the request information associated with the access request into the register array in the target communication channel; obtains the timeout time point corresponding to the access request; if the response information of the target AXI slave is not received when the value of the watchdog counter reaches the timeout time point, it is determined that the access request times out; triggers an interrupt, and reports the request timeout according to the information recorded in the register array.

[0040] The target AXI slave can receive access requests sent by the AXI master through the target communication channel, generate response information according to the access requests, and send the response information to the target AXI master.

[0041] Please refer to Figure 2 , Figure 2 which is a flowchart of the steps of a bus timeout monitoring method based on the AXI protocol shown in an exemplary embodiment of the present application. As Figure 2 shown, the bus timeout monitoring method based on the AXI protocol is executed by any AXI master, and may include steps S210 to S240.

[0042] S210. Initiate an access request to the target AXI slave through the target communication channel, and record the request information associated with the access request in the register array in the target communication channel.

[0043] In the embodiment of the present application, when the AXI master wants to access the AXI slave, it can select the target communication channel according to the access request. For example, if the access request is a write request, the selected target communication channel is the write channel; if the access request is a read request, the selected target communication channel is the read channel.

[0044] In one example, when the AXI master generates an access request, it will generate request information associated with the access request. This request information does not involve the access content. For example, the request information includes the slave information of the target AXI slave, such as the address of the slave and the unique identifier of the slave. The request information may also include the unique identifier of the AXI master, etc.; when the AXI master sends the access request, the AXI master will record the request information in the register array in the target communication channel; it should be noted that since read and write transactions are separated, read and write requests each use an independent register array.

[0045] In one example, the number of access requests can be one or more, and a group of register arrays is used to record the request information corresponding to one access request.

[0046] S220. Obtain the timeout time point corresponding to the access request.

[0047] In the embodiment of the present application, in order to avoid the access request getting stuck or not responding for a long time, each access request corresponds to a timeout time point. This timeout time point can be set in advance or set when generating the access request; among them, the timeout time points corresponding to each access request can be the same, and the timeout time points corresponding to each access request can also be different. For example, the timeout time point of the read request is less than the timeout time point of the write request. It can be understood that the timeout time point corresponding to the access request can be flexibly adjusted according to the actual situation and is not limited here.

[0048] S230. If the response information of the target AXI slave is not received when the value of the watchdog counter reaches the timeout time point, it is determined that the access request has timed out.

[0049] S240. Trigger an interrupt and report the request timeout according to the information recorded in the register array.

[0050] In the embodiment of the present application, when the AXI master initiates an access request, the watchdog counter starts counting. The watchdog counter can be a decrement counter, for example, the counter decrements from the count value corresponding to the timeout time point until it decrements to 0; the watchdog counter can also be an increment counter, which increments based on the access time of the access request sent by the AXI master until it reaches the timeout time point; when the watchdog counter reaches the timeout time point of the access request, the master checks whether a response from the slave is received; if no response is received, it is determined that the access request has timed out.

[0051] If the access request times out, it indicates that there is an abnormal situation in the transmission between the master and the slave. In order to avoid abnormal bus transmission caused by the abnormal situation, an interrupt needs to be triggered. This interrupt will notify the processor (CPU) that there is a timeout event to be processed, so as to ensure that the processor can respond and process the abnormal situation in a timely manner. And through the interrupt mechanism, the processor can manage resources more effectively and avoid resource waste caused by unresponsive requests.

[0052] In one example, when the master determines that the access request has timed out, it reads the information recorded in the register array, sends the information to the interrupt controller, and then the interrupt controller generates an interrupt and reports the information to indicate that a request timeout has occurred.

[0053] In one example, the information recorded in the register array includes the request information of the access request. It is necessary to read the information recorded in the register array and report it to explain that the interrupt is due to the timeout of the access request. In addition, the read information can be saved to an external debug register to avoid information loss. Then the processor can execute the corresponding error handling program according to the reported information, such as retrying the request, recording the error log or taking other corrective measures.

[0054] In the embodiment of the present application, in order to cope with the timeout problem in AXI transmission, a design scheme of sharing a watchdog counter is proposed, allowing multiple communication channels between the AXI master and the slave to share a watchdog counter, thus significantly reducing the power consumption and hardware area occupation of the system; when the master initiates an access request, the relevant request information will be recorded in the register array, and by detecting whether the watchdog counter reaches the timeout time point of the access request, it is judged whether the response information of the slave is received, ensuring the accuracy and real-time of the timeout detection.

[0055] When a timeout occurs, the interruption mechanism will be automatically triggered, and the information recorded in the register array will be reported, enabling the chip to quickly locate the problem, ensuring that the AXI bus can still operate stably in high-performance and high-concurrency complex scenarios, effectively handling timeout problems, avoiding data loss or system suspension caused by transmission delays or device anomalies, and further improving the robustness and processing efficiency of the bus.

[0056] Please refer to Figure 3 , Figure 3 which is the flowchart of the steps of the bus timeout monitoring method based on the AXI protocol shown in another exemplary embodiment of the present application. As Figure 3 shown, for the bus timeout monitoring method based on the AXI protocol, after sending an access request to the target AXI slave as shown in Figure 2 , steps S310 to S330 may further be included.

[0057] S310. Obtain the timeout threshold corresponding to the access request, and obtain the timeout time point based on the sending time of the access request and the timeout threshold.

[0058] S320. Record the timeout time point in the timeout register corresponding to the register array.

[0059] S330. Turn on the comparator corresponding to the timeout register. The comparator is used to determine whether the watchdog counter reaches the timeout time point.

[0060] In the embodiment of the present application, there is a timeout threshold corresponding to the access request, and the timeout threshold can be flexibly adjusted according to the actual situation, such as 10 minutes. When the host sends an access request, record the sending time of the access request, and use the sum of the sending time and the timeout threshold as the timeout time point of the access request.

[0061] It should be noted that in the target communication tunnel, the register array, the timeout register, and the comparator correspond one by one. The timeout time point can be recorded in the timeout register corresponding to the register array, and the comparator corresponding to the timeout register is turned on. The comparator is connected to the watchdog counter, and then the value output by the watchdog counter can be compared with the timeout time point to determine whether the timeout time point is reached, and further detect whether a timeout occurs.

[0062] It should be noted that the timeout threshold is fixed and can be applied to most channels; however, with the increase in chip complexity, different types of transactions may require different timeout strategies, so a dynamic timeout adjustment mechanism can be introduced.

[0063] In one example, obtaining the timeout threshold corresponding to the access request includes: obtaining the initial time threshold for the target AXI slave; obtaining the access type of the access request, and adjusting the initial time threshold according to the access type to obtain the timeout threshold corresponding to the access request.

[0064] In the embodiments of the present application, the host can set an initial time threshold for each AXI slave respectively. The initial time threshold is a fixed time threshold. The initial time thresholds corresponding to different AXI slaves can be the same or different. For example, the initial time threshold for the target AXI slave can be determined according to the past response time of the target AXI slave. For example, the average response time of the target AXI slave within a period of time can be used as the initial time threshold.

[0065] The host can dynamically adjust the time threshold based on the initial time threshold. Among them, different access types corresponding to the access request have different response requirements. Therefore, the initial time threshold is increased or decreased according to the access type of the access request to obtain the timeout threshold corresponding to the access request; among them, the increase or decrease of the initial time threshold can be flexibly adjusted.

[0066] For example, the initial time threshold set by the host for the target AXI slave is 8 minutes, and the access type of the access request is the type of immediate read. The response requirement of this type is immediate response and requires a shorter time. Therefore, 8 minutes is adjusted to 5 minutes as the timeout threshold; if the access type of the access request is the type of large amount of data writing, the response requirement of this type is accurate response and requires a longer time. Therefore, 8 minutes is adjusted to 15 minutes as the timeout threshold.

[0067] In the embodiments of the present application, by recording the timeout time point into the timeout register, and then turning on the comparator, and determining whether the watchdog reaches the timeout time point through the comparator, it can ensure that the timeout detection is accurate.

[0068] Please refer to Figure 4 , Figure 4 which is the step flowchart of the bus timeout monitoring method based on the AXI protocol shown in another exemplary embodiment of the present application. As Figure 4 shown, on the basis of what is shown in Figure 2 , the process of clearing records is added, including steps S410 to S420.

[0069] S410. If the response information of the target AXI slave is received before the value of the watchdog counter reaches the timeout time point, then find the target register array from multiple register arrays according to the response information, and find the target comparator from multiple comparators.

[0070] S420. Clear the information recorded in the target register array and stop the target comparator.

[0071] Among them, the number of access requests sent by the host to the target AXI slave includes multiple, and one access request corresponds to one register array and one comparator. Therefore, if it is detected that the response information of the target AXI slave has been received when the value of the watchdog counter reaches the timeout time point, it means that a certain target access request among the multiple access requests has not timed out and the target access request has been properly processed by the slave. Since the slave has responded to the access request, but the comparator is still running, it may wrongly consider that the target access request has timed out, thus triggering unnecessary interrupts. And since one access request corresponds to one register array and one comparator, there are multiple register arrays and multiple comparators. To avoid invalid timeouts, it is necessary to find the corresponding target register array and target comparator, clear the information recorded in the target register array, and stop the target comparator to indicate that the target access request has been completed and no further timeout monitoring is required. Among them, stopping the target comparator means resetting the target comparator and turning off the target comparator.

[0072] It can be understood that when the target AXI slave sends response information, the access request responded by the target AXI slave can be obtained through this response information. Therefore, the target register array can be found from the multiple register arrays and the target comparator can be found from the multiple comparators according to the response information.

[0073] In one example, the information recorded in the register array includes an access ID. That is, the request information associated with the access request includes the access ID, which can be set by the host when generating the access request to uniquely identify the access request. The access ID is generated based on the unique identifier of the slave device that the host wants to access (i.e., the slave ID). That is, the access ID can not only uniquely identify the access request but also indicate the slave device to be accessed. Finding the target register array and the target comparator includes: extracting the response ID from the response information; retrieving the access IDs recorded in each register array according to the response ID to obtain the target access ID that matches the response ID; taking the register array that records the target access ID as the target register array, and determining the target comparator corresponding to the target register. The AXI host can extract the response ID from the response information. The response ID can be generated by the target AXI slave when generating the response message. The response ID can indicate the access ID to which the slave responds and can also indicate the host itself. Therefore, the response ID can be the same as the access ID, or the response ID includes the access ID. Each register array records the access IDs of each access request. The extracted response ID can be compared one by one with the access IDs recorded in each register array to determine the target access ID that matches the response ID, and then determine the register array that records the target access ID as the target register array. Since the register array and the comparator are in one-to-one correspondence, the target comparator corresponding to the target register can be determined.

[0074] In some embodiments of the present application, by clearing the corresponding register array and stopping the comparator when the slave responds, it can be ensured that only truly unresponsive requests will be marked as timeouts, avoiding invalid timeout detection, improving the reliability and efficiency of the system, and ensuring that the timeout mechanism is triggered only when it is truly needed.

[0075] Please refer to Figure 5 , Figure 5 which is a flowchart of the steps of the bus timeout monitoring method based on the AXI protocol shown in another exemplary embodiment of the present application. As Figure 5 shown, Figure 5 shows Figure 2 the flowchart of the exemplary embodiment shown in step S240, including steps S510 to S520.

[0076] S510. Read the request information from the register array.

[0077] S520. Determine the access type of the access request according to the type of the register array, and generate timeout information for reporting according to the request information and the access type of the access request.

[0078] In the embodiment of the present application, request information is read from the register array, such as the address of the target AXI slave, the unique slave identifier (i.e., slave ID), the access ID, etc. From the request information, it can be known which slave has not responded.

[0079] As described above, the register arrays used for reading and writing are independent of each other. Therefore, the access type of the access request can be determined through the register array as a read access or a write access. Then, the access type and the request information are encapsulated to obtain timeout information. For example, the request information and the access type are concatenated to obtain the timeout information, and the timeout information is reported. Subsequently, the specific situation of the timeout of the access request can be obtained according to the timeout information.

[0080] The bus timeout monitoring method provided in the embodiment of the present application supports not only single host and single slave, but also single host and multiple slaves, as well as multiple hosts and multiple slaves. If the bus timeout monitoring system includes at least two AXI hosts and at least two AXI slaves, in order to facilitate the distinction between each host and slave, before recording the request information corresponding to the access request into the register array of the target communication channel, it further includes: obtaining the slave address of the target AXI slave; obtaining the host number and the unique host identifier of the AXI host itself, and concatenating the host number and the unique host identifier to obtain host information; generating request information according to the host information and the slave address.

[0081] Among them, the host stores the slave addresses of each AXI slave. Therefore, the slave address of the target AXI slave can be extracted. Since the address and the slave are in one-to-one correspondence, the slave information can be obtained from the address, and then it can be determined which slave has not responded, which helps to quickly locate the problem device.

[0082] Since there are multiple hosts, the system can assign a unique number to each host. For example, the number of host 0 is 0, the number of host 1 is 1, the number of host 2 is 2, and the number of host 3 is 3. The host number and the host ID can be concatenated to obtain host information when initiating an access. Then, the host information and the slave address can be used as the request information, or the host information, the slave address, the slave ID, and the access ID can be used as the request information.

[0083] During timeout or response, the system can parse the request information to judge the specific host, so as to quickly locate which host initiated the timeout access and which slave has not responded.

[0084] Please refer to Figure 6 , Figure 6 which is a schematic diagram of the timeout monitoring of the AXI host and the slave shown in an exemplary embodiment of the present application. As Figure 6As shown, it may include multiple hosts and slave devices, and also includes an Interrupt Controller (INTC). There are read channels and write channels between the host and the slave devices. Each channel includes multiple groups of register arrays entry0~N, and multiple comparators with the same number as the register arrays; Each channel also includes an adder, and the above-mentioned timeout register is the timer value when the host issues a request + the warning value of the adder; In order to handle the timeout problem in AXI transmission, a watchdog mechanism is introduced. The following are two watchdog design schemes.

[0085] a) Alarm clock scheme: A watchdog can be allocated for each AXI channel. After the host initiates an access, it starts counting down. If no response from the slave device is received when the countdown ends, it is considered a timeout.

[0086] b) Watch table scheme: Only one shared watchdog is needed. After the host initiates an access, it records the current time + the timeout threshold as the timeout time point for this access. If no response from the slave device is received when the watchdog counter reaches the timeout time point, it is considered a timeout.

[0087] Since the main sources of the chip's power consumption are the frequently flipped signals and logic, therefore, the watch table scheme is finally selected. In Figure 6 the read channel and the write channel share a watchdog (TIMER), which can not only save power but also save area resources.

[0088] Since the AXI protocol supports read and write outstanding, multiple groups of register arrays are required to record the addresses and IDs of this access, and the register arrays used for reading and writing are independent of each other and cannot be shared.

[0089] When the host wants to perform a read access to the slave device, it will initiate a read request (RD_REQ) and the activation signal of the read request (RD _ACTIVE), record the address and ID of the slave device in the register array, such as entry0, record the timeout time point of this access (current time + timeout threshold) in the register corresponding to the array, and turn on the corresponding comparator (the register array, the timeout register, and the comparator are in one-to-one correspondence).

[0090] Meanwhile, the watchdog starts counting when it receives the activation signal of the read request. If the timeout is set to 15 minutes, the value of the timeout register is the current timer value plus 15 minutes. The comparator will compare whether the value of the watchdog has reached the corresponding timeout point. If the corresponding slave response has not been received when the timeout point is reached, it is considered that the read request access has timed out. The comparator triggers the read signal (RD) to retrieve the information recorded in entry0 and send it to the INTC module, so that the INTC module generates an interrupt, and the recorded information is read out and forwarded to the CPU and saved in the external debug register. As long as the power is not turned off, the CPU can determine which access has timed out by reading these registers. Among them, since the read and write register arrays are separated, it is easy to determine whether the timeout transmission is a read access or a write access.

[0091] It can be understood that the slave can send response information and response activation status (RSP_ACTIVE) to the master. If the slave response information is received before the timeout time, this response activation status is used to indicate that the master can clear the information recorded in the corresponding register array, Reset and turn off the comparator to avoid invalid timeout detection; among them, the master can extract the response ID from the response message. Since the ID initiated by the master is the same as the ID responded by the slave, the ID can be used as the register array label to determine the register array to be cleared and the comparator to be stopped.

[0092] In the embodiment of the present application, an AXI bus timeout monitoring scheme (watch table scheme) based on a single watchdog is proposed. This timeout monitoring scheme supports the monitoring of AXI read and write outstanding transmissions. Among them, the recorded timeout information includes ID, address, and read / write type, but is not limited to this. The recorded information can be used by system debuggers to help the system formulate reasonable software and hardware solutions to improve the flexibility of the debugging system.

[0093] It should be noted that the present application is not limited to using the AMBA bus protocol. The same technical solution as above can be adopted for all buses similar to those without considering the functional safety design of automotive-grade chips to improve the reliability of on-vehicle on-chip bus transmission.

[0094] Figure 7 It is a schematic structural diagram of a bus timeout monitoring device based on the AXI protocol shown in an exemplary embodiment of the present application. The device is applied to a bus timeout monitoring system. The bus timeout monitoring system includes at least one AXI master and at least one AXI slave. Multiple communication channels are set between the AXI master and the AXI slave. The multiple communication channels share a watchdog counter. The device is deployed on the AXI master, as Figure 7 shown, in an exemplary embodiment, it includes.

[0095] A sending module 710, configured to initiate an access request to a target AXI slave through a target communication channel, and record request information associated with the access request in a register array in the target communication channel.

[0096] An obtaining module 720, configured to obtain a timeout time point corresponding to the access request.

[0097] A monitoring module 730, configured to determine that the access request times out if, when the value of the watchdog counter reaches the timeout time point, no response information from the target AXI slave is received.

[0098] A reporting module 740, configured to trigger an interrupt and report the request timeout according to the information recorded in the register array.

[0099] In an embodiment of the present application, based on the foregoing solution, the device further includes a recording module; the recording module is configured to obtain a timeout threshold corresponding to the access request, obtain the timeout time point according to the initiation time of the access request and the timeout threshold; record the timeout time point in a timeout register corresponding to the register array; turn on a comparator corresponding to the timeout register, and the comparator is used to determine whether the value of the watchdog counter reaches the timeout time point.

[0100] In an embodiment of the present application, based on the foregoing solution, the recording module is further configured to obtain an initial time threshold for the target AXI slave; obtain the access type of the access request, and adjust the initial time threshold according to the access type to obtain the timeout threshold corresponding to the access request.

[0101] In an embodiment of the present application, based on the foregoing solution, the number of access requests includes a plurality, and one access request corresponds to one register array and one comparator; the device further includes a clearing module, configured to, if, before the value of the watchdog counter reaches the timeout time point, response information from the target AXI slave is received, find the target register array from the multiple register arrays according to the response information, and find the target comparator from the multiple comparators; clear the information recorded in the target register array and stop the target comparator.

[0102] In an embodiment of the present application, based on the foregoing solution, the information recorded in the register array includes an access ID; the clearing module is further configured to extract a response ID from the response information; retrieve the access IDs recorded in each register array according to the response ID to obtain a target access ID that matches the response ID; use the register array that records the target access ID as the target register array, and determine the target comparator corresponding to the target register.

[0103] In one embodiment of the present application, based on the foregoing solution, the reporting module is further configured to read request information from the register array; determine the access type of the access request according to the type of the register array, and generate timeout information based on the request information and the access type of the access request for reporting.

[0104] In one embodiment of the present application, based on the foregoing solution, the bus timeout monitoring protocol system includes at least two AXI masters and at least two AXI slaves; the device further includes a generation module configured to obtain the slave address of the target AXI slave; obtain the master number and the unique master identifier of the AXI master itself, and splice the master number and the unique master identifier to obtain master information; generate request information according to the master information and the slave address.

[0105] It should be noted that the device provided in the above embodiment and the bus timeout monitoring method based on the AXI protocol provided in the above embodiment belong to the same concept. The specific manners in which each module and unit perform operations have been described in detail in the method embodiment, and will not be elaborated here.

[0106] An embodiment of the present application further provides a bus timeout monitoring system, including at least one AXI master and at least one AXI slave. A plurality of communication channels are provided between the AXI master and the AXI slave. The plurality of communication channels share a watchdog counter for counting; a plurality of groups of register arrays for recording information are provided in the communication channels; the AXI master is configured to execute the bus timeout monitoring method based on the AXI protocol described above.

[0107] In one embodiment of the present application, based on the foregoing solution, the system further includes an interrupt controller for generating an interrupt based on the trigger of the AXI master; a plurality of comparators respectively corresponding to the plurality of groups of register arrays are further provided in the communication channels, and the comparators are configured to determine whether the value of the watchdog counter reaches the timeout time point.

[0108] An embodiment of the present application further provides an electronic device, including: one or more processors; a storage device for storing one or more programs, which when executed by the one or more processors, cause the electronic device to implement the bus timeout monitoring method based on the AXI protocol provided in the above embodiments.

[0109] Figure 8 The structural diagram of a computer system of an electronic device suitable for implementing the embodiments of the present application is shown.

[0110] It should be noted that Figure 8 The computer system 800 of the electronic device shown is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present application.

[0111] As Figure 8 shown, computer system 800 includes a central processing unit (CPU) 801, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 802 or a program loaded from a storage section 808 into a random access memory (RAM) 803, such as executing the method in the above embodiments. In the RAM 803, various programs and data required for system operations are also stored. The CPU 801, ROM 802, and RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0112] The following components are connected to the I / O interface 805: an input section 806 including a keyboard, a mouse, etc.; an output section 807 including, for example, a cathode ray tube (CRT), a liquid crystal display (LCD), etc. and a speaker, etc.; a storage section 808 including a hard disk, etc.; and a communication section 809 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 809 performs communication processing via a network such as the Internet. A drive 810 is also connected to the I / O interface 805 as needed. A removable medium 811, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 810 as needed so that a computer program read from it can be installed into the storage section 808 as needed.

[0113] Specifically, according to an embodiment of the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present application includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a computer program for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 809, and / or installed from the removable medium 811. When the computer program is executed by a central processing unit (CPU) 801, various functions defined in the system of the present application are executed.

[0114] It should be noted that the computer-readable medium shown in the embodiments of the present application may be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. The computer-readable medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of the computer-readable medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, the computer-readable medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. And in the present application, the computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable computer program. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer-readable signal medium may also be any computer-readable medium other than the computer-readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium may be transmitted by any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0115] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present application. Among them, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and the above module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in an order different from that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, as well as the combination of blocks in the block diagram or flowchart, may be implemented by a dedicated hardware-based system for performing the specified functions or operations, or may be implemented by a combination of dedicated hardware and computer instructions.

[0116] The units involved in the embodiments described in this application can be implemented in software or in hardware, and the described units can also be provided in a processor. Among them, the names of these units do not, in some cases, constitute a limitation on the unit itself.

[0117] Another aspect of this application also provides a computer-readable medium, on which a computer program is stored. When the computer program is executed by a processor, the method for monitoring bus timeout based on the AXI protocol as described above is implemented. The computer-readable medium can be included in the electronic device described in the above embodiments, or can exist separately and not be assembled into the electronic device.

[0118] Another aspect of this application also provides a computer program product or a computer program. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable medium. The processor of the computer device reads the computer instructions from the computer-readable medium, and the processor executes the computer instructions, so that the computer device executes the method for monitoring bus timeout based on the AXI protocol provided in the above various embodiments.

[0119] The above content is only a preferred exemplary embodiment of this application and is not used to limit the implementation of this application. Those of ordinary skill in the art can easily make corresponding adaptations or modifications according to the main concept and spirit of this application. Therefore, the protection scope of this application should be subject to the protection scope required by the claims.

Claims

1. A bus timeout monitoring method based on the AXI protocol, characterized in that Applied to a bus timeout monitoring system, the bus timeout monitoring system includes at least one AXI master and at least one AXI slave, a plurality of communication channels are arranged between the AXI master and the AXI slave, the plurality of communication channels share a watchdog counter, and a plurality of register arrays are arranged in the communication channels. The method is executed by the AXI master and includes: Initiate an access request to a target AXI slave through a target communication channel, and record the request information associated with the access request into the register array in the target communication channel. One access request corresponds to an independent set of register arrays; Obtain the timeout threshold corresponding to the access request, and obtain the timeout time point corresponding to the access request according to the initiation time of the access request and the timeout threshold; Record the timeout time point into the timeout register corresponding to the register array; Open the comparator corresponding to the timeout register, and the comparator is used to determine whether the value of the watchdog counter reaches the timeout time point; in the target communication channel, the register array, the timeout register, and the comparator correspond one by one; If the response information of the target AXI slave is not received when the value of the watchdog counter reaches the timeout time point, it is determined that the access request times out; Trigger an interrupt and report the request timeout according to the information recorded in the register array.

2. The method according to claim 1, wherein The obtaining the timeout threshold corresponding to the access request includes: Obtain the initial time threshold for the target AXI slave; Obtain the access type of the access request, and adjust the initial time threshold according to the access type to obtain the timeout threshold corresponding to the access request.

3. The method according to claim 1, characterized in that The number of the access requests includes a plurality, one access request corresponds to one register array and one comparator; the method further includes: If the response information of the target AXI slave is received before the value of the watchdog counter reaches the timeout time point, search for the target register array from the plurality of register arrays according to the response information, and search for the target comparator from the plurality of comparators; Clear the information recorded in the target register array and stop the target comparator.

4. The method according to claim 3, wherein The information recorded in the register array includes an access ID; the searching for the target register array from the plurality of register arrays according to the response information and the searching for the target comparator from the plurality of comparators include: Extract the response ID from the response information; Retrieve the access ID recorded in each register array according to the response ID to obtain the target access ID that matches the response ID; Use the register array recording the target access ID as the target register array, and determine the target comparator corresponding to the target register.

5. The method according to claim 1, characterized in that The reporting of the request timeout according to the information recorded in the register array includes: Read the request information from the register array; Determine the access type of the access request according to the type of the register array, and generate timeout information for reporting according to the request information and the access type of the access request.

6. The method according to claim 1, characterized in that, The bus timeout monitoring system includes at least two AXI masters and at least two AXI slaves; before recording the request information corresponding to the access request into the register array in the target communication channel, it further includes: Obtaining the slave address of the target AXI slave; Obtaining the master number and the unique master identifier of the AXI master itself, and splicing the master number and the unique master identifier to obtain master information; Generating the request information according to the master information and the slave address.

7. A bus timeout monitoring device based on the AXI protocol, characterized in that, Applied to a bus timeout monitoring system, the bus timeout monitoring system includes at least one AXI master and at least one AXI slave, multiple communication channels are arranged between the AXI master and the AXI slave, the multiple communication channels share a watchdog counter, and multiple groups of register arrays are arranged in the communication channels. The device is deployed on the AXI master and includes: A sending module, configured to initiate an access request to a target AXI slave through a target communication channel, and record the request information associated with the access request into the register array in the target communication channel, and one access request corresponds to an independent group of register arrays; An obtaining module, configured to obtain the timeout threshold corresponding to the access request, and obtain the timeout time point corresponding to the access request according to the initiation time of the access request and the timeout threshold; record the timeout time point into the timeout register corresponding to the register array; turn on the comparator corresponding to the timeout register, and the comparator is used to determine whether the value of the watchdog counter reaches the timeout time point; in the target communication channel, the register array, the timeout register, and the comparator are in one-to-one correspondence; A monitoring module, configured to determine that the access request times out if the response information of the target AXI slave is not received when the value of the watchdog counter reaches the timeout time point; A reporting module, configured to trigger an interrupt and report the request timeout according to the information recorded in the register array.

8. A bus timeout monitoring system, including at least one AXI master and at least one AXI slave, multiple communication channels are arranged between the AXI master and the AXI slave, the multiple communication channels share a watchdog counter, and the watchdog counter is used for counting; Multiple groups of register arrays for recording information are arranged in the communication channel. In the communication channel, the register array, the timeout register, and the comparator are in one-to-one correspondence, and the comparator is used to determine whether the value of the watchdog counter reaches the timeout time point; The AXI master is used to execute the bus timeout monitoring method based on the AXI protocol according to any one of claims 1 to 6.

9. The system according to claim 8, wherein The system further includes an interrupt controller for generating an interrupt based on the trigger of the AXI master.

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