Cache consistency verification method and device for multi-core system

Abstract

The invention provides a cache consistency verification method and device for a multi-core system, and the method comprises the steps: building a test pool corresponding to a test case, and enabling the test pool to comprise a plurality of randomly generated memory access addresses and a test identifier for indicating the verification of the cache consistency; for any command pool corresponding to the test pool, generating at least one command in the command pool based on any memory access address and the test identifier in the test pool; commands among different command pools can be executed in parallel; randomly generating an excitation corresponding to any command in any command pool, and sending a plurality of excitations corresponding to the plurality of command pools to the multi-core system and the reference unit in parallel; obtaining a correct execution result obtained by simulating and executing the multiple excitations through the reference unit, and obtaining a to-be-verified execution result obtained by executing the multiple excitations through the multi-core system; and determining a cache consistency verification result according to the correct execution result and the to-be-verified execution result. According to the scheme, the cache consistency verification of the multi-core system can be accurately and effectively carried out.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a cache consistency verification method and device for a multi-core system. Background Art

[0002] Cache consistency issues in multi-core systems are a common challenge. When multiple processor cores share cache, without the correct consistency protocol and mechanism, data inconsistency issues may occur, leading to program errors and system instability. Therefore, it is very important to verify the cache consistency of multi-core systems. Cache consistency verification of multi-core systems often requires large-scale simulation and debugging work. As the number of cores increases, the complexity and resource requirements of verification also increase, making targeted debugging and fault location difficult.

[0003] So, how to accurately and effectively verify cache consistency in multi-core systems remains to be seen. Summary of the invention

[0004] The present application provides a cache consistency verification method and device for a multi-core system, which can accurately and effectively perform cache consistency verification on the multi-core system.

[0005] In the first aspect, the embodiment of the present application provides a cache consistency verification method for a multi-core system, which can be executed by a cache consistency verification device of the multi-core system, and the cache consistency verification device of the multi-core system can be a terminal device or a module for a terminal device, or a server or a module for a server. The present application does not limit the execution subject of the method. The method includes: constructing a test pool corresponding to a test case, wherein the test pool includes a plurality of randomly generated memory access addresses and a test identifier indicating cache consistency verification; for any command pool corresponding to the test pool, based on any memory access address and the test identifier in the test pool, generating at least one command in the command pool; the command pool corresponding to the test pool is multiple, and commands between different command pools can be executed in parallel; randomly generating a stimulus corresponding to any command in any command pool, and sending multiple stimuli corresponding to multiple command pools in parallel to the multi-core system and the reference unit; obtaining the correct execution results obtained by simulating the execution of the multiple stimuli by the reference unit, and obtaining the execution results to be verified obtained by the multi-core system executing the multiple stimuli; determining the cache consistency verification result according to the correct execution result and the execution result to be verified.

[0006] In the above scheme, on the one hand, memory access addresses and stimuli are generated randomly, which improves the randomness of cache consistency verification. Random testing can discover some hidden defects and improve the effectiveness of cache consistency verification of multi-core systems. On the other hand, commands between different command pools can be executed in parallel, which improves the efficiency of cache consistency verification of multi-core systems. On the other hand, based on the correct execution results and the execution results to be verified, the cache consistency verification results can be accurately and effectively determined.

[0007] In one possible implementation method, at least one command pool and a test pool are initialized; based on a first number of command pools set in the test case, the first number of command pools are obtained from the at least one command pool and bound to the test pool to obtain a test pool corresponding to the test case.

[0008] The above scheme can achieve accurate and effective determination of generating a specified number of command pools.

[0009] In a possible implementation method, based on the second number of memory access addresses set in the test case, the second number of memory access addresses is randomly generated; and the test identifier set in the test case and the second number of memory access addresses are stored in the test pool.

[0010] The above scheme can achieve accurate and effective generation of a specified number of access addresses, and ensure that the memory access addresses are randomly generated, thereby improving the randomness of cache consistency verification. Random testing can discover some hidden defects and improve the effectiveness of cache consistency verification of multi-core systems.

[0011] In a possible implementation method, based on the second number of memory access addresses set in the test case and the constraint conditions of the memory access addresses, the second number of memory access addresses that meet the constraint conditions of the memory access addresses are randomly generated.

[0012] The above scheme constrains the access address and can accurately and effectively verify the cache consistency of the target access address.

[0013] In a possible implementation method, any memory access address and the test identifier are obtained from the test pool; based on the test identifier and the memory access address, at least one command in the command pool is generated according to the constraints of the memory access mode set in the test case.

[0014] In the above scheme, the constraint condition of the memory access mode is used to determine that if there are multiple commands accessing the same memory access address at the same time, then multiple commands in multiple command pools will inevitably cause cache consistency problems in the multi-core system, thereby accurately and effectively verifying the cache consistency of the multi-core system.

[0015] In a possible implementation method, according to the correspondence between the command pool and the single core in the multi-core system, the stimulus corresponding to the command pool is sent to the single core that meets the correspondence for execution.

[0016] The above scheme can realize accurate and effective execution of the stimulus corresponding to the command pool in a single core that meets the corresponding relationship.

[0017] In a possible implementation method, the method is applied to a UVM verification platform; before building a test pool corresponding to a test case, the method further includes: triggering and running the test case on the UVM verification platform.

[0018] The above solution, through the UVM verification platform, can accurately and effectively verify the cache consistency of the multi-core system.

[0019] In the second aspect, the embodiment of the present application provides a cache consistency verification device for a multi-core system, comprising: a construction unit, a generation unit, a transceiver unit and a determination unit. The construction unit is used to construct a test pool corresponding to a test case, wherein the test pool includes a plurality of randomly generated memory access addresses and a test identifier indicating cache consistency verification; the generation unit is used to generate at least one command in the command pool for any command pool corresponding to the test pool based on any memory access address and the test identifier in the test pool; the test pool corresponds to multiple command pools, and commands between different command pools can be executed in parallel; the transceiver unit is used to randomly generate a stimulus corresponding to any command in any command pool, and send multiple stimuli corresponding to multiple command pools in parallel to the multi-core system and the reference unit; obtain the correct execution results obtained by simulating the execution of the multiple stimuli by the reference unit, and obtain the execution results to be verified obtained by the multi-core system executing the multiple stimuli; the determination unit is used to determine the cache consistency verification result according to the correct execution result and the execution result to be verified.

[0020] In one possible implementation method, the construction unit is specifically used to initialize at least one command pool and a test pool; based on a first number of command pools set in the test case, the first number of command pools are obtained from the at least one command pool, and bound to the test pool to obtain a test pool corresponding to the test case.

[0021] In a possible implementation method, the construction unit is specifically used to randomly generate a second number of memory access addresses based on the second number of memory access addresses set in the test case; and store the test identifier set in the test case and the second number of memory access addresses in the test pool.

[0022] In a possible implementation method, the construction unit is specifically used to randomly generate the second number of memory access addresses that meet the constraints of the memory access addresses based on the second number of memory access addresses and the constraints of the memory access addresses set in the test case.

[0023] In a possible implementation method, the generation unit is specifically used to randomly obtain any memory access address and the test identifier from the test pool; based on the test identifier and the memory access address, generate at least one command in the command pool according to the constraints of the memory access mode set in the test case.

[0024] In a possible implementation method, the transceiver unit is specifically used to send the stimulus corresponding to the command pool to the single core that meets the corresponding relationship for execution according to the corresponding relationship between the command pool and the single core in the multi-core system.

[0025] In a possible implementation method, the method is applied to a UVM verification platform; the above-mentioned device also includes an operation unit, and the operation unit is used to trigger and run the test case on the UVM verification platform.

[0026] In a third aspect, an embodiment of the present application further provides a computing device, including: A memory for storing program instructions; The processor is used to call the program instructions stored in the memory, and execute any method of implementing the above-mentioned first aspect according to the obtained program instructions.

[0027] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, in which computer-readable instructions are stored. When a computer reads and executes the computer-readable instructions, any method of the above-mentioned first aspect is implemented.

[0028] In a fifth aspect, an embodiment of the present application provides a computer program product, comprising a computer program executable by a computer device, wherein when the program is run on the computer device, the computer device executes any method for implementing the above-mentioned first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of a flow chart of a cache consistency verification method for a multi-core system provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of a UVN platform provided in an embodiment of the present application; Figure 3 A schematic diagram of the structure of a cache consistency verification system for a multi-core system provided in an embodiment of the present application; Figure 4A schematic diagram of the structure of a cache consistency verification device for a multi-core system provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure of a cache consistency verification device for a multi-core system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] Figure 1 A flow chart of a cache consistency verification method for a multi-core system provided in an embodiment of the present application, the method can be executed by a cache consistency verification device for a multi-core system, the cache consistency verification device for the multi-core system can be a terminal device or a module for a terminal device, or a server or a module for a server. The present application does not limit the execution subject of the method.

[0031] The method comprises the following steps: Step 101: Build a test pool corresponding to the test case.

[0032] The test pool includes a plurality of randomly generated memory access addresses and a test identifier indicating cache consistency verification.

[0033] Step 102: for any command pool corresponding to the test pool, based on any memory access address in the test pool and the test identifier, generate at least one command in the command pool.

[0034] There are multiple command pools corresponding to the test pool, and commands in different command pools can be executed in parallel.

[0035] Step 103 , randomly generating an excitation corresponding to any command in any command pool, and sending multiple excitations corresponding to multiple command pools in parallel to the multi-core system and the reference unit.

[0036] In a possible implementation method, there are at least two core systems in a multi-core system that access multiple stimuli corresponding to the same memory access address at the same time.

[0037] Step 104 , obtaining correct execution results obtained by simulating the execution of the multiple stimuli by the reference unit, and obtaining execution results to be verified obtained by the multi-core system executing the multiple stimuli.

[0038] Step 105: Determine a cache consistency verification result according to the correct execution result and the execution result to be verified.

[0039] In one possible implementation method, if the correct execution result and the execution result to be verified are inconsistent, it is determined that the multi-core system has a cache consistency problem; after multiple rounds of verification, if the correct execution result of each round of verification is consistent with the execution result to be verified, it is determined that the multi-core system does not have a cache consistency problem.

[0040] In a possible implementation method, if it is determined that the multi-core system has a cache consistency problem, error log information is collected and encoded, and the encoded error log is output and printed according to the encoding type.

[0041] In the above scheme, on the one hand, memory access addresses and stimuli are generated randomly, which improves the randomness of cache consistency verification. Random testing can discover some hidden defects and improve the effectiveness of cache consistency verification of multi-core systems. On the other hand, commands between different command pools can be executed in parallel, which improves the efficiency of cache consistency verification of multi-core systems. On the other hand, based on the correct execution results and the execution results to be verified, the cache consistency verification results can be accurately and effectively determined.

[0042] In a possible implementation method, the above step 101, the construction of the test pool corresponding to the test case, includes: initializing at least one command pool and a test pool; based on the first number of command pools set in the test case, obtaining the first number of command pools from the at least one command pool, and binding them with the test pool to obtain the test pool corresponding to the test case. Exemplarily, if the first number of command pools set in the test case is 100, then 100 command pools are obtained, and these 100 command pools are bound to the test pool to obtain the test pool corresponding to the test case; wherein each command pool includes multiple commands, for example, each command pool may include 10,000 commands. This application does not limit the first number.

[0043] Optionally, at least one command pool is determined according to different attributes; wherein the different attributes include one or more of the following: Independent read and write channels: including write request channel AW, write data channel W, write response channel B, read request channel AR and read response channel R. These channels have independent signals and can be executed in parallel, thereby improving bus performance. Burst transmission: In burst transmission, only the first address needs to be provided, unaligned access is supported, and efficient data transmission can be achieved in burst transmission. Unaligned access: Unaligned data transmission is supported, which means that it can handle data blocks of different sizes, improving the flexibility of data processing. Atomic operation: Atomic operation is supported to ensure data integrity during data transmission. Outstanding transmission: Outstanding transmission is supported, that is, multiple transactions are allowed to proceed simultaneously, improving the parallel processing capability of the system. Out-of-order transmission: Out-of-order transmission is allowed, that is, data can be processed out of order between different clock domains, further improving the efficiency of the system. QOS (Quality of Service): QOS is supported to ensure that different types of data transmission can get appropriate service quality assurance.

[0044] Optionally, the attributes (members) in the stimulus are determined according to the bus used, and generally standard AXI, ACE and other buses are used. This application does not limit the bus type, so the corresponding attributes are also not limited.

[0045] Optionally, multiple stimuli corresponding to the multiple command pools interact with the test unit DUT through a custom bus or a standard bus.

[0046] Optionally, burst transfers include three types: FIXED, INCR, and WRAP. FIXED mode: In this mode, the address corresponding to each transfer in a burst is a fixed value, which is suitable for repeated access to the same location, such as loading or clearing a FIFO. INCR mode: In this mode, the address corresponding to each transfer in a burst increases sequentially, which is suitable for accessing normal sequential memory. WRAP mode: In this mode, the address corresponding to each transfer in a burst has upper and lower limits, and the address increases within the limit, which is suitable for cache line access (such as MCU).

[0047] In a possible implementation method, the step 101, constructing a test pool corresponding to the test case, includes: randomly generating the second number of memory access addresses set in the test case based on the second number of memory access addresses set in the test case; storing the test identifier and the second number of memory access addresses set in the test case in the test pool. Exemplarily, if the second number of memory access addresses set in the test case is 10, 10 memory access addresses are randomly generated, and the test identifier and the 10 memory access addresses are stored in the test pool.

[0048] Optionally, the first number of command pools are obtained from the at least one command pool and bound to the test pool, including: each command in the command pool selects a test identifier and a memory access address from the test pool in turn for binding. Exemplarily, the second number of memory access addresses set by the test case is 10, and the first number of command pools is 100, then 10 memory access addresses and 100 command pools are randomly generated, and the command pool includes multiple commands, each command corresponding to a combination of the above multiple attributes; for any command pool of the 100 command pools, select an access address from the 10 memory access addresses in turn to bind to each command of the command pool, and bind the test identifier to each command of the command pool. That is, any command in each command pool includes a memory access address, a test identifier and multiple attributes.

[0049] Optionally, multiple command pools may select test identifiers and memory access addresses from the same test pool for binding; multiple command pools may also select test identifiers and memory access addresses from different test pools for binding. This application does not limit this.

[0050] In a possible implementation method, based on the second number of memory access addresses set in the test case and the constraint condition of the memory access address, the second number of memory access addresses that meet the constraint condition of the memory access address are randomly generated. The present application does not limit the constraint condition, and the constraint condition is used to constrain the address information of the memory access address. Exemplarily, if the constraint condition is that the last digit value of the memory access address is 0, then the second number of memory access addresses is randomly generated, and the last digit value of each memory access address of the second number is 0.

[0051] In a possible implementation method, the above step 102, the generation of at least one command in the command pool based on any memory access address and the test identifier in the test pool, includes: randomly obtaining any memory access address and the test identifier from the test pool; based on the test identifier and the memory access address, generating at least one command in the command pool according to the constraints of the memory access mode set in the test case. Among them, the constraints of the memory access mode are used to determine whether there are multiple commands accessing the same memory access address at the same time. The present application does not limit the specific implementation method of the constraints of the memory access mode. If multiple commands are restricted from accessing the same memory access address at the same time, multiple commands in multiple command pools will inevitably cause cache consistency problems in multi-core systems, thereby achieving accurate and effective verification of the cache consistency of multi-core systems.

[0052] Each command in the command pool further includes one or more of the following contents: read operation, write operation, atomic access, flush or interrupt. The present application does not limit the specific contents of each command.

[0053] In a possible implementation method, the above step 103, sending multiple stimuli corresponding to multiple command pools to the multi-core system and the reference unit in parallel, includes: determining the device to be verified of the multi-core system corresponding to each stimulus, and sending the multiple stimuli corresponding to the multiple command pools in parallel to the corresponding device to be verified and the reference unit. The access addresses of the multiple stimuli to be processed corresponding to at least two devices to be verified are the same at the same time. The device to be verified includes a central processing unit (CPU), and / or an I / O device.

[0054] In a possible implementation method, the above step 103, sending multiple stimuli corresponding to multiple command pools to the multi-core system in parallel, includes: according to the correspondence between the command pool and the single core in the multi-core system, sending the stimuli corresponding to the command pool to the single core that meets the correspondence for execution. Specifically, for any command pool in the multiple command pools, determine the Core subsystem to be tested that will process each stimulus in the command pool, and send the stimuli corresponding to the command pool to the Core subsystem to be tested for execution. The access addresses of the multiple stimuli to be processed corresponding to at least two Core subsystems to be tested are the same.

[0055] In a possible implementation method, the method is applied to a UVM verification platform; before building a test pool corresponding to a test case, the method further includes: triggering and running the test case on the UVM verification platform.

[0056] Among them, UVM is a set of verification methodologies that are easy to use and scalable. The most significant aspect of UVM's ease of use is that it contains a large number of standard libraries. Users can directly use existing functions and tasks to avoid a lot of duplication of work, thereby focusing their work on a deep understanding of the design to be tested and the careful design of test cases. UVM provides base classes such as uvm_object, uvm_component, and uvm_sequence, and uvm_component includes inheritable uvm_agent, uvm_monitor, uvm_scoreboard, uvm_model, and uvm_env classes. If the tree structure recommended by UVM is used, users basically do not need to define new classes. The management of verification platform components can be achieved by adjusting the connection and inheritance relationships. Common tree organizational structures of UVM are as follows: Figure 2 As shown in the figure, this is the verification platform management method recommended by UVM. Figure 2Each node shown is derived from the class of uvm_component and is instantiated by the new function. Agents are usually divided into in_agent (or i_agt), which contains uvm_sequencer and uvm_driver, or out_agent (or o_agt), which contains uvm_monitor. The function of uvm_sequencer is to generate stimulus (sequencen_item), and then pass the sequencen_item to uvm_driver, which converts it into port signal and drives the design under test. A sequencen_item is not necessarily a signal of a clock cycle, but may be a combination of port signals of multiple consecutive clock cycles. The separation of agent from other components allows different functional verifications to be switched by overloading sequencer.

[0057] UVM components can communicate through transaction level modeling (TLM). This communication mode is more like packaging a group of data together into a transaction. UVM also provides a flexible and automatic port connection mechanism, which can define the port connection relationship and the FIFO for handling transaction accumulation with just a few statements.

[0058] UVM provides a phase mechanism to manage the running order. Test cases will be executed in sequence according to the phase order. Phase includes function phase that does not consume simulation time and task phase that consumes simulation time. Function phase includes build_phase, connect_phase, report_phase, and uvm_componnet. Instantiation through new function must occur in build_phase, while there is no restriction on instantiation of uvm_object. Task phase includes reset_phase, configure_phase, main_phase and shutdown_phase. These phases all consume simulation time and can be executed in parallel. Function phase cannot be executed in parallel.

[0059] The embodiment of the present application adopts a UVM-based verification platform, uses the SV (SystemVerilog) language to write test cases, and uses the randomization and constraint mechanism of SV to generate randomized or directed test cases. First, multiple independently running command pools are constructed to form a test pool test pool. These pools are used to generate test scenarios, and then the testpool is added to the same test case test block. In this way, each time a test case is run, multiple different test scenarios can be randomly generated. Stimuli, and command pools are executed in parallel, which also improves the simulation speed. In addition, random testing can discover some hidden defects, run automatically, and improve verification efficiency.

[0060] Based on the same technical concept, Figure 3A cache consistency verification system 300 for a multi-core system provided by an embodiment of the present application is exemplarily shown. The cache consistency verification system 300 includes a test module 301, wherein the test module 301 includes a transaction generator 302 (Transaction Generator); the transaction generator 302 includes multiple command pools 303. Of course, the test module 301 also includes a stimulus agent, a reference model, a monitor, a sequencer, a scorebord, etc., and the reference model is also a reference unit. Among them, each command pool is used to generate multiple corresponding stimuli according to multiple commands, and the test module 301 sends the multiple stimuli generated by the multiple command pools to the test unit (Design Under Test, DUT), obtains the execution results to be verified corresponding to the multiple test units and the correct execution results corresponding to the reference unit, determines the cache consistency verification result according to the correct execution result and the execution result to be verified, and writes the cache consistency verification result into the log; wherein, DUT is the cache of the multi-core system. The function of the monitor monitor is to take out the signals of the DUT, which include not only the output signals of the port, but also the values ​​of the internal variables. After the signal is extracted, these variable values ​​are packaged into transactions in a specific format, and then handed over to the scoreboard for comparison with the reference unit output results. The scoreboard prints out the results that are inconsistent with the expected results output by the reference unit. If there is an inconsistency in the comparison results, it means that there are potential design defects in the original design to be tested. The reference unit is an ideal model written based on the design description of the Cache. The reference unit is written in C language and uses the DPI-C interface provided by SystemVerilog to interact with it. The data structure of the reference unit includes two arrays, which store the values ​​of Meta and Data respectively. In order to simulate the work of the Cache, the reference unit is driven by instructions rather than clock signals, and is not a clock-accurate model. Each time an instruction is loaded, it is checked in turn whether there is data missing or permission conflict, and data modification is made. The reference unit uses an overall check, focusing more on the final result after executing each memory access instruction, rather than the internal register state accurate to each clock.

[0061] Optionally, the transaction generator 302 includes multiple interfaces to be verified, and each interface to be verified can be connected to multiple devices to be verified. Exemplarily, the transaction generator 302 includes 8 interfaces to be verified, and the 8 interfaces to be verified are respectively connected to 8 cores to be tested of the multi-core system, then the transaction generator 302 is used to verify the cache consistency of the 8 core subsystems to be tested of the multi-core system; or, the 8 interfaces to be verified are respectively connected to 4 cores to be tested of the multi-core system and 4 I / O devices, then the transaction generator 302 is used to verify the cache consistency of the 4 core subsystems to be tested and 4 I / O devices of the multi-core system.

[0062] Optionally, each command pool is treated as an independent thread of execution. A particular command pool can be assigned to any number of stimulus agents, and any stimulus agent can contain any number of command pools. Command pools assigned to a particular agent can execute concurrently. For example, if the CPU0 command pool issues a load request (which takes many cycles to complete), another command pool can issue a new request in a subsequent cycle. In each cycle, the command pool to be used is randomly selected; if it cannot perform the operation for some reason (for example, it is in the middle of a blocking request), the next command pool in the list is selected. This continues until all pools in the agent have been traversed, or one of the pools actually sends a request.

[0063] Optionally, the Transaction generator is a UVM sequencer that is responsible for sending stimuli to each stimulus agent. There is only one Transaction generator in the environment, and each agent has a pointer to the same Transaction generator, which can be used to access different agents.

[0064] Based on the same technical concept, Figure 4 The cache consistency verification device 400 of a multi-core system provided by an embodiment of the present application is exemplarily shown. Figure 4As shown, it includes: a construction unit 401, a generation unit 402, a transceiver unit 403 and a determination unit 404. The construction unit 401 is used to construct a test pool corresponding to the test case, and the test pool includes a plurality of randomly generated memory access addresses and a test identifier indicating cache consistency verification; the generation unit 402 is used to generate at least one command in the command pool for any command pool corresponding to the test pool based on any memory access address and the test identifier in the test pool; the test pool corresponds to multiple command pools, and commands between different command pools can be executed in parallel; the transceiver unit 403 is used to randomly generate a stimulus corresponding to any command in any command pool, and send multiple stimuli corresponding to multiple command pools to the multi-core system and the reference unit in parallel; obtain the correct execution results obtained by simulating the execution of the multiple stimuli by the reference unit, and obtain the execution results to be verified obtained by the multi-core system executing the multiple stimuli; the determination unit 404 is used to determine the cache consistency verification result according to the correct execution result and the execution result to be verified.

[0065] In one possible implementation method, the construction unit 401 is specifically used to initialize at least one command pool and a test pool; based on a first number of command pools set in the test case, the first number of command pools are obtained from the at least one command pool, and bound to the test pool to obtain a test pool corresponding to the test case.

[0066] In a possible implementation method, the construction unit 401 is specifically used to randomly generate a second number of memory access addresses based on the second number of memory access addresses set in the test case; and store the test identifier set in the test case and the second number of memory access addresses in the test pool.

[0067] In a possible implementation method, the construction unit 401 is specifically used to randomly generate the second number of memory access addresses that meet the constraints of the memory access addresses based on the second number of memory access addresses and the constraints of the memory access addresses set in the test case.

[0068] In one possible implementation method, the generation unit 402 is specifically used to randomly obtain any memory access address and the test identifier from the test pool; based on the test identifier and the memory access address, generate at least one command in the command pool according to the constraints of the memory access mode set in the test case.

[0069] In a possible implementation method, the transceiver unit 403 is specifically used to send the stimulus corresponding to the command pool to the single core that meets the corresponding relationship in the multi-core system for execution.

[0070] In a possible implementation method, the method is applied to a UVM verification platform; the apparatus further includes an operation unit 405, and the operation unit 405 is used to trigger and run the test case on the UVM verification platform.

[0071] Based on the same technical concept, the embodiment of the present application provides a cache consistency verification device 500 for a multi-core system, and the cache consistency verification device 500 for a multi-core system may be, for example, a computing device. Figure 5 As shown, a cache consistency verification device 500 for a multi-core system includes at least one processor 501 and a memory 502 connected to the at least one processor. The specific connection medium between the processor 501 and the memory 502 is not limited in the embodiment of the present application. Figure 5 For example, the processor 501 and the memory 502 are connected via a bus. The bus can be divided into an address bus, a data bus, a control bus, etc.

[0072] In an embodiment of the present application, the memory 502 stores instructions that can be executed by at least one processor 501. The at least one processor 501 can execute the above-mentioned cache consistency verification method of a multi-core system by executing the instructions stored in the memory 502.

[0073] Among them, the processor 501 is a control center of a cache consistency verification device 500 of a multi-core system, and can use various interfaces and lines to connect various parts of the computer device, and perform resource settings by running or executing instructions stored in the memory 502 and calling data stored in the memory 502. Optionally, the processor 501 may include one or more determination units, and the processor 501 may integrate an application processor and a modem processor, wherein the application processor mainly processes an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 501. In some embodiments, the processor 501 and the memory 502 may be implemented on the same chip, and in some embodiments, they may also be implemented separately on independent chips.

[0074] The processor 501 may be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor, an application-specific integrated circuit (ASIC), a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and may implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0075] The memory 502 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules. The memory 502 may include at least one type of storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory, a random access memory (Random Access Memory, RAM), a static random access memory (Static Random Access Memory, SRAM), a programmable read-only memory (Programmable Read Only Memory, PROM), a read-only memory (Read Only Memory, ROM), an electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), a magnetic memory, a disk, an optical disk, and the like. The memory 502 is any other medium that can be used to carry or store the desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The memory 502 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.

[0076] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer-executable program. The computer-executable program is used to enable a computer to execute a cache consistency verification method for a multi-core system listed in any of the above methods.

[0077] An embodiment of the present application provides a computer program product, including a computer program executable by a computer device. When the program is run on the computer device, the computer device executes a cache consistency verification method for a multi-core system listed in any of the above-mentioned methods.

[0078] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0079] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0080] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0081] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0082] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A cache consistency verification method for a multi-core system, characterized in that: include: Constructing a test pool corresponding to the test case, wherein the test pool includes a plurality of randomly generated memory access addresses and a test identifier indicating cache consistency verification; For any command pool corresponding to the test pool, based on any memory access address and the test identifier in the test pool, at least one command in the command pool is generated; there are multiple command pools corresponding to the test pool, and commands between different command pools can be executed in parallel; Randomly generate a stimulus corresponding to any command in any command pool, and send multiple stimuli corresponding to multiple command pools to the multi-core system and the reference unit in parallel; Acquire correct execution results obtained by simulating and executing the multiple stimuli through the reference unit, and acquire execution results to be verified obtained by the multi-core system executing the multiple stimuli; A cache consistency verification result is determined according to the correct execution result and the execution result to be verified.

2. The method according to claim 1, characterized in that The test pool corresponding to the test case is constructed, including: Initialize at least one command pool and the test pool; Based on a first number of command pools set in the test case, the first number of command pools are obtained from the at least one command pool, and are bound to the test pool to obtain a test pool corresponding to the test case.

3. The method according to claim 1, characterized in that The test pool corresponding to the test case is constructed, including: Based on a second number of memory access addresses set in the test case, randomly generating the second number of memory access addresses; The test identifier and the second number of memory access addresses set in the test case are stored in the test pool.

4. The method according to claim 3, characterized in that The randomly generating the second number of memory access addresses based on the second number of memory access addresses set in the test case includes: Based on the second number of memory access addresses set in the test case and the constraint condition of the memory access addresses, the second number of memory access addresses satisfying the constraint condition of the memory access addresses are randomly generated.

5. The method according to claim 1, characterized in that The generating at least one command in the command pool based on any memory access address in the test pool and the test identifier includes: Obtain any memory access address and the test identifier from the test pool; Based on the test identifier and the memory access address, at least one command in the command pool is generated according to the constraint conditions of the memory access mode set in the test case.

6. The method according to claim 1, characterized in that The method of sending multiple stimuli corresponding to the multiple command pools to the multi-core system in parallel includes: According to the correspondence between the command pool and the single core in the multi-core system, the stimulus corresponding to the command pool is sent to the single core that meets the correspondence for execution.

7. The method according to any one of claims 1 to 6, characterized in that The method is applied to the UVM verification platform; Before building the test pool corresponding to the test case, it also includes: Triggering and running the test case on the UVM verification platform.

8. A cache consistency verification device for a multi-core system, characterized in that: include: A construction unit, used to construct a test pool corresponding to the test case, wherein the test pool includes a plurality of randomly generated memory access addresses and a test identifier indicating cache consistency verification; A generating unit, for generating at least one command in the command pool for any command pool corresponding to the test pool based on any memory access address in the test pool and the test identifier; the test pool corresponds to multiple command pools, and commands between different command pools can be executed in parallel; A transceiver unit, used for randomly generating a stimulus corresponding to any command in any command pool, and sending multiple stimuli corresponding to multiple command pools to the multi-core system and the reference unit in parallel; Acquire correct execution results obtained by simulating and executing the multiple stimuli through the reference unit, and acquire execution results to be verified obtained by the multi-core system executing the multiple stimuli; A determination unit is used to determine a cache consistency verification result according to the correct execution result and the execution result to be verified.

9. A computing device, characterized in that include: A memory for storing program instructions; A processor is used to call the program instructions stored in the memory, and execute the method according to any one of claims 1 to 7 according to the obtained program instructions.

10. A computer-readable storage medium, characterized in that: The method comprises computer-readable instructions, and when a computer reads and executes the computer-readable instructions, the method according to any one of claims 1 to 7 is implemented.

11. A computer program product, characterized in that The invention comprises a computer program executable by a computer device, and when the program is run on the computer device, the computer device is caused to execute the steps of the method according to any one of claims 1 to 7.

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